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Cavium Networks Confidential
Cavium Networks UpdateCavium Networks Update
Corporate and OCTEON Product Update
August 2006
Cavium Networks ConfidentialPage 2
Cavium Networks OverviewCavium Networks Overview
●● Industry Leading portfolio of Intelligent Processors for SecuritIndustry Leading portfolio of Intelligent Processors for Security, y, Network and Communication ProcessingNetwork and Communication Processing
OCTEON MultiOCTEON Multi--core MIPS64 Processor Family with 1 to 16 core MIPS64 Processor Family with 1 to 16 cnMIPScnMIPS cores and cores and most advanced application accelerationmost advanced application accelerationNITROX Security Processor Family that accelerates IPsec, SSL andNITROX Security Processor Family that accelerates IPsec, SSL and WLAN WLAN security protocols with performance up to 10+Gbps of IPsec and 4security protocols with performance up to 10+Gbps of IPsec and 40K RSA 0K RSA OPSOPSNITROX SOHO MIPS32 broadband communication processorsNITROX SOHO MIPS32 broadband communication processors
●● Fabless Semiconductor Company established 2001Fabless Semiconductor Company established 2001World Class Engineering Team: Strong Patent and IP position World Class Engineering Team: Strong Patent and IP position #1 Market leader for Security Processors#1 Market leader for Security ProcessorsOn track to become #1 MultiOn track to become #1 Multi--core Processor vendor for Networkingcore Processor vendor for Networking
Headquarters, Mountain View,
CA
IC Design Center
Marlboro, MACavium Networks
India Ltd. (Software Co-Dev)
Cavium Networks Taiwan
Cavium Networks China
Cavium Networks ConfidentialPage 3
World Class TeamWorld Class Team
●● Seasoned Team with ProvenSeasoned Team with ProvenTrack record of building businessesTrack record of building businessesManagement
Chip Design●● Majority from Renowned Majority from Renowned
DEC Alpha Processor TeamDEC Alpha Processor Team●● Full Custom Design CapabilityFull Custom Design Capability
●● Extensive Experience in Extensive Experience in Application, Networking and Application, Networking and Security SoftwareSecurity Software
Software Development
Security Networking
SoftwareProcessorDesign
Cavium Networks ConfidentialPage 4
Cavium Networks Product FamiliesCavium Networks Product Families
Comprehensive Solutions for Secure, Intelligent NetworksComprehensive Solutions for Secure, Intelligent NetworksComprehensive Solutions for Secure, Intelligent Networks
Security ProcessorsSecurity ProcessorsSecurity Processors
100Mb to 10Gbps Secure Access for Wired and Wireless Networks
Network Services ProcessorsNetwork Services ProcessorsNetwork Services Processors
Industry’s Largest family of 64 bit Multi Core processors for Intelligent Data and Security Services
Embedded Processors for Networking and CommunicationsEmbedded Processors for Networking and CommunicationsEmbedded Processors for Networking and Communications
Highly Integrated Single and Dual Core SOC processors for wired and wireless networking and communications equipment
Cavium Networks ConfidentialPage 5
Publicly Disclosed CustomersPublicly Disclosed Customers
Cavium Networks ConfidentialPage 6
Selected Awards and RecognitionSelected Awards and Recognition
2005 Outstanding FinancialPerformance by a Private CompanyFabless Semiconductor Association 12/05
2003 & 2004 Most Respected Private Fabless CompanyFabless Semiconductor Association 12/04 and 12/03
Top 100 Hot Products of 2004, 2005EDN Magazine 12/04, 12/05
Best Security Product 2003 & 2004Analog Zone 1/04 and 1/05
2003, 2004 & 2005 Top 100 Private Technology Innovators
Best Security ProcessorMicroprocessor Report 2003
Cavium Networks ConfidentialPage 7
Equipment Powered by Cavium ProductsEquipment Powered by Cavium Products
Enterprise
DataCenter
Triple Play GatewaysWired/Wireless
Access
Service Provider
Core
Soho /SME
Router
Router
Router
UTM AppliancesFW, VPN, IDS, AV
Security Appliances
Security Appliances
Routers
Storage, Servers
L3+/WLAN Switch
L4-L7 Switches
UTM Appliances
Secure RoutersUTM Appliances
Media Gateway
Metro Ethernet
802.16 Wimax
Wireless(3G, UMA)
802.11
Cavium Networks Confidential
Cavium Networks Cavium Networks
Product Overview
Aug 2006
Cavium Networks ConfidentialPage 9
Cavium Product SolutionsCavium Product Solutionsfrom 10Mbps to 10Gbps performancefrom 10Mbps to 10Gbps performance
Security ProcessorsSecurity
ProcessorsEmbedded ProcessorsNetworking & Comm
Embedded ProcessorsNetworking & Comm
Chip ProductsNITROX Lite
NITROXNITROX II
NITROX LiteNITROX
NITROX II
NITROX Soho
(MIPS32)
NITROX Soho
(MIPS32)
OCTEON CN30XXCN31XX1-2 Core
(MIPS64)
OCTEON CN30XXCN31XX1-2 Core
(MIPS64)
NITROX XLAdd In Cards & NICs
PCI/PCI-X
NITROX XLAdd In Cards & NICs
PCI/PCI-X
NITROX XLHigh Assurance
FIPS 140-2 Level 3 Boards
NITROX XLHigh Assurance
FIPS 140-2 Level 3 Boards
Board ProductsOCTEON XL
Secure, Intelligent NICs1 – 10Gbps
OCTEON XLSecure, Intelligent NICs
1 – 10Gbps
OCTEON CN31XX
CN36XX/38XX2-16 Core
(MIPS64)
OCTEON CN31XX
CN36XX/38XX2-16 Core
(MIPS64)
Broad rangeof OS supportLinux, VxWorks,
Proprietary, Other
Broad rangeof OS supportLinux, VxWorks,
Proprietary, Other
Tools/APIsHW Level and
Macro-level APIs,GNU Tools for MIPS
Tools/APIsHW Level and
Macro-level APIs,GNU Tools for MIPS
ComprehensiveSoftware Support
Reference/ProductionStacks
IPv4/v6, TCP, SSL, IPsec …
Reference/ProductionStacks
IPv4/v6, TCP, SSL, IPsec …
NSPsNSPs
Cavium Networks ConfidentialPage 10
NITROX Security ProcessorsNITROX Security Processors
Value Proposition
Value Value PropositionProposition
●● Offload Host CPU, Lower cost, Higher PerformanceOffload Host CPU, Lower cost, Higher Performance●● GluelessGlueless Connectivity to standard CPUs/Connectivity to standard CPUs/NPUsNPUs●● Fully software compatible from low end to high endFully software compatible from low end to high end●● Highest Performance and Broadest line in the IndustryHighest Performance and Broadest line in the Industry
FunctionFunctionFunction Packet ProcessingEncryption/DeAuthentication
VPN, SSL, WLAN
ClearEncrypted
ProductsProductsProductsNITROX™NITROX™Lite NITROX™ II
100M-1G 1G-3G 1G-10G
Cavium Networks ConfidentialPage 11
NITROX NITROX SohoSoho & Octeon SOC Processors for & Octeon SOC Processors for Embedded Applications Embedded Applications
Value Proposition
Value Value PropositionProposition
●● Highly Integrated SOC Processor Highly Integrated SOC Processor ●● Low Cost, High Performance, Low PowerLow Cost, High Performance, Low Power●● Rich set of I/O connectivityRich set of I/O connectivity●● Supports VDSL2, 802.11n, FTTH, GPON at Line RateSupports VDSL2, 802.11n, FTTH, GPON at Line Rate
FunctionFunctionFunctionWLAN
MPEGEnc/Dec
32b/64b CPUVPN/SSL EnginePacket Processor
FE/GE MACs
PCI,USB UARTs
TDM, SPI
HDD
Phone
ProductsProductsProductsNITROX™Soho Octeon™ 30xx/31xx
50M-100M 100M-200M 200M-1 Gbps
NITROX™Soho
Cavium Networks ConfidentialPage 12
ProductsProductsProducts
Octeon: IndustryOcteon: Industry’’s Broadest Line of Multi Core s Broadest Line of Multi Core Network Services ProcessorsNetwork Services Processors
Value Proposition
Value Value PropositionProposition
●● Highly Integrated SOC Processors Highly Integrated SOC Processors ●● Highest Performance, Lowest Power for Intelligent NetworkingHighest Performance, Lowest Power for Intelligent Networking●● Rich set of I/O connectivity for line cards, stand alone Rich set of I/O connectivity for line cards, stand alone
appliances and NIC applicationsappliances and NIC applications●● Supports 1Gbps to 10Gbps Line RatesSupports 1Gbps to 10Gbps Line Rates●● Common Software from low end to high endCommon Software from low end to high end
2/4 Core 16 Core1G-2G 2G-5G 5G-10G
8 Core
Cavium Networks Confidential
OCTEONOCTEON®® MultiMulti--core MIPS64 core MIPS64 Processors Processors
For Next Generation Secure, ContentFor Next Generation Secure, Content--AwareAware
Networking, Wireless, Storage and Server ApplicationsNetworking, Wireless, Storage and Server Applications
Cavium Networks ConfidentialPage 14
OCTEON is Being Used in a Broad Range of Applications OCTEON is Being Used in a Broad Range of Applications
FTTXRouters
802.11a/b/g/n
BroadBandGateways
SecurityAppliances
Wireless WAN & LAN
BBAggregation
Control Plane
Routers and
Switches
StorageHBAs
Network CentricLinux
Servers
Broadband /Consumer
NetworkingInfrastructure
Servers,Storage,Other
xDSL, MoCA
StorageEquipment
IntelligentNICs
VoIPCable
Cavium Networks Confidential
Introduction: Secure ContentIntroduction: Secure Content--Aware NetworkingAware Networking
OCTEONOCTEON®® MultiMulti--core MIPS64 core MIPS64 Processors Processors
Cavium Networks ConfidentialPage 16
Internet 1.0 Internet 1.0 Traditional Networks: 1995 Traditional Networks: 1995 -- 2000 2000
MainOffice
MobileWorkers
Business Partners
Home Offices
Regional/RemoteOffices
Processing required at L2/L3/L4 Header Level only
WLANUsers
DataCenter
Cavium Networks ConfidentialPage 17
Internet 2.0 is EvolvingInternet 2.0 is EvolvingSecure, Content Aware NetworksSecure, Content Aware Networks
MainOffice
Business Partners
Regional/RemoteOffices
WLANUsers
DataCenter
V
Need L2-L7 Data and Security Services
IPsec VPNIPsec VPN
IPsec VPNIPsec VPN
V
V
V
IPsec VPN
SSLVPN
V
Wireless Broadband
3G WiMax
MobileWorkersHome
Offices
Cavium Networks ConfidentialPage 18
Next Generation Networks Need to ProcessNext Generation Networks Need to ProcessNetwork Protocols, Services and Security at Wire SpeedNetwork Protocols, Services and Security at Wire Speed
L2L2 EthernetEthernetBridging, Bridging,
VirtualizationVirtualization(LAN)(LAN)
WirelessWireless
IPsec VPNIPsec VPNStatefulStatefulFirewallsFirewalls
SSL VPN & SSL VPN & EE--
CommerceCommerceDeep packet Deep packet inspection,inspection,
IPS, IPS, Gateway Gateway
AntiAnti--Virus, Virus, AV Scanning,AV Scanning,
AntiAnti--spamspam
Routing / Routing / Switching, ACL, Switching, ACL,
Traffic Traffic ManagementManagement
(WAN, Enterprise (WAN, Enterprise Edge)Edge)
Content Aware Content Aware Switching, Switching,
Routing, Filtering; Routing, Filtering; Load Balancing, Load Balancing,
MirroringMirroring
IPIP
TCP / UDPTCP / UDP
SessionSession
Application Application PayloadPayload
ApplicationsApplications
L3L3
L4L4
L5L5
L6+L6+
L7L7
Network Protocols Types of Security Services
Types of Data Services
Cavium Networks ConfidentialPage 19
Requirements of Secure, Content Aware Requirements of Secure, Content Aware Networks for Voice, Video and DataNetworks for Voice, Video and Data
●● L4L4--L7 Data ServicesL7 Data ServicesRead and interpret messages Read and interpret messages at application level instead of at application level instead of packet levelpacket levelContent Switching & RoutingContent Switching & Routing
–– Receive an order and Receive an order and convert and route to credit, convert and route to credit, sales & shipping applicationssales & shipping applications
–– Data center load balancing Data center load balancing based upon contentbased upon content
Application Level QoSApplication Level QoS–– Provide priority based on Provide priority based on
packet data from one packet data from one customer customer vsvs anotheranother
Content TransformationContent Transformation–– Convert from one application Convert from one application
format to anotherformat to another
●● L4 L4 –– L7 Security ServicesL7 Security ServicesSSL SSL VPNsVPNs
–– Enterprise access from Enterprise access from anywhere using any device anywhere using any device securelysecurely
Intrusion Detection and Intrusion Detection and PreventionPrevention
–– Real time detection of hacker Real time detection of hacker attacks and responseattacks and response
Anomaly DetectionAnomaly DetectionGateway AntiGateway Anti--virusvirus
–– Real time scanning of virusesReal time scanning of viruses–– Automatic updates at Automatic updates at
network points with latest network points with latest antianti--virus signaturesvirus signatures
AntiAnti--Spam, AntiSpam, Anti--phishingphishingContent FilteringContent Filtering
Cavium Networks Confidential
Product Line DetailsProduct Line Details
OCTEONOCTEON®® MultiMulti--core MIPS64 core MIPS64 Processors Processors
Cavium Networks ConfidentialPage 21
OCTEON NSP OCTEON NSP –– A New Class of ProcessorA New Class of Processor
NPUControl Plane
ProcessorNetwork Services
ProcessorProgrammability / Ease of porting
Ability to run OS xC/C++ software, standard instr set xNo instruction size limits (reqd for L3-7) xMemory Protection x
High Data Plane PerformanceOptimized pkt processing instructions Microcode based x C basedHigh perf memory subsystem, IO's xOptimized pkt ordering, forwarding, buffer mgmt xLevel 2 Cache (for L3-7 data perf) x
Content, Security Processing AccelerationSecurity (IPsec, SSL, IKE, RSA, RNG) very limited xRegex, pattern-match for IDS/AV x xTCP HW x xCompress / Decompress HW x x
Feature NPUControl Plane
ProcessorNetwork Services
ProcessorProgrammability / Ease of porting
Ability to run OS xC/C++ software, standard instr set xNo instruction size limits (reqd for L3-7) xMemory Protection x
High Data Plane PerformanceOptimized pkt processing instructions Microcode based x C basedHigh perf memory subsystem, IO's xOptimized pkt ordering, forwarding, buffer mgmt xLevel 2 Cache (for L3-7 data perf) x
Content, Security Processing AccelerationSecurity (IPsec, SSL, IKE, RSA, RNG) very limited xRegex, pattern-match for IDS/AV x xTCP HW x xCompress / Decompress HW x x
Feature NPUControl Plane
ProcessorNetwork Services
ProcessorProgrammability / Ease of porting
Ability to run OS xC/C++ software, standard instr set xNo instruction size limits (reqd for L3-7) xMemory Protection x
High Data Plane PerformanceOptimized pkt processing instructions Microcode based x C basedHigh perf memory subsystem, IO's xOptimized pkt ordering, forwarding, buffer mgmt xLevel 2 Cache (for L3-7 data perf) x
Content, Security Processing AccelerationSecurity (IPsec, SSL, IKE, RSA, RNG) very limited xRegex, pattern-match for IDS/AV x xTCP HW x xCompress / Decompress HW x x
Feature NPUControl Plane
ProcessorNetwork Services
ProcessorProgrammability / Ease of porting
Ability to run OS xC/C++ software, standard instr set xNo instruction size limits (reqd for L3-7) xMemory Protection x
High Data Plane PerformanceOptimized pkt processing instructions Microcode based x C basedHigh perf memory subsystem, IO's xOptimized pkt ordering, forwarding, buffer mgmt xLevel 2 Cache (for L3-7 data perf) x
Content, Security Processing AccelerationSecurity (IPsec, SSL, IKE, RSA, RNG) very limited xRegex, pattern-match for IDS/AV x xTCP HW x xCompress / Decompress HW x x
Feature
Cavium Networks ConfidentialPage 22
Network Services Processor Design PhilosophyNetwork Services Processor Design Philosophy
●● Focus on Delivering High Application PerformanceFocus on Delivering High Application Performance
●● Use multiple cores instead of pushing clockUse multiple cores instead of pushing clock--ratesrates
●● BuiltBuilt--in Hardware Acceleration in each processor corein Hardware Acceleration in each processor core
●● Incorporate application specific coprocessorsIncorporate application specific coprocessors
●● Extensive conditional clocking to reduce power Extensive conditional clocking to reduce power consumptionconsumption
●● Simple software model with standard ISASimple software model with standard ISA
Cavium Networks ConfidentialPage 23
OCTEON Integrates Multiple Chips into A Single Chip OCTEON Integrates Multiple Chips into A Single Chip
GHz Class control plane processing required for shuttling
data between co-processors
Memory
GHz classExamples: PQ III, x86, BCM1250
Memory
Memory
Memory
Memory
Bridge / Chipset
Security Processor
NPU for Packet and
TCP
Compression
Pattern Matching OCTEON:OCTEON:
A complete A complete system on a chipsystem on a chip
Provides Provides significant lower significant lower system cost and system cost and
powerpower
Security Processor
Packet Processor and TCP
Compression
Pattern Matching
OCTEON
Memory
Issues with existing multiIssues with existing multi--chip solutionschip solutions
• Performance Bottlenecks• High cost with multiple chips• High power and board real-estate• Long time to market• Fragmented Software
Existing Generic System Design
Cavium Networks ConfidentialPage 24
Octeon Network Services Processor FamilyOcteon Network Services Processor Family
●● Standard MIPS64 ISAStandard MIPS64 ISAStandard Standard OSOS’’ss ( Linux, VxWorks, ( Linux, VxWorks, etc)etc)Standard C Based software Standard C Based software
●● Multi Core ArchitectureMulti Core ArchitectureIntegrates 1 core to 16 cores on a Integrates 1 core to 16 cores on a single chipsingle chip
●● Integrated perIntegrated per--core hardware core hardware acceleration engines for data, acceleration engines for data, content and securitycontent and security
●● Integrated coIntegrated co--processorsprocessorsTCP, IDS, AntTCP, IDS, Ant--Virus, Virus, Compression/DecompressionCompression/Decompression
●● Integrated networks I/OIntegrated networks I/O’’ssCN38XX: Up to 8 Gig Ethernet CN38XX: Up to 8 Gig Ethernet MACsMACs, SPI, SPI--4, PCI4, PCI--XX
●● Tuned architecture for maximum Tuned architecture for maximum application performanceapplication performance
From 100 From 100 MbsMbs to 10 to 10 GbpsGbps
1MB SharedL2 Cache
1MB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
Hyper Access Low Latency Memory Controller
Hyper Access Low Latency Memory Controller
Optional 2x18-bit RLDRAM2
DDR II up to DDR-800
72 or 144 wide 4GB x 4 DIMMs max
SPI 4.2or
4x RGMII
SPI 4.2or
4x RGMII
Boot/flashGPIO
2xUART
64-bit, 133MHz
Compress/ Decomp
Compress/ Decomp
16x RegExEngines
16x RegExEngines
Packet InterfacePacket
Interface
Packet InterfacePacket
Interface
Misc I/OMisc I/O
SecureVault
SecureVault
PCI-XPCI-X
TCP UnitTCP Unit
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
4 -16
cnMIPS
cores
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet InputPacket Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
Cavium Networks ConfidentialPage 25
OCTEON 38xx NSP Block DiagramOCTEON 38xx NSP Block Diagram
1MB SharedL2 Cache
1MB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
Hyper Access Low Latency Memory Controller
Hyper Access Low Latency Memory Controller
Optional 2x18-bit RLDRAM2
DDR II up to DDR-800
72 or 144 wide 4GB x 4 DIMMs max
SPI 4.2or
4x RGMII
SPI 4.2or
4x RGMII
Boot/flashGPIO
2xUART
64-bit, 133MHz
Compress/ Decomp
Compress/ Decomp
16x RegExEngines
16x RegExEngines
Packet InterfacePacket
Interface
Packet InterfacePacket
Interface
Misc I/OMisc I/O
SecureVault
SecureVault
PCI-XPCI-X
TCP UnitTCP Unit
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
4 -16
cnMIPS
cores
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
Cavium Networks ConfidentialPage 26
OCTEON cnMIPS64OCTEON cnMIPS64™™ Core FeaturesCore Features
ISA (MIPS Arch. License) ISA (MIPS Arch. License) MIPS64 rel2 integer (industryMIPS64 rel2 integer (industry’’s first s first relrel. 2). 2)(MIPS32 and MIPS64 bit support)(MIPS32 and MIPS64 bit support)
Clock frequencyClock frequency 600MHz in 0.13600MHz in 0.13µµMicroarchitectureMicroarchitecture DualDual--issue superissue super--scalar, 5scalar, 5--stage pipelinestage pipeline
MIPS64 Release 2 MIPS64 Release 2 instructions for packetinstructions for packetprocessingprocessing
Instructions to accelerate Networking Instructions to accelerate Networking PerformancePerformance
Cavium NetworksCavium Networksinteger instructionsinteger instructions
Instructions to accelerate Networking Instructions to accelerate Networking PerformancePerformance
L1 cachesL1 caches Instruction: 32K, 4Instruction: 32K, 4--waywayData / local memory: 8K, 64Data / local memory: 8K, 64--waywayWrite buffer: 2K, 16Write buffer: 2K, 16--wayway
TLBTLB 3232--entry (64 pages, each up to 256MB)entry (64 pages, each up to 256MB)
Multiprocessing supportMultiprocessing support Fully coherent data cacheFully coherent data cache
Debug supportDebug support Robust MIPS EJTAG implementationRobust MIPS EJTAG implementationMulticore debug features (EPI Probe support)Multicore debug features (EPI Probe support)
Cavium Networks ConfidentialPage 27
OCTEON Family Standard CoOCTEON Family Standard Co--ProcessorsProcessors
●● Packet Input processorPacket Input processorPerforms in hardware error checks, memory Performs in hardware error checks, memory management, generates Work unit for management, generates Work unit for Synch/Schedule/Order UnitSynch/Schedule/Order Unit
●● Synch/Synch/SchedSched/Order Hardware Unit/Order Hardware UnitPerforms flowPerforms flow--loadload--balancing and synchronization balancing and synchronization across cores in a flexible manneracross cores in a flexible manner
Removes requirement for locks in software, enables Removes requirement for locks in software, enables linear scaling of application performance using linear scaling of application performance using multiple coresmultiple cores
●● TCP / IP accelerationTCP / IP accelerationHardware based accelerationHardware based acceleration
●● Packet Output ProcessorsPacket Output ProcessorsSupports dynamically allocated output queues with Supports dynamically allocated output queues with configurable priority optionsconfigurable priority optionsSupports virtual output portsSupports virtual output portsL4 (TCP/UDP) HW checksum insertionL4 (TCP/UDP) HW checksum insertionHW supports gatherHW supports gather
Cavium Networks ConfidentialPage 28
OCTEON Optional CoOCTEON Optional Co--processorsprocessors
●● Cavium security HW additions (Only on NSP Cavium security HW additions (Only on NSP or SCP option)or SCP option)
Used for encryption, CRC, HashingUsed for encryption, CRC, Hashing
●● Pattern and Regular Expression matching Pattern and Regular Expression matching (Only on NSP option)(Only on NSP option)
Separate memory interface for storing Separate memory interface for storing signaturesignatureUp to 32 DFA hardware enginesUp to 32 DFA hardware enginesDirect connection from cores to RLDRAMDirect connection from cores to RLDRAM
●● Compression / Decompression Compression / Decompression Programmable processor for GZIP, PKZIP Programmable processor for GZIP, PKZIP and variant protocols (Only on NSP option)and variant protocols (Only on NSP option)
GZIP (Deflate, inflate) RFC1951, RFC 1950GZIP (Deflate, inflate) RFC1951, RFC 1950Fixed or dynamic HuffmanFixed or dynamic HuffmanADLER32 checksumADLER32 checksum
Cavium Networks ConfidentialPage 29
OCTEON Product OptionsOCTEON Product Options
OCTEON Products Available in 4 Options:
1) CP = Communication Processor• Multi-core MIPS + Networking + TCP + QoS
HW acceleration2) SCP = Secure communication processor
• CP + Encryption HW3) EXP = Extreme processor
• CP + Compression/Decompression + Regex4) NSP = Network Services Processor
• EXP + Encryption HW
Cavium Networks ConfidentialPage 30
OCTEON Product Family SummaryOCTEON Product Family Summary
CN38XXCN38XX CN3630CN3630 CN31XXCN31XX CN30XXCN30XX# of cnMIPS 4 – 16 cores 4 cores 1 - 2 cores
300-500MHz
256 KB
72b DDR2, 667DDR; 1x 16b
DDR2
3xRGMII or 1x RGMII + 1x GMII; PCI-X 32b /
100MHz
Co-processors: Compr., Regex
SW
4-7 W
Package 1521 FCBGA 1521 FCBGA 868 BGA 564 BGA
Now
1 core
Core Frequency 400-600MHz 400-600MHz 300-500MHz
L2 Cache 1 MB 512 KB 128 KB / 64KB
External Memory 72/144b DDR2 800DDR, 2x 18b
RLDRAM2
72 b DDR2 800DDR; 1x 18b
RLDRAM2
36bit DDR2 667DDR
High Speed Interfaces
2x [4x RGMII or SPI 4.2]
PCI-X 64bit / 133MHz
4x RGMII or SPI4.2, PCI-X 64bit/133MHz
1RGMII/MII + 2RGMII or 1RGMII/MII +
1GMII/MII; PCI 32b/66
Co-processors:Sec., Packet., TCP
Flash boot bus, I2C, GPIO, 2xUARTs
USB 2.0 MAC/PHY
Power 10-30 W 10-15 W 2-4W
Availability Now Now Now
Cavium Networks ConfidentialPage 31
OCTEON Family Product TableOCTEON Family Product Table
Device cnMIPS Cores
CnMIPSCore Frequency Options
Max. Available Instructions per second
NSP
EXP
SCP
CP
L2Cache Size
Packet Interfaces PCI/ PCI-X
Main Memory I/O w/ ECC
DFA Memory I/O w/ ECC
Package
CN3010 1 300, 400, 500MHz 1.0G X X 128KB
3x RGMII/MII
or 1x RGMII/MII + 1x GMII
32-bit/66MHz PCI
DDR2: 36-bit NA 525-pin
BGA
CN3110 1 1.0G X X X X 256KB
CN3120 2 2.0G X X X X 256KB
CN3630 4 4.8G X X X 512KB4x RGMII
or 1x SPI4.2
DDR2: 72-bit
CN3830 4 4.8G X X X 1MB
CN3840 8 9.6G X X X 1MB
CN3850 12 14.4G X X X 1MB
CN3860 16 19.2G X X X 1MB
CN58xxOCTEON
Plus4-16 600MHz-
1GHz 6.4G – 32G X X X 1-2MB
2x [4x RGMII
or1x SPI4.2]
64-bit/133MHz PCI-X
DDR2-72-bit or 144-bit
RLDRAM2: 2x 18-bit
1521-pin
FCBGA
2x [4x RGMII
or1x SPI4.2]
DDR2: 72-bit or 144-bit
RLDRAM2: 2x 18-bit
1521 –pin
FCBGA
64 bit/ 133MHz PCI-X
400, 500, 500,
600MHz
3x RGMII or 1x
RGMII + 1x GMII
32-bit/100MHz PCI-X
DDR2: 72-bit
DDR2: 16-bit
868-pin BGA300, 400,
500 MHz
Cavium Networks ConfidentialPage 32
Unmatched ScalabilityUnmatched Scalability
●● OCTEON Family delivers a fully OCTEON Family delivers a fully
software compatible product line software compatible product line
that scales from:that scales from:
100 Mbps to Full Duplex 10G 100 Mbps to Full Duplex 10G GbpsGbps
with more content serviceswith more content services
<$20 to several hundred $ price <$20 to several hundred $ price
pointspoints
2 to 40W 2 to 40W
564 to 1521 pin package564 to 1521 pin package
OCTEON CN36XX
OCTEON CN38XX
Performance
10Gbps
100Mbps
2Gbps
1MB SharedL2 Cache
1MB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
Hyper Access Low Latency Memory Controller
Hyper Access Low Latency Memory Controller
Optional 2x18-bit RLDRAM / FCRAM
DDR II 400MHz 72 or 144 wide
4GB x 4 DIMMs max
SPI 4.2or
4x RGMII
SPI 4.2or
4x RGMII
Boot/flashGPIO
2xUART
64-bit, 133MHz
Compress/ Decomp
Compress/ Decomp
16x RegExEngines
16x RegExEngines
Packet InterfacePacket
Interface
Packet InterfacePacket
Interface
Misc I/OMisc I/O
SecureVault
SecureVault
PCI-XPCI-X
TCP UnitTCP Unit
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
4 -16
cnMIPS
cores
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet InputPacket Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
512KB SharedL2 Cache
512KB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
Hyper Access Low Latency Memory Controller
Hyper Access Low Latency Memory Controller
Optional 1x18bit RLDRAM / FCRAM
DDR II 400MHz72 bit wide
SPI 4.2or
4x RGMII
Boot/flashGPIO
2xUART
64-bit, 133MHz
Compress/ Decomp
Compress/ Decomp
4x RegExEngines
8x RegExEngines
Packet InterfacePacket
Interface
Misc I/OMisc I/O
SecureVault
SecureVault
PCI-XPCI-X
TCP UnitTCP Unit
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
4
cnMIPS
cores
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet InputPacket Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
256KB SharedL2 Cache
256KB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
Hyper Access Low Latency Memory Controller
Hyper Access Low Latency Memory Controller
DDR2
DDR II
72b 4GB max
3 RGMII / MIIor
1 RGMII / MII,1GMII
TDM /PCM
Boot/flashGPIO
2xUART
32-bit, 133MHz
Compress/ Decomp
Compress/ Decomp
8x RegExEngines
8x RegExEngines
TDM /PCM
TDM /PCM
Packet InterfacePacket
Interface
Misc I/OMisc I/O
SecureVault
SecureVault
PCI /PCI-XPCI /PCI-X
TCP UnitTCP Unit
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
1-2
cnMIPS
cores
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet InputPacket Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
2xUSB 2.0 OTG
64KB SharedL2 Cache
64KB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
DDR I/II 400MHz 36 bit wide
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
1
cnMIPS
core
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet InputPacket Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
Boot/flashGPIO
2xUART
32-bit, 133MHz
USBUSB
Packet InterfacePacket
Interface
Misc I/OMisc I/O
SecureVault
SecureVault
PCI-XPCI-X
TCP UnitTCP Unit
USB 2.0OTG
3x RGMII / MIIor
1x RGMII / MII + 1x GMII
OCTEON CN31XX
OCTEON CN30XX
OCTEON Plus CN58XXFull Duplex
10Gbps
Cavium Networks ConfidentialPage 33
OCTEON CN38XX Product FamilyOCTEON CN38XX Product FamilyCore: cnMIPS (MIPS64 w/R2) @ 400-600MHz
• 4 to 16 cores on a single chip, MMU• L1: 32K Icache, 8K Dcache w/parity• L2: 1MB cache size with ECC
External Memory (ECC):• 72/144 DDR II 400 DDR, 16GB Max• 2x 18bit RLDRAM2, 512MB Max. (Optional)
High-Speed Interfaces:• 2x [4x RGMII or SPI 4.2]• PCI-X 64/133
On-chip Coprocessors:• Security, TCP, Network Packets, Multi-core scaling, Compression/ Decompression, Regular Expression
Package: 1521 FCBGA
1MB SharedL2 Cache
1MB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
Hyper Access Low Latency Memory Controller
Hyper Access Low Latency Memory Controller
Optional 2x18-bit RLDRAM2
DDR II up to DDR-800
72 or 144 wide 4GB x 4 DIMMs max
SPI 4.2or
4x RGMII
SPI 4.2or
4x RGMII
Boot/flashGPIO
2xUART
64-bit, 133MHz
Compress/ Decomp
Compress/ Decomp
16x RegExEngines
16x RegExEngines
Packet InterfacePacket
Interface
Packet InterfacePacket
Interface
Misc I/OMisc I/O
SecureVault
SecureVault
PCI-XPCI-X
TCP UnitTCP Unit
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
4 -16
cnMIPS
cores
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet InputPacket Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
Cavium Networks ConfidentialPage 34
OCTEON CN36XX Product FamilyOCTEON CN36XX Product Family
Core: cnMIPS (MIPS64 w/R2) @ 400-600MHz• 4 cores on a single-chip, MMU• L2: 512KB cache size with ECC
External Memory (ECC): • 72 DDR II 400MHz DDR, 8GB Max.• 2 x 18bit RLDRAM2
High-Speed Interfaces:• 4x RGMII or SPI4• PCI-X 64/133
On-chip Coprocessors:• Security, TCP, Network Packets, Multi-core scaling & ordering, Compression/ Decompression, Regular Expression
Package: 1521 BGA
512KB SharedL2 Cache
512KB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
Hyper Access Low Latency Memory Controller
Hyper Access Low Latency Memory Controller
Optional 2x18-bit RLDRAM2
DDR II up to DDR-800 72b wide
SPI 4.2or
4x RGMII
Boot/flashGPIO
2xUART
64-bit, 133MHz
Compress/ Decomp
Compress/ Decomp
8x RegExEngines
8x RegExEngines
Packet InterfacePacket
Interface
Misc I/OMisc I/O
SecureVault
SecureVault
PCI-XPCI-X
TCP UnitTCP Unit
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
4
cnMIPS
cores
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet InputPacket Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
Cavium Networks ConfidentialPage 35
Core: cnMIPS @ 300, 400, 500MHz• 1 to 2 cores on a single-chip, MMU• L2: 256KB cache size with ECC
External Memory (ECC): • 64bit DDR II, 4GB max• 1x 16bit DDR2
High-Speed Interfaces:• Interface Options: 3xRGMII
or 1x RGMII + 1x GMII• PCI-X 32bit / 133MHz • USB 2.0 Host w/ PHY, TDM / PCM
On-chip Coprocessors:• Security, TCP, Network Packets, Multi-core scaling• Compression/ Decompression, Regular Expression
Package: 868 BGA
OCTEON CN31XX Product FamilyOCTEON CN31XX Product Family
256KB SharedL2 Cache
256KB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
72 bit wide – DDR IIup to 667MHz
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
Packet Input
Packet InputPacket Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
3x RGMIIor
1x RGMII + 1x GMII
Boot/flashGPIO
2xUART
32-bit, 100MHz
USBUSB
Packet InterfacePacket
Interface
Misc I/OMisc I/O
RNGRNG
PCI-XPCI-X
TCP UnitTCP Unit
USB 2.0Host w/PHY
16bit DDR2Optional
8x RegExEngines
8x RegExEngines
Hyper Access Low Latency Memory Controller
Hyper Access Low Latency Memory Controller
Compress/ Decomp
Compress/ Decomp
1 - 2
cnMIPS
cores
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
8K Dcache
2K Write BufferTDM/PCMTDM/PCMTDM/PCM
Cavium Networks ConfidentialPage 36
OCTEON CN3010 Product FamilyOCTEON CN3010 Product FamilyUnmatched features for next-gen multifunction, secure gateways,
802.11n SMB gateways & UTMUnmatched features for next-gen multifunction, secure gateways,
802.11n SMB gateways & UTM
128KB SharedL2 Cache
128KB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
DDR232/36 bit wide
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
1
cnMIPS
core
SecurityMIPS64 r2
Integer
Packet
16K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
Boot/flashGPIO
2xUART
32-bit, 66MHz
Packet InterfacePacket
Interface
Misc I/OMisc I/O
RNGRNG
PCIPCI
TCP UnitTCP Unit
2x RGMII + 1x RGMII/MII
OR 1x RGMII/MII +
1x GMII/MII
USBUSBUSB 2.0
Host w/ PHY
TDM/PCMTDM/PCMTDM/PCM
Cavium Networks ConfidentialPage 37
OCTEON CN3005 Product FamilyOCTEON CN3005 Product FamilyUnmatched features for next-gen multifunction, secure gateways,
802.11n SMB gateways & UTMUnmatched features for next-gen multifunction, secure gateways,
802.11n SMB gateways & UTM
64KB SharedL2 Cache
64KB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent Bus
DDR II 16 bit wide
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
1
cnMIPS
core
SecurityMIPS64 r2
Integer
Packet
16K Icache
8K Dcache
2K Write Buffer
Packet Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge
Boot/flashGPIO
2xUART
32-bit, 66MHz
Packet InterfacePacket
Interface
Misc I/OMisc I/O
RNGRNG
PCIPCI
TCP UnitTCP Unit
2x RGMII/MIIOR
1x GMII
USBUSBUSB 2.0
Host w/ PHY
TDM/PCMTDM/PCMTDM/PCM
Cavium Networks ConfidentialPage 38
CN3840 • 600 MHz• RGMII, SPI4• PCI/PCI-X,
CN3840 • 600 MHz• RGMII, SPI4• PCI/PCI-X,
OCTEON MIPS64 Processors RoadmapOCTEON MIPS64 Processors Roadmap
CN3860 • 16x cnMIPS• To 600 MHz• RGMII, SPI4• PCI/PCI-X,
CN3860 • 16x cnMIPS• To 600 MHz• RGMII, SPI4• PCI/PCI-X,
20072007
8 - 16Cores
2 - 4Cores
1- 2Cores
CN3830 • MIPS64 r2+• To 600 MHz• RGMII, SPI4• PCI/PCI-X
CN3830 • MIPS64 r2+• To 600 MHz• RGMII, SPI4• PCI/PCI-X
2006200620052005
CN3110 • MIPS64 r2+• To 550 MHz• RGMII, GMII• PCI/PCI-X
CN3110 • MIPS64 r2+• To 550 MHz• RGMII, GMII• PCI/PCI-X
CN3630 • 4x cnMIPS• To 600 MHz• RGMII, SPI4• PCI/PCI-X
CN3630 • 4x cnMIPS• To 600 MHz• RGMII, SPI4• PCI/PCI-X
CN3005 • MIPS64 r2+• To 500 MHz• RGMII, GMII• PCI
CN3005 • MIPS64 r2+• To 500 MHz• RGMII, GMII• PCI
CN3010 • cnMIPS• To 500 MHz• RGMII, GMII• MII, PCI
CN3010 • cnMIPS• To 500 MHz• RGMII, GMII• MII, PCI
CN3120• 2x cnMIPS• To 550 MHz• RGMII, GMII• PCI/PCI-X,
CN3120• 2x cnMIPS• To 550 MHz• RGMII, GMII• PCI/PCI-X,
Available NOW
20082008
Next Generation OCTEON parts•Software compatible •Higher Performance•Improved Performance /Watt
CN58XX• SW, Pin Compatible with CN38XX• 4 – 16 cnMIPS cores• Up to 1GHz, 2MB L2
CN58XX• SW, Pin Compatible with CN38XX• 4 – 16 cnMIPS cores• Up to 1GHz, 2MB L2
Cavium Networks ConfidentialPage 39
OCTEONOCTEON™™ Plus CN58XX Processor FamilyPlus CN58XX Processor Family
●● MultiMulti--core Processors up to 1GHzcore Processors up to 1GHz4 to 16 cores on a single chip4 to 16 cores on a single chip
●● Enhanced Enhanced cnMIPScnMIPS®® Plus corePlus coreUltraUltra--Efficient Design in latest TSMC Efficient Design in latest TSMC 90nm process90nm processFully MIPS32/MIPS64 compatibleFully MIPS32/MIPS64 compatible
Standard OS / C Based softwareStandard OS / C Based software
●● PerPer--core HW acceleration for Packet core HW acceleration for Packet processing and Securityprocessing and Security
KASUMI added for Wireless securityKASUMI added for Wireless security
●● Integrated CoIntegrated Co--processorsprocessorsPacket I/O, QoS, TCP, IDS, AntiPacket I/O, QoS, TCP, IDS, Anti--Virus, Virus, Compression/ DecompressionCompression/ Decompression
●● Integrated networks I/OIntegrated networks I/O’’ssUp to 8 Up to 8 GbGb Ethernet, SPIEthernet, SPI--4, PCI4, PCI--XX
●● Highest Application PerformanceHighest Application PerformanceUp to Full Duplex 10GbpsUp to Full Duplex 10Gbps
●● 1521 FCBGA package1521 FCBGA package●● Fully pin and software compatible Fully pin and software compatible
with OCTEON CN38XX/36XXwith OCTEON CN38XX/36XX
2MB SharedL2 Cache
2MB SharedL2 Cache
Hyper Access Memory
Controller
Hyper Access Memory
Controller
Coherent, Low-latency Interconnect
Hyper Access Low Latency Memory Controller
Hyper Access Low Latency Memory Controller
Optional 2x18-bit RLDRAM2
DDR2 up to 1066 MHz
72 or 144-bit wide
SPI 4.2or
4x RGMII
SPI 4.2or
4x RGMII
Boot/flashGPIO
2xUART
64-bit, 133MHz
Compress/ Decomp
Compress/ Decomp
32x RegExEngines
32x RegExEngines
Packet InterfacePacket
Interface
Packet InterfacePacket
Interface
Misc I/OMisc I/O
SecureVault
SecureVault
PCI-XPCI-X
TCP UnitTCP Unit
I/O
Bus
Sched/ Synch/ Order
Sched/ Synch/ Order
Up to 16
cnMIPS
cores
SecurityMIPS64 r2
Integer
Packet
32K Icache
16K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
16K Dcache
2K Write Buffer
SecurityMIPS64 r2
Integer
Packet
32K Icache
16K Dcache
2K Write Buffer
SecurityMIPS64 r2
IntegerMIPS64 r2
Integer
Packet
32K Icache
16K Dcache
2K Write Buffer
Packet Input
Packet InputPacket Input
Packet Input
Packet OutputPacket Output
I/O Bridge
I/O Bridge 640 Gbps
136
Gbps
Cavium Networks Confidential
Software OverviewSoftware Overview
OCTEONOCTEON®® MultiMulti--core MIPS64 core MIPS64 Processors Processors
Cavium Networks ConfidentialPage 41
OCTEON Software EcosystemOCTEON Software Ecosystem
●● SDKSDKgccgcc and and gdbgdb modified for cnMIPS architecturemodified for cnMIPS architectureDDD Graphical Debugger interfaceDDD Graphical Debugger interfaceOCTEON Simple ExecutiveOCTEON Simple ExecutiveLinux kernelLinux kernelBoot loaderBoot loaderExample applicationsExample applications
●● Licensable ToolLicensable Tool--kits from Cavium with no perkits from Cavium with no per--unit royaltyunit royaltyIPSecIPSecTCP OffloadTCP OffloadSSL OffloadSSL Offload
●● Commercial Operating SystemsCommercial Operating SystemsMontaVista LinuxMontaVista LinuxWindriverWindriver VxWorks, LinuxVxWorks, LinuxENEA OSEENEA OSE
●● Application Software from PartnersApplication Software from PartnersNetworking Stacks Networking Stacks –– 6WIND6WINDUTM UTM –– IntotoIntoto and unannouncedand unannouncedVoIP processing VoIP processing –– D2 TechD2 TechJVM (java), IPS, AntiJVM (java), IPS, Anti--Virus Virus -- unannouncedunannounced
Cavium Networks ConfidentialPage 42
Software Standards SupportedSoftware Standards Supported
●● Industry standard MIPS32/MIPS64 instruction set Industry standard MIPS32/MIPS64 instruction set architecturearchitecture
AnsiAnsi C, C++C, C++
●● Industry standard tools supportedIndustry standard tools supportedGnu, DDD, EJTAGGnu, DDD, EJTAG
●●Support for Linux & Support for Linux & VxworksVxworksDefactoDefacto standard operating systemsstandard operating systems
●●Support for BSD socket APIs, Support for BSD socket APIs, OpenSSLOpenSSL, IPv4 & , IPv4 & IPv6IPv6
DefactoDefacto networking standardsnetworking standards
Cavium Networks ConfidentialPage 43
OCTEON cnMIPSOCTEON cnMIPS™™ Multicore UsageMulticore Usage
●● Flexible cnMIPS cores can:Flexible cnMIPS cores can:Run a full operating system, Run a full operating system, and/orand/orRun tuned dataRun tuned data--planeplane--like codelike code
●● Example OCTEON applications:Example OCTEON applications:All cores run dataAll cores run data--plane codeplane codeAll cores run multiprocessor All cores run multiprocessor LinuxLinux11--2 cores run Linux, remaining 2 cores run Linux, remaining cores run datacores run data--plane codeplane codeHybrid Linux threads running Hybrid Linux threads running datadata--plane codeplane code
DataDataDataDataDataDataDataDataDataDataDataDataDataDataDataData
DataDataDataDataDataDataDataDataDataDataDataDataDataDataDataOS
DataDataDataDataDataDataDataDataDataDataDataDataDataDataDataOS
Data-plane only:
Operating system only:
Mixed:
Cavium Networks Confidential
EcoEco--system Overviewsystem Overview
OCTEONOCTEON®® MultiMulti--core MIPS64 core MIPS64 Processors Processors
Cavium Networks ConfidentialPage 45
OCTEON Hardware EcosystemOCTEON Hardware Ecosystem
Complementary Silicon EJTAG, Appliances, AMC, ATCA cards
Mentor EJTAG probe available
Vweb Video codecs
Netlogic TCAMs
Motherboards & Cards available from ODMs
Asus, Portwell, Movidis
Infineon DSP for VoIP
Micron Support. Special RLDRAM2 pricing for OCTEON customers
Ample Comm SPI-4.2 to 10GE MAC
SLIC used with VoIP in SW
802.11a/b/g, 801.11n chipsets
Radisys OCTEON based Cards
Lanbird Dual OCTEON ATCA Carrier Card
Home networking & WAN usingCoax (MOCA)
Cavium Networks ConfidentialPage 46
OCTEON Software EcosystemOCTEON Software Ecosystem
OS & Tools Software Stacks
Linux support
VxWorks and Linux
Networking Stacks
UTM Software
ENEA OSE
Apogee IBM JVM
D2 Tech VoIP SW
Linux and GNU Tool-chain
Critical Office in a box
TeamF1 Security SW
Kaspersky AV gatewaysignatures
Services: CustomSW Development
Cavium Networks Confidential
System Block DiagramsSystem Block Diagrams
OCTEONOCTEON®® MultiMulti--core MIPS64 core MIPS64 Processors Processors
Cavium Networks ConfidentialPage 48
OCTEON in Enterprise and Service ProvidersOCTEON in Enterprise and Service Providers
SYSTEMDRAM
RLDRAM
18bits
PHYMAC
FabricGigabit, 10Gigabit Interfaces
72 or 144 bits
SYSTEMDRAM
72 or 144 bits
FICOCTEONCN3xxx
OCTEONCN3xxx
Line Cards or Service Blades
Appliances, UTM Gateways
RGMII
PHYor
Switch
DRAM DDR II
72 or 144 bits
OCTEONCN3xxx PCI-X
64bit133MHz
PCI-X Slot
Key BoardMouseParallel PortUARTUSBOptional
RLDRAM
BootFlash
SATA
BridgeBridge
VGA Monitor
Optional
Cavium Networks ConfidentialPage 49
OCTEON in SME OCTEON in SME
DRAM DDR2
16-72 bits
PCI/PCI-X 32bitUp to 100 MHz
USB 2.0
PHYRJ45DMZ
PHYRJ45WAN
PHYRJ45LAN OCTEON
CN31XXCN30XX
802.11nWLAN
Radio / MAC
SLIC
SATA Controller
MPEGSOC
Triple Play Gateway
Gigabit Routers
LAN
OCTEONCN31XXCN30XX
PCI 32bitUp to 100 MHz
USB 2.0
RJ45
Radio / MAC
Optional802.11nWireless
LANSwitch
+PHY
PHY
RJ45
RJ45WAN
DRAM DDR2
32 bits
TDM / PCM
SLIC
3x GigabitInterfaces
5x GigabitInterfaces
Cavium Networks ConfidentialPage 50
OCTEON in StorageOCTEON in Storage
Network Attached Storage
Host Bus Adaptors and Intelligent NIC cards
OCTEON 3xxx
Up to 144 bits
PCI-X / PCIe
Disk Controller
Disk Controller
SATA / SAS
SATA / SAS
SYSTEMDRAM
64-bit PCI-X133MHz
PHY
4x RGMII
OCTEON3xxx
4x GigabitInterfaces
or 1x 10GE interface
4x GigabitInterfaces
or 1x 10GE interface
DRAM DDR2
Cavium Networks ConfidentialPage 51
SummarySummary
●● OCTEONOCTEON™™ is a new class of processor is a new class of processor –– The Network The Network Services ProcessorServices Processor
●● 22--16 cnMIPS16 cnMIPS™™ cores with extensive hardware acceleration cores with extensive hardware acceleration and standard networking interfaces and standard networking interfaces
●● Standard OS, CStandard OS, C--code based software developmentcode based software development
●● Ideal for Layer 3 to Layer 7 Internet Service and Security Ideal for Layer 3 to Layer 7 Internet Service and Security applicationsapplications
●● Rich Ecosystem for hardware and software Rich Ecosystem for hardware and software
●● OCTEON delivers 5x power, area and performance benefit OCTEON delivers 5x power, area and performance benefit
Cavium Networks ConfidentialPage 52
For More Information Please ContactFor More Information Please Contact
●● Web: http://Web: http://www.caviumnetworks.comwww.caviumnetworks.com
●● Email: Email: [email protected]@caviumnetworks.com
Cavium Networks Confidential
Thank YouThank You