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International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November 2014

2897 ISSN: 2278 – 7798 All Rights Reserved © 2014 IJSETR

Cascaded Hybrid Seven Level Inverter with

Different Modulation Techniques for

Asynchronous Motor

Abstract- This paper presents a asymmetric cascaded hybrid

7 level multilevel inverter using different switching techniques

i.e. phase disposition pulse width modulation, degree

modulated pulse generator and hybrid mixed switching

technique. This paper presents comparison between motor

output and THD of Asymmetrical Cascaded hybrid 7 level

Multilevel Inverter (MLI) using different modulation

techniques. These control schemes is applied to 7 level

Asymmetrical Cascaded hybrid Multilevel Inverter

(CHMLI). Different topologies of multilevel inverter have

been reported in the literature, but this work mainly

focuses on the asymmetrical cascaded hybrid multilevel

inverter circuit with reduced number of switches and input

DC sources. THD and motor output are analyzed in FFT

window. The results are observed by MATLAB/SIMULINK

software.

keywords- Asymmetrical CHMLI, Mixed switching, Degree

modulated pulse generator , PDPWM.

1. INTRODUCTION

Inverter is a device that converts electrical power from DC

to AC form using electronic circuits. Generally simple

inverter gives 2 or 3 level output voltage .The inverters with

number of voltage level equal to three or above that are

known as multilevel inverter.MLI are capable of producing

high power high voltage as the unequal voltage sources of

of MLI allows to reach high voltage wiyh low harmonics

without the use of transformer.MLI is a latest alternative to

implement low frequency based inverter with low output

voltage distortion.Basic Multilevel topologies are of 3 types

shown in below:

Diode clamped inverter

Flying capacitor inverter

Cascaded

Figure 1.1 Multilevel inverter topologies

2. CASCADED H-BRIDGE MLI

Cascaded H-Bridge (CHB) configuration has recently

become very popular in high-power AC supplies and

adjustable-speed drive applications. A cascade multilevel

inverter consists of a series of H-bridge (single-phase full

bridge) inverter units in each of its three phases. Each H-

bridge unit has its personal dc source, which for an

induction motor would be a battery unit, fuel cell or solar

cell. Each SDC (separate D.C. source) is associated with a

single-phase full-bridge inverter. The ac terminal voltage

of different level inverters is connected in series. Through

different combinations of the four switches, S1,S2,S3 &

S4, each converter level can generate three different

voltage outputs, +Vdc, -Vdc and zero. The AC outputs of

different full-bridge converters in the same phase are

connected in series such that the synthesized voltage

waveform is the sum of the individual converter outputs,

Note that the number of output-phase voltage levels is

defined in different way from those of the two previous

converters (i.e. flying capacitor and diode clamped). In

Ankur Chourasiya, Poonam Chouksey, Nayna Bhargava, S. P. Phulambrikar



these topologies the number of output-phase voltage

levels is defined by m= 2N+1, where N is the number of

DC sources

A seven-level cascaded converter, for example, consists

of three DC sources and three full bridge converters are

Minimum harmonic distortion can be obtained by

controlling the conducting angles at different converters

levels. Each H- bridge unit generates a quasi-square

waveform by phase shifting its positive and negative

phase legs‟ switching timings. Every switching devices

always conduct for 180° or half cycle regardless of the

pulse width of a quasi-square wave. These switching

methods make all of the switching devices current stress

equal. In the motoring mode a power flows from the

batteries through the cascade inverter to the motor.

In the charging mode, the cascade

converters act as rectifiers, and power flows from the

charger (ac source) to the batteries. The cascade

converters can also act as rectifiers to help recover the

kinetic energy of the vehicle if regenerative braking is

used. The cascade inverter can also be used in parallel

HEV configurations. This new converter can avoid extra

clamping diodes or voltage balancing capacitors

.

The combination of the 180° conducting method and the

pattern-swapping scheme make the cascade inverter’s

voltage and current stresses the same and battery voltage

balanced.

Figure 2.1 Block of a h-bridge Multi-level inverter

Figure 2.4 shows the basic block of cascade H-bridge

Multi-level inverter and its associated switching instants.

As shown it consists of a DC source and. The switching

states for four power devices are constant i.e., When S1 is

on, S2 cannot be on and vice versa, similarly with S3 or

S4.

3.1 H-BRIDGE MLI USING HYBRID MIXED

SWITCHING SCHEME

seven level hybrid cascaded multilevel inverter with a

mixed pulse width modulation method is designed by

reducing a number of switches.

A simulation diagram using a mixed switching scheme of

Seven-level HMLI with asynchronous motor are shown

in a figure 3.1 using MATLAB/SIMULINK.

Figure-3.1 Seven-level HMLI using hybrid mixed

switching scheme simulation diagram with asynchronous

motor

The simulation block diagram has seven level cascaded

hybrid multilevel inverter with asynchronous motor is



shown in Fig-3.1 These are combination two types

inverter: first one is H-bridge inverter and other is two

conventional inverter. The conventional inverter is acting

as the main inverter and H bridge inverter is acting as the

auxiliary inverter.

3.1.1 HYBRID MIXED SWITCHING SCHEME Table:5.1. Pulse Generation Formula in seven level

HMLI.

These pulses are given for eight switches. Two

conventional inverter has a S1, S2, S3, S4 and H-bridge

inverter has four pulse Sa3, Sa4, Sa5, Sa6. By using these

modulation technique to have controlled seven level

output voltage Then seven level output voltage of Hybrid

multilevel inverter is produce in asynchronous motor

drives & parameters of the motor are analysis in a output

figure 4.2.

3.2. H-BRIDGE MLI USING DEGREE

MODULATED PULSE GENERATOR (DMPG)

SWITCHING SCHEME

In seven levels H bridge MLI total eight switches and two

batteries are uses to control the output voltage. IN

multilevel inverter with unequal voltage sources are

utilize to generate same number of voltage level per

phase. The MLI consist of full bridge cell for maximum

voltage and half bridge cell for intermediate voltage.

When MLI fed an induction motor drive system, to

reduce harmonics losses and saving energy. In topology

we have generated 7 level voltage as 0V, 100V,200V and

300V.

A simulation diagram using degree modulated pulse

generator (DMPG) switching scheme of Seven-level

HMLI with asynchronous motor are shown in a figure

3.2 using MATLAB/SIMULINK.

Figure-3.2.1 Using degree modulated pulse generator

(DMPG) switching scheme of Seven-level HMLI with

asynchronous motor



3.2.1 DEGREE MODULATED PULSE

GENERATOR (DMPG) SWITCHING SCHEME

Figure 3.2.2: Simulink model for Gate driver circuit of 7

levels HMLI

The switching technique here used is degree modulated

pulse generated to identification and reference angle

generation. We have generated a switching pulse to obtain

staircase output voltage which resembles nearly equal to

sine wave. For different switching angles the power

circuit behaves defiantly producing different waveform.

To obtain equal step firing a 7 level output is divided into

equal segment.

3.3 H-BRIDGE MLI USING PHASE DISPOSITION

(PD) PWM SWITCHING SCHEME.

The simulation circuit for asymmetric cascaded 7 level

with induction motor is shown in fig 3.3.1 CHMLI 7 level

has two unequal magnitude DC sources and 8 power

switches are used.

A simulation diagram using phase disposition (PD) PWM

switching scheme of Seven-level HMLI with

asynchronous motor are shown in a figure 3.3 using

MATLAB/SIMULINK.

Figure 3.3.1: Seven-level HMLI with asynchronous

motor using phase disposition (PD) PWM switching

scheme

3.2.1 PHASE DISPOSITION (PD) PWM

SWITCHING SCHEME

Figure 3.3.2 Reference and carrier waveform for PD

Seven-level HMLI



4. SIMULATION RESULTS

Figure-4.1 Output voltage waveform for Seven-level

HMLI using hybrid mixed switching scheme

Show the above figure-4.1 MATLAB simulation result

for a seven level inverter with hybrid mixed switching

scheme. Multilevel carrier based pulse width modulation

methods are used in these inverter topologies.

Figure-4.2 FFT analysis for Seven-level HMLI using

hybrid mixed switching scheme

Fig 4.3: Motor output of seven-level HMLI using hybrid

mixed switching scheme

Figure 4.4: Output voltage of Seven-level HMLI using

degree modulated pulse generator (DMPG) switching

scheme

Show the above figure MATLAB simulation result for a

seven level inverter with equal step firing using degree

modulation switching scheme

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-400

-300

-200

-100

0

100

200

300

400

TIME (Seconds)

Magnitude in V

oltage(V

)

Output voltage wave forms in Seven Level HMLI

0 2 4 6 8 10 12 14 16 18 200

1

2

3

4

5

6

Harmonic order

Fundamental (50Hz) = 265.7 , THD= 10.59%

Mag

(%

o

f F

un

da

me

nta

l)

0 0.02 0.04 0.06 0.08 0.1

-300

-200

-100

0

100

200

300

TIME(SEC)

VO

LT

AG

E A

MP

LIT

UD

E

Output voltage of Seven-level HMLI using degree modulated pulse generator (DMPG) switching scheme





scheme

Figure-4.6: Motor output of seven-level HMLI using


scheme

Figure-4.7 Output voltage waveform for Seven-level

HMLI using phase disposition (PD) PWM switching

scheme

The output voltage waveform of 7 level CHMLI with

capacitor start run motor induction motor is shown in fig

4.7


phase disposition (PD) PWM switching scheme

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08

-200

-100

0

100

200

Selected signal: 4 cycles. FFT window (in red): 4 cycles

Time (s)

0 100 200 300 400 500 600 700 800 900 10000

5

10

15

20

Frequency (Hz)


Mag

(%

o

f F

un

dam

en

tal)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-400

-300

-200

-100

0

100

200

300

400

Output voltage waveform for Seven-level HMLI using degree modulated pulse generator (DMPG) switching scheme

TIME (SEC)

VO

LT

AG

E A

MP

LIT

UD

E

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08

-200

-100

0

100

200

Selected signal: 4 cycles. FFT window (in red): 4 cycles

Time (s)

0 100 200 300 400 500 600 700 800 900 10000

0.5

1

1.5

2

2.5

Frequency (Hz)


Mag (%

of F

undam

ental)



Figure-4.9: Motor output of seven-level HMLI using

phase disposition (PD) PWM switching scheme

Table no. 3: Steady state value for Induction Motor

HMLI

using

switching

scheme

Time to

reached

Steady

state value

of Main

winding

current

Time to

reached

Steady

state

value of

Rotor

Speed

Time to

reached Steady

state value of

Electromagneti

c Torque

THD

mixed

switching

0.25 sec 0.25 sec 0.25sec 11.53 %

degree

modulate

d

0.2 sec. 0.25 sec 0.2 sec 22.89%

phase

dispositio

n

0.2 sec. 0.2 sec. 0.2 sec. 9.76%

Table no. 4: Variation of Induction Motor Parameters

HMLI

using

switching

scheme

Main

winding

current

(Amp)

Rotor speed (

rad /sec)

Electromagnetic

Torque (Nm)

mixed

switching

6.5 151 3.8

degree

modulated

9.2 151 6.8

phase

disposition

6.7 157 4.7

All simulation results are shown in above table no. 3 and

table no. 4 respectively.

5. CONCLUSION

The paper deals with a comparison of cascaded 7 level

multilevel inverters for Asynchronous motor using

different modulation techniques i.e. phase disposition

pulse width modulation, degree modulated pulse

generator and hybrid mixed switching technique. Indeed,

asymmetrical 7 level multilevel inverter have been

compared in order to find an optimum motor speed,

torque and main winding current with lower switching

losses, Total harmonic distortion and optimized output

voltage quality. The asymmetric cascaded 7 level inverter

gives optimum motor output and reduced THD using

pulse width modulation technique. The steady state

condition of motor output has reached earlier in case of

asymmetrical cascaded 7 level inverter using pulse width

modulation (phase disposition) as compared to other

two techniques.

6. REFERENCES

1. Ankur Chourasiya, S.S Thakur, S. P. Phulambrikar, “Harmonic

Reduction in New PWM Switching Scheme of Hybrid Multilevel Inverter” International Journal of Engineering Research & Technology

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2. Nayna Bhargava, Sanjeev Gupta, S. P. Phulambrikar “Analysis of

Asymmetric Cascaded 7 level and 9 level Multilevel Inverter for Asynchronous Motor” International Journal of Engineering Research &

Technology (IJERT) ISSN:2278-0181 Vol. 3,Issue 8,August-2014.

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Efficient Novel Multilevel Inverter By Reducing Harmonics With

Reduces Number of Batteries and Switches” International Journal of Engineering Research & Technology (IJERT) ISSN:2278-0181 Vol.

3,Issue 8,August-2014.



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Modelling Of Space Vector Modulated Direct Controlled Matrix

Converter", 2005-2010 JATIT.

Ankur chourasiya - received the B.E.degree in

Electronics and communication. From the Peoples collage of research and technology, Bhopal (M.P.) India, in 2008-2012 .and M.Tech pursuing From Samrat ashok technical institute Vidisha (m.p.) India, done M Tech thesis on “Harmonic Reduced In New PWM Switching

Scheme of Hybrid Multilevel Inverter” paper publish on “Harmonic

Reduction in New PWM Switching Scheme of Hybrid Multilevel Inverter” International Journal of Engineering Research & Technology

(IJERT) ISSN: 2278-0181 Vol. 3 Issue 8, August – 2014.and “Five

level hybrid Cascaded multilevel inverter Harmonic reduced in PWM switching scheme” International journal for scientific

research & development (IJSRD) ISSN: volume 2,issue $, in oct

2014.

Poonam Chouksey recrived the B.E. degree in Electrical engineering From Indira Gandhi

Engineering collage Sager, M.P. India in 2008 to

2012.& Master of Engineering pursuing from samrat ashok technological institute, vidisha, M.P. india.

done M.E. thesis topic on “Design of Efficient

Novel Multilevel Inverter By Reducing Harmonics With Reduces Number of Batteries and Switches” and paper published

on “Design of Efficient Novel Multilevel Inverter By Reducing

Harmonics With Reduces Number of Batteries and Switches” International Journal of Engineering Research & Technology (IJERT)

ISSN:2278-0181 Vol. 3,Issue 8,August-2014.

.

Nayna Bhargava received B.E. degree in Electrical engineering from Lakshmi Narain College Of

Technology Bhopal , MP. India in 2006 to 2010 &

Master Of Engineering pursuing from Samrat Ashok Technological Institute, Vidisha, M.P. India. done

M.E. thesis topic on “Analysis of Asymmetric

Cascaded 7 level and 9 level Multilevel Inverter for Asynchronous Motor” and paper published on

“Analysis of Asymmetric Cascaded 7 level and 9 level Multilevel

Inverter for Asynchronous Motor” International Journal of Engineering Research & Technology (IJERT) ISSN:2278-0181 Vol. 3,Issue

8,August-2014.

.

Sudhir phulambrikar,,BE, M.TEC. having more then 30 years teaching experience. Has published

several papers in conferences, national and

international, He is currently working on head of electrical engineering department of Samrat ashok

technological institute Vidisha (m.p.)

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