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1
MR. IRFAN KHORAKIWALA NITESH KUMAR SINGHPRABHANSHU SHARMASHUBHAM SAHTRIVENDRA JOSHI
Multi‐level inverters are operating with low frequency and present high efficiency than PWM inverters, because of low switching losses.H‐Bridge inverter has significant advantage over other multi level inverter topologies.This project work involves the hardware implementation of two‐level cascaded inverter with the elimination of 3rd and 5th harmonics using micro‐controller (P89V51RD2).
May 12, 2013 2
To develop a system which is more efficient and cost effective ever.Project particular through us to a practical understanding of the devices and components we have studied earlier.And a chance to enhance and put our knowledge &experiences to use.
May 12, 2013 3
Initially the circuit has been simulated in MULTISIM(NI‐ National Instrumentation) software.After the successful simulation the hardware implementation is done.Fourier analysis has been made to eliminate the 3rdand 5th harmonics.The switching sequences are calculated so as to equally utilize all the MOSFETs and dc sources.
May 12, 2013 4
MOSFET (IRF630FP) is used as power switching device.
Elimination of 3rd and 5th harmonics using micro‐controller (P89V51RD2).
Opto‐coupler (4 pin DIP 817B) is used to overcome the common ground problem and also to give the sufficient gate driving voltage.
May 12, 2013 5
May 12, 2013 6
Basic schematic of two level H‐Bridge Inverter using MOSFET switch
May 12, 2013 7
+V+2V
-2V-V
0
The previous circuit can produce five different levels of output voltage. By modulating the switches correctly we can produce a stepped sine
waveform as shown in the above figure. The output voltage contains +V, +2V, 0, ‐V & ‐2V voltage levels.
May 12, 2013 8
+V+2V
-2V-V
0
Va
Vb
+V
+V
-V
-V
After the Fourier series analysis and harmonics elimination the output waveform of the system is shown in figure, i.e. voltage output Vb.
output wave of a multilevel inverter can viewed as the summation of square waves having different conducting angles.
The conducting angles a1 and a2 can be chosen such that the total harmonic distortion of the output voltage is minimized.
May 12, 2013 9
Power MOSFET IRF630FP
o Manufactured by ‘STMicroelectronics’.o An N‐Channel, 200V, 9A MOSFET.o ON‐state resistance of 0.35 W only.o Its turn‐ON time is only 34ns and its turn‐OFF time is 70ns.
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May 12, 2013 11
817B opto‐coupler in a 4‐pin dual in‐line package. Pin description is shown right above at right. The maximum Vce0 that can be applied is 70V. It can sustain a continuous collector current of 50mA. The max rise time and fall time are 18 ms at load resistance of 100W.
May 12, 2013 12
May 12, 2013 13
Step 1st : Switching timing control.Input desired voltage and connections is fed to the microcontroller 80C51.Port ‘0’ of the microcontroller is so programmed to switch the required MOSFETS in desirable conduction angles and timing.
Step 2nd : AC. Generation & Harmonics Elimination.Two different alternated switched outputs are cascaded to produce five level of voltage output.Five level AC output is being produced by switching of MOSFETS and undesirable low level harmonics has been removed.
Step 3rd : Result/Observation.The output observed at output of the second step is then fed to the CRO and the output is then observed.The observed output waveform can be seen that the lower order harmonics has been successfully eliminated.
Can be used to produce AC for home or industrial uses,(where pure SINE‐WAVE is not hardly required).
Further advancements and developments can be done.
Can be used in laboratories for research purpose.
May 12, 2013 14
May 12, 2013 15
A PROJET REPORT ON
IMPLEMENTATION OF TWO LEVEL CASCADED INVERTER
ADVANTAGES & APPLICATIONS
submitted for the partial fulfilment of the award of
Degree of Bachelor of Technology
In
Electronics & Communication Engineering
From
Uttarakhand Technical University, Dehradun
Submitted by: Under the Guidance of:
Shubham Sah 0009070102122 Mr. Irfan Khorakiwala
Nitesh Kumar Singh 0600701021051 (Lecturer)
Prabhanshu Sharma 0600701021053
Trivendra Joshi 0600701021054
Department of Electronics & Communication Engineering
Dehradun Institute of Technology
Dehradun, (May 2013)
i
IMPLEMENTATION OF TWO LEVEL CASCADED INVERTER
ADVANTAGES & APPLICATIONS
ii
Dehradun Institute of Technology
Mussoorie diversion road
Village, Makkawala
Dehradun, 248009
Department of Electronics & Communication Engineering
CERTIFICATE
This is to certify that the project work entitled “Implementation of two level cascaded
Inverter, Advantages & Applications” have carried out by Shubham Sah, Prabhanshu
Sharma, Nitesh Kumar Singh and Trivendra Joshi in partial fulfilment for the award of
Bachelor of Technology final year in Electronics & Communication Engineering from
Uttarakhand Technical University, Dehradun, under the supervision of “Mr Irfan
Khorakiwala” during the year 2012-13. It is also certified that all corrections/suggestions
mentioned in internal assessment have been incorporated in this Report submitted. The project
report has been approved as it satisfies the academic requirements in respect of Project work
prescribed for the said Degree.
Mr. Irfan Khorakiwala Mr. P.S. Sharma Mr. Sandeep Vijay
Lecturer Professor H.O.D.
Project Guide Project Co-ordinator Head of Department
iii
ACKNOWLEDGEMENT
Firstly we would like to thank Mr. Irfan Khorakiwala for his great support, knowledge sharing
and his persistent motivation throughout the project making process which helped us in
executing the work smoothly.
Further we would like to thank Mr. Sandeep Vijay (H.O.D, ECE Dept., DIT Dehradun) and
our project coordinator Mr. P.S. Sharma for their continuous support and guidance throughout
our project.
We also owe our sincere gratitude to our friends and acquaintances who helped us in different
steps and modules in our project.
Date:
Shubham Sah Prabhanshu Sharma
0009070102122 060070102153
B.Tech(ECE, 4th year) B.Tech(ECE, 4th year)
Nitesh Kumar Singh Trivendra Joshi
060070102151 060070102154
B.Tech (ECE, 4th year) B.Tech(ECE, 4th year)
iv
ABSTRACT
Multi-level inverters are operating with low frequency and present high efficiency than PWM
inverters, because of low switching losses. H-Bridge inverter has significant advantage over
other multi-level inverter topologies. It requires least number of components; optimized circuit
layout and packaging are possible. This project work involves the hardware implementation of
two-level cascaded inverter with the elimination of 3rd and 5th harmonics using micro-controller
(P89V51RD2). Initially the circuit has been simulated in MULTISIM software. After the
successful simulation the hardware implementation is done. MOSFET (IRF630FP) is used as
power switching device. Fourier analysis has been made to eliminate the 3rd and 5th harmonics.
Opto-coupler (4 pin DIP 817B) is used to overcome the common ground problem and also to
give the sufficient gate driving voltage. The switching sequences are calculated so as to equally
utilize all the MOSFETs and dc sources.
v
TABLE OF CONTENTS
CHAPTER NO. TITLE PAGE NO.
LIST OF TABLES ix
LIST OF FIGURES x
LIST OF SYMBOLS xii
1 INTRODUCTION 1
1.1 Harmonics 2
1.2 Inverter 3
1.3 Conventional Two-Level & Three-Level Voltage Source Inverter 3
1.4 PWM Techniques 5
1.5 Multi-Level Voltage Source Inverter 5
1.6 Cascaded Multi-Level Inverter 6
1.6.1 Features of cascaded inverter 6
2 CONFIGURATION AND OPERATIONAL PRINCIPLE OF PROPOSED INVERTER 7
2.1 Circuit Configuration 8
2.2 Block Diagram 9
2.3 Operation 9
3 FOURIER ANALYSIS AND HARMONICS ELIMINATION 11
3.1 Fourier Series for Periodic Function 12
3.2 Harmonics Elimination 13
3.2.1 Conduction angles calculation 14
3.3 C++ program for iteration 14
4 COMPONENT DESCRIPTION 16
4.1 POWER MOSFET 16
4.1.1 Introduction 17
4.1.1.1 Basic structure and operation 17
4.1.1.2 Switching characteristics 18
4.1.1.3 ON state resistance 18
4.1.1.4 Internal body diode 19
4.1.2 Power MOSFET IRF630 FP 19
vi
4.2 MICRO-CONTROLLER 22
4.2.1 General Description and Features 22
4.2.2 Block Diagram of P89V51RD2 22
4.2.3 Pin Configuration 23
4.2.4 Functional Description 23
4.2.4.1 Memory organization 23
4.2.4.2 Timers 0 and 1 24
4.2.4.3 Modes of operation 26
4.2.4.3.1 Mode 0 26
4.2.4.3.2 Mode 1 26
4.2.4.3.3 Mode 0 26
4.2.5 Programming 26
4.2.5.1 Switching sequence selection 26
4.2.5.2 Delay time calculation 26
4.2.5.3 Calculation of values for timer register 27
4.2.5.4 Port 0 output values 28
4.2.5.5 Program 28
4.3 OPTO-COUPLER 33
4.3.1 Introduction 33
4.3.2 Importance of Opto-Coupler 33
4.3.2.1 Common ground problem 33
4.3.2.2 Gate driving voltage 34
4.3.2.3 Opto-Coupler 817B 34
4.3.2.4 Characteristics 35
4.4 TRANSFORMER (STEP-UP) 36
4.4.1 Introduction 36
4.4.2 Induction Law 36
5 SIMULATION IN MULTISIM SOFTWARE 38
5.1 Introduction 39
5.2 Fourier Analysis Result 40
6 HARDWARE IMPLEMENTATION 42
6.1 PCB Designing 43
6.2 PCB Designing using NI- ULTIboard 47
vii
6.2.1 NI-ULTIboard 47
6.3 The Whole Setup 50
6.4 Micro-Controller 50
6.5 Circuit Setup 51
6.6 Output Waveform 51
6.7 Cost Estimation 52
7 CONCLUSION AND FUTURE ASPECTS 53
7.1 Conclusion 54
7.2 Future aspect 54
REFERENCES AND BIBLIOGRAPHY
viii
LIST OF TABLES
TABLE No TITLE PAGE No
2.1 Switching techniques for various voltage levels 10
4.1 TMOD Timer/counter control register bit allocation 24
4.2 TMOD Timer/counter control register bit description 24
4.3 TMOD Timer/counter control register M1/M0 operating mode 25
4.4 TCON Timer/counter control register bit allocation 25
4.5 TCON Timer/counter control register bit description 25
4.6 Port 0 output values 28
5.1 Magnitude of each harmonic component 41
6.7 Cost Estimation 52
ix
LIST OF FIGURES
FIGURE No. TITLE PAGE No.
1.1 Fourier series representation of a distorted waveform 2
1.2 Half-Bridge configuration 3
1.3 Full-Bridge configuration 4
1.4 Output waveform of half-bridge configuration 4
1.5 Output waveform of full-bridge configuration 4
1.6 A sinusoidal PWM waveform 5
1.7 Schematic of multi-level inverter by a switch 5
1.8 Typical output voltage of a three-level multilevel inverter 5
1.9 Single-phase multilevel cascaded H-bridge inverter 6
2.1 Typical two-level inverter 8
2.2 Block diagram of H-Bridge cascaded inverter 9
2.3 Output waveform 9
3.1 Waveform of 2-level inverter 13
3.2 Output of the program 14
4.1 n-channel enhancement type MOSFET 17
4.2 Transfer characteristics of n-channel enhancement MOSFET 17
4.3 Switching waveforms and times 18
4.4 MOSFET internal body diode 19
4.5 MOSFET IRF630 FP 19
4.6 Internal Schematic diagram 18
4.7 Output characteristics 20
4.8 Transfer characteristics 20
4.9 Static Drain-Source ON resistance characteristics 21
4.10 Block diagram of P89V51RD2 22
4.11 Pin configuration of P89V51RD2 23
4.12 Switching sequence 27
4.13 Output waveform of port 0, pins 0-7, from top to down 31
4.14 ON and OFF pulses to the opto-coupler 32
4.15 Opto-coupler 33
4.16 Common ground 33
x
4.17 Signal coupling using opto-coupler 34
4.18 817B opto-coupler in a 4-pin dual in-line package 34
4.19 Pin description 34
4.20 Forward voltage vs. forward current 35
4.21 Collector current vs. collector emitter voltage 35
4.22 Primary and secondary winding turn ratio.. 36
4.23 Schematic of primary and secondary windings and core.. 37
5.1(a) NI-MULTISIM 39
5.1(b) Circuit Simulation in MULTISIM 40
5.2 Fourier analysis – Magnitude of each component 40
6.1 PCB dipped in FeCl3 Solution 45
6.2 Impression developed after some time 45
6.3 PCB drilling 46
6.4 NI-ULTIboard circuit PCB layout 47
6.5 Optocoupler Unit circuit PCB layout Design 48
6.6 Mirrored Impression for etching process 49
6.7 3-D View of Optocoupler Unit 49
6.8 The whole setup of the project 50
6.9 Micro-controller 50
6.10 Circuit setup 51
6.11 Output waveform 51
xi
LIST OF SYMBOLS
PWM - Pulse Width Modulation
MOSFET - Metal Oxide Semiconductor Field Effect Transistor
dc - Direct current
ac - Alternating current
THD - Total Harmonic Distortion
rms - root mean square
SDCS - Separate DC Source
VGS - Gate to Source voltage
td(on) - Turn-on delay time
tr - rise time
td(off) - Turn-off delay time
tf - rise time
VT - Threshold voltage
RDS(on) - ON state resistance
VDS - Drain to Source voltage
ID - Drain current
kB - kilo byte
TTL - Transistor-Transistor Logic
CMOS - Complementary MOSFET
EMI - Electromagnetic Interference
ALE - Address Latch Enable
RAM - Random Access Memory
LED - Light Emitting Diode
IEEE - Institute of Electrical and Electronics Engineers
IEC - International Electrotechnical Commission
1
CHAPTER 1
INTRODUCTION
2
CHAPTER 1
INTRODUCTION
1.1 HARMONICS
Presence of harmonics in power system causes various problems; especially the low frequency
harmonics reduce the overall efficiency of the system to a greater extent. Fourier transformation is applied in
harmonic analysis. Any periodic waveform can be shown to be the super position of a fundamental and a set
of harmonic components. By applying Fourier transformation, magnitude of these components can be known.
The frequency of each harmonic component is an integral multiple of its fundamental.
Fig 1.1 Fourier series representation of a distorted waveform Normally to eliminate the harmonics, filters are used. When the order of harmonics decreases, size of
the filter increases. When size of the filter increases, it occupies more space and sometimes it needs cooling
system and also it becomes costly. So it is important to eliminate the low frequency harmonics. There are
several methods to indicate the quantity of harmonics content. The most widely used measure is the total
harmonic distortion (THD), which is defined in terms of the amplitudes of the harmonics; Mh. THD is a
measure of the effective value of the harmonic components of a distorted waveform. That is, it is the potential
heating value of the harmonics relative to the fundamental.
(1.1)
50 Hz(h = 1)
150 Hz(h = 3)
250 Hz(h = 5)
350 Hz(h = 7)
450 Hz(h = 9)550 Hz(h = 11)
650 Hz(h = 13)
3
where Mh is the rms value of harmonic component h of the quantity M.
1.2 INVERTER
Dc-to-ac converters are known as inverters. The function of an inverter is to change a dc input voltage
to a symmetric output voltage of desired magnitude and frequency. The output voltage waveforms of ideal
inverters should be sinusoidal. However the waveforms of practical inverters are non-sinusoidal and contain
certain harmonics. Generally the inverters can be classified into two types,
1) Voltage source inverters
2) Current source inverters.
Multi-level inverter falls under the category of voltage source inverter.
1.3 CONVENTIONAL TWO-LEVEL AND THREE-LEVEL VOLTAGE
SOURCE INVERTER
A half-bridge is the simplest topology, which is used to produce a two-level square wave output
waveform. A center-tapped voltage source supply is needed in such a topology. It may be possible to use a
simple supply with two-well matched capacitors in series to provide the center tap. The full-bridge topology is
used to synthesize a three level square-wave output waveform. The half-bridge and full-bridge configurations
of the single-phase voltage-source inverter are shown in Fig. 1.2 and 1.3 respectively.
In a single-phase half-bridge inverter, only two switches are needed. To avoid short-through fault, both
switches are never turned on at the same time. S+ is turned on and S- is turned off to give a load voltage, vo in
Fig. 1.2 of +vi/2. To complete one cycle, S+ is turned off and S- is turned on to give a load voltage of –vi/2.
Fig 1.2 Half-Bridge configuration
In full-bridge configuration, turning on S1+ and S2- and turning off S2+ and S1- give a voltage of vi
between point A and B (vo), in Fig. 1.3, while turning off S1+ and S2- and turning on S2+ and S1- give a
voltage of -vi. To generate zero level in a full bridge inverter, the combination can be S1+ and S2+ ON while
4
S1- and S2- OFF or vice verse. Note that S1+ and S1-should not be closed at the same time, nor should S2+
and S2-. Otherwise, a short circuit would exist across the source.
Fig 1.3 Full-Bridge configuration
The output waveforms of half-bridge and full-bridge of single-phase voltage source inverter are shown
in fig 1.4 and 1.5 respectively.
Fig 1.4 Output waveform of half-bridge configuration
Fig 1.5 Output waveform of full-bridge configuration
5
1.4 PWM TECHNIQUES
To obtain a quality output voltage or a current waveform with a minimum amount of ripple content,
they require high-switching frequency along with various pulse-width modulation (PWM) strategies. PWM
techniques have some limitations in operating under high frequencies mainly due to switching losses and
constraints of device ratings.
Fig 1.6 A sinusoidal PWM waveform
1.5 MULTI-LEVEL VOLTAGE SOURCE INVERTER
Fig 1.7 Schematic of multi-level inverter by a switch
The general structure of the multi-level inverter is to synthesize a near sinusoidal waveform from
several levels of dc voltages. As the number of levels increases, the synthesized output waveform has more
steps, which produces a staircase wave that approaches a desired waveform. Also, as more steps are added to
the waveform, the harmonic distortion of the output waveform decreases.
Fig 1.8 Typical output voltage of a three-level multilevel inverter
6
1.6 CASCADED MULTI-LEVEL INVERTER
A cascaded multilevel inverter consists of a series of H-Bridge (single-phase, full-bridge) inverter
units. The general function of this multilevel inverter is to synthesize a desired voltage from several separate
dc sources (SDCSs), which may be obtained from batteries, fuel cells, or solar cells. Fig 1.8 shows the basic
structure of a single-phase cascaded inverter with SDCSs. Each SDCS is connected to an H-Bridge inverter.
The ac terminal voltages of different level inverters are connected as series.
Fig 1.9 Single-phase multilevel cascaded H-bridge inverter
1.6.1 Features of Cascaded Inverter
The main features are as follows:
The cascaded inverters need separate dc sources. The structure of separate dc sources is well suited for
various renewable energy sources such as fuel cell, photovoltaic and biomass.
It requires least number of components relatively.
Optimized circuit layout and packaging are possible because each level has the same structure.
7
CHAPTER 2
CONFIGURATION AND OPERATIONAL PRINCIPLE OF
PROPOSED INVERTER
8
CHAPTER 2
CONFIGURATION AND OPERATIONAL PRINCIPLE OF
PROPOSED INVERTER
2.1 CIRCUIT CONFIGURATION
Fig 2.1 Typical two-level inverter
A typical two-level H-Bridge cascaded inverter is shown in the above fig 2.1. It has two separate
voltage sources V1 & V2 and eight power electronic switches. The desired output waveform as shown in the
fig 2.2 can be produced by correctly switching on and off the appropriate switches at correct instants.
9
2.2 BLOCK DIAGRAM
Fig 2.2 Block diagram of H-Bridge Cascaded Inverter Circuitry
2.3 OPERATION
This circuit can produce five different levels of output voltage. By modulating the switches correctly
we can produce a stepped sine waveform as shown in the fig 2.2. The output voltage contains +V, +2V, 0, -V
& -2V voltage levels.
To produce +V, we can either use V1 as voltage source or V2 as voltage source. If V1 is used, switches
S1S4S5S6 or S1S4S7S8 should be closed. If V2 is used as voltage source, switches S1S2S5S8 or S3S4S5S8
should be closed.
+V+2V
-2V-V
0
Fig 2.3 Output waveform
To produce +2V, both the voltage sources should be connected in series. So switches S1S4S5S8 are
closed.
To produce 0V, the load should be short-circuited. We have four switching options to short the load.
Closing of S1S2S5S6 or S1S2S7S8 or S3S4S5S6 or S3S4S7S8 switches short circuit the load.
10
To produce -V, we can either use V1 as voltage source or V2 as voltage source. If V1 is used, switches
S2S3S5S6 or S2S3S7S8 should be closed. If V2 is used as voltage source, switches S1S2S6S7 or S3S4S6S7
should be closed.
To produce -2V, both the voltage sources should be connected in series. So switches S2S3S6S7 are
closed.
The switching sequences must be selected in such a way that both the sources are equally utilized and
also all the eight devices are equally used.
Table 2.1 Switching techniques for various voltage levels
Voltage level S1 S2 S3 S4 S5 S6 S7 S8
+V (V1)
1
1
0
0
0
0
1
1
1
0
1
0
0
1
0
1
+V (V2)
1
0
1
0
0
1
0
1
1
1
0
0
0
0
1
1
+2V 1 0 0 1 1 0 0 1
0V
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
-V (V1)
0
0
1
1
1
1
0
0
1
0
1
0
0
1
0
1
-V (V2) 1
0
1
0
0
1
0
1
0
0
1
1
1
1
0
0
-2V 0 1 1 0 0 1 1 0
11
CHAPTER 3
FOURIER ANALYSIS AND HARMONICS ELIMINATION
12
CHAPTER 3
FOURIER ANALYSIS AND HARMONICS ELIMINATION
3.1 FOURIER SERIES FOR PERIODIC FUNCTION
Under steady-state condition, the output voltage of power converters is, generally, a periodic function of time
defined by
vo(t) = vo (t + T) (3.1)
where T is the periodic time. If f is the frequency of the output voltage in hertz, the angular frequency is
= 2 /T = 2f (3.2)
and Eq.(3.1) can be rewritten as
vo(t) = vo (t +2 ) (3.3)
The Fourier theorem states that a periodic function vo(t) can be described by a constant term plus an infinite
series of sine and cosine terms of frequency n where n is an integer. Therefore, vo(t) can be expressed as
vo(t)= a0ancos nt + bnsin nt
n varies from 1 to infinity
where a0/2 is the average value of the output voltage . The constants a0, an and bn can be determined from the
following expressions:
a 0 = 1
(3.5)
a n = 1
(3.6)
b n = 1
(3.7)
If the output voltage has a half-wave symmetry, the number of integrations within the entire
period can be reduced significantly. A waveform has the half-wave symmetry if the waveform satisfies the
following condition:
vo(t) = -vo (t + ) (3.8)
In a waveform with a half-wave symmetry, the negative half-wave is a mirror image of the
positive half-wave, but phase shifted by T/2 s (or rad) from the positive half-wave. A waveform with a half-
wave symmetry does not have the even harmonics (i.e., n = 2,4,6, … ) and possess only the odd harmonics
(i.e., n = 1,3,5, …. ). Due to the half-wave symmetry, the average value is zero (i.e., a0 = 0). Moreover if the
wave is symmetric about y-axis, it contains only cosine terms (i.e., bn = 0) and if the wave is anti-symmetric, it
contains only sine terms (i.e., an = 0).
13
3.2 HARMONICS ELIMINATION
+V+2V
-2V-V
0
Va
Vb
+V
+V
-V
-V
Fig 3.1 Waveform of 2-level inverter
As shown in the fig 3.1, the output wave of a multilevel inverter can viewed as the summation
of square waves having different conducting angles.
vo(t) = va(t) + vb(t) (3.9)
Due to the quarter-wave symmetry along the x-axis, both Fourier coefficients a0 and an are
zero. We get bn as
(3.10)
(3.11)
which gives the instantaneous voltage von(t) of nth component as
(3.12)
The conducting angles a1 and a2 can be chosen such that the total harmonic distortion of the output
voltage is minimized. These angles are normally chosen so as to cancel some predominant lower frequency
harmonics. Here the conducting angles should be chosen so as to eliminate the 3rd and 5th harmonics. So we
must solve the following equations.
cos 31 + cos 32 = 0 (3.13)
cos 51 + cos 52 = 0 (3.14)
14
3.2.1 Conduction angles calculation
Rearrange the equations 3.13 & 3.14; we can get the following equations,
2=cos-1(-cos(3*1)))/3; (3.15)
1=cos-1(-cos(5*2)))/5; (3.16)
Initially the simple gauss-siedel iteration method is used to solve the above equations. But iteration
starts oscillating between two values. So a slight change is introduced in the normal iteration procedure. A
simple C++ program is developed to solve the above equations.
3.2.1.1 C++ Program for iteration
#include<conio.h>
#include<iostream.h>
#include<math.h>
void main()
float a1,a2,a11,a22;
clrscr();
cout<<"\n\tGIVE THE INITIAL GUESS\n\t";
cin>>a1;
cout<<"\n\t a1"<<"\t\t"<<" a2\n\n";
while((a1!=a11)&&(a2!=a22))
a11=a1;
a22=a2;
a2=(acos(-cos(3*a1)))/3;
a1=(acos(-cos(5*a2)))/5;
cout<<"\t"<<a1<<" \t"<<a2<<"\n";
a1=(a11+a1)/2;
getch();
Output:
15
Fig 3.2 Output of the program
1 = 0.20944 rad = 120 (3.17)
2 = .837758 rad = 480 (3.18)
Thus the conducting angles are successfully found.
16
CHAPTER 4
COMPONENT DESCRIPTION
17
CHAPTER 4
COMPONENT DESCRIPTION
4.1 POWER MOSFET
4.1.1 INTRODUCTION
A power MOSFET is a voltage-controlled device and requires only a small input current. The
switching speed is very high and the switching times are of the order of nanoseconds. Power MOSFETs find
increasing applications in low-power high-frequency converters. MOSFETs do not have problem of second
breakdown phenomena as do BJTs. However, MOSFETs have the problems of electrostatic discharge and
require special care in handling.
4.1.1.1 Basic structure and Operation
Fig 4.1 n-channel enhancement type MOSFET
The two types of MOSFETs are 1) depletion MOSFETs and 2) enhancement MOSFETs. The
gate is isolated from the channel by a thin oxide layer. The three terminals are called gate, drain, and source.
An n-channel enhancement-type MOSFET has no physical channel, as shown in fig 4.1. If VGS is positive, an
induced voltage attracts the electrons in the p-layer and accumulates them at the surface beneath the oxide
layer. If VGS is greater than or equal to a value known as threshold voltage VT, a sufficient number of electrons
are accumulated to form a virtual n-channel and the current flows from the drain to source. The polarities of
VDS, IDS, and VGS are reversed for a p-channel enhancement type MOSFET.
Fig 4.2 Transfer characteristics of n-channel enhancement-type MOSFET
18
4.1.1.2 SWITCHING CHARACTERISTICS
Without any gate signal, an enhancement-type MOSFET may be considered as two diodes
connected back to back or as an NPN-transistor. The gate structure has parasitic capacitances to the source,
Cgs, and to the drain, Cgd. The npn-transistor has a reverse-bias junction from the drain to the source and offers
a capacitance, Cds.
Fig 4.3 Switching waveforms and times
The typical switching waveforms and times are shown in fig. 4.3. the turn-on delay time td(on)
is the time that is required to charge the input capacitance to threshold voltage level. The rise time tr is the
gate-charging time from the threshold level to the full gate voltage Vg, which is required to drive the
MOSFET into the saturated region. The turn off time delay td(off) is the time required for the input capacitance
to discharge from the overdrive gate voltage to the pinch-off region. VGS must decrease significantly before
VDS begins to rise. The fall time tf is the time that is required for the input capacitance to discharge from the
pinch-off region to threshold voltage. If VGS<VT, the transistor turns off.
4.1.1.3 ON state resistance
When the MOSFET is in the on-state, the channel of the device behaves like a constant
resistance RDS(on) that is linearly proportional to the change between vDS and iD as given by the following
relation:
(4.1)
The total conduction (on-state) power loss for a given MOSFET with forward current ID and
on-resistance RDS(on) is given by
(4.2)
19
The value of RDS(on) can be significant and varies between tens of milliohms and a few ohms
for low-voltage and high-voltage MOSFETS, respectively. The on-state resistance is an important data sheet
parameter, because it determines the forward voltage drop across the device and its total power losses.
4.1.1.4 Internal body diode
The modern power MOSFET has an internal diode called a body diode connected between the
source and the drain as shown in Fig. 4.4. This diode provides a reverse direction for the drain current,
allowing a bidirectional switch implementation.
Fig 4.4 MOSFET internal body diode
4.1.2 MOSFET IRF630 FP
Fig 4.5 MOSFET IRF630 FP
The MOSFET, which we are using now, is IRF630FP. It is manufactured by
‘STMicroelectronics’. It is an N-Channel, 200V, 9A MOSFET. It has an ON-state resistance of 0.35
only
It has good switching characteristics. Its turn-ON time is only 34ns and its turn-OFF time is
70ns.
Fig 4.6 Internal Schematic diagram
1. Gate 2. Drain 3. Source
20
Fig 4.7 Output characteristics
Fig 4.8 Transfer characteristics
21
Fig 4.9 Static Drain-Source ON resistance characteristics
The maximum VGS allowed is 20V. To turn ON the device, 9V is applied as gate to source
voltage using a battery.
22
4.2 MICRO-CONTROLLER
4.2.1 GENERAL DESCRIPTION AND FEATURES
The micro-controller is used here to create accurate on, off pulses for all the eight MOSFETs.
Using a micro-controller for generating the switching sequence is very advantageous in many aspects. It is
very compact, occupies very less space, allows reprogramming of time-delays, and is very reliable.
The P89V51RD2 is an 80C51 microcontroller with 64 kB Flash and 1024 bytes of data RAM.
Some features of P89V51RD2:
5 V Operating voltage from 0 to 40 MHz
Three 16-bit timers/counters
TTL- and CMOS-compatible logic levels
Low EMI mode (ALE inhibit)
Four 8-bit I/O ports
It is plastic dual in-line package. It has 40 pins.
4.2.2 BLOCK DIAGRAM OF P89V51RD2
The block diagram gives the architecture of micro-controller. The diagram is self-explanatory.
Fig 4.10 Block diagram of P89V51RD2
23
4.2.3 PIN CONFIGURATION
Fig 4.11 Pin configuration of P89V51RD2
4.2.4 FUNCTIONAL DESCRIPTION
4.2.4.1 Memory organization
24
The device has separate address spaces for program and data memory. There are two internal
flash memory blocks in the device. We use only the Block 0. It has 64 kB and contains the user’s code. The
data RAM has 1024 bytes of internal memory. The device can also address up to 64 kB for external data
memory.
4.2.4.2 Timers 0 and 1
The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured to operate
either as timers or event counters. In the ‘Timer’ function, the register is incremented every machine cycle. A
machine cycle consists of six oscillator periods. Timer 0 and Timer 1 have four operating modes from which
to select.
Control bits C/T in the Special Function Register TMOD select the ‘Timer’ or ‘Counter’
function. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in
TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating
modes are described in the table 5.1 and 5.2.
Table 4.1 TMOD Timer/counter control register bit allocation
Table 4.2 TMOD Timer/counter control register bit description
Table 4.3 TMOD Timer/counter control register M1/M0 operating mode
25
Table 4.4 TCON Timer/counter control register bit allocation
Table 4.5 TCON Timer/counter control register bit description
26
4.2.4.3 Modes of operation
4.2.4.3.1 Mode 0
In the mode 0 timer register is configured as a 13-bit register. The 13-bit register consists of all
8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored.
Setting the run flag (TRn) does not clear the registers. Mode 0 operation is the same for Timer 0 and Timer 1.
There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
4.2.4.3.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are
used.
4.2.4.3.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload; Mode 2
operation is the same for Timer 0 and Timer 1.
4.2.5 PROGRAMMING
4.2.5.1 Switching sequence selection
Switching sequence should be selected so as to equally utilize both the voltage sources and to
equally use all the eight MOSFETs. The switching sequence is shown in fig. The MOSFETs are equally used,
that is, four times per cycle.
+V+2V
-2V-V
0V1
V1V2 V2
V1 V1
V2
V2
1, 4, 5, 6 - 1, 4, 5, 81, 2, 5, 81, 2, 5, 6
V - V + V - V - 0V
1
1 2
2
2, 3, 7, 8 - (-2, 3, 6, 73, 4, 6, 73, 4, 7, 8
V )- (-V ) + (-V ) - (-V ) - 0V
1
1 2
2
MOSFETs switched ON:
Fig 4.12 Switching sequence
4.2.5.2 Delay time calculation
1. Time gap for +V output:
t1=((2-1)/360)*20 ms
=((48-12)/360)*20 ms
=2 ms
27
2. Time gap for +2V output:
t2=(((180-36-1)-2)/360)*20 ms
=(((180-36-12)-48)/360)*20 ms
=4.6667 ms
3. Time gap for 0V output:
t3=(21/360)*20 ms
=(24/360)*20 ms
=1.3333 ms
Since the waveform is half-wave symmetry and also quarter-wave with respect to x-axis, time gap for
other voltage levels can be easily calculated.
4. Time gap for -V output:
t -1 = t1
= 2 ms
5. Time gap for -2V output:
t -2 = t2
= 4.6667 ms
5.5.3 Calculation of values for timer register
‘Timer 0’ is used in 16-bit mode. The clock frequency used in micro-controller is 11.0592
MHz. The micro-controller is used with 12-clock rate, i.e., 12 clocks per machine cycle.
Therefore, to execute a one-machine cycle instruction, it takes,
(1/11.0592)*12 = 1.085 s
The decrementing operation in timer needs one machine cycle. Therefore the value to be stored
in the timer register can be calculated as follows,
c1 = (2/1.085)*1000
= 1843 cycles = 733H cycles
T1 = FFFFH-733H = F8CC H
c2 = (4.6667/1.085)*1000
= 4301 cycles = 10CDH cycles
T2 = FFFFH-10CDH = EF32 H
c3 = (1.3333/1.085)*1000
= 1288 cycles = 508H cycles
T3 = FFFFH-508H = FAF7 H
28
For all the above values, last 30 to 90 cycles, of the output of port 0 is maintained at zero to
avoid short-through problem, because of switching delay in opto-coupler and MOSFET.
4.2.5.4 Port 0 output values
Since all the outputs are taken from port 0, it is unable to drive the opto-coupler. To avoid this
problem, anode is connected to the source voltage of micro-controller and cathode is connected to the ports.
So, to drive an opto-coupler LED, the port pin should be at 0-level not at 1-level. The port 0 output values are
calculated based on the above idea.
Table 4.6 Port 0 output values
S8 S7 S6 S5 S4 S3 S2 S1 Port 0 output value
1 1 0 0 0 1 1 0 C6H
0 1 1 0 0 1 1 0 66H
0 1 1 0 1 1 0 0 6CH
1 1 0 0 1 1 0 0 CCH
0 0 1 1 1 0 0 1 39H
1 0 0 1 1 0 0 1 99H
1 0 0 1 0 0 1 1 93H
0 0 1 1 0 0 1 1 33H
4.2.5.5 Program
Device: P89V51RD2
ORG 0H;
MOV TMOD,#01;
CLR TF0; HERE: MOV A,#0C6H;
MOV P0,A;
MOV TL0,#0FCH;
MOV TH0,#0F8H;
ACALL DELAY;
MOV A,#0FFH;
MOV P0,A;
MOV TL0,#0E1H;
29
MOV TH0,#0FFH;
ACALL DELAY;
MOV A,#66H;
MOV P0,A;
MOV TL0,#8FH;
MOV TH0,#0EFH;
ACALL DELAY;
MOV A,#0FFH;
MOV P0,A;
MOV TL0,#0E1H;
MOV TH0,#0FFH;
ACALL DELAY;
MOV A,#6CH;
MOV P0,A;
MOV TL0,#0FCH;
MOV TH0,#0F8H;
ACALL DELAY;
MOV A,#0FFH;
MOV P0,A;
MOV TL0,#0EBH;
MOV TH0,#0FFH;
ACALL DELAY;
MOV A,#0CCH;
MOV P0,A;
MOV TL0,#23H;
MOV TH0,#0FBH;
ACALL DELAY;
MOV A,#0FFH;
MOV P0,A;
MOV TL0,#0EBH;
MOV TH0,#0FFH;
ACALL DELAY;
MOV A,#39H;
MOV P0,A;
MOV TL0,#0FCH;
MOV TH0,#0F8H;
ACALL DELAY;
30
MOV A,#0FFH;
MOV P0,A;
MOV TL0,#0E1H;
MOV TH0,#0FFH;
ACALL DELAY;
MOV A,#99H;
MOV P0,A;
MOV TL0,#6AH;
MOV TH0,#0EFH;
ACALL DELAY;
MOV A,#0FFH;
MOV P0,A;
MOV TL0,#0E1H;
MOV TH0,#0FFH;
ACALL DELAY;
MOV A,#93H;
MOV P0,A;
MOV TL0,#0FCH;
MOV TH0,#0F8H;
ACALL DELAY;
MOV A,#0FFH;
MOV P0,A;
MOV TL0,#0EBH;
MOV TH0,#0FFH;
ACALL DELAY;
MOV A,#33H;
MOV P0,A;
MOV TL0,#25H;
MOV TH0,#0FBH;
ACALL DELAY;
MOV A,#0FFH;
MOV P0,A;
MOV TL0,#0EBH;
MOV TH0,#0FFH;
ACALL DELAY;
LJMP HERE;
31
DELAY:
SETB TR0;
AGAIN: JNB TF0,AGAIN;
CLR TR0;
CLR TF0;
RET;
END
The above program is simulated in ‘keil u-vision’ software. The output waveform for each pin
of port 0 is shown in fig 5.6
Fig 4.13 Output waveform of port 0, pins 0-7, from top to down
The fig 4.13 shows the actual ON and OFF time pulses to the opto-coupler.
32
Fig 4.14 ON and OFF pulses to the opto-coupler
33
4.3 OPTO-COUPLER
4.3.1 INTRODUCTION
Opto-coupler is nothing but a combination of LED and a phototransistor. It provides optical
coupling between input and output. The input side has a LED. It emits photons, when it is forward biased. The
output side has a phototransistor. When the emitted photons hit the phototransistor, it induces the base current
to flow. The transistor is switched on. When the LED is not forward biased, the transistor remains in off state.
Fig 4.15 Opto-coupler
4.3.2 IMPORTANCE OF OPTO-COUPLER
Opto-coupler is used to solve two main problems. One is common ground problem, which
arises because of MOSFETs, which need individual signal grounds. Second problem is the gate driving
voltage of MOSFET.
4.3.2.1 Common ground problem
When the signal is directly given from micro-controller, the ‘source’ of all MOSFETs should
be commonly grounded to the micro-controller ground. It makes some MOSFETs permanently shorted as
shown in fig 6.2. To avoid this problem opto couplers are used. Each phototransistor is driven by individual dc
supply.
Fig 4.16 Common ground
The common ground problem eliminated circuit is shown in fig 6.3
34
V1
9Vdc
U1PS25011
2
3
4
R1
10k
U1PS25011
2
3
4
0
Q3IRF630/TO
0
V1
9Vdc
R1
10k
Q4IRF630/TO
Fig4.17 Signal coupling using opto-coupler
4.3.2.2 Gate driving voltage
The driving voltage from micro-controller is only 5V. It is not sufficient to drive a power
MOSFET IRF630. The usage of opto-coupler paves the way to increase the gate driving voltage. A 9V dc
source is used to drive the gate of the MOSFET. It is shown in fig 6.3.
4.3.3 OPTO-COUPLER 817B
Fig 4.18 817B opto-coupler in a 4-pin dual in-line package
Fig 4.19 Pin description
35
It consists of a gallium arsenide infrared emitting diode driving a silicon phototransistor. It is in
dual in-line package as shown in fig 6.4 and pin description is shown in fig 6.5.
4.3.3.1 Characteristics
The maximum Vce0 that can be applied is 70V. It can sustain a continuous collector current of
50mA. The maximum rise time and fall time are 18 s at the load resistance of 100
Fig 4.20 Forward voltage vs. forward current
Fig4.21 Collector current vs. collector emitter voltage
36
4.4 TRANSFORMER
4.4.1 Introduction
A transformer is a static electrical device that transfers energy by inductive coupling between its winding
circuits. A varying current in the primary winding creates a varying magnetic flux in the transformer's core
and thus a varying magnetic flux through the secondary winding. This varying magnetic flux induces a
varying electromotive force (emf) or voltage in the secondary winding. Transformers range in size from
thumbnail-sized used in microphones to units weighing hundreds of tons interconnecting the power grid. A
wide range of transformer designs are used in electronic and electric power applications. Transformers are
essential for the transmission, distribution, and utilization of electrical energy.
Fig 4.22 Primary and secondary winding turn ration and voltage formula
4.4.2 Induction law
The transformer is based on two principles: first, that an electric current can produce a magnetic field and
second that a changing magnetic field within a coil of wire induces a voltage across the ends of the coil
(electromagnetic induction). Changing the current in the primary coil changes the magnetic flux that is
developed. The changing magnetic flux induces a voltage in the secondary coil.
Referring to the two figures here, current passing through the primary coil creates a magnetic field. The
primary and secondary coils are wrapped around a core of very high magnetic permeability, usually iron, so
that most of the magnetic flux passes through both the primary and secondary coils. Any secondary winding
connected load causes current and voltage induction from primary to secondary circuits in indicated
directions.
37
Fig 4.23: Schematic of primary and secondary windings and core with flux density
Ideal transformer and induction law. The voltage induced across the secondary coil may be calculated from
Faraday's law of induction, which states that:
where Vs = Es is the instantaneous voltage, Ns is the number of turns in the secondary coil, and dΦ/dt is the
derivative[d] of the magnetic flux Φ through one turn of the coil. If the turns of the coil are oriented
perpendicularly to the magnetic field lines, the flux is the product of the magnetic flux density B and the area
A through which it cuts. The area is constant, being equal to the cross-sectional area of the transformer core,
whereas the magnetic field varies with time according to the excitation of the primary. Since the same
magnetic flux passes through both the primary and secondary coils in an ideal transformer,[6] the instantaneous
voltage across the primary winding equals
Taking the ratio of the above two equations gives the same voltage ratio and turns ratio relationship shown
above, that is,
.
The changing magnetic field induces an emf across each winding. [8] The primary emf, acting as it does in
opposition to the primary voltage, is sometimes termed the counter emf.[9] This is in accordance with Lenz's
law, which states that induction of emf always opposes development of any such change in magnetic field. As
still lossless and perfectly-coupled, the transformer still behaves as described above in the ideal transformer.
38
CHAPTER 5
SIMULATION IN MULTISIM SOFTWARE
39
CHAPTER 5
SIMULATION IN MULTISIM SOFTWARE
5.1 INTRODUCTION
MULTISIM is user-friendly simulation software. The entire circuit is simulated in
MULTISIM. But the exact components are unavailable in MULTISIM. So the components are chosen such
that their characteristics are almost similar to the originally used components.
Fig 5.1(a) NI-MULTISIM (National Instrumentation Multisimulator 11.0) Simulation Circuitry.
40
V112 V
XSC1
A B
Ext Trig+
+ _
_ + _
V212 V
17
U1
8051
P1B0T2 1 P1B1T2EX 2 P1B2 3 P1B3 4 P1B4 5 P1B5MOSI 6 P1B6MISO 7 P1B7SCK 8 RST 9 P3B0RXD 10 P3B1TXD 11 P3B4T0 14 P3B5T1 15 XTAL2 18 XTAL1 19 GND 20 P2B0A8 21 P2B1A9 22 P2B2A10 23 P2B3A11 24 P2B4A12 25 P2B5A13 26 P2B6A14 27 P2B7A15 28
P0B7AD7 32 P0B6AD6 33 P0B5AD5 34 P0B4AD4 35 P0B3AD3 36 P0B2AD2 37 P0B1AD1 39 P0B0AD0 38 VCC 40
P3B2INT0 12 P3B3INT1 13 P3B6WR 16 P3B7RD 17
PSEN 29 ALEPROG 30 EAVPP 31
2
VCC 5V
VCC
Q2IRF530
Q3IRF530
Q4IRF530
Q5IRF530
Q1IRF530
Q6IRF530
Q7IRF530
Q8IRF530
V3
9 V R410k
U3
PS2561-1 2
1
3
4 5 V5
9 V R2 10k
U2
PS2561-12
1
3
4 8
V6
9 V R3 10k
U4
PS2561-12
1
3
4 15V7
9 V R510k
U5
PS2561-12
1
3
4 20
V8
9 V R610k
U6
PS2561-1 2
1
3
4 23
V9
9 V R710k
U7
PS2561-1 2
1
3
4 26
V10
9 V R810k
U8
PS2561-1 2
1
3
4 29 V11
9 V R9 10k
U9
PS2561-1 2
1
3
4 32
7 14
2219
4
25
9 28
3134
18
0
6
R1100
24
0
R12 500
10
R13
500
R14 500
11R15
50012
R16 500
13
R17
50016
R18
50021
R19
500
27
30
33
35
36 37
38
39
40 41
Fig 5.1(b) Circuit simulated in MULTISIM
5.2 FOURIER ANLAYSIS RESULT
The Fourier analysis has been done in the output (stepped) waveform using MULTISIM software.
Fig 5.2 Fourier analysis – Magnitude of each component
41
Table 5.1 Magnitude of each harmonic component
From the above table 6.1 the harmonics dominating are 7, 11, 13, 17, 19, etc.
42
CHAPTER 6
HARDWARE IMPLEMENTATION
43
CHAPTER 6
HARDWARE IMPLEMENTATION
6.1 PCB Designing
PCB Designing Steps
A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic
components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto
a non-conductive substrate. It is also referred to as printed wiring board (PWB) or etched wiring board.
This unit introduces the process of developing a Printed Circuit Board (PCB).
Objectives
• Expose the photoresist of a PCB using a circuit mask and Ultraviolet Light
• Develop the exposed PCB with photoresist developer
• Etch a developed PCB
• Prepare the PCB for use and drill the PCB
• Solder electronic components onto a PCB
Materials List
• Unexposed printed circuit board (positive photoresist PCB)
• Approximately 50 grams of developing solution
• Approximately 100 grams of dry concentrated etchant (Ferric Chloride)
• Circuit transparency mask
Tools List
• UV exposer setup
• Drill with appropriate drill bit
• Soldering iron and solder
• A medium strength scrub pad
• Plastic (preferred) or glass container large enough to immerse the PCB
• Glass stirrer
Safety Precautions
ALWAYS wear rubber gloves, a disposable apron and eye goggles when developing and etching the
board. Follow all instructions on the chemical packages.
The Job
The unexposed PCB should be kept in its packet until it is ready to be exposed. Make sure all your
equipment is clean before starting the UV expose positive photoresist PCB.
1) Prepare the UV exposer for use; make sure there is as little light as possible in the room.
44
2) When you are ready to expose the unexposed PCB.
3) Set the unexposed PCB down on the UV exposer, taking care not to touch the copper side of the
board, and place the circuit trace on top of the PCB. Make sure the circuit trace is oriented correctly and
not upside down.
4) Close the UV exposer and turn the UV light on.
5) At exactly 10 minutes, turn off the UV light and open the UV exposer.
Develop an exposed PCB with PCB Developer
1) Put on your rubber gloves, disposable apron and eye goggles.
2) Pour 1,000 ml. of warm water (25 - 30oC) into the plastic container.
3) Pour the developing solution into the plastic container and stir it with the glass stirrer until there are
no more solid’s left in the container.
4) Remove the exposed PCB from its package, taking care not to touch the surface of the PCB, and
slowly place the PCB (copper side up) in the plastic container.
5) Gently rock the plastic container from side to side, taking care not to splash the developing solution.
6) Rock the container until the blue smoke film stops floating from the PCB. This procedure should last
between 0.5 to 2.0 minutes. Exceeding 2.0 minutes might cause the photoresist film to be over exposed
thus making the board unusable.
7) When this is done, remove the PCB from the container and wash the PCB under cold running water.
If possible, use gentle flowing water to wash off any remaining developer from the PCB; this stops the
developing process from continuing.
8) Gently dab the PCB dry with a dry paper towel and put it aside.
9) Store the remaining developing solution in a plastic container for later use. Clean the plastic
container, with water, thoroughly. You are now ready to etch the PCB.
Etch a developed PCB
1) Dip the PCB in etching tank and set the temperature about 40-600C.
2) The process of etching the PCB can take anywhere from a few minutes to 2 hours; the key idea is to
etch the unprotected copper from the PCB.
3) When the unprotected copper on the PCB seems to be all gone, remove the PCB from the container
and verify that this is the intended circuit.
4) Clean the PCB under flowing water, ensuring that all the etching solution is removed from the board.
Dry the board with clean paper towels and set the board aside.
45
Fig 6.1 PCB dipped in FECl3 solution
Fig 6.2 Impressing made after some time
46
Prepare the PCB for use and drill the PCB
5) Using the appropriate drill bit, drill the white holes on the PCB. Place the drill bit up to the PCB
(copper side up) and start the drill, firmly push the drill bit through the PCB continue doing so for all the
holes.
6) Once all the holes are drilled, wash the PCB under running water and dry it well. If the PCB is not
fully dried, soldering will not work well on the PCB. The PCB is now ready to be soldered.
Fig 6.3 PCB Drilling
Solder onto a PCB
1) Place the component to be soldered into the holes drilled in the board.
2) Refer to the enclosed sheet on how to solder.
3) Once you are done soldering, check the solder joints under a magnifying glass to ensure proper solder
joints.
4)Once you are done soldering all the components, check to make sure there are no short circuits on the
traces; i.e. no solder has flowed between two pins.
47
6.2 PCB Designing using NI-ULTIBOARD
6.2.1 NI-ULTIBOARD
NI Ultiboard or formerly ULTIboard is an electronic Printed Circuit Board Layout program which is part
of a suite of circuit design programs, along with NI Multisim. One of its major features is the Real Time
Design Rule Check, a feature that was only offered on expensive work stations in the days when it was
introduced. ULTIboard was originally created by a company named Ultimate Technology, which is now
a subsidiary of National Instruments. Ultiboard includes a 3D PCB viewing mode, as well as integrated
import and export features to the Schematic Capture and Simulation software in the suite, Multisim.
Fig
6.4
Nat
ion
al I
nst
rum
enta
tion
NI-
Ult
iboa
rd C
ircu
it P
CB
layo
ut.
48
Fig 6.5 Optocoupler Unit Circuit PCB layout Design.
49
Fig: 6.6: Mirrored Impressions for Etching process.
Fig: 6.7: 3D view of optocoupler unit, NI (National Instrumentation) Ultiboard (Circuit designing
Solutions).
50
6.3 THE WHOLE SETUP
Fig 6.8: Whole setup of the project
6.4 MICRO-CONTROLLER
The wires shown in fig 8.2 are output wires taken from port 0 of micro-controller.
Fig 6.9 Micro-controller
51
6.5 CIRCUIT SETUP
Chips, which are in left-hand side in the fig 8.3, are opto-couplers. The output of the opto coupler is given as
VGS to the MOSFET.
Fig 6.10 Circuit setup
6.6 OUTPUT WAVEFORM
The output of the inverter is connected to a resistive load. The waveform is seen using a CRO.
Fig 6.11 Output waveform
52
6.7 COST ESTIMATION:
PARTS QUANTITY COST
Microcontroller (P89V51RD2) 1 250
Power MOSFETS (IRF630-FP) 8 200
OPTO-Coupler (817B) 8 160
Power Supplies (9V, 12V & 5V) 11 1250
PCB 1 200
Resistances (500Ω, 10k Ω, 10 Ω) 17 50
Burning Module and Programming
kit
1 2000
Other expenditures - 350
Total= ₹4450 approx.
53
CHAPTER 7
CONCLUSION & FUTURE ASPECTS
54
CHAPTER 7
CONCLUSION & FUTURE ASPECTS
The 3rd and 5th order harmonics eliminated, two-level cascaded inverter is successfully implemented in
hardware. It is giving the expected output. It is well suited for dc-ac conversion from batteries, fuel cells and
solar cells. Compared to other multilevel inverter topologies, it requires least no of components. Since the
circuit for all the levels are same, optimized circuit layout and packaging are possible. This two-level inverter
has only 8 transitions in each cycle, but a PWM inverter of same type needs 10 transitions. Moreover in each
transition only half of the voltage is applied across the MOSFET so switching loss is halved. Thus switching
loss is substantially reduced compared to PWM inverters.
55
REFERENCES AND BIBLIOGRAPHY
[1] Muhammad H.Rashid (2004) “Power electronics Circuits, Devices and Applications”, Third Edition,
Prentice Hall, India.
[2] Muhammad H.Rashid (2001) “Power electronics Handbook”, Academic press.
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