Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.

C H A P T E R 15

Advanced MOS (and Bipolar) Logic Circuits

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.

Figure 15.1 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load (or saturated-load) NMOS inverter. (c) The depletion-load NMOS inverter.

15.1.1 The pseudo-NMOS Inverter

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.

nMOS amplifier with depletion load VTC transfer characteristic

Depletion nMOS always ON

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Pseudo-NMOS Logic Circuits

!  Despite many advantages, CMOS suffers from the increased area, and correspondingly increased capacitance and delay as the logic gates becomes more complex.

!  For pseudo-NMOS logic inverter, only one additional transistor will be needed for each additional gate input.

This structure is similar to depleted-load NMOS but with rather improved characteristics. It also has the advantage of being directly compatible with CMOS circuits. PMOS always ON

Figure 15.1 (a) The pseudo-NMOS logic inverter

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Static Operation of A Pseudo-NMOS Logic Inverter (1)

!  The obvious disadvantage of the inverter is the non-zero VOL for VI=VDD (point E). It causes the static power dissipation to be PD= Istat x VDD.

These 2 parameters approach zero for conventional CMOS inverter.

Figure 15.2 Graphical construction to determine the VTC of the inverter in Fig. 15.1(a).

15.1.2 Static characteristics

kn > kp

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!  VTC for the pseudo-NMOS inverter.

Figure 15.3 VTC for the pseudo-NMOS inverter. This curve is plotted for VDD = 5 V,

Vtn = −Vtp = 1 V, and r = 9.

Static Operation of A Pseudo-NMOS Logic Inverter (2) 15.1.3 Derivation of the VTC

€

r =kpkn

=µ pWp

µnWn

same channel length L

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Gate Circuit of A Pseudo-NMOS Logic

! 4-input pseudo-NMOS NOR and NAND gates are shown below. Note that each requires only 5 transistors compared to 8 used in complementary CMOS.

! NOR type consumes less area than NAND type. ! Pseudo-NMOS is suited for applications in which the output remains high most of the time.

Figure 15.4 NOR and NAND gates of the pseudo-NMOS type.

NOR NAND

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Pass-Transistor Logic Circuits (1)

!  A simple approach for implementing logic functions utilizes series and parallel combinations of switches that are controlled by input variables to connect the input and output nodes.

!  Each of the switches can be implemented either by a single NMOS transistor or by a pair of CMOS transistors connected in CMOS transmission gate configuration.

CMOS transmission gate

Y=AC

Figure 15.5 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the

function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C).

Figure 15.6 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate.

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Operation with NMOS as Switches (1) (IT IS NOT AN INVERTER!!!!)

!  Although switches with single NMOS transistor is a simple circuit, there are serious shortcomings in both static and dynamic performance.

!  For dynamic operation (poor “1”):

The high output voltage (VOH) will not be equal to VDD; rather, it will be lower by Vt, and to make matters worse, the value of Vt can be as high as 1.5 to 2 times Vto (due to body effect).

!  For static consideration, the low value of VOH can cause the Qp of the next CMOS inverter stage to conduct and thus has a finite static current and static power dissipation.

Figure 15.8

Q (NMOS) will stop conducting when vo= VDD-Vt

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!  Operation of the NMOS switch as the input goes low is shown below.

!  It results in a “good 0”. Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles in comparison to previous case.

Operation with NMOS as Switches (2) (IT IS NOT AN INVERTER!!!!)

Operation with CMOS Transmission Gate as Switches (1)

!  Great improvement in static and dynamic performance are obtained when the switches are implemented with CMOS transmission gate.

" Qn will stop conducting when vo= VDD-Vtn # Qp will enter triode region at vo= |Vtp|, but will continue to

conduct until C is fully charged and vo= VDD. $  Qp provides the gate with a good “1”. %  tPLH will be lower than that in the case of single NMOS switch

due to additional current available from Qp. & Additional Qp, however, increases the value of C.

VSG-P=VDD

Operation with CMOS Transmission Gate as Switches (2)

!  With vI goes from high to low, the output waveform is shown below.

" Qp will cease conduction when vo falls to |Vtp|. # Qn, however, will continue to conduct until C is fully discharged

and vo = VOL = 0V.

! The transmission gates provide far superior performance than single NMOS switches. The price paid is increased circuit complexity, area and capacitance.

Fig.  5.64    The  CMOS  transmission  gate  with  analog  signal.  

Carico

Segnale  ananalogico  

di  uscita

Segnale  analogico  di  ingresso

vC

Fig.  5.65    Equivalent  circuits  for  visualizing  the  operaBon  of  the  transmission  gate  in  the  closed  (on)  posiBon:    (a)  vA  is  posiBve;    (b)  vA  is  negaBve.    

NMOS

NMOS

PMOS

PMOS

vA RL

vo

Switch closed

vA RL

vo

€

vo =RL

REQ + RLvA

REQ < RL vo – vA Piccola differenza

Tensioni di comando sui gate vGN = +vC vGP = -vC

IP: vA>0; NMOS e PMOS in triodo (NMOS spento Se vo> vC-VTN )

iN ≈ KN 2(vC-vo-VTN) (vA-vo) RonN=(vA-vo)/iN 1/RonN=2KN (vC-vo-VTN)

iP ≈ KP 2(vA+vC-|VTP|) (vA-vo) RonP=(vA-vo)/ip 1/RonP=2KP (vA+vC-|VTP|)

REQ = RonN//RonP =[2KN (vC-vo-VTN) + 2KP (vA+vC-|VTP|)]-1

Se KN=KP=K VTN=|VTP|=VT allora REQ = [4K (vC-VT+vA-vo)]-1

REQ = RonN//RonP

Variation in the REQ of a Transmission Gate as input signal is varied. (NMOS and PMOS un-matched)

REQ

vA(vo)

REQ = RonN//RonP