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CAD for Physical Design

of VLSI Circuits

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Course Outline by Topics• Circuit Partitioning• Floorplanning• Placement• Global / Detailed Routing• Technology Mapping in FPGA• Interconnect Optimization

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VLSI Design Cycle

System Specification

Architectural Design

Logic Design

Circuit Design

Physical Design

Functional Design Fabrication

Packaging

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VLSI Design Cycle

System Specification

ArchitecturalSpecification

RTL in HDL

Netlist

Layout

Timing & relationshipbetween functional units

Chips

Packaged andtested chips

ArchitecturalDesign

FunctionalDesign

LogicDesign

PhysicalDesign

Fabrication

Packaging

Circuit Designor

Logic Synthesis

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VLSI Design CycleSystem Specification – Specification of the size, speed,

power and functionality of the VLSI system.

Architectural Design – Decisions on the architecture, e.g., RISC/CISC, # of ALU’s, pipeline structure, cache size, etc. Such decisions can provide an accurate estimation of the system performance, die size, power consumption, etc.

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VLSI Design Cycle Functional Design – Identify main functional units and

their interconnections. No details of implementation.

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VLSI Design Cycle

Logic Design – Design the logic, e.g., boolean expressions, control flow, word width, register allocation, etc. The outcome is called an RTL (Register Transfer Level) description. RTL is expressed in a HDL (Hardware Description Language), e.g., VHDL and Verilog.

X = (AB+CD)(E+F)Y= (A(B+C) + Z + D)

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VLSI Design Cycle

Circuit Design – Design the circuit including gates, transistors, interconnections, etc. The outcome is called a netlist.

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VLSI Design Cycle Physical Design – Convert the netlist into a geometric

representation. The outcome is called a layout.

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VLSI Design Cycle

Fabrication – Process includes lithography, polishing, deposition, diffusion, etc. to produce a chip.

Packaging – Put together the chips on a PCB (Printed Circuit Board) or an MCM (Multi-Chip Module)

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Physical Design Cycle

Circuit Partitioning

Floorplanning & Placement

Routing

Layout Compaction

Extraction and Verification

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Physical Design Cycle Circuit Partitioning – Partition a large circuit into sub-

circuits (called blocks). Factors like #blocks, block sizes, interconnection between blocks, etc. are considered.

1

2

3

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Physical Design Cycle Floorplanning – Set up a plan for a good layout. Place

the modules (modules can be IP blocks, functional units, etc.) at an early stage when details like shape, area, I/O pin positions of the modules, …, are not yet fixed.

Deadspace

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Physical Design Cycle Placement – Exact placement of the modules (modules

can be gates, standard cells, etc.) when details of the module design are known. The goal is to minimize delay, total area and interconnect cost.

v

Feedthrough

Standard cell type 1

Standard cell type 2

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Physical Design Cycle

Routing – Complete the interconnections between modules. Factors like critical path, clock skew, wire spacing, etc. are considered. Include global routing and detailed routing.

v

Feedthrough

Type 1 standard cel1

Type 2 standard cell

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Physical Design Cycle

Compaction – Compress the layout from all directions to minimize the total chip area.

Verification – Check the correctness of the layout. Include DRC (Design Rule Checking), circuit extraction (generate a circuit from the layout to compare with the original netlist), performance verification (extract geometric information to compute resistance, capacitance, delay, etc.)

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Design Styles

• Full-Custom Design• Standard Cell Design• Gate Array Design• Field Programmable Gate Array Design (FPGA)

… or mixtures of the above

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Full-Custom Design

• No rigid restrictions on layout.• More compact design.• Longer design time.• Hierarchical: chip clusters units functional

units.

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Full Custom Design

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Standard Cell Design• Rectangular cells of the same height.• Cell library (has 500 - 1200 cells).• Cells placed in rows and space between rolls are called

channels for routing.• Feedthroughs

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Standard Cell Design

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Gate Array Design• Each chip is prefabricated with an array of identical gates

or cells.• The chip is “customized” by fabricating routing layers on

top.

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An Uncommitted Gate Array

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A Committed Gate Array

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Field Programmable Gate Array• Chips are prefabricated with logic blocks and

interconnects.• Logic and interconnects can be programmed (erased and

re-programmed) by users. No fabrication is needed.• Interconnects are predefined wire segments of fixed

lengths with switches in between.

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Field Programmable Gate Array

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Trends in VLSI

• Transistor

• Smaller, faster, use less power• Interconnect

• Less resistive, faster, longer (denser design)

• Yield

• Smaller die size, higher yield

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Chip Area

micron

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Processor Performance

0.1

1

10

100

1,000

10,000

100,000

1000,000

75 80 85 90 95 00 05 10 15

MIPS

Source: Intel

808680286

80386 Processor80486 Processor

Pentium ProcessorPentium Pro Processor

100,000 MIPS

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Transistor Count

1975 1980 1985 1990 1995 2000 2005 2010 20151

10

100

1,000

10,000

100,000

1,000,000K

Source: Intel

Projection

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Average Transistor Price

68 70 72 74 76 78 80 82 84 86 88 90 92 94 96

$

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

10

100

Source: Intel

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Technology Characteristics

Year 1999 2001 2003 2006 2009 2012

Technology(m)Density(# transistors / cm2)Chip size(cm2)Power(W)

# RoutingLayers

0.18 0.15 0.13 0.1 0.07 0.05

6.2M 10M 18M 39M 84M 180M

3.40 3.85 4.30 5.20 6.20 7.50

1250 1500 2100 3500 6000 10000

6-7 7 7 7-8 8-9 9

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Scaling

• The process of shrinking the layout in which every dimension is reduced by a factor is called Scaling.

• Transistors become smaller, less resistive, faster, conducting more electricity and using less power.

• Designs have smaller die sizes, higher yield and increased performance.

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Can Scaling Continue?• Scaling work well in the past:

• In order to keep scaling work in the future, many technical problems need to be solved.

Year 1989 1992 1995 1997 1999Technology(m) 0.65 0.5 0.35 0.25 0.18

2001

0.15

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Can Scaling Continue?

• Some characteristics of transistors do not scale uniformly, e.g., leakage current, threshold voltage, etc.

• Mismatch in scaling of transistors and interconnects. Interconnect delay has increased from 5-10% of the overall delay to 50-70%.

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Roadmap

• International Technology Roadmap for Semi-conductors (ITRS)• Projection of future technology requirements for the next 15

years.

http://public.itrs.net

Edition Year of Publication1st2nd

3rd4th

1992199419971999

5th 2001

20036th

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These trends have brought many changes and new challenges to circuit design.

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Complicated DesignToo many transistors and no way to handle them manually.

Solutions:• CAD• Hierarchical design• Design re-use

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Power and Noise

Huge power consumption and heat dissipation becomes a problem

Noise and cross talk.

Solutions:• Better physical design

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Interconnect AreaToo many interconnects

Solutions:• More interconnect layers (made possible by Chemical-

Mechanical Polishing)• CAD tools for 3-D routing

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Metal Layers

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Interconnect DelayInterconnect delay becomes a dominating factor in circuit performance

Solutions:• Use copper wire• Interconnect optimization in physical design, e.g., wire

sizing, buffer insertion, buffer sizing.

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Interconnect Delay

0.651989

0.51992

0.351995

0.251998

0.182001

0.132004

0.12007

0

5

10

15

20

25

30

35

40

Gate delayInterconnect delay

Source: SIA Roadmap 1997