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DIGITAL SYNTHETIC RIPPLE MODULATOR FOR A DC-DC CONVERTER
By
BHARATH BALAJI KANNAN
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2006
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Copyright 2006
by
Bharath Balaji Kannan
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To the Almighty God.
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ACKNOWLEDGMENTS
I would like to sincerely express my gratitude and appreciation for my advisor, Dr. Khai
D.T. Ngo, for his constant encouragement and thought-provoking ideas that helped me in the
development of this dissertation. I would also like to thank the Department of Electrical and
Computer Engineering at the University of Florida, for providing me the necessary financial
support. I would like to thank Dr. John G. Harris and Dr. William R. Eisenstadt for their valuable
suggestions and for being on my dissertation committee. I would also like to thank Dr. Jih-Kwon
Peir for serving as my external committee member.
I would also like to take this opportunity to thank Dr. Robert M. Fox, who helped me to
acquire the skills in the field of integrated circuit design. I am also grateful to Dr. Jacob Hammer
for helping me to secure the departmental financial assistance towards my research. I would also
like to express my gratitude and appreciation to the College of Engineering, Anna University,
India, for providing an ambient environment to study and learn.
Last but not least, I would like to thank my parents, sister, brother-in-law, and my
resourceful friends who gave me the necessary impetus towards the development of this
dissertation.
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TABLE OF CONTENTS page
ACKNOWLEDGMENTS ...............................................................................................................4
LIST OF TABLES...........................................................................................................................8
LIST OF FIGURES .........................................................................................................................9
LIST OF SYMBOLS AND ACRONYMNS.................................................................................14
ABSTRACT...................................................................................................................................16
CHAPTER
1 INTRODUCTION ..................................................................................................................18
1.1 Conventional Carrier Signal Generation ..........................................................................19 1.2 Carrier Signals in Digitally Controlled DC-DC Converters.............................................21
2 DIGITAL PULSE WIDTH MODULATOR..........................................................................22
2.1 DPWM Modules in Digitally Controlled DC-DC Converter ...........................................22 2.2 DPWM Modules in Digitally Controlled DC-AC Inverter ..............................................24
3 DIGITAL SYNTHETIC RIPPLE MODULATOR................................................................34
3.1 Design Concept of DSRM................................................................................................34 3.1.1 Digital Inverse Timing Generator ..........................................................................35 3.1.2 Extraction of Digital Timing Generator Parameters ..............................................37 3.1.3. Scaling Approaches ...............................................................................................39 3.1.4. Successive Accumulation......................................................................................42
3.2 Architecture of Digital Synthetic Ripple Modulator ........................................................44 3.3 Application Illustration of the Digital Synthetic Ripple Modulator.................................47
3.3.1 Design of Buck Converter-Output LC filter...........................................................49 3.3.2 Design of Digital Synthetic Ripple Modulator.......................................................50
3.3.2.1 Digital timing generator ...............................................................................50 3.3.2.2 Output voltage A/D resolution .....................................................................53
3.4 Modeling and Simulation of Digital SRM Based Buck Converter ..................................55 3.4.1 Modeling of PWM Switch......................................................................................55 3.4.2 Modeling of Output LC filter .................................................................................56 3.4.3 Modeling of Digital SRM Controller .....................................................................56 3.4.4 Simulation of Adaptive Voltage Position for Digital SRM based Buck
Converter......................................................................................................................59 3.4.5 Modeling of Dynamics involved in the Digital SRM Controller for a Buck
Converter......................................................................................................................65
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3.4.6 Design Methodology for Digital SRM Controlling the Synchronous Buck Converter......................................................................................................................69
3.5 Performance Analysis of Digital Synthetic Ripple Modulator.........................................72 3.5.1 Open-loop Linear Control of Controlled Variable with Command Signal ............72 3.5.2 Influence of Component Variations on the Digital SRM Performance .................72 3.5.3 Open-loop Dynamic Response of the Digital SRM Controlled Buck
Converter......................................................................................................................73 3.6 Advantages of Digital Synthetic Ripple Modulator .........................................................73
4 DESIGN AND EXPERIMENTAL IMPLEMENTATION OF DIGITAL SYNTHETIC RIPPLE MODULATOR ......................................................................................................106
4.1 Experimental Implementation of Synchronous Buck Converter....................................106 4.1.1 Power MOSFET Design and Selection ................................................................107 4.1.2 Output Filter Inductor Selection...........................................................................108 4.1.3 Output Filter Capacitor Selection.........................................................................109 4.1.4 Synchronous Buck Gate driver.............................................................................109
4.2 Experimental Implementation of Signal Conditioning Circuit.......................................109 4.3 Hardware Implementation of DC-DC Buck Converter and A/D Signal Conditioning
Circuit................................................................................................................................114 4.4 Experimental Implementation of the Digital Timing Generator ....................................114 4.5 Experimental Implementation of Digital Synthetic Ripple Modulator Controlling the
DC-DC Buck Converter....................................................................................................115
5 TESTING AND ANALYSIS OF DIGITAL SRM CONTROLLED BUCK CONVERTER ......................................................................................................................132
5.1 DC-DC Buck Converter Testing and Measurement .......................................................132 5.2 Signal Conditioning Circuit Testing and Measurement .................................................134 5.3 Digital Synthetic Ripple Modulator Controlled Buck Converter Testing and
Measurement .....................................................................................................................135 5.3.1 Digital Inverse Timing Generator Testing ...........................................................137 5.3.2 Command to Output Transfer Characteristic of Digital Synthetic Ripple
Modulator Controlled Buck Converter ......................................................................138 5.3.3 Load transient response Step-Response of Digital Synthetic Ripple Modulator
Controlled Buck Converter ........................................................................................138 5.3.4 Variation of Switching Frequency Based on Load Conditions ............................139
5.4 Future Directives for Research .......................................................................................139
6 CONCLUSION.....................................................................................................................158
6.1 Summary.........................................................................................................................158 6.2 Future Work....................................................................................................................158
APPENDIX
MATLAB FUNCTIONS .............................................................................................................160
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LIST OF REFERENCES.............................................................................................................164
BIOGRAPHICAL SKETCH .......................................................................................................170
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LIST OF TABLES
Table page 2-1 DPWM architecture realizations ............................................................................................27
2-2. Hardware/FPGA realization of DPWM module in DC-DC converters ................................28
2-3. DSP/Micro-controller realization of DPWM module in DC-DC converters ........................29
2-4. Hardware/FPGA realization of DC-AC PWM inverter control ............................................30
2-5. DSP/Micro-controller realization of DC-AC PWM inverter control ....................................31
3-1. Sequential steps involved in Step Value generation..............................................................74
3-2. DC-DC converter specifications............................................................................................74
3-3. Scaling factor Approximations..............................................................................................74
4-1. Comparison of time duration from simulations...................................................................117
4-2 Bill of materials for the synchronous buck DC-DC converter .............................................117
4-3 Bill of materials for the A/D converter and signal conditioning circuit ...............................117
4-4 Bill of materials for the FPGA based digital controller........................................................118
5-1 Equipment list and specifications .........................................................................................140
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LIST OF FIGURES
Figure page 2-1. Generic architecture of digitally controlled DC-DC switching converter.............................32
2-2. Duty ratio based on hybrid DPWM (NDPWM=8bits) .........................................................32
2-3. Architecture of PWM inverter based 3-Φ induction motor drive..........................................33
3-1. Conceptual implementation of digital duty ratio generation .................................................75
3-2. Inductor current indicating the current ripple and time intervals along with the buck converter inductor voltage .................................................................................................75
3-3. Scaling approaches for step value generation........................................................................76
3-4. Timing error performance for various scaling factor approximations used in step value generation...........................................................................................................................76
3-5. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A/D gain-block scaling ...................................................................................77
3-6. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A/D gain-block scaling ...................................................................................78
3-7. Generic architecture of a system controlled by digital synthetic ripple modulator...............79
3-8. Generic synthetic ripple modulation showing the hysteretic thresholds, command variable and PWM signal...................................................................................................79
3-9. Architecture of digital SRM controlled synchronous buck DC-DC converter. ....................80
3-10. Inductor current waveform during load current step-up and steady-down transient...........81
3-11. Simulation analysis of percentage error for various scaling factor approximations ...........81
3-12. Transfer characteristic of the A/D converter sampling the error voltage between output and command voltage. ............................................................................................82
3-13. Simulink model of the PWM switch ...................................................................................82
3-14. Simulink model of buck LC filter........................................................................................83
3-15. Simulink model of the A/D converter .................................................................................83
3-16. Simulink model of digital timing generator ........................................................................84
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3-17. Block diagram depicting the Simulink model of digital SRM controlled buck converter ............................................................................................................................85
3-18. Simulation outputs of the synchronous buck converter using MATLAB/Simulink for Vcmd=1.3V........................................................................................................................86
3-19. Simulation outputs indicating the step value, integer value and VPWM signal of the digital timing generator......................................................................................................87
3-20. Comparison between on-time/off-time generated based on theoretical equations and simulated synthetic ripple modulator.................................................................................88
3-21. Percentage error between digital timing generator and theoretical expression using simulation analysis.............................................................................................................89
3-22. Voltage change across the output capacitor during a step-down load transient..................90
3-23. Integer_value, modified hysteretic count, VPWM, and Error_binary for AVP implementation in digital SRM..........................................................................................91
3-24. Integer_value, modified hysteretic count, VPWM, and Error_binary for AVP implementation in digital SRM..........................................................................................92
3-25. Inductor current and AVP of the output voltage based on optimal AVP design for the load step-up transient .........................................................................................................93
3-26. Inductor current and AVP of the output voltage based on optimal AVP design for load step-down transient ............................................................................................................94
3-27. Inductor current and AVP of the output voltage - Vcmd reaches higher level before the peaking of Vout (Vout_max) .......................................................................................95
3-28. Inductor current and AVP of the output voltage - Vcmd reaches higher level before the peaking of Vout (Vout_max) .......................................................................................96
3-29. Inductor current, VPWM, and AVP of the output voltage - Vcmd reaches higher level after the peaking of Vout (Vout_max)...............................................................................97
3-30. Modulator output, Error_binary, and AVP of the output voltage - Vcmd reaches higher level after the peaking of Vout ...............................................................................98
3-31. Dynamic system model of the digital SRM controlled synchronous buck converter .........99
3-32. Magnitude and phase of command (vcmd) to duty ratio (d) transfer function..................100
3-33. Magnitude and phase of duty ratio (d) to output voltage (vout) transfer function ............101
3-34. Magnitude and phase of command (vcmd) to output voltage (vout) transfer function.....102
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3-35. Plot indicating the linear control of output voltage with command voltage based on MATLAB/Simulink simulation .......................................................................................103
3-36. Simulation plot indicating the effect of component variations on the performance of the digital SRM................................................................................................................104
3-37. Simulation of open-loop load transient response of digital SRM controlled buck converter with Vcmd=1.5 V and load step of 5A to 10A in 100 ns (50 A/µs) ..................105
4-1. Schematic of synchronous buck DC-DC converter.............................................................119
4-2. Current through the UFET in a switching cycle..................................................................119
4-3. Schematic of signal conditioning circuit for the A/D converter with inclusion of the scaling factor....................................................................................................................120
4-4. Block diagram of the experimental digital synthetic ripple modulator indicating the register enable and timing signals....................................................................................121
4-5. Frequency response of the signal conditioning circuit amplifier ........................................122
4-6. Phase voltage, converter output voltage, and signal conditioning circuit scaled voltages for Vcmd=1.5V...................................................................................................................123
4-7. Inductor voltages at the input of the A/D converter for a duty cycle of D=0.325 and Vcmd=1.5V ........................................................................................................................124
4-8. Buck converter output voltages, error voltage and output A/D input voltage for Vcmd=1.5V ........................................................................................................................125
4-9. Gerber file indicating the top layer of the PCB board.........................................................126
4-10. Gerber file indicating the bottom layer of the PCB board.................................................127
4-11. Photograph of the manufactured PCB board indicating the buck converter and the signal conditioning circuit................................................................................................128
4-12. Timing signals and A/D converter input voltages for the signal conditioning circuit ......129
4-13. ALTERA board based digital synthetic ripple modulator outputs indicating VPWM outputs for step values (100)10 and (42)10 ........................................................................130
4-14. Experimental implementation of DSRM controlled buck converter system.....................131
5-1. Experimental test-bed setup used for characterizing the DC-DC synchronous buck converter ..........................................................................................................................141
5-2. Phase node voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3........................141
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5-3. Output voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3................................142
5-4. PWM Input (CH2) and high-side gate drive (CH1) for Vin=5V and D=0.3 .......................142
5-5. PWM input (CH2) and Vphase (CH1) for Vin=5V and D=0.3 ..........................................143
5-6. PWM input (CH2) and low-side gate drive (CH1) for Vin=5V and D=0.3........................143
5-7. Phase node voltage (CH1) and low-side gate drive (CH4) for Vin=5V and D=0.3............144
5-8. Phase node voltage (CH1), output voltage (CH2) and inductor voltage (Math2) for Vin=5V and D=0.3 ..........................................................................................................144
5-9. Vphase_pos1 (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25 ......145
5-10. Vout_neg1 (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25........145
5-11. VLpos_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25......................146
5-12. VLneg_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25......................146
5-13. Verr_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.3 ...........................147
5-14. VLpos_adc_input (CH3), register-enable - blnk_pos (CH4) and VPWM from digital modulator (CH1) for Vin=5V and Vcmd=1.38 ...............................................................147
5-15. VLneg_adc_input (CH3), register-enable - blnk_neg (CH4) and VPWM from digital modulator (CH1) for Vin=5V and Vcmd=1.38 ...............................................................148
5-16. A/D converter output for inductor voltage during on-time-VLPOS [7-0] (CH3), register enable-blnk_pos (CH4), and VPWM (CH1). A) VLPOS0 (LSB). B) VLPOS1. C) VLPOS2. D) VLPOS3. E) VLPOS4. F) VLPOS5. G) VLPOS6. H) VLPOS7 (MSB)...............................................................................................................149
5-17. A/D converter output for inductor voltage during off-time-VLNEG [7-0] (CH3), register enable-blnk_neg (CH4), and VPWM (CH1). A) VLNEG0 (LSB). B) VLNEG1. C) VLNEG2. D) VLNEG3. E) VLNEG4. sF) VLNEG5. G) VLNEG6. H) VLNEG7 (MSB)..............................................................................................................150
5-18. A/D output for error voltage between Vcmd and Vout – VERRAD [7-0] (CH3), register enable-blnk_neg (CH4), and VPWM (CH1). A) VERRAD0 (LSB). B) VERRAD1. C) VERRAD2. D) VERRAD3. E) VERRAD4. F) VERRAD5. G) VERRAD6. H) VERRAD7 (MSB). ................................................................................151
5-19. Verr_adc_input (CH1) and VPWM from digital modulator (CH4) for Vin=5V and Vcmd=1.38 ......................................................................................................................152
5-20. Timing generation comparison based on simulation, theory and experimental digital timing generation approach..............................................................................................152
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5-21. Percentage timing error based on experimental digital timing generation approach ........153
5-22. Linear plot of Vout Vs Vcmd for Vin=4.5V and load resistance RL=1Ω ........................153
5-23. Linear plot of Vout Vs Vcmd for Vin=4.96V and load resistance RL=1Ω ......................154
5-24. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=1Ω ......................154
5-25. Linear plot of Vout Vs Vcmd for Vin=5V and load resistance RL=0.67Ω ......................155
5-26. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=0.67Ω .................155
5-27. Load transient response of the digital SRM Vout (CH2), inductor current (CH4) and load current step (CH3)....................................................................................................156
5-28. Variation of switching frequency with respect to load current for Vin=3.75V, 4.00V and 4.35V.........................................................................................................................157
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LIST OF SYMBOLS AND ACRONYMNS
A/D Analog to Digital
D Steady-state duty ratio of the converter
DLL Delay-locked loop
DPWM Digital Pulse Width Modulator
DSRM Digital synthetic ripple modulator
FPGA Field-programmable gate array
NC Number of bits for the hysteretic count resolution
NL Number of bits for the sampled inductor voltage
NQ(V,I) Sampled converter/inverter parameter
NSC Scaling factor used in inverse timing generation
NSC_A/D Ratio of scaling factor used in the signal conditioning circuit
PCB Printed circuit board
PFC Power factor correction
q(V,I) Control input for the inverse timing generator
qSTEP Step value used in the accumulator
tCLK Time period of the clock used for successive accumulation
tOFF Off-time of the upper MOSFET switch
tON On-time of the upper MOSFET switch
TS Switching time period
VCDL Voltage-controlled delay line
verrq LSB equivalent of the quantized error voltage between output and command voltage
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vLbin Binary equivalent of the quantized inductor voltage
vLq LSB equivalent of the quantized inductor voltage
VRM Voltage regulator module
vOUT Output voltage of the buck converter
∆error Percentage timing error metric for the timing generator
∆IL Peak-peak inductor current ripple
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
DIGITAL SYNTHETIC RIPPLE MODULATOR FOR A DC-DC CONVERTER
By
Bharath Balaji Kannan
December 2006
Chair: Khai D.T. Ngo Cochair: John G. Harris Major Department: Electrical and Computer Engineering
Voltage regulator modules (VRMs) powering the future microprocessors are required to
meet the stringent specifications on the core voltage ripple and voltage regulation. These
specifications are driven by the microprocessor’s higher di dt requirements and the need to
operate at a lower supply voltage for reduced power consumption. The conventional VRMs
resort to multi-phase pulse width modulation (PWM) control schemes to cater to the high current
demands and provide balanced load current sharing. The control schemes also involve a
combination of voltage-mode and current-mode or current-mode and hysteretic-mode control.
Thus, these schemes add to the cost and complexity of the VRM.
Synthetic ripple modulation (SRM) involves the generation of an artificial ripple,
synthesized from a converter parameter which is then bonded to the output voltage of the VRM.
This artificial scheme of carrier signal generation for PWM control enables voltage-hysteretic
modulation to be achieved in the low-voltage VRM modules for microprocessors. With the
inherent low-voltage ripple exhibited by a low-voltage VRM that is insufficient for conventional
hysteretic operation, the SRM scheme on the other hand provides sufficient ripple for the PWM
carrier signal. The SRM scheme blends in the advantages of current-mode control and hysteretic
control providing superior transient performance.
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The introduction of digital control to the PWM control of switching power converters has
gained popularity owing to its benefits of lower sensitivity to process and mismatch variations,
programmability, and the reduction of passive components used in tuning. The digital control
based SRM generates the duty ratio with inverse relation to a sampled converter parameter. The
on-time and off-time duration of the switches forming the duty ratio is generated by successively
accumulating the sampled inductor voltage. The accumulated output forming the synthetic ripple
is added to the error between output voltage and reference voltage. The carrier signal thus
generated is modulated between the higher and lower hysteretic thresholds, thus generating the
duty ratio. A unique scaling process also allows the implementation of programmable switching
frequency for converters. The major contributions of the dissertation in the field of engineering
are given below.
• Digital synthetic ripple modulator architecture for applications in power electronics. • Digital inverse timing generator with wide dynamic range and programmable frequency.
The digital SRM scheme is verified experimentally in the control of a synchronous buck
DC-DC converter. Experimental data are provided to delineate the potential advantages such as
inverse timing generation, programmable switching frequency, linear control of output variable
with reference variable under open-loop conditions, natural feed-forward control, and superior
transient performance.
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CHAPTER 1 INTRODUCTION
Low-voltage power supplies powering future microprocessors are under constant pressure
to provide higher di dt requirement. The core-voltages of current and future microprocessors are
on the order of 0.8-1.0V, enabling lower power consumption. The trend towards low-voltage
operation increases the burden on the switching regulators which are required to maintain a tight
tolerance on the core voltage. The allowed tolerance on the core voltage remains at a fixed
percentage of the supply voltage instead of an absolute value in volts. This indicates that as the
core voltages go down, the tolerance that the processors can handle also scales down
proportionately. It is also predicted that the load current requirements of these microprocessor
cores will increase up to 200A with dynamic current slew-rates on the order of 120A/ns [1-2].
These dynamic loads are tackled with point-of-load power supplies which derive their output
voltage from power conversion of existing 12V supply systems. The dynamic loads also present
stricter transient regulation requirements, thereby creating the need for the design of efficient and
enhanced power supply operation and control.
The dissertation focuses on the generation of carrier signals utilized in pulse width
modulation (PWM) control of converters/inverters with hysteretic mode of operation. The carrier
signals are derived from converter/inverter parameters such as inductor voltage, drain-source
voltage of power MOSFET, inductor current, and stator winding current. The carrier signal is
composed of the ripple associated with the variable to be controlled and a synthetic ripple
derived by filtering (analog approach – integration or digital approach – accumulation) a
converter parameter. Since the PWM control involves artificial carrier signal generation, the term
synthetic ripple modulation promptly applies. The superimposing of the controlled variable with
that of the synthetic ripple creates a significant amount of ripple similar to that exhibited in
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conventional current mode control. The modulation strategy is theoretically validated with an
application involving the control of a DC-DC synchronous buck converter used as a switching
regulator for powering microprocessors. The tight tolerance required on the output voltage of the
switching regulator and the higher di/dt (120A/ns) requirement can be achieved with the
synthetic ripple modulation (SRM) technique. Since the SRM based control is a form of
hysteretic control modulating the controlled variable directly within a hysteretic band, superior
dynamic performance is inherently attained. The fact that the output voltage is bonded to a
synthetic ripple, resulting in a carrier signal with sufficient ripple for PWM operation, allows the
output voltage to be controlled directly and with the required tight tolerance.
The digital SRM (DSRM) scheme employed in the control of the buck converter also
involves a novel method for deriving the duty ratio, with the generated time-intervals inversely
related to a sampled converter parameter. The duty ratio generation scheme is based on a unique
scaling process and eliminates the need for a high clock frequency. The modulation scheme
utilizes the sampled inductor voltage, which is scaled and successively accumulated to generate
the synthetic ripple. The error in the output voltage when compared to a reference or command
voltage is added to the synthetic ripple resulting in the carrier signal for PWM operation. The
carrier signal is modulated between hysteretic limits, resulting in the required duty ratio. Since
the carrier signal involved in the PWM signal generation is derived from the converter
parameters in the SRM scheme, natural input feed-forward control is also attained. This enables
better rejection of line input disturbances.
1.1 Conventional Carrier Signal Generation
Conventional PWM control relies on three main control schemes, namely, voltage-mode
control, current-mode control and hysteretic control [3]. In voltage-mode control, the carrier
signal required for PWM signal generation is based on an external oscillator. The oscillator
20
providing the carrier signal is conventionally realized by charging or discharging a capacitor
using a constant current source. It suffers from the serious drawback of external component
variations and requires better matching between an on-chip current source and an external
capacitor. The transient performance of voltage-mode control is limited by the delays involved in
the compensation circuit forming the feed-back loop. The current-mode control counterpart
utilizes the inductor current ripple for the carrier signal. The commutation instants of the
MOSFET switches are based on the type of current-mode control, namely peak current-mode
control, average current-mode control, and valley current-mode control. Current-mode control
offers better transient performance when compared to voltage-mode control.
This tradeoff is made possible only with accurate current sensing employing a current
sense resistor or a current transformer. The advantage thus gained over the voltage-mode control
is offset by the additional loss in the resistor for higher load currents or by the cost and space
requirements of the current sense transformer.
In hysteretic control, the carrier signal is implicitly generated by regulating the desired
output variable within a hysteretic band centered about a reference. The hysteretic mode of
control provides fast load transient response, requires no feedback loop compensation, and no
input filter interaction problems when compared to voltage-mode or current-mode control. In
applications requiring the controlled parameter to be within a marginal hysteresis band, the
PWM comparator used in power switch commutation is required to exhibit high resolution and
fast response. One of the major drawbacks involved in the hysteretic mode of control is the
variation of the switching frequency, increasing the complexity involved in output filter design.
The artificial ripple superimposed onto the controlled variable in the discussed synthetic
ripple modulator is significant enough to eliminate the need for a high resolution PWM
21
comparator. The synthetic ripple modulator also blends in the advantages of hysteretic
modulation by virtue of the control variable being directly tracked by the PWM comparator.
1.2 Carrier Signals in Digitally Controlled DC-DC Converters
The conventional voltage/current-mode control based on analog approaches involves more
real-estate to accommodate for the external components like resistors, capacitors, current
transformer, current-sense resistor, etc. The introduction of digital control for DC-DC
converters/inverters offers a multitude of benefits like insensitivity to component and parameter
variations, better noise immunity, ease of programmability, reduced size and cost. An application
involving the digital control of microprocessor power supplies also offers the benefits of easier
VID code (Voltage Identification Code) integration, fault protection, programmed soft-start, the
inevitable features of modern-day voltage-regulator modules (VRM) [2].
Carrier signals for digital control of DC-DC systems are generated using a specific
module, namely the Digital Pulse Width Modulator (DPWM). The DPWMs are based on current
starved inverters, fast-clocked counter, tapped delay-lines, hybrid approach involving
multiplexer and delay-lines, and binary-weighted delay lines. The architectural realization and
implementation issues associated with the DPWM architectures are dealt with in chapter 2. The
list of symbols and acronyms used in the dissertation are outlined in Table 1-1.
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CHAPTER 2 DIGITAL PULSE WIDTH MODULATOR
The digital pulse width modulator (DPWM) block in a digitally controlled power
converter/inverter generates the PWM pulse signal controlling the commutation instants of the
switches. A typical application involving a DC-DC converter relies on the control and regulation
of output voltage or the line/input current of the converter. Similarly a DC-AC inverter
application involves the control/regulation of stator current or inverter output voltage for the
speed control of motor-drives.
2.1 DPWM Modules in Digitally Controlled DC-DC Converter
The DPWM module in a DC/DC converter generates a discrete set of duty ratio values
based on a digital command input word from a discrete-time compensator. The carrier signal
involved in the PWM pulse signal generation is implicitly created by the DPWM module. The
DPWM module quantizes the switching time period into a number of discrete time slots. A
particular time slot is selected based on the digital duty command input (d[n]) [4-5]. The
selection of a particular time slot and the time duration elapsed during the slot selection
determines the commutation instant of the switch and the duty ratio respectively. The carrier
signal information is embedded in the architecture forming the DPWM module. The generic
architecture of a digitally controlled switching DC-DC converter is outlined in Figure 2-1. The
discrete set of duty ratio values involved in a digitally controlled DC/DC converter imposes
restrictions on the set of steady-state values taken by the output voltage. The resolution of the
DPWM module should be higher than that of the output voltage A/D resolution to avoid limit-
cycle oscillations [6].
23
The DPWM module serves as a D/A converter interfacing the digital control block with
that of the switching converter. Several realizations of the DPWM module based on linearity,
high-frequency capability, area, complexity and power consumption are outlined in literature [7-
11]. A summary of the DPWM realizations are shown in Table 2-1.
Due to the profound developments in Field-programmable gate-array (FPGA) and the DSP
processors sector of the semiconductor industry, the realization of such DPWM modules is
becoming much easier. A comparative listing of the current approaches for the realization of
DPWM modules in DC-DC converters based on FPGA/IC-level and DSP implementation is
indicated in Table 2-2 and Table 2-3 respectively. The approaches are also distinguished based
on voltage-mode, current-mode and hysteretic control of DC-DC converters. The set of duty
ratio generated from a hybrid DPWM [8] involving multiplexers and counters is shown in Figure
2-2. Based on the characteristic in Figure 2-2, a linear relation between the digital command
word and the output duty ratio is sought in the digital control schemes which are based on Figure
2-1.
The realizations based on IC-level/FPGA implementation are tailored to a particular
application resulting in restricted programmability of the switching frequency. The linearity
between the duty-ratio command input and the PWM pulse signal exhibited by silicon-based
DPWM modules relies on careful layout techniques and better matching between the delay cells
[7]. The DPWMs based on tapped delay-lines are susceptible to drifts in the switching frequency,
due to process and temperature variations in individual delay cells. The power supply ripple-
rejection performance necessitates differential delay cell designs [11]. The DPWMs realized
from the counter/comparator scheme suffers from the serious drawback of higher power
consumption. The need for higher resolution in low-voltage VRMs, leads to higher clock
24
frequency requirement in the range of 200-800MHz attributing to higher power consumption
[12].
DC-DC converters employed in low-voltage VRM’s are tied with stricter static and
transient specifications with regulation tolerance less than 5%. This demands a higher resolution
for the A/D converter sampling the output voltage. It also necessitates a lesser conversion time
for the A/D converter when switching frequencies on the order of MHz are targeted in digitally
controlled power supplies. This has become an inevitable requirement since higher switching
frequencies allow smaller values for output filter components, reducing their size dramatically.
DSP processor based realization of VRMs switched at higher frequency [13-16] results in the
requirement of lesser computation time for the duty-ratio to achieve near one-cycle control [17].
This proves to be an expensive solution when DSPs with higher processing power are targeted.
The VRMs utilizing DSPs and based on the architecture of Figure 2-1 cannot accurately track
component variations in the buck output LC filter.
2.2 DPWM Modules in Digitally Controlled DC-AC Inverter
The closed-loop regulated DC-AC PWM inverters are widely employed in programmable
ac power sources, uninterruptible power supplies and induction motor drives [18-21]. The
architecture of a typical motor drive application is illustrated in Figure 2-3. In a typical motor
drive application, the control strategy relies on comparing the stator current or the inverter output
voltage with a desired reference to maintain regulation and thereby control the speed of the drive.
In hysteretic control, the controlled variable is regulated within a hysteretic band [22-27]. The
comparative listing of the implementation of PWM inverter control, utilizing FPGA and DSP
processors are outlined in Table 2-4 and Table 2-5 respectively.
The DSP processor based current hysteretic control of PWM inverter in [22] and [24],
relies on continuous stator current sensing and sampling. The sampled current value is compared
25
with predefined upper and lower limits stored in registers. The digitized stator current value is
updated at every sampling instant of the A/D converter. If the sampling frequency is too low, it
can lead to current overshoot or undershoot, deviating from the hysteretic band. This necessitates
a higher sampling frequency, thereby increasing the cost and power consumption.
The various control and implementation strategy of DC-DC converters and DC-AC
inverters discussed above determine the static and dynamic performance. The static performance
is mostly met by the aforementioned methods, while the transient performance is limited by the
delays involved in sampling and processing. The computation time involved in the various
digital blocks restrict the maximum switching frequency [28-30], since a portion of the switching
time period is to be used for the housekeeping operations. The dynamic characteristics of
hysteretic-mode of control are superior when compared to voltage/current-mode control [31],
while it is dependent on the hysteresis band employed. A wider hystereis band for the
modulation can alleviate the expensive requirements of faster and higher resolution of digital
comparators. On the other hand a wider hysteresis band based modulation may not be a viable
solution for low-voltage VRMs (DC-DC converter), where output voltage ripple requirements on
the order of 10-20mV are desired.
Hence a modulation strategy that can offer the dynamic performance of hysteretic mode of
operation while employing significant ripple as that of current-mode control and without the
need for current sensing is desired. A good linearity between the controlled variable and a
command reference under open-loop operation can prove to be desirable characteristic with
respect to control strategy implementation.
These requirements paved the way for synthetic ripple modulation, wherein the controlled
variable is bonded to any ac waveform derived from the converter or the inverter, to create a
26
significant amount of ripple. This allows the controlled variable to be regulated with very less
ripple. The synthetic ripple composed of the controlled variable and the ac waveform is
favorable for hysteretic mode of control to reap the benefit of superior dynamic performance.
The design, modeling, simulation, and implementation of the synthetic ripple modulator establish
the focus of the remaining chapters.
27
Table 2-1 DPWM architecture realizations Parameters DPWM architecture Complexity Linearity Area
Fast-clock counter approach [12]
Requires fast-clock
DPWMNclk Sf f= 2
Good 1 mm × 1 mm
Tapped delay-line PWM [11] Externally imposed clock-Open loop
External oscillator, delay-cell variations
Poor
Delay cell based – closed loop 2 1N : MUX Poor
0.75 mm × 1.2 mm
Hybrid counter /Tapped delay line [8]
Tradeoff power for better THD
Good 0.25 mm × 1 mm
Binary-weighted delay line Requires better-matching of delay between cells
Poor
Segmented DPWM architecture Requires 2 1N : MUX and thermometer coding
Moderate 0.0675mm2
28
Table 2-2. Hardware/FPGA realization of DPWM module in DC-DC converters Digital control Hardware/ FPGA Implementation
Application DC-DC converters
Comparison Parameters Voltage-mode control Hysteretic control
Reference [Chandraksan98]
[Maksimovic 02] [Rinne04] [Sanders01] [Yau04]
Silicon area 3.2mm*2.8mm 1mm2 <2.7k gates 3.2mm*2.8mm N/A Power consumption 10µW - - - -
Clock speed 2.5MHz 8MHz 35MHz-145MHz 5MHz 8MHz
Architecture 10bit -Hybrid MUX/Counter DPWM
8bit -Hybrid delay-line/counter DPWM
6-12bit VCDL/DLLDPWM
8-bit Ring Osc/MUX DPWM
ALTERA EPM7064SLC44
Application Buck VRM Buck converter Buck converter Buck VRM Forward converter Multi-Phase control N/A N/A 4-PWM signals 4-phase VRM N/A
Programmable switching frequency
330kHz 1MHz 100kHz-15MHz 100kHz 180kHz-200kHz
Features Low-power Novel delay-line A/D
Programmable DPWM
Passive current sharing Ultra-fast transient response
29
Table 2-3. DSP/Micro-controller realization of DPWM module in DC-DC converters DSP/Micro-controller Implementation
Application DC-DC converters
Comparison Parameters Voltage/Current-mode control Hysteretic control
Reference [Zhang04] [Maksimovic01] [Erickson03] [Batarseh02]
Processor engine 16-bit fixed point DSP 16-bit ADSP-2171 ADMC401 TMS320LF2407
Instruction cycle parameters 40MHz 38.5ns 26MIPS 26MHz 33ns
ADC 10-bit ADC 8 channel 12bit 8-channel 12bit ADS807
12-bit 53MHz Hysteretic window N/A N/A N/A ±10mV(steady-state)
±20mV(transient)
Features Predictive PFC control 8-bit DPWM module
Predictive current control (CCM/DCM) Constant ON time Line current THD = 2.8%
Multi-phase interleaved current-sharing
Multi-Phase control N/A N/A N/A 4-phase
Switching frequency 160kHz 1MHz 120kHz-190kHz
30
Table 2-4. Hardware/FPGA realization of DC-AC PWM inverter control Digital control Hardware FPGA Implementation
Application DC-AC inverters
Comparison Parameters Voltage/Current-mode control Hysteretic control
Reference [Yokoyama04] [Tzou99] [Guinjoan03] [Betz99]
FPGA/Hardware ALTERA Stratix 1S25 Xilinx XC4005 Xilinx XC4010E-3-PC84 ALTERA
FLEX10K50
Silicon area/ Number of gates <500k gates 5000 logic gates,196 CLB, 112
IOB
245 CLB(Config.Logic Blocks) 30 IOB( I/O blocks) 84 Flip-flops
1204 Logic cells
Clock speed 80MHz 8MHz 6MHz 10MHz
Architecture Dead-beat control law based on multiplication and additions
Counter/Comparator/Timer PWM generator
8-b DPWM – Counter/Comparator
Counter/Comparator/Timer PWM generator
Multi-Phase control
3-phase control PWM inverter control 3-phase PWM inverter control N/A 3-phase PWM
inverter control Programmable switching frequency
20kHz 31.25kHz 20kHz-40kHz 2.9kHz
31
Table 2-5. DSP/Micro-controller realization of DC-AC PWM inverter control DSP/Micro-controller Implementation
Application DC-AC inverters
Comparison Parameters Voltage/Current-mode control Hysteretic control
Reference [Tzou95] [Toliyat04] [Mattavelli04] [Mattavelli00] [Round97] Processor engine TMS320C14 TMS320C50/FLEX6000 TMS320F2812 TMS320F240 TMS320C30 Instruction cycle parameters 160ns 50ns 6.67ns 50ns
ADC 16-bit ADC 16-bit ADC 12-bit ADC 16 channel Dual 10-bit ADC 12-bit serial
ADC Hysteretic feature N/A N/A Uses inductor
Current slope Adaptive hysteretic band
Current hysteretic band
Features
Multi-loop digital control (Current, Voltage and Feed-forward control)
Predictive stator current control Voltage-source inverter
Switching-time prediction control Switching frequency stabilization
Adaptive Dead-beat hysteretic control Utilizes on-board PWM modules for gate signals
Application 1 φ− PWM inverter 1.5kW induction motor drive Active power
filter Switching frequency 30.72kHz 6.7kHz 10kHz 20kHz
32
Switching Converter LoadoutV
Gain H=
/A D[ ]outV n
inV
[ ]refV n
[ ]e nDigitalCompensator
[ ]d nDPWM
SDT
STd t( )
Figure 2-1. Generic architecture of digitally controlled DC-DC switching converter
Figure 2-2. Duty ratio based on hybrid DPWM (NDPWM=8bits) [8]
33
3 Inductionmotor
φ−
inV
ADC
ai bi ci
/DSP FPGA REFi
P Q R S T U
P
Q
R
S
T
U
ω
Figure 2-3. Architecture of PWM inverter based 3-Φ induction motor drive
34
CHAPTER 3 DIGITAL SYNTHETIC RIPPLE MODULATOR
Digital Synthetic Ripple modulator (DSRM) functions as a digital to analog converter in
producing the PWM pulse signal based on sampled converter waveforms. The DSRM utilizes
sampled version of converter parameters like inductor voltage, inductor current, or drain-source
voltage of MOSFETS to synthesize an artificial ripple used as carrier signal in pulse width
modulation. The modulation strategy is based on bonding the controlled variable to the synthetic
ripple generated by the DSRM. The resulting carrier signal is bound between hysteretic limits
which dictate the commutation instants of the power MOSFET switches. The modulation
strategy can be applied to the control of DC-DC and DC-AC power converters.
3.1 Design Concept of DSRM
In DC-DC converters or DC-AC inverters employing current-mode control [32-34], the
on-time and off-time of the power MOSFET switches are inversely proportional to the inductor
voltage under steady-state conditions as given in Eq. 3-1.
LON OFF
L
L It or tv×∆
= (3-1)
where L is the value of the inductor and ∆IL indicates the peak-peak inductor current ripple.
In the generic case, the time duration to be generated can be inversely proportional to a
control input ( ( , )q V I ) as given in Eq. 3-2.
( , )theoreticalKt
q V I= 3-2)
where q(V,I) is a function of voltage or current and K is a constant depending on the application.
Similar duty ratio or time duration requirements are exhibited in hysteretic PWM control
[35-39] having variable switching frequency. The conventional analog approach based duty-
ratio/timing generators involve current sources and on-chip/off-chip capacitors. These
35
approaches generally exhibit poor noise sensitivity and offer limited programmability. Timing
generators [40-43] and duty ratio generators based on digital schemes involve digital pulse width
modulators (DPWMs) [44-52] that are characterized by a linear relation between the time
duration generated and the control input. The DPWMs are based on delay-lines [8] [11],
propagation-delay of basic gates or the time period of a fast running clock [12].
Synthetic Ripple Modulation based control of power converters involve carrier signal
generation from converter based parameters. This modulation strategy, when applied to the
control of a DC-DC buck converter, utilizes the inductor voltage for its carrier signal generation.
Hence, this modulation also involves generation of on-time and off-time duration for power
MOSFET switches with inverse relation to a control voltage. In the analog domain, the inverse
relation between the on/off-time of the power MOSFET switches and the inductor voltage as in
Eq. 3-1 can be realized by employing a Gm-C circuit [53] [54]. An all-digital realization to
generate timing inversely related to a voltage would involve area-intensive digital division
hardware or a cost-intensive DSP processor based solution. The need for the inverse relation
based duty ratio generation as in Eq. 3-2 led to the development of the digital inverse timing
generator.
3.1.1 Digital Inverse Timing Generator
The conceptual implementation of the digital duty ratio generation is shown in Figure 3-
1. In the developed duty ratio generation scheme, output of an A/D converter sampling a
converter parameter is scaled by NSC to generate a step value (qstep), which is interpreted as a
floating point binary number. The step value is successively accumulated at each clock instant
(tCLK) until the hysteretic count ( 2 CN ) is reached, thereby generating a time duration that is
inversely proportional to the binary input. The integer portion of the accumulator output is
36
compared to the hysteretic count using a digital comparator. The timing signal is set at the
beginning of the accumulation process and reset at the onset of the comparison hit. The number
of clock counts required to reach the hysteretic count ( 2 CN ) and the slope of the staircase-shaped
accumulator output are determined by the step value. Hence, a larger step value results in a
steeper slope or fewer clock counts, generating shorter time duration and vice versa. The
assumption of the step value as a floating point binary number enables the realization of inverse
timing generation.
The timing generation scheme is based on digital time quantization and accumulation. The
digital timing expression embodying the design concept is given to be
( , )
2 CN
Digital CLKSC Q V I
t tN N
= ××
(3-3)
2 CN
Digital CLKstep
t tq
= × (3-4)
where 2 CN denotes the hysteretic count, CN is the number of bits used for count resolution,
( , )Q V IN denotes the sampled value of the converter parameter (q(vL,iL,…VDS)), SCN indicates the scaling factor, and CLKt is the time period of the clock used for timing quantization of the switching period.
The sampled value (A/D output) is related to the converter parameter as
1( , ) ( ) st
Q V IN G A e−= × (3-5)
where “A” is the amplitude of the converter parameter used as input in the describing function
G(A), “t1” models the phase delay due to the sampling process. The quantization process
involved in sampling the converter parameter is modeled using describing function analysis [55].
The describing function for the A/D quantization is expressed by the following relation [56].
37
2
1
0 2
( )4 2 1 2 1 2 11
2 2 2
LSB
nLSB
LSB LSB LSBi
qA
G Aq i n nq q A q
A Aπ =
⎧ <⎪⎪= ⎨
− − +⎛ ⎞⎪ − < <⎜ ⎟⎪ ⎝ ⎠⎩∑
(3-6)
where qLSB is the LSB equivalent of the sampled analog input, “A” is the amplitude of the analog input, and “n” is the quantization bin number in the sampling process.
The LSB equivalent is obtained from the maximum analog input amplitude (q(V,I)max), the
number of bits (NL) allocated for the step value, and the control input.
max( , )2 1LLSB N
q V Iq =−
(3-7)
Based on the static characteristic of the A/D converter, the binary equivalent of the A/D output is
equal to the bin number for which the describing function G(A) in Eq. 3-6 is satisfied.
( , )Q V IN n= (3-8)
The quantized analog output can be determined using Eq. 3-8 as
_( , )quant hardware LSBQ V I n q= × (3-9)
3.1.2 Extraction of Digital Timing Generator Parameters
The key parameters involved in the design of digital timing generator are the clock
frequency (fCLK), the count resolution (NC), and the scaling factor (NSC). The determination of the
design parameters follows an iterative procedure supplemented with simulation analysis as a
direct consequence of the non-linear relation described in (3-2).
The parameter extraction procedure begins with an initial assumption for the control input
A/D resolution namely NL=10. The digital timing generator can be evaluated with reference to
the generated time duration by determining how closely it approximates the time duration
obtained from the theoretical expression of Eq. 3-1. The performance metric for the digital
inverse timing generator, namely percentage timing error (∆error), can be defined as
38
_theoretical Digital hardwareerror
theoretical
t tt−
∆ = (3-10)
The selection of the number of bits for step value (NL) and count resolution (NC) influences
the timing accuracy between the digital and the theoretical expression for time duration. The
total hysteretic count in the digital SRM is mapped to a hysteretic voltage (Vhys). The hysteretic
voltage is selected to be much larger than the ripple on the output voltage of the DC-DC buck
converter as given in Eq. 3-11
Vhys ≥ vout_ripple (3-11)
The voltage mapping between the hysteretic voltage and the digital hysteretic count is
given as
2 CNLSB hysq V× = (3-12)
Using Eq. 3-7 in Eq. 3-12 the relation governing the number of bits for the sampled
converter parameter and the hysteretic count can be obtained.
max( , )2 2
C
L
NhysN
q V I V× ≤ (3-13)
max2
( , )L C
hys
q V IN N logV
⎛ ⎞− ≥ ⎜ ⎟⎜ ⎟
⎝ ⎠ (3-14)
In the limit of the step value approaching unity, the minimum time period of the clock to
guarantee a specified timing accuracy can be derived by using Eq. 3-2 and Eq. 3-4.
min
max
1;2 2 ( , ..)C C
theoreticalCLK CLKN N
CLK
t Kt fq V I t
= = =×
(3-15)
The current through an inductor in a power converter under continuous conduction mode is
shown in Figure 3-2 [31]. Also indicated in figure is the DC-DC buck converter inductor voltage.
39
The slope of the inductor current during the on-time (tON) and off-time (tOFF) intervals as shown
in Figure 3-2 is given by
and LToffLTon vvm mL L
−= =1 2 (3-16)
where L is the inductor value, LTonv and LToffv are the voltages across the inductor during on-time and off-time respectively.
The on/off-time of the power MOSFET switch from the Figure 3-2 can be inferred to be
; L L L LON OFF
LTon LToff
I I L I I Lt tm v m v∆ ∆ × ∆ ∆ ×
= = = =−1 2
(3-17)
The time duration expression involving the inductor voltage is equated with that of the
digital duty ratio generation expression to obtain the scaling factor. The digital timing generator
utilizes the inductor voltage of the converter to generate the duty ratio for the switches. By
equating Eq. 3-1 to Eq. 3-3 and utilizing the sampled inductor voltage ( Lbinv ) as the converter
parameter, the scaling factor can be determined.
2 CNL
Digital CLKSC Lbin L
I Lt tN v v
∆ ×= × =
× (3-18)
where Lbinv is determined using Eq. 3-6 for the given inductor voltage (Amplitude A= vL),
the quantization level max
2 1L
LLSB Lq N
vq v= =−
indicates the LSB equivalent of the sampled
inductor voltage and LN is the number of bits allocated for the sampled inductor voltage.
The scaling factor reduces to
2 CNLq
SC CLKL
vN t
L I×
= ××∆
(3-19)
3.1.3. Scaling Approaches
The scaling of the sampled inductor voltage with SCN can be carried out either by binary
multiplication or by utilizing the gain of the inductor voltage A/D signal conditioning block. The
40
two approaches are outlined in Figure 3-3 and their effectiveness is compared by evaluating the
timing error performance metric error∆ .
The scaling of the sampled inductor voltage results in a floating point binary number in
both cases. In binary multiplication based scaling, the binary point of the floating point number
is dictated by the input and the scaling factor. Hence the feasibility of this approach is affected
by the need for additional logic to keep track of the floating point location in the step value and
the overhead of binary multiplication. The alternative scaling approach efficiently separates the
scaling factor as two ratios, one of which is incorporated into the A/D converter gain block and
the other ratio is used for binary shifting. The ratios are indicated in the following equation.
_2
2
B
B
N
SC SC hardware N
NR NRN NDR DR
≅ = = × (3-20)
The ratios are based on the following set of conditions that ensures maximum number of
bits for the fractional portion of the step value to aid in timing accuracy.
( )2 2; 1 and log2 B BN
NRDR power of N ceil NR= < = ⎡ ⎤⎢ ⎥ (3-21)
The ratio formed using “NR” and 2 BN is incorporated into the A/D signal conditioning
circuit gain. On the other hand the ratio formed between 2 BN and “DR” forms the binary shifting
ratio. Hence, this approach eliminates the need for binary multiplication and additional logic
required for tracking the initial floating point location. The sequential steps involved in the step
value generation for the two approaches are illustrated in Table 3-1 for a given input. The
parameter values used for illustration are NL=10, tCLK=40ns, q(V,I)max=12, and 66.2 10K −= × .
The scaling factor obtained from Eq. 3-19 is 31.21 10SCN −= × and it is approximated as 5/ (212)
to aid in binary operations. The various approximations for the scaling factor are determined
from Eq. 3-21 and the optimum value is chosen by evaluating the timing error performance
41
metric. In Figure 3-4 various scaling factor approximations are considered and the optimum
value (5/212) is determined based on the criteria of minimum timing error (less than 2% over
most of the input range).
Considering the data in Table 3-1, in binary multiplication scaling, the A/D output is
multiplied with the numerator (NR) of NSC. The multiplied result (i.e. 882X5=4410) is construed
as a floating point binary number with the virtual binary point dictated by the denominator of
NSC. The step value is truncated to NL =10 bits, resulting in 1.076= 1 X 20+0 X 2-1+0 X 2-2+0 X
2-3+1 X 2-4+0 X 2-5+0 X 2-6+1 X 2-7+1 X 2-8+1 X 2-9. In the A/D gain scaling approach, the ratio
of (5/23) is included in the A/D block. The scaling factor inclusion modifies the A/D gain as
( ) ( )3/ 5 / 2A D Gain × and results in the output of (551)10 for the given input. The output is
considered as a floating point binary number with the binary point location determined by the
binary shifting ratio, namely (23/212). Thus the step values are similar in both the cases while the
latter approach eliminates the need for binary multiplication. It also avoids the need for
additional logic to keep track of the initial floating point location in the step value. It allows for a
constant initial floating point location over the entire input range. The parameter ∆error is
determined for the two approaches and indicated in Figure 3-5. From Figure 3-5 it is evident that
A/D gain scaling can yield the minimum percentage error over the entire input range. Hence A/D
gain scaling is used in the experimental implementation of the digital timing generator. The
difference in time duration from the theoretical expression of Eq. 3-2 arises from the fact that the
scaling factor is approximated using Equations 3-20 and 3-21. This timing error is modeled
along with the timing error resulting from the successive accumulation and described in the
following section.
42
3.1.4. Successive Accumulation
The successive accumulation is carried out by proper alignment of the integer and
fractional portion of the step value with that of the accumulator output. The control logic in
Figure 3-1 ensures the alignment of the integer/fractional portion based on the carry output from
the accumulator. A carry output of “1” from the accumulator indicates an increment in the
integer portion requiring an additional bit for its representation. The step value is logically
shifted to the right by one bit with an insertion of a “0” bit at the MSB location. Similarly the
accumulator output is shifted to the right by one bit with an insertion of “1” bit at the MSB
location. The LSB bit is discarded in the above set of operations to truncate the result to NL bits
of precision. A barrel shifter is used to extract the integer portion of the accumulator output and a
digital comparator is used to compare with 2 CN . The above set of operations involved in the
successive accumulation is explained with the snapshot of the accumulator and input registers
shown below.
Considering an inductor voltage input of vL=5V and using the derived scaling factor of
( ) ( )3 3 125 / 2 2 / 2SCN = × the step value can be determined to be
( ) ( ) ( )3
1210 2
55 285 266 0,10000101012 /1023 2L stepv V q round
⎛ ⎞×⎜ ⎟= ==> = = × =⎜ ⎟
⎜ ⎟⎝ ⎠
(3-22)
Let ACC[k] and qstep[k] represent the accumulator output and the step value at the “kth”
clock instant. A snapshot of the sequence of operations occurring in the accumulator is indicated
below.
43
( ) ( ) ( )
( ) ( )( ) ( )
( ) ( )( )
10 2 10
2 10
2 10
2 10
2
266 0,100001010 0.51953
[1] 0,100001010 0.51953
[1] 0,100001010 0.51953 +
[2] 1,000010100 1.0390625
[2] 0,100001010 0.
step
step
step
q
ACC
q
ACC
q
= ==> =
==> ==>
==> ==>
− − − − − − − − − − − − − − − − − − − − − − − − − −
==> ==>
==> ==> ( )
( ) ( )( ) ( )
( )
( )
10
2 10
2 10
2
2
51953 +
[3] 1,100011110 1.55859
[3] 0,100001010 0.51953 +
[4] 0,000101000 and CY=1
[4 ] 10,00010100 2.0781
step
ACC
q
ACC
ACC +
− − − − − − − − − − − − − − − − − − − − − − − − − −
==> ==>
==> ==>
− − − − − − − − − − − − − − − − − − − − − − − − − −
==>
==> ==> ( )( ) ( )
10
2 10
25
[4 ] 00,10000101 0.51953stepq + ==> ==>
The ACC[4+] and qstep[4+] indicate the accumulator output and step values that are
modified to account for the carry generated at k=4 clock instant.
The timing error due to the various quantizations can be modeled as the increase in the
quantized amplitude produced at the A/D output. The difference in time duration (tDigital_diff) from
the theoretical expression is indicated in Figure 3-6. The change in the quantized amplitude of
the inductor voltage can be modeled by the following equation.
_ __
Lquant amp hardwaretheoretical Digital diff
Kvt t
=+
(3-23)
The resulting amplitude modeling the quantization error can be determined from Equations
3-6, 3-7 and 3-8. The digital timing expression including the various truncation and quantization
errors is indicated in Eq. 3-24.
44
__ _
2 CN
Digital hardware CLKSC hardware Lbin hardware
t tN v
= ××
(3-24)
where _Lbin hardwarev n= for which the amplitude _ _Lquant amp hardwarev satisfies Eq. 3-6. The MATLAB function modeling the quantization is given in Appendix A.
3.2 Architecture of Digital Synthetic Ripple Modulator
In conventional PWM control, the output variable is regulated by comparing a modulating
function with that of a carrier signal. The comparison process effectively modulates the time
duration of a pulse controlling the on/off position of a switch which in turn determines the duty
ratio. In synthetic ripple modulation, the carrier signal utilized in the comparison process is
derived from a system parameter unlike the traditional approach of using external oscillators.
The modulation strategy is based on bonding the error between the controlled variable and
a command variable to a synthetic ripple derived by filtering any ac waveform of the system.
The combination of the error and the synthetic ripple forms the carrier signal (modulator output)
which is bounded between hysteretic limits. The hysteretic limits dictate the on/off time duration
of the switches in the system. Synthetic ripple modulation also allows open-loop linear control of
an output variable with reference to a command input. Since the modulation scheme derives the
carrier signal from the system parameter, it enables natural feed-forward control. This
modulation scheme when applied to the control of DC-DC converter or DC-AC inverters, the
output voltage of a voltage regulator or the rotor speed in a motor drive can be controlled. In
such applications the on/off-time or the duty ratio of the power MOSFET switches can be
inversely related to a control voltage input as given in Eq. 3-1 or Eq. 3-2. Thus, the above
mentioned digital timing generator can be used for generating the duty ratio. The generic
architecture of a digital synthetic ripple modulator controlling a desired output variable in a
system is illustrated in Figure 3-7.
45
As indicated in Figure 3-7, the system parameter related to the duty ratio is sampled and
given as input to the digital timing generator. The digital timing generator scales the sampled
input and generates the step value. The step value is successively accumulated between the
hysteretic limits and the required duty ratio is generated. The PWM output is set to logic high or
“1” when the modulator output exceeds the upper hysteretic threshold ( 12 CN − ). The PWM output
is set to logic low or “0” when the modulator output is lesser than the lower hysteretic threshold
( 12 CN −− ).
( )( )
1
1
1 2
0 2
C
C
N
N
Modulator OutputPWM
Modulator Output
−
−
⎧ ≤ −⎪= ⎨≥ +⎪⎩
(3-25)
The PWM signal is retained in logic 1 or logic 0 when the modulator output is outside the
hysteresis band. The PWM signal is set to the appropriate logic level once the modulator output
is within the hysteresis band based on Eq. 3-25 and normal SRM operation is resumed.
The generic expression modeling the synthetic ripple modulator in the analog domain is
given in Eq. 3-26.
_ ModulatorOutput Analog Output Variable Synthetic Ripple= + (3-26)
The modulator output forming the carrier signal is modulated between the hysteretic limits
given as
( )( )
2
2
Modulator Command variable Hys
Modulator Command variable Hys
+
−
= +
= − (3-27)
where Modulator+ and Modulator− are the higher and lower hysteretic thresholds in the analog domain and Hys indicates the hysteresis band.
The schematic representation of Equations 3-26 and 3-27 is shown in Figure 3-8. The
subtraction of the command variable from the modulator output expression of Eq. 3-26 modifies
46
the hysteretic thresholds to (+Hys/2) and (-Hys/2). The modulator output expression is changed
accordingly as
( )_ ModulatorOutput Analog Command Output Command
SyntheticRipple− = − +
(3-28)
In the digital SRM implementation, the error resulting from the difference between the
command variable and the output variable is sampled by an A/D converter. The sampled error
value (Error_binary) indicated in Figure 3-7 and the synthetic ripple information from integer
value of the accumulator are used in the formulation of digital SRM modulator expression. The
digital SRM modulator output is given as
( ) _ Modulator Output Error binary Integer Value= + (3-29)
In the digital SRM, the sampling of the error value between the command and output
variable instead of the actual output variable provides the benefit of allocating higher number of
bits for the error. It also offers the benefit of controlling the output variable with better precision.
The dynamics of the SRM is also enhanced by the fact that when the sampled value of the error
between output and command variable exceeds its higher or lower quantization levels [saturation
limits of the A/D (e.g. 0 or 255 with 8 bits of precision)], the PWM signal can be immediately set
to logic “1” or logic “0” depending on the saturation limits. The subtraction of the command
variable from Eq. 3-26 as explained earlier modifies the digital SRM hysteretic thresholds as
( )12 CN − and ( )12 CN −− with the “Hys” level in analog SRM mapped to 2 CN in the digital SRM.
The integer value from the accumulator spans from 0 to 2 CN during both the on-time and off-
time durations. Thus, to account for the modified hysteretic thresholds, the terms ( )12 CN − and
( )12 CN −− are added to the digital SRM modulator expression during the off-time and on-time
47
duration respectively. This ensures that with the integer value spanning from 0 to 2 CN , the
modulator output is always modulated with a hysteretic level of 2 CN . The resulting digital SRM
modulator expression is given in Eq. 3-30.
( )( )
1
1
2 _ [ ] [ ] ; 0
2 _ [ ] [ ] ; 1
C
C
N
N
Error binary n Integer Value n PWMModulator Output
Error binary n Integer Value n PWM
−
−
⎧ − − =⎪= ⎨− − + =⎪⎩
(3-30)
In the expression describing the digital SRM modulator, Error_binary[n] indicates the
sampled error voltage of the output A/D and Integer Value[n] is the integer output extracted from
the accumulator at tCLK instant “n”. Considering the modulator expression Eq. 3-30,
Error_binary is negative when the output voltage is above Vcmd. Thus when PWM =1, the higher
hysteretic threshold will be attained earlier and Integer Value will span to less than 2 CN resulting
in reduced on-time. Similarly when Vout is less than Vcmd, Error_binary is positive causing
Integer Value to span to 2 CN , resulting in increased on- time. Similar argument can be applied
for the factor of ( )12 _CN Error binary− − during PWM=0. A low-pass filtering effect similar to
integration is obtained in the digital timing generator’s accumulator during floating point
addition by discarding the least significant bits. Thus the Integer Value[n] qualitatively
represents the low-pass filtered output of the sampled converter parameter.
3.3 Application Illustration of the Digital Synthetic Ripple Modulator
The DSRM architecture is illustrated below with reference to an application. The
modulation strategy is used in the output voltage control of a synchronous buck DC-DC
converter. The architecture of the digital SRM controlled synchronous buck DC-DC converter is
shown in Figure 3-9. The specifications of the DC-DC converter are outlined in Table 3-2.
The DC-DC buck converter controlled by the digital SRM operates in three distinct modes.
48
• Mode 1: When the error between the output voltage (controlled variable) and command voltage exceeds the upper hysteretic limit ( )12 CN − , the VPWM signal is set to logic “0” or the UFET switch is turned OFF. The switch is retained in this position until the error reduces to within the hysteretic band.
• Mode 2: When the error is within the hysteretic band, the digital synthetic ripple modulator controls the converter output voltage.
• Mode 3: When the error falls below the lower hysteretic limit ( )12 CN −− , the VPWM signal is set to high or the UFET switch is turned ON. The switch is retained in this position until the error returns to the hysteretic band.
The digital SRM employs hysteretic mode of control with switching frequency variations,
the on-time and off-time of the high-side MOSFET (UFET) is given in Eq. 3-17 and repeated
here for clarity
; ON OFF
L LON OFF
LT LT
I L I Lt tv v∆ × ∆ ×
= = (3-31)
where LI∆ is the peak-to-peak inductor current ripple under steady-state conditions, vLTon and
vLToff are the inductor voltages during the on-time and off-time respectively. From this the duty
ratio can be derived as
ON
ON OFF
tdt t
=+
(3-32)
From Eq. 3-31 it can be inferred that the on/off time duration can be generated using the
digital timing generator with the inductor voltage as the system input parameter for the DSRM.
The output voltage of the synchronous buck converter is the variable to be controlled by the
digital SRM. The output voltage of the buck converter is related to the generated duty ratio as
given in Eq. 3-33. The output voltage is controlled by modulating the duty ratio of the DC-DC
buck converter.
( ) ( ) ( )out inv t d t v t= × (3-33)
49
The design of the complete system involves the design of L-C output filter and the digital
SRM controller.
3.3.1 Design of Buck Converter-Output LC filter
The buck converter is designed with an input voltage of 5V and an output voltage of 1.5 V.
The L-C filter design assumes a switching frequency for the converter to be 1 300 SS
f kHzT
= = .
The converter output current is assumed to have a nominal value of 4 A. Using steady-state
analysis for a buck converter, 4 L outI I A≈ =
The peak-peak inductor current ripple, 16%( ) 0.64L hys LI I I A∆ = = =
_ min 1.5 out no alV V= , _ min 5 in no alV V= , 0.375 LoadR = Ω , 10Lr m= Ω (3-34)
The steady-state duty ratio based on the averaged PWM-switch model [57] can be derived
from Eq. 3-35.
( )diodeinLLoad
Loadout VDDV
rRR
V '−×⎟⎟⎠
⎞⎜⎜⎝
⎛+
= (3-35)
Thus, the steady-state duty ratio can be determined to be D=0.39.
The design of the output filter parameters is based on current ripple requirements and
transient regulation requirements. The output filter inductor is determined from the inductor
current ripple [58].
(1 )out S
hys
V D TLI
× − ×= (3-36)
61.5 (1 0.39) 3.33 10 4.760.64
L Hµ−× − × ×
= = (3-37)
The design of output filter capacitor is based on transient and output voltage ripple
requirements. Considering the change in the inductor current for a buck converter during a load
50
step-up and step–down transient as shown in Figure 3-10, the inductor current slope can be
derived.
: During step-up transientin outL v vdidt L
−= (3-38)
: During step-down transientoutL vdidt L
−= (3-39)
From Equations 3-38 and 3-39 it can be concluded that the output-voltage overshoot
during a load-step down transient sets the limit on the transient performance of the converter
[58].
In order to keep the output voltage outV within regulation range outV∆ during a load-
transient of maxoutI∆ , the minimum required output filter capacitance [58] can be obtained as
2max
min1 12
o F
out out out
I LCV V di dt
⎛ ⎞∆= × × −⎜ ⎟∆ ⎝ ⎠
(3-40)
For a voltage deviation of 60outV mV∆ = and max 4oI A∆ = , the minimum output
capacitance is determined.
min 415C Fµ= (3-41)
3.3.2 Design of Digital Synthetic Ripple Modulator
The digital SRM controller involves the design of digital timing generator and the
resolution of the output variable A/D converter.
3.3.2.1 Digital timing generator
The design of the digital timing generator involves the determination of key parameters,
namely the input clock frequency (fCLK), count resolution (NC), scaling factor (NSC) and the step-
value resolution (NL). The resolution for the A/D converter is assumed to be NL =8 bits. The
count resolution can be determined from Eq. 3-14.
51
max2
LL C
hys
VN N logV
⎛ ⎞− ≥ ⎜ ⎟⎜ ⎟
⎝ ⎠ (3-42)
( )( )max max 1 5% 5.25 L in inV V V V= = + × = (3-43)
Assuming ( ) ( )_320 >> 60 hys out rippleV mV v mV= =
25.25 ; 320
320 L C hysN N log V mVmV
⎛ ⎞− ≥ =⎜ ⎟⎝ ⎠
(3-44)
25.25
320 L CN N logmV
⎛ ⎞− ≥ ⎜ ⎟⎝ ⎠
(3-45)
4 8 4L C L CN N N N− ≥ ⇒ = ⇒ = (3-46)
By comparing Equations 3-2 and 3-18 the parameter K can be determined to be
60.64 4.76 3.046 10LK I L A Hµ −= ∆ × = × = × (3-47)
In a buck converter the maximum voltage across the inductor can occur during startup or
during an output short circuit. The inductor voltage under these conditions can be derived using
Table 3-2 to be
L in outv V v= − (3-48)
max max 05.25
outL in V
V V V=
= = (3-49)
The minimum time period of the clock required to guarantee minimum time duration
accuracy as determined from Eq. 3-15.
6
4max
3.046 10 36.26 2 2 5.25CCLK N
L
Kt nsV
−×= = =
× × (3-50)
The experimental implementation of the digital timing generator utilizes the onboard
oscillator from the ALTERA UP2 board [59]. The time period of the clock used for the digital
timing generator
52
__
125.175 39.72 OSC ALTERA CLKOSC ALTERA
f MHz t nsf
= ⇒ = = (3-51)
The scaling factor can be determined from Eq. 3-19 to be
48
9 36
5.2522 2 1 39.72 10 4.2955 103.046 10
CNLq
SC CLK
vN t
K− −
−
⎛ ⎞×⎜ ⎟× −⎝ ⎠= × = × × = ××
(3-52)
Due to restricted availability of the hardware resources, values of NL=8 and NC=4 results
in percentage timing error less than 8%. The buck converter application can tolerate this
percentage of timing error due to the delays involved in gate driver and the power MOSFETs.
As discussed earlier the experimental implementation utilizes A/D gain block scaling to
minimize the ∆error parameter. The scaling factor of Eq. 3-52 can be approximated based on the
conditions stated in Equations 3-20 and 3-21.
4
11 11
9 9 22 16 2SCN = = × (3-53)
In the above scaling factor, the ratio (9/16) is incorporated into A/D gain and the ratio
(24/211) is used to interpret the A/D output as being binary shifted to the left by 4 bits followed
by a binary shift to the right by 11 bits. This effectively provides a binary shift to the right by 7
bits. Hence, the 8 bit A/D output is construed as a floating point binary number with 1 bit for the
integer portion and 7 bits for the fractional portion.
The approximation of the scaling factor indicated in Eq. 3-53 also influences the timing
accuracy between the theoretical and the digital timing generation approach. The possible scaling
factors which closely approximate the estimated value are indicated in Table 3-3. Similarly the
binary shifting ratios determining the initial binary point location for the step value are also
indicated in Table 3-3. The optimum approximation for the scaling factor can be deduced by
evaluating the timing error performance metric as indicated in Figure 3-11. The final count value
53
to which the respective step values are accumulated in each case is modified to reduce the
percentage timing error. The plot of Figure 3-11 indicate that timing errors less than 6% can be
obtained for the parameter ∆error with NSC=(9/211), thereby yielding the factor for the
experimental implementation.
3.3.2.2 Output voltage A/D resolution
The output voltage of the buck converter during the interval when the upper MOSFET
(UFET) is ON is given to be
out in Lv v v= − (3-54)
out in Lv v v∆ = ∆ −∆ (3-55)
If the input voltage of the buck converter is assumed to be a constant value
out Lv v∆ ≅ −∆ (3-56)
The above equation can be interpreted in the digital domain to be the change in output
voltage caused by a single LSB change in the inductor voltage. The above equation can be used
to derive the limit-cycle oscillation constraint [6] [56]. The duty ratio change caused by a single
LSB change in the inductor voltage must be less than the output error-voltage A/D LSB change.
The error between the output voltage and the command voltage is given by
error cmd outv v v= − (3-57)
The maximum value of the error voltage can be determined based on the dynamic response
requirement. Considering the modulator expression of Eq. 3-30 the maximum value of
Error_binary determines how fast the modulator reacts to a transient condition (load step-up or
step-down). The error voltage between the command and the output voltage is sampled based on
the A/D transfer characteristic shown in Figure 3-12. Under a load step-up or step-down transient
condition, the maximum value for the A/D output (Error_binary ) in either direction is ( )2 1EN −
54
or ( )2 EN− . The magnitude of this maximum value should be such that the term
( )12 _CN Error binary− − in Eq. 3-30 attains the higher or lower hysteretic threshold to trigger the
PWM comparator. Thus, the maximum allowable error voltage is given to be
maxerr hysV V≤ (3-58)
Using Vhys value of Eq. 3-44 in Eq. 3-58
max 320 errV mV≤ (3-59)
The LSB of the inductor voltage is given as max
2 L
LLq N
Vv ≈ , and the LSB of the error voltage is
given to be max
2 E
errerrq N
Vv =
Lq errqv v≤ (3-60)
max max
2 2L E
L errN N
V V≤ (3-61)
max2
max
int log LL E
err
VN NV
⎡ ⎤⎛ ⎞− ≥ ⎢ ⎥⎜ ⎟
⎝ ⎠⎢ ⎥ (3-62)
where maxLV is the maximum inductor voltage, NE is the resolution of the output error voltage
A/D converter and NL is the number of bits used for the step value in the digital timing generator.
Hence in a digital synthetic ripple modulator, to avoid limit-cycle oscillation, the above
conditions need to be satisfied. The above equations when applied to buck converter
specifications from Table 3-2 would yield the following results.
5 25 and V 320 Lmax err maxV . V mV= = (3-63)
- 4L EN N ≥ (3-64)
55
The number of bits required for the output error voltage A/D is determined from static
regulation requirements. The error voltage resolution must be greater than that of the inductor
voltage resolution to ensure that the change in output voltage is tracked by the digital timing
generator. Thus, the number of bits to be allocated for the error voltage A/D converter in order to
provide a resolution of verrq=30 mV ( ( )20.588 errq Lqv v mV≥ = ) is determined to be
max2int log
30 err
EvN
mV⎡ ⎤⎛ ⎞= ⎜ ⎟⎢ ⎥⎝ ⎠⎢ ⎥
(3-65)
4EN = (3-66)
Using Equations 3-64 and 3-66, the NL can be determined to be NL = 8.
3.4 Modeling and Simulation of Digital SRM Based Buck Converter
The buck converter controlled by the Digital Synthetic Ripple modulator involves both
digital and analog blocks, which are modeled using MATLAB and Simulink [58] [60-62]. The
choice of MATLAB/Simulink allows easier system-level implementation of the digital SRM,
integrating the continuous-time output filter, switching PWM action, and the digital controller.
The buck converter shown in Figure 3-7 comprises of three major components namely the PWM
switch, the output L-C filter, and the digital SRM controller. The modeling of each of these
components is explained in the following sections.
3.4.1 Modeling of PWM Switch
For a Buck converter, based on the PWM gate drive, the input to the LC filter is either the
input voltage (Vin) or the voltage drop across the synchronous rectifier (catch diode voltage
(Vdiode) can be used if a catch diode is used instead of the synchronous rectifier) neglecting the
drop across the UFET MOSFET. Hence the converter is modeled as a switch driving the output
filter, with the switch outputs decided based on PWM signal (Vin when switch is ON and Vsync_rect
56
when switch is OFF). The on-time and off-time of the PWM switch is determined from the
timing signal VPWM, the output of the digital SRM controller. The Simulink model is indicated
in Figure 3-13.
3.4.2 Modeling of Output LC filter
The output LC filter network with input voltage phasev , input current Li and output voltage
outv is described by the following set of equations.
inphase out L L
diL v v i rdt
= − − (3-67)
cL out
dvC i idt
= − (3-68)
( )out C C L outv v r i i= + − (3-69)
where Cr and Lr are the equivalent series resistance of the output capacitor and DC resistance of
the inductor respectively. The above set of equations is incorporated into the Simulink model of
the Buck filter shown in Figure 3-14.
3.4.3 Modeling of Digital SRM Controller
The modeling of the digital SRM controller involves the A/D converter modeling, digital
timing generator modeling. It also includes the generation of the modulator output which
combines the output error voltage and the digital timing generator output.
The A/D converter or the quantizer model [61-65] is based on the LSB equivalent of the
A/D converter. The A/D converter model is shown in Figure 3-15. The zero order hold is used
for sampling, the quantizer is used for rounding to the nearest integer, and the saturation block
limits the lower and higher digital output levels as specified.
The A/D gain used for sampling the inductor voltage is based on the scaling factor.
57
8
( )1 1 9/ 27.325.252 162 1
B
scN
Lq
Num NA D Gainv
= × = × =⎛ ⎞⎜ ⎟−⎝ ⎠
(3-70)
where Lqv is the LSB equivalent of the inductor voltage, max
2 1L
LLq N
vv =−
. The lower and
higher digital output levels of inductor voltage A/D are 0 and 255.
The A/D gain used in the sampling of the error voltage between output voltage and
command reference is given as
max
1 2 1/ 16.756EN
errq err
A D Gainv v
−= = = (3-71)
The lower and higher digital output levels of the error voltage A/D are -16 and +15 based
on whether the output voltage is higher or lesser than the command voltage.
The digital timing generator as described earlier utilizes the sampled inductor voltage to
generate the on-time/off-time. The timing generator is modeled with Level 2 M-file S function
utility in Simulink [66]. The block accepts the sampled inductor voltage, timing generator enable
signal and the initial binary point location. The accumulated value, integer value, the current step
value, and the carry output are fed back as inputs to the timing generator block. The carry output
indicates the number of bits currently used for the integer portion of the accumulator output. The
Simulink model is indicated in Figure 3-16.
The modulator output is derived from the generic architecture expression of Eq. 3-30,
( )( )
+8 - VerrAD[n] - Integer_val[n] ; PWM=0mod_op =
-8 - VerrAD[n] + Integer_val[n] ; PWM=1
⎧ ⎡ ⎤⎪ ⎣ ⎦⎨⎡ ⎤⎪ ⎣ ⎦⎩
(3-72)
The system implementation of the synchronous buck converter controlled by the digital
SRM modeled in MATLAB/Simulink is shown in Figure 3-17.
The buck converter waveforms are depicted in Figure 3-18. The waveforms indicate the
inductor voltage (vL), inductor current (iL), output voltage (vout) and the phase voltage (vphase) for
58
a command input of vcmd=1.3 V. As seen from the waveforms, the inductor voltage during the
UFET on-time is 3.66 ONLTv V= and that during the off-time is 1.54
OFFLTv V= − . The output
voltage under the steady-state condition can be determined to be 1.34 outv V= . The on-time and
off-time duration corresponding to these voltages based on the theoretical expression of Eq. 3-17
are 1.027µs and 2.44µs. The step value for accumulation, the accumulator output, and the PWM
signal are indicated in Figure 3-19.
The on-time and off-time duration from the simulation waveforms can be determined to be
1.1 µs and 2.6 µs. The parameter error∆ can be determined to be less than 7% when comparing
the generated time duration with that of the theoretical expression. The step value obtained in the
waveforms during the on-time and off-time can be derived as given in Equations 3-73 and 3-74.
( ) ( )_ 10 2
8
93.6616 100 0,1100100 0.78125
5.252 1
LON STEPVALv round
⎛ ⎞⎛ ⎞×⎜ ⎟⎜ ⎟⎝ ⎠⎜ ⎟= = = ⇒⎛ ⎞⎜ ⎟⎜ ⎟⎜ ⎟−⎝ ⎠⎝ ⎠
(3-73)
( ) ( )_ 10 2
8
91.5416 42 0,0101010 0.328
5.252 1
LOFF STEPVALv round
⎛ ⎞⎛ ⎞×⎜ ⎟⎜ ⎟⎝ ⎠⎜ ⎟= = = ⇒⎛ ⎞⎜ ⎟⎜ ⎟⎜ ⎟−⎝ ⎠⎝ ⎠
(3-74)
The actual step values without A/D gain block scaling while based on multiplication can
be determined to be
( )10
8
3.66/ 1785.252 1
A D output round
⎛ ⎞⎜ ⎟⎜ ⎟= =⎛ ⎞⎜ ⎟⎜ ⎟⎜ ⎟−⎝ ⎠⎝ ⎠
(3-75)
( ) 3_ _ 10
178 4.2955 10 0.7645LON STEPVAL MULTv −= × × = (3-76)
59
( )10
8
1.54/ 755.252 1
A D output round
⎛ ⎞⎜ ⎟⎜ ⎟= =⎛ ⎞⎜ ⎟⎜ ⎟⎜ ⎟−⎝ ⎠⎝ ⎠
(3-77)
( ) 3_ _ 10
75 4.2955 10 0.322LOFF STEPVAL MULTv −= × × = (3-78)
By comparing Equations 3-73 and 3-74 with Equations 3-76 and 3-78 respectively, it is
evident that the A/D scaling closely approximates the required step value.
The time duration generated using the digital timing generator is compared with the
theoretical expression and plotted in Figure 3-20. The percentage error is compared in Figure 3-
21.
3.4.4 Simulation of Adaptive Voltage Position for Digital SRM based Buck Converter
Adaptive voltage position (AVP) is an essential function of low-voltage VRM designs. The
AVP concept utilizes the entire voltage tolerance window during a step-down or step-up load
transient [67]. In AVP, the output voltage is positioned at a voltage level slightly higher than the
minimum value (Vout_min) at full load. Similarly the output voltage is positioned at a voltage level
slightly lower than the maximum value (Vout_max) under light load conditions. The AVP design
was simulated in MATLAB/Simulink and needs to be experimentally verified in future.
The AVP specs are Vin=5 V, Vout=1.55 V, and ∆Iout=5 A. The step-down load transient is
considered with a load current slew rate of 50 A/µs. The maximum load current change is
specified as 5 outI A∆ = and the assumed Rdroop=16 mΩ. The output voltage change under a step-
down transient is illustrated in Figure 3-22 indicating the inductor current, load current, capacitor
current and the allowed voltage tolerance window. For AVP, it is evident from Figure 3-22 that
the output voltage resonates to the maximum value when the load current reaches zero. This is
due to the fact that once the load current is zero, the inductor current flows into the output
60
capacitor to charge it to Vout_max. In the digital SRM, the AVP can be easily implemented by
turning off the UFET during the step-down load transient and turning on the UFET once the
inductor current reaches zero.
The required voltage tolerance window can be determined as,
max_ 5 16 20 100 out required out droop toleranceV I R V A m mV mV∆ = ∆ × + = × Ω+ = (3-79)
The L and C are designed such that the output voltage resonates within the tolerance
window. The inductor design is based on the ripple spec and given to be
( ) ( )1 1LToff S out S
L L
v D T V D TL
I I× − × −
= =∆ ∆
(3-80)
1.55 ; / 1.55 / 5 0.31; 0.4 ; 600 out out in L SV V D V V I A f kHz= = = = ∆ = =
( )1.55 14.7 S
L
D TL H
Iµ
× −= ≈
∆ (3-81)
During the load-step transient the output voltage change occurring across the capacitor is
given by
_ _ max _out C out out ESRV V V∆ = ∆ −∆ (3-82) where ∆Vout_ESR is the change in Vout due to the ESR of the output capacitor (C) and ∆Vout_C is the voltage change across the capacitor due to the load current change of ∆Iout.
( )_ _ max _ 100 (5 5 ) 75 out C out outV V I esr C mV A m mV∆ = ∆ − ∆ × = − × Ω = (3-83)
The charging time for the output capacitor can be determined from the load current change
and the slope of the inductor current during off-time for a buck converter. The AVP design
utilizes a load step of 5A at a slew rate of 50 A/µs. Thus ∆Iout=5 A.
_out
LToff buck outCHG
Iv V Lt∆
= − = − (3-84)
4.7 5 15.16121.55
outCHG
out
L I H At sV
µ µ×∆ ×= = = (3-85)
61
Thus, the net charge in the capacitor due to the load current change is given as
12 CHG outQ t I∆ = × ×∆ (3-86)
The capacitor value can be determined from Equations 3-83 and 3-86 as
( )( )
( )2 2
_ _
5 4.71 1 4002 2 1.55 95
out
out C tolerance out out C tolerance
I LQC FV V mVV V V
µµ
∆ × ×∆= = × = × =∆ + ×× ∆ +
(3-87)
The capacitor used is 425µF. The capacitor current is shown in Figure 3-22 and can be
derived as
( ) outC out
CHG
Ii t I tt
⎛ ⎞= − ⎜ ⎟
⎝ ⎠ (3-88)
( )1( ) ( ) _ ( ) OUT C Cv t i t esr C i tC
= + ×∫ (3-89)
At the instant when Vout peaks, dVout/dt=0. Thus, the instant at which Vout peaks can be
determined from Equations 3-88 and 3-89.
( ) ( )_ _ 15.1612 5 425 13.0362 Vout peak CHGt t esr C C s m F sµ µ µ= − × = − Ω× = (3-90)
Using the time duration determined from Equation 3-90, the slew rate for the command
signal can be determined as shown in Equation 3-91.
_ max
_
100_ _ 7.6713.0362
outcmd
Vout peak
V mVSlew rate v mV st s
µµ
∆= = = (3-91)
The UFET need to be turned on after 13.0362 µs based on the time duration from Eq. 3.90.
This can be accomplished by modifying the original hysteretic count of 2 16CN = under the load
transient condition. The change in the hysteretic count to turn on the UFET at the instant when
Vout peaks is determined from Eq. 3-96.
The inverse timing generator expression in the digital SRM timing is given as
62
2 CNCLK
DigitalSTEP
ttq×
= (3-92)
Under the step-down load transient condition, the voltage across the inductor is the output
voltage, 1.55 LToff outv V V= − = − . The step value used for the successive accumulation under the
given load condition is given to be
( )1
1.55 / 5.25 / 2550.58816 0.6
2 128L
out
LqSTEP N
Vv
q −
⎛ ⎞⎜ ⎟⎜ ⎟⎝ ⎠= = = ≈ (3-93)
Hence to turn on the MOSFET after the time duration determined from Eq. 3-90, the
modification in the hysteretic count can be determined as
CLKVout_peak
STEP
Hys_Count×t =tq
(3-94)
13.0362 0.6Hys_Count 196 ; 40 40 CLK
s t nsnsµ ×
= = = (3-95)
Thus, the increment in the hysteretic count is determined to be
CN
Hys_count 196Modified Hysteretic count= = =132 16
⎡ ⎤⎢ ⎥⎢ ⎥
(3-96)
In the digital SRM implementation the hysteretic count of 2 16CN = is carried out for 13
additional cycles to determine the turn on instant of the UFET. A counter increments the
modified hysteretic count each time the digital timing generator output, namely, Integer_value,
reaches 2 16CN = . The error voltage between the command signal and the output voltage is
sampled by an A/D converter with NE=4 bits of precision and one additional bit for sign
representation (error voltage (+ve) when Vcmd>Vout and (-ve) when Vout > Vcmd ). The
maximum error voltage is determined from Eq. 3-59. The error voltage A/D resolution is
sufficient enough to track the output voltage change under the load transient. The error_binary
63
signal can have oscillations due to the output voltage not exactly coinciding with the peaking of
the command signal (caused due to overshoot or undershoot). Because of the flexibility of digital
control, the digital SRM compares the current error_binary signal to a range of error_binary (+1,
0, -1) values based on the error voltage resolution of verrq=30 mV. Thus to determine the turn on
instant of the UFET, the modulator compares the modified hysteretic count to the required value
of 13 and also compares the error_binary signal to the allowed digital tolerance band. When the
required hysteretic count and the range of error values coincide, the UFET is turned on. The
simulation outputs for the modified hysteretic count based AVP implementation of the digital
SRM is shown in Figure 3-23 and Figure 3-24. In Figure 3-23, the inverse timing generator
output (integer_value), the modified hysteretic count, and the error_binary signal are shown. As
evident from Figure 3-23, integer_value spans to the count of 32 for 6 cycles and an additional
count of 16 resulting in 13 cycles of the original hysteretic count ( 2 16CN = ). From the figure it is
also evident that the error_binary signal at the vicinity of turning on the UFET lies within the
allowed digital tolerance band. In Figure 3-24, the output voltage, inductor current, modulator
output and the command signal are indicated. The overshoot evident in the output voltage is
within the allowed tolerance band of 20 mV. The modified hysteretic count changes the lower
hysteretic threshold as -208 ( 2 13CN= − × ). The resulting modulator output is also indicated in
Figure 3-24. The inductor current, output voltage, modulator output are indicated in Figure 3-25
for a load step-up condition. A load current step of 5 A is used and the resulting AVP of the
output voltage is indicated. Similar to a load-step down transient the hysteretic count is modified
to 208 (=16X13) during the load transient. The upper MOSFET is turned off when the modified
hysteretic count is reached and when the error_binary signal is within the tolerance band.
64
In the transient AVP design methodology for digital SRM, three difference cases are
considered for ramping up the command signal. The three cases are outlined below:
Case 1: The command signal is ramped up once the UFET is turned “OFF” and the slew
rate is designed such that the peaking of output voltage coincides with the higher level of Vcmd
(Vout_max). This is the optimum case of transient AVP design. Since Vcmd exactly coincides with
the peaking of output voltage, by virtue of SRM the output voltage follows Vcmd without any
overshoot or undershoots. The command signal is ramped up with a slew rate of 6.59mV/µs. The
AVP of the output voltage is indicated in Figure 3-26.
Case 2: The command signal is ramped up once the UFET is turned “OFF” and the slew
rate is designed such that Vcmd reaches Vout_max before the peaking of output voltage. In this
case the output voltage slightly overshoots and the follows Vcmd. The command signal is
ramped up with a slew rate of 11.9mV/µs. The AVP of the output voltage, inductor current,
modulator output, VPWM, and Error_binary for this case are indicated in Figure 3-27 and Figure
3-28.
Case 3: The command signal is ramped up once the UFET is turned “OFF” and the slew
rate is designed such that Vcmd reaches Vout_max after the peaking of the output voltage. In
this case the output voltage slightly undershoots due to the fact that it tries to follow Vcmd. The
command signal is ramped up with a slew rate of 5.43 mV/µs. The AVP of the output voltage,
inductor current, modulator output, VPWM, and Error_binary for this case are indicated in
Figure 3-29 and Figure 3-30.
The slew rate of the command signal in each of the above cases is designed to be less than
the modulator output slew rate. The determination of modulator output slew rate is shown below
( )mod 2 16 5.25 / 255658
500
CNLq
ON
vdV mV sdt t ns
µ× ×
= = = (3-97)
65
Since the on-time modulator output has a steeper slope when compared to off-time the on-
time slope was used above. The digital SRM provides the significant advantage of programmable
slew rate for the modulator to meet the required transient and steady-state specifications.
3.4.5 Modeling of Dynamics involved in the Digital SRM Controller for a Buck Converter
The dynamics involved in the digital SRM can be obtained from the command to duty ratio
and duty ratio to output voltage transfer functions. The dynamic system model of the digital
SRM is indicated in Figure 3-31. The duty ratio to output transfer function can be obtained from
converter system dynamics [31]. The command to output voltage transfer function can be
obtained by deriving the command to duty ratio transfer function. The command to output
voltage transfer function is thus given to be
^ ^ ^
^ ^ ^out out
cmd cmd
v v d
v d v= × (3-98)
From the digital SRM modulator expression of Eq. 3-30, the Error_binary and Integer
value can be derived based on Equations 3-5, 3-6, 3-7, 3-8, and 3-9.
( )_ error E cmd out E errError binary v G v v G N= × = − × = (3-99)
L SC LInteger Value v N G= × × (3-100)
where GL and GE are the describing function of the A/D quantizer based on Eq. 3-6 for sampling
the inductor voltage and error voltage respectively.
Thus the A/D converter model for sampling the inductor voltage is given by
1( ) stL NLG G A e−= × 3-101)
The e-st1 term models the phase delay due to the sampling process. The delay t1 is given as
1 2STt Processing delays= + (3-102)
where TS is the switching frequency and processing delays are on the order of 40-50 ns.
66
Similarly the A/D converter for the error voltage is modeled as
22( ) :
2st S
E NETG G A e t Processing delays−= × = + (3-103)
The on-time of the power MOSFET switch in a buck converter whose output voltage is
controlled by the digital SRM can be derived using Equations 3-17 and 3-29 as,
( )( )
( )( )
2 CNerr CLK hys error CLK
onSC LTon L in out SC L
N t v v tt
N v G v v N G
− × − ×= =
× × − × × (3-104)
Similarly the off-time of the power MOSFET can be derived as
( )( )
( )( )
2 CNerr CLK hys error CLK
offout SC LSC LToff L
N t v v tt
v N GN v G
+ × + ×= − = −
− × ×× × (3-105)
The resulting duty ratio is given by Eq. 3-31 and can be derived as
( ) ( )( ) ( ) ( )2
hys error out SC Lon
on off error in SC L out SC L hys in SC L
v v v N Gtdt t v v N G v N G v v N G
− × × ×= =
+ − +⎡ ⎤⎣ ⎦ (3-106)
The time varying duty ratio can be given as the sum of the DC operating point (quiescent
point) and the small signal ac component.
( )
( )
( )
^ ^ ^
^
^ ^ ^2
hys cmd cmd out out out out SC L
cmd cmd out out in SC L out out SC L
hys in SC L
V V v V v V v N GD d
V v V v V N G V v N G
V V N G
⎛ ⎞⎡ ⎤⎛ ⎞ ⎛ ⎞ ⎛ ⎞− + − + × + × ×⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎜ ⎟⎢ ⎥⎝ ⎠ ⎝ ⎠ ⎝ ⎠⎣ ⎦⎛ ⎞ ⎝ ⎠+ =⎜ ⎟ ⎧⎝ ⎠ ⎡ ⎤⎡ ⎤ ⎛ ⎞⎛ ⎞ ⎛ ⎞ ⎛ ⎞+ − + − +⎨ ⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎢ ⎥⎜ ⎟⎢ ⎥⎝ ⎠ ⎝ ⎠ ⎝ ⎠⎣ ⎦ ⎝ ⎠⎣ ⎦⎩
+
(3-107)
By cross-multiplying and grouping similar terms the following relation can be determined.
The non-linear terms involving the multiplication of 2 ac quantities are neglected.
67
( ) ( ) ( )( ) ( ) ( )( ) ( )( ) ( ) ( )
( )( ) ( ) ( ) ( )( ) ( )
^
^
^
2
2
2
hys in L in L cmd out E out L cmd out E
out cmd E in L hys L
cmd out E out L out
out L in L out L cmd
V V G V G V V G V G V V G d
D V V G D V G V G
V V G V G v
D V G D V G V G v
⎡ ⎤ ⎡ ⎤⎡ ⎤ + − − −⎣ ⎦ ⎣ ⎦ ⎣ ⎦
⎡ ⎤⎡ ⎤+ − − −⎡ ⎤⎣ ⎦⎣ ⎦ ⎣ ⎦
⎡ ⎤+ − − ⎡ ⎤⎣ ⎦⎣ ⎦
⎡ ⎤= − −⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦⎣ ⎦
(3-108)
The duty ratio to output transfer function is given as
^
^ 2
1( ) ; ; ;
1
out do outvd do o
o o
v G V CG s G Q RD LLCs sd
Q
ω
ω ω
= = = = =⎛ ⎞ ⎛ ⎞
+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
(3-109)
The above expression can be modified as
^20
^ 22 2
0
( ) out dovd
o
v G GdG ss Vs Wd s s
Q
ωω ω
×= = =
+ +⎛ ⎞+ +⎜ ⎟⎝ ⎠
(3-110)
where 20W ω= , 2
0doGd G ω= × and 0VQω
= . Using Eq. 3-110 in 3-108, the command to
duty ratio transfer can be derived as
( )( ) ( )( ) ( ) ( )( ) ( ) ( )( )
( )( ) ( ) ( )( ) ( )
^
^
2 1
2
( ) ( ) 2 4 ( )
( ) ( )
out L in L
hys in L in L cmd out E out L cmd out Ecmd
vd in L vd cmd out E vd hys L
vd cmd out E vd out L
D V G D V GdV V G V G V V G V G V V Gv
G s D V G G s D V V G G s V G
G s V V G G s V G
− −⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦=⎡ ⎤ ⎡ ⎤⎡ ⎤ + − − −⎣ ⎦ ⎣ ⎦ ⎣ ⎦
⎡ ⎤⎡ ⎤− − − −⎡ ⎤⎣ ⎦⎣ ⎦ ⎣ ⎦
− − −⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦
(3-111)
Defining the terms in the numerator and denominator of Eq. 3-103 as
68
( )( ) ( )( )
( ) ( )( ) ( ) ( )( )( )( ) ( )
( ) ( )
2 1
2
( ) ( ) 2
- ( ) ( ) (
out L in L
hys in L
in L cmd out E out L cmd out E
vd in L vd out cmd E
vd hys L vd cmd out E vd
NumA D V G D V G
DenA V V G
DenB V G V V G V G V V G
DenC G s D V G G s D V V G
G s V G G s V V G G
= − −⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦⎡ ⎤= ⎣ ⎦⎡ ⎤ ⎡ ⎤= − − −⎣ ⎦ ⎣ ⎦
⎡ ⎤= − + −⎡ ⎤⎣ ⎦⎣ ⎦
⎡ ⎤ + − −⎡ ⎤⎣ ⎦⎣ ⎦ ( ) ) out Ls V G⎡ ⎤⎣ ⎦
(3-112)
^2
^2 2 2 2
2
SW
SW SW SW SW
Ts
T T T Ts s s scmd
d Num eGdv DenA e DenB e e DenC e
s Vs W
−
− − − −
×=⎛ ⎞ ⎛ ⎞ ⎛ ⎞⎛ ⎞× + × × + × ×⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎜ ⎟+ +⎝ ⎠⎝ ⎠ ⎝ ⎠ ⎝ ⎠
(3-113)
Using the first order Padé approximation for 1ste− in Equations 3-93 and 3-95,
( )( )
11
1 / 4 ;
1 / 4 2SWst S
SWSW
sT Te t delays TsT
− −= = + =
+ (3-114)
Thus, the command to duty ratio transfer function can be obtained with numerator and
denominator coefficients in the “s” domain as
( ) ( )( ) ( )( )( )
( ) ( )( ) ( )
( ) ( )
3 2
^
^ 3
2
1
SW SW SW
SW SWcmd
SW SW
NumA T s NumA VT s NumA V WT s
NumAWdDenA T DenB T svDenA DenB DenA VT DenB VT s
DenA V DenB V D
× + + + +
+=
× − × +⎡ ⎤⎣ ⎦
+ + + × − ×⎡ ⎤⎣ ⎦+ × + × + ( ) ( ) ( )
( ) ( ) ( ) SW SW SWenA WT DenB WT DenC GdT s
DenA W DenB W DenC Gd
× − × + ×⎡ ⎤⎣ ⎦
+ × + × + ×⎡ ⎤⎣ ⎦
(3-115)
The digital SRM controlled buck converter is simulated in MATLAB/Simulink and the
steady-state parameters were derived from the converter outputs. The inputs to digital SRM
controlled converter are Vin=5 V, Vcmd=1.3 V, and Rload=0.5 Ω. The parameters of the digital
timing generator used in simulation are NC=4, NL=8, tCLK=40 ns, NE=5, and TS=3.33 µs. The
MATLAB function used to determine the coefficients of the command to duty ratio expression is
69
given in Appendix A. The steady-state outputs determined from the simulation are D=0.27 and
Vout=1.34 V. The resulting command to duty ratio expression based on Eq. 3-115 is given as
^6 3 2 4 9
^ 6 3 2 4 10
3.27 10 1.997 2.312 10 2.09 102.255 10 1.952 4.225 10 1.44 10
cmd
d s s ss s sv
−
−
× + + × + ×=
× + + × + × (3-116)
The above expression can be expressed in the pole-zero gain form as
( )( )( )( )
^ 5 2 4 9
^ 5 2 4 9
1.4504 6.006 10 1 10 1.064 10
8.525 10 1.319 10 7.491 10cmd
s s sds s sv
+ × + × + ×=
+ × + × + × (3-117)
The magnitude and phase of the command to duty ratio transfer function, duty ratio to
output transfer function, and command to output voltage transfer function are plotted in Figures
3-32, 3-33, and 3-34 respectively. These functions need to be verified experimentally.
3.4.6 Design Methodology for Digital SRM Controlling the Synchronous Buck Converter
A summary of the design methodology involved in the design of the digital SRM
controlling the buck converter is outlined in this section. The digital SRM design process
assumes that the parameters of the buck converter, namely, output filter inductor (L=4.7 µH),
output capacitor (C=425 µF), input voltage (Vin=5 V; +5%/-8%), output voltage (Vout=1.5 V),
and peak-peak inductor ripple current (∆IL=0.65 A) are known beforehand. The next step of the
design process involves determination of the parameters in the digital inverse timing generator.
The number of bits for the step value (NL) and the hysteretic count resolution (NC) are
determined from the maximum inductor voltage (VLmax=5.25 V) and the hysteretic voltage
(Vhys=320 mV) selected. The equation relating NL and NC is given from Eq. 3-14 as
max2
LL C
hys
VN N logV
⎛ ⎞− ≥ ⎜ ⎟⎜ ⎟
⎝ ⎠ (3-118)
4L CN N− ≥ (3-119)
70
Based on an initial assumption of NL=8 for the inductor voltage resolution, the hysteretic
count resolution is determined from Eq. 3-118 as NC=4. The time period of the clock
(tCLK=(1/fCLK)) required for successive accumulation and timing generation is then determined.
_ _max
136.26 ; 27.58 2 C
LCLK required CLK requiredN
L CLK
L It ns f MHzV t
×∆= = = =
× (3-120)
Based on the availability of resources, the clock used in the experimental implementation
is fCLK=25.175 MHz (tCLK=39.72 ns). The next step involves the determination of the scaling
factor based on parameters determined above.
324.2955 10
CNLq
SC CLKL
vN t
L I−×
= × = ××∆
(3-121)
The following step involves the approximation of the scaling factor based on Equations 3-
20 and 3-21 to aid in binary operations.
4
11 11
9 9 22 16 2SCN = = × (3-122)
_ /9
16SC A DN = (3-123)
The ratio NSC_A/D from Eq. 3-123 is incorporated into the A/D signal conditioning circuit
utilized for sampling the inductor voltage while the ratio (24/211) is utilized for virtual binary
shifting in the step value generation. The final step of the design process involves the
determination of number of bits for quantizing the error between the command and the output
voltage. The inductor voltage and the error voltage resolution are related by the following
equation.
max2
max
int log LL E
err
VN NV
⎡ ⎤⎛ ⎞− ≥ ⎢ ⎥⎜ ⎟
⎝ ⎠⎢ ⎥ (3-124)
71
The error voltage resolution and the maximum error voltage are based on transient
requirements. Based on the modulator expression of Eq. 3-30, the maximum error voltage
(Verrmax) is selected to be less than or equal to the hysteretic voltage (Vhys) for the PWM
comparator to respond instantaneously under a step-up or step-down load transient. Thus, the
relation between the number of bits for the inductor voltage and the error voltage is obtained as
25.25 int log320 L E
VN NmV
⎡ ⎤⎛ ⎞− ≥ ⎜ ⎟⎢ ⎥⎝ ⎠⎢ ⎥ (3-125)
4L EN N− ≥ (3-126)
The LSB equivalent of the error voltage (verrq=30 mV) is chosen to be greater than the LSB
of the inductor voltage (vLq=20.58 mV) resulting in
max2int log 4
30err
EVN
mV⎡ ⎤⎛ ⎞= =⎜ ⎟⎢ ⎥⎝ ⎠⎢ ⎥
(3-127)
The AVP requirement of Vout_min=1.5V and Vout_max=1.6V indicates a voltage change
of 100 mV. Thus, the number of bits determined for the error voltage and its resolution (verrq=30
mV) can track this voltage change under a transient load step-up or step-down condition and
satisfy the transient AVP requirement. Based on the parameters determined, the timing
generation accuracy is evaluated by comparing the time duration from digital timing generator
with that of the theoretical expression as shown in Eq. 3-128.
2 CNL
CLKL L
SCLq
errorL
L
L I tv vN
v
L Iv
⎛ ⎞⎜ ⎟
⎛ ⎞×∆ ⎜ ⎟− ×⎜ ⎟ ⎜ ⎟⎛ ⎞⎝ ⎠ ⎜ ⎟×⎜ ⎟⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠∆ =⎛ ⎞×∆⎜ ⎟⎝ ⎠
(3-128)
72
In order to improve the timing generation accuracy, the number of bits for NL can be
increased or the time period of the clock (tCLK) used for accumulation can be reduced. The
parameter determination procedure is reiterated to reflect the changes.
3.5 Performance Analysis of Digital Synthetic Ripple Modulator
3.5.1 Open-loop Linear Control of Controlled Variable with Command Signal
The digital SRM allows open loop linear control of the output variable as stated earlier.
The command signal cmdV is varied from 1.2 V to 1.8 V and the resulting output voltages are
shown in Figure 3-35. It is evident from Figure 3-35 that the output voltage follows cmdV in a
linear fashion even under open-loop conditions. The open-loop operation of the modulator
results in an error voltage between the actual output voltage and the command voltage. This
arises from the fact that the term VerrAD in Eq. 3-72 is not adequately compensated. Hence an
offset results between the desired output voltage and the actual output voltage in the open-loop
control of the converter. On the other-hand, the open-loop control still provides a linear control
of the output voltage with respect to the command voltage.
3.5.2 Influence of Component Variations on the Digital SRM Performance
The digital SRM involving generation of carrier signal from converter waveforms allows
natural feed-forward control. The SRM scheme also enables the carrier signal to better track the
component variations. This is shown in Figure 3-36, which indicates the variation in output
voltage for a command signal Vcmd=1.36 V due to variations in converter components values
(e.g. L, C, esr_C, rL ) over aging. A variation of 15%± is included in the output filter component
values of the buck converter. The nominal inductor value used in simulation is L=4.7 µH (
Lmax_var = 1.15X4.7 µH=5.4µH and Lmin_var=0.85X4.7 µH=3.99 µH) and the nominal output
capacitor value is 4.11 mF ( Cmax_var=4.73 mF and Cmin_var=3.87 mF ). As evident from Figure 3-
73
36, the output voltage remains within an allowable tolerance level over the 4 combinations of
component variations.
3.5.3 Open-loop Dynamic Response of the Digital SRM Controlled Buck Converter
The open-loop load transient response of the digital SRM controlled buck converter is
indicated in Figure 3-37. A step-up load transient is presented to the buck converter with its
command voltage held constant at Vcmd=1.5 V. As evident from the figure, the sudden change in
load current is immediately supplied by the converter with the help of the digital SRM triggering
the UFET VPWM signal to logic high or “1”. Also evident from the figure is the droop in the
output voltage. The droop in the output voltage results in the increase of the error voltage
between command and output voltage. The increased error voltage causes the A/D converter
sampling the error voltage to saturate to the higher limit based on Figure 3-12. Thus the lower
hysteretic threshold is reached in Eq. 3-25 instantaneously, causing the VPWM signal to go to
logic high or “1”. The current implementation of the digital SRM is based on open-loop control
with no regulation for the output voltage, causing a droop in the output voltage for the given load
transient.
3.6 Advantages of Digital Synthetic Ripple Modulator
Digital Synthetic Ripple modulator generates the carrier signal from converter parameter
allowing for natural feed-forward characteristic. Linear control of the controlled variable can be
obtained in open-loop configuration and transient performance is better because the controlled
variable is directly bonded to synthetic ripple. The principle of digital SRM when applied to
speed control of motor drives can eliminate the need for stator current sensing, while providing
superior transient performance due to hysteretic operation.
74
Table 3-1. Sequential steps involved in Step Value generation Parameter Binary Multiplication Scaling A/D Gain-block scaling 1 Analog Input 10.35 10.35 2 A/D Output
(NQ(V)) round(10.35/(12/1023)) =(882)10=(1101110010)2
round((10.35X5)/((12/1023)X8)) =(551)10=(1000100111)2
3 Scaled output (882X5)/212=(1,000100111)2 =1.0762
(551)X(23/212)=(1,000100111)2 =1.0762
4 Step Value qstep=(1,000100111)2 qstep=(1,000100111)2
Table 3-2. DC-DC converter specifications S.No Parameter Specification 1 Input Voltage 5V +5%,-8% 2 Output Voltage 1.1 – 1.85V 3 Output current slew rate 50A/µs 4 Output current selected 4A 5 Output voltage resolution 30mV
Table 3-3. Scaling factor Approximations Actual Scaling Factor 34.2955 10SCN −= × NSC approximation Virtual binary point factor
10 35 / 2 4.88 10−= × 23/210 11 39 / 2 4.3945 10−= × 24/211 11 38 / 2 3.90625 10−= × 24/211
75
stepq( ), , ..L L DSq v i V
Scaling SCN
LN
Control LogicShift enable
LN
LN
Carry
Register
Digital Comparator2 CN
stepq
DigitaltCLKt
2 CN
OFFtONt
Accumulator
Timing Output
CLKf
Barrel Shifter
Integer Value1
CLKCLK
ft
=
/A D
( , )Q V IN
Figure 3-1. Conceptual implementation of digital duty ratio generation
ONt
( )Li t
1LTonvmL
= 2LToffv
mL
−=
OFFt
LI∆
( )Lv tin outv v−
outv−(sec)t
Figure 3-2. Inductor current indicating the current ripple and time intervals along with the buck converter inductor voltage
76
1NLb − 0b1b2b
Virtual Decimal Pt
Fractional Portion
stepq( , ..)q V I
Fractional PortionIntegerportion
SCN1
LSBq
LN/A D
1NLb − 0b1b2b
Virtual Decimal Pt
Fractional Portion
stepq( , ..)q V I
Fractional PortionIntegerportion
( )2 B
SCN
LSB
Numerator Nq ×
LN/A D
LN 2( )
BN
SCDen N
/ Binary Multiplication Scaling A D Gain Block Scaling
1 2 3
4
1 2
3
Figure 3-3. Scaling approaches for step value generation
0 2 4 6 8 10 120
1
2
3
4
5
6
Control Input Voltage (V)
Perc
enta
ge e
rror
bet
wee
n di
gita
l tim
ing
gene
rato
r and
theo
retic
al e
xpre
ssio
n (%
)
NSC = 5/212 ; Count = 16
NSC = 9/213 ; Count = 14
NSC = 8/213 ; Count = 13
NL =10 ; tCLK = 40ns
Figure 3-4. Timing error performance for various scaling factor approximations used in step value generation
77
1 2 3 4 5 6 7 8 9 10 11 120
2
4
6
8
10
12
Control Input Voltage (V)
Perc
enta
ge e
rror
bet
wee
n di
gita
l
timin
g ge
nera
tor a
nd th
eore
tical
exp
ress
ion
(%)
A/D Gain block scalingBinary multiplication scalingNSC = 5/212 ; NC = 4
NL = 10 ; tCLK = 40ns
Figure 3-5. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A/D gain-block scaling
78
100 200 300 400 500 600 700 800 900 1000
-40
-20
0
20
40
60
80
100
120
140
Sampled Inductor voltage in binary
Tim
e du
ratio
n di
ffere
nce
from
the
theo
retic
al e
xpre
ssio
n (n
s)NL =10 ; tCLK = 40ns ; NSC = (5/23)X(23/212)
Figure 3-6. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A/D gain-block scaling
79
/Converter Inverter
ADC
12 CN −
12 CN −−
RS
Q
Q
Input Output
(
)
System ParameterDigital Timing
Generator Input
Digital Timing Generator
& Scaling Successive
Accumulation
ADC
Command Input
_Error binary
CLKf
onT
offT1
0
PWM
PWM
Error
2 CN
Integer Value
Modulator OutputDigital SRM
LN< >
EN< > 12 CN −−12 CN −
PWMB A
/A B A B+ −
0 1
ONtOFFt
OFFtONt
Figure 3-7. Generic architecture of a system controlled by digital synthetic ripple modulator
2HysModulator Command+ = +
PWM
Hys
ONt
2HysModulator Command− = −
Synthetic Ripple
OFFt
Output Variable
Modulator Output
Figure 3-8. Generic synthetic ripple modulation showing the hysteretic thresholds, command variable and PWM signal
80
/A D
12 CN −
12 CN −−
RS
Q
Q
Digital Timing Generator
& Scaling Successive
Accumulation
/A D
cmdv
CLKf
PWM
PWM
errorv
PWM
2 CN
Integer Value
Modulator OutputDigital SRM
LN< >EN< >
ONtOFFt
Lv
inV, LL r
C
phasevCr
PWM
( )outv t
ONtOFFt1
0
B A/A B A B+ −
0 1
12 CN −−12 CN −
_Error binary
OFFtONt
Figure 3-9. Architecture of digital SRM controlled synchronous buck DC-DC converter.
81
Li1
in outV VmL−
=2
outVmL
−=
hysI
outi
t
maxoutI∆
Figure 3-10. Inductor current waveform during load current step-up and steady-down transient
1 1.5 2 2.5 3 3.5 4 4.5 5 5.50
2
4
6
8
10
12
14
16
18
20
Inductor Voltage (V)
Perc
enta
ge e
rror
bet
wee
n di
gita
l tim
ing
gene
rato
r an
d th
eore
tical
exp
ress
ion
(%)
NSC = 5/23 ; NB = 23/210 ; Count = 16
NSC = 9/24 ; NB = 24/211 ; Count = 15
NSC = 8/24 ; NB = 24/211 ; Count = 15
Figure 3-11. Simulation analysis of percentage error for various scaling factor approximations
82
errv
321
0123
+++
−−−
( )2 1EN+ −
( )2 EN−
cmdv outv
Figure 3-12. Transfer characteristic of the A/D converter sampling the error voltage between output and command voltage.
inV
_sync rectVphaseV
VPWM
Figure 3-13. Simulink model of the PWM switch
83
phasev1
L
∫
1s Li
Lr
1C
1s
outV
Cr∫
1
LoadRouti
Figure 3-14. Simulink model of buck LC filter
/ A D Gain Analog Input N Digital Output
Zero order
Hold− Quantizer Saturation
_ max
2 1analog
LSB N
VV =
−
Figure 3-15. Simulink model of the A/D converter
84
_ _digital timing gen
LbinaryV_Timgen en
_Init cy
_Sample delay
_Acc val_Integer val
_Carry out
_Step value
_Acc val
Figure 3-16. Simulink model of digital timing generator
85
Buck LC Filter5inV V=
outv
errADV
8
IntegerValue
_MOD OP
8
8−
RS
Q
Q
VPWM
phasev PWMSwitch
+ −
Lv
_ _digital timing gen
_Sample delay
8LN< = >
_ 0.2sync rectV V= −
+ −
cmdv
errVADC ADC
/ 5A DN< = >
1 0
8−
0..7 A 0..7B < > < >
/ADD SUB
VPWM/A B A B+ −
onT
offT
DigitalTimingGenerator
Figure 3-17. Block diagram depicting the Simulink model of digital SRM controlled buck converter
86
( )LInductor Current i
( )LInductor Voltage v
( )phasePhase Voltage V
( )outOutput Voltage v
1.1µs2.6µs
2 /µs div
Figure 3-18. Simulation outputs of the synchronous buck converter using MATLAB/Simulink for Vcmd=1.3V
87
Step Value
_Integer val
VPWM
Modulator Output
1.1µs2.6µs
2 /s divµ
Figure 3-19. Simulation outputs indicating the step value, integer value and VPWM signal of the digital timing generator
88
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.50.5
1
1.5
2
2.5
3
3.5
Inductor Voltage (V)
Tim
e du
ratio
n fr
om d
igita
l tim
ing
gene
rato
r (us
)
Digital Timing Generator Simulation dataTheoretical expression data
Figure 3-20. Comparison between on-time/off-time generated based on theoretical equations and simulated synthetic ripple modulator.
89
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.50
2
4
6
8
10
12
14
Inductor Voltage (V)
Perc
enta
ge e
rror
bet
wee
n di
gita
l tim
ing
gene
rato
r and
theo
retic
al e
xpre
ssio
n (%
)
Figure 3-21. Percentage error between digital timing generator and theoretical expression using simulation analysis
90
Figure 3-22. Voltage change across the output capacitor during a step-down load transient
91
Figure 3-23. Integer_value, modified hysteretic count, VPWM, and Error_binary for AVP implementation in digital SRM
92
Figure 3-24. Integer_value, modified hysteretic count, VPWM, and Error_binary for AVP implementation in digital SRM
93
Figure 3-25. Inductor current and AVP of the output voltage based on optimal AVP design for the load step-up transient
94
Figure 3-26. Inductor current and AVP of the output voltage based on optimal AVP design for load step-down transient
95
Figure 3-27. Inductor current and AVP of the output voltage - Vcmd reaches higher level before the peaking of Vout (Vout_max)
96
Figure 3-28. Inductor current and AVP of the output voltage - Vcmd reaches higher level before the peaking of Vout (Vout_max)
97
Figure 3-29. Inductor current, VPWM, and AVP of the output voltage - Vcmd reaches higher level after the peaking of Vout (Vout_max)
98
Figure 3-30. Modulator output, Error_binary, and AVP of the output voltage - Vcmd reaches higher level after the peaking of Vout
99
^
^
( )
outvd
Buck Converter
vG sd
Duty ratio to Outputvoltage
=
( )outv td
( )cmdv t2( ) st
E NEG G A e−=( )errorv t
1( ) stL NLG G A e−=
( )phasev t
^
^ ( )
dvcmd
cmd
dG sv
Command to Duty ratio
=
SCN
Figure 3-31. Dynamic system model of the digital SRM controlled synchronous buck converter
100
100 101 102 103 104 105 106-30
-20
-10
0
10
20
100 101 102 103 104 105 1060
50
100
150
200
Frequency (Hz)
( )Command to Dutyratio Magnitude dB
4.7 ; 200 ; 0.50.27; 5 ; 1.34 ; 1.3
o load
in out cmd
L H C F RD V V V V V V
µ µ Ω= = == = = =
( )Command to Dutyratio Phase degrees
Figure 3-32. Magnitude and phase of command (vcmd) to duty ratio (d) transfer function
101
100 101 102 103 104 105 106-60
-40
-20
0
20
40
100 101 102 103 104 105 106-200
-150
-100
-50
0
Frequency(Hz)
( )Dutyratio to Output voltage Magnitude dB
( )Dutyratio to Output voltage Phase degrees
4.7 ; 15 ; 200 ; 100.5 ; 0.27; 5 ; 1.34
L o C
load in out
L H r m C F r mR D V V V
µ µΩ Ω
Ω
= = = =
= = = =
Figure 3-33. Magnitude and phase of duty ratio (d) to output voltage (vout) transfer function
102
100 101 102 103 104 105 106-50
-40
-30
-20
-10
0
10
20
100 101 102 103 104 105 106-200
-150
-100
-50
0
Frequency (Hz)
^ ^( ) ( ) ( )cmd outCommand v to Output voltage v Magnitude dB
^ ^( ) ( ) ( )cmd outCommand v to Output voltage v Phase degrees
4.7 ; 15 ; 200 ; 100.5 ; 0.27; 5 ; 1.34
L o C
load in out
L H r m C F r mR D V V V
µ µΩ Ω
Ω
= = = =
= = = =
Figure 3-34. Magnitude and phase of command (vcmd) to output voltage (vout) transfer function
103
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.81.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Command or Reference voltage Vcmd (V)
Buc
k C
onve
rter
Out
put V
olta
ge V
out (V
)
Output Voltage (Simulation data)Linear Fit
Figure 3-35. Plot indicating the linear control of output voltage with command voltage based on MATLAB/Simulink simulation
104
3.478 3.48 3.482 3.484 3.486 3.488 3.49
x 10-3
1.371
1.372
1.373
1.374
1.375
1.376
1.377
1.378
time (sec)
Out
put V
olta
ge (V
out (
V))
Effect of Output Filter Variations on Output voltage
L-5.44uH C=4.73mFL=3.99uH C=3.87mFL=3.99uH C=4.73mFL=5.44uH C=3.87mF
Figure 3-36. Simulation plot indicating the effect of component variations on the performance of the digital SRM
105
2.495 2.5 2.505 2.51 2.515 2.52 2.525 2.53 2.535 2.54 2.545
x 10-3
468
101214
2.495 2.5 2.505 2.51 2.515 2.52 2.525 2.53 2.535 2.54 2.545
x 10-3
1.4
1.5
1.6
2.495 2.5 2.505 2.51 2.515 2.52 2.525 2.53 2.535 2.54 2.545
x 10-3
-5
0
5
2.495 2.5 2.505 2.51 2.515 2.52 2.525 2.53 2.535 2.54 2.545
x 10-3
-0.5
0
0.5
1
Load currentInductor current
(sec)time
_ (A/D output of sampled error voltage)Verr AD
(V) (OutputVoltage)outV
( ) ( ) LLoad Current step and Inductor current i A
(UFET - PWM Signal)VPWM
Figure 3-37. Simulation of open-loop load transient response of digital SRM controlled buck converter with Vcmd=1.5 V and load step of 5A to 10A in 100 ns (50 A/µs)
106
CHAPTER 4 DESIGN AND EXPERIMENTAL IMPLEMENTATION OF DIGITAL SYNTHETIC RIPPLE
MODULATOR
The hardware implementation of the digital SRM controlled synchronous buck converter
involves the implementation of digital timing generator, synchronous buck converter, and signal
conditioning blocks. The digital timing generator is implemented using the ALTERA UP2
FPGA/CPLD board and utilizes Quartus® II software for timing analysis simulation. The signal
conditioning block and the synchronous buck converter are implemented using discrete
components based on simulation analysis from LTSpice/SwitcherCAD™.
4.1 Experimental Implementation of Synchronous Buck Converter
The synchronous buck DC-DC converter implementation involves the design of power
MOSFETs, inductor selection and output capacitor selection. The converter shown in Figure 4-1
also requires synchronous buck gate drivers for driving the power MOSFETs. The various
component selections are based on the specifications outlined in Table 3-2 and the allocated loss
budget. For a nominal output voltage of 1.5 V and load current of 4 A, the output power can be
calculated as
1.5 4 6 out out outP V I V A W= × = × = (4-1)
Assuming an efficiency of η=85% for the synchronous buck converter, the total loss
budget can be determined to be
_out
Loss total in out outPP P P Pη
= − = − (4-2)
_6 6 1.060.85Loss total in out
WP P P W W= − = − = (4-3)
The stead-state duty ratio based on the specifications listed in Table 3-2 is determined to be
107
1.5 0.35
out
in
VDV
= = = (4-4)
4.1.1 Power MOSFET Design and Selection
The selection of the power MOSFET (UFET and LFET) is based on the switch blocking
voltage and the on-resistance ( DSonr ) of the device. The voltage across the UFET switch during
the OFF-state (VPWM=0) is
_ maxDS UFET inV V= (4-5)
Hence the blocking voltage considering a safety factor of 2 is
_ max2 2 5.25 10.5Block UFET inV V V= × = × = (4-6)
Similarly the blocking voltage across the lower FET (LFET) is 10.5 V when the UFET is
ON (VPWM=1).
The current through the UFET MOSFET during a switching cycle is shown in Figure 4-2.
In a buck converter the average value of the inductor current is equal to that of the load
current and given by
L L outi I I= = (4-7)
The power loss in the FETs can be determined based on the rms current.
( ) ( )( )2_ ' 0UFET rms outI D I D= × + × (4-8)
_ 2.2UFET rms outI I D A= × = (4-9)
Assuming a 30% loss in the power MOSFETs,
__
0.3159
2Loss total
Loss UFET
PP mW
×= = (4-10)
The require on-resistance of the UFET can be determined to be
108
( )_
2_ @150_
33 Loss UFETDSON HOT C
UFET rms
Pr m
I= = Ωo (4-11)
_ ( @150 )_ @25
13.2 2.5
DSON UFET HOT CDSON UFET C
rr m= = Ω
o
o (4-12)
Based on Equations 4-6 and 4-12, the power MOSFET chosen for the UFET and LFET is
IRF7455 [68]. The IRF7455 N-channel power MOSFET is specifically designed for use in high
frequency DC-DC converters with synchronous rectification. The power MOSFET can withstand
a maximum drain-source voltage of VDSS=30V and exhibits low on-resistance (rDSON=7.5 mΩ)
for VGS=4.5 V. Thus the actual power loss can be estimated.
2_ _ 37 Loss UFET UFET rms DSONP I r mW= × = (4-13)
Thus the remaining loss budget can be recalculated as
( )_ _ 2 37 0.986 Loss rem Loss totalP P mW W= − × = (4-14)
4.1.2 Output Filter Inductor Selection
The component selection for the inductor is based on ESR (rL) of the inductor and the
value of the inductor. The copper loss occurring in an inductor for a given current is estimated as
2_CuLoss L Lrms LP I r= × (4-15)
Assigning 25% of the remaining loss for the inductor loss budget, the ESR can be
determined as
2_ _0.25 ; CuLoss L Loss rem Lrms L Lrms outP P I r I I= × = × = (4-16)
15 Lr m= Ω (4-17)
The inductor value determined from Eq. 3-36 is given to be L=4.76µH. Based on the above
calculations, an axial type inductor from Coilcraft® was used for the experimental
implementation. The inductor part number from the website is PCV-1-472-10L. The DC
109
resistance or ESR of the chosen inductor is 12 mΩ (i.e. 12 Lr m= Ω ) with a variation in the
inductor value of ±15%.
4.1.3 Output Filter Capacitor Selection
The output capacitor based on voltage regulation specifications as determined from
Equation 3-40 is 425µF. The output capacitance is realized by a capacitor bank consisting of 5
capacitors each of 100µF. The part-number for the 100 µF is 293D107X9020E from Vishay
electronics. Each capacitor has an ESR (equivalent series resistance) of 10 mΩ.
4.1.4 Synchronous Buck Gate driver
The experimental implementation utilizes the TPS2830 [69] synchronous buck MOSFET
driver from Texas Instruments™. The driver has an in-built bootstrap diode which helps to
reduce noise due to switching transitions. The driver also incorporates an adaptive dead time
control to prevent shoot-through currents through the UFET and LFET during the switching
transitions. The adaptive dead-time control also provides higher efficiency for the buck
converter.
4.2 Experimental Implementation of Signal Conditioning Circuit
The signal conditioning circuit incorporates the scaling factor used in scaling and
successive accumulation process. It is also used to interface the DC-DC buck converter signals to
the input of the A/D converter. The scaling factor to be included in the A/D signal conditioning
circuit as determined from Eq. 3-52 is
4
11 11
9 9 22 16 2SCN = = × (4-18)
_ /9
16SC A DN = (4-19)
110
The inductor voltage is sampled by the A/D converter for generating the synthetic ripple
used for carrier signal. The polarity of the inductor voltage is positive during the on-time
(VPWM=1) and negative during the off-time (VPWM=0). The negative polarity is an indication
of the discharge phase of the output capacitor. The digital timing generator requires only the
absolute value of the inductor voltage to generate the step value. Thus the polarity of the inductor
voltage needs to be reversed during the off-time or the discharge phase.
An 8-bit A/D converter is used for sampling the inductor voltage based on the step value
resolution requirement of NL=8. The A/D converter selected for the current application is
ADS930 [70] from Texas Instruments™. The ADS930 is an 8-bit, 30 MHz converter with a
single ended full-scale range spanning from 1 V to 2 V (1Vp-p) and a common-mode voltage of
1.5 V. The choice of ADS930 is influenced by the availability of the 25.175 MHz oscillator from
the ALTERA UP2 board and the range of output voltages (1.2-1.85 V) of the buck converter.
The inductor voltage of the buck converter is obtained from the difference between the
phase voltage (Vphase) and the output voltage (Vout). The range of voltages from the converter at
the phase node and output voltage node need to be mapped to the allowable range of voltages at
the input of the A/D converter. If KSC is the voltage scaling ratio for the inductor voltage, then
the buck converter voltage can be mapped into the A/D input range by
max/ max
L NA D
SC
V A VK×
= (4-20)
where VLmax is the maximum inductor voltage (=Vinmax), VA/Dmax is the maximum voltage swing of the A/D converter, and AN is the gain of the operational amplifier used for buffering the scaled voltages.
The scaling factor can be included in the voltage scaling ratio to yield the resistive voltage
division ratio as
_1 1
SC ADR SC
NK K
= × (4-21)
111
Assuming an opamp gain of 3 and using the specifications of the buck converter and the
A/D converter the scaling is determined to be
max
/ max
5.25 3 15.751
L NSC
A D
V AKV
× ×= = = (4-22)
_1 1 1 9 1
15.75 16 28SC ADR SC
NK K
= × = × = (4-23)
For the voltage division at the phase node and output voltage node, assuming one of the
resistances as 18 kΩ, the resistive divider can be determined to be
_1
18phase pos phase phaseR
RV V VK R k
⎛ ⎞= × = ×⎜ ⎟+⎝ ⎠ (4-24)
1 128 18R
RK R k
= =+
(4-25)
660 R = Ω (4-26)
The schematic representation of the voltage scaling to map the buck converter voltages
into the A/D input voltage range is shown in Figure 4-3. The simulation of the schematic in
Figure 4-3 using LT Spice involved the actual components used in the experimental
implementation.
From Figure 4-3, the voltages at the output of the operational amplifier A1 (Gain=3) and A2
(Gain=3), namely Vphase_pos1 and Vout_neg1, are the scaled phase node and output voltages
respectively. The inductor voltage during the on-time is obtained by applying Vphase_pos1 to
the non-inverting input and Vout_neg1 to the inverting input of the operational amplifier A3.
Thus, VLpos_adc_input, the amplifier A3 output represents the inductor voltage during on-time. It is
connected to the A/D converter which generates the sampled binary value VLPOS [7...0]. The
inductor voltage during the off-time is obtained by applying Vphase_pos1 to the inverting input
and Vout_neg1 to the non-inverting input of the operational amplifier A4. Thus, the polarity is
112
switched during the off-time resulting in the output VLneg_adc_input. This output is connected to A/D
converter which yields the sampled output namely, VLNEG [7…0]. The output of the difference
amplifiers are level shifted to account for the A/D converter input range. The error voltage
between command (Vcmd) and output voltages (Vout) is obtained using the difference amplifier
A5. The output of the difference amplifier A5, namely Verr_adc_input, is connected to the A/D
converter which produces the sampled error voltage VERRADC [7…0].
( )_ _ _ 1 _ 1 1.0VLpos adc input phase pos out negV V V= − + (4-27)
( )_ _ _ 1 _ 1 1.0VLneg adc input out neg phase posV V V= − + (4-28)
The A/D converter outputs form the input to the digital synthetic ripple modulator shown
in Figure 4-4. The A/D outputs VLPOS [7..0] and VLNEG[7..0] are given as input to the 8-bit 2-
to-1 multiplexer. The signals blnk_pos and blnk_neg are used to enable the 8-bit registers during
on-time and off-time respectively. In a given switching cycle, when the modulator output reaches
the higher hysteretic threshold, the signal vh_set is set to logic 1. Similarly when the modulator
output reaches the lower hysteretic threshold, vl_set is set to logic 1. A set of combinational logic
employing counters and latches are used to generate the ADC register enable signals. As stated
earlier, once vl_set is set to logic 1, the counters are enabled and blnk_pos signal is generated.
The signal blnk_pos is delayed by 840 ns (determined from experimental signal conditioning
circuit delays) with reference to vl_set. Similarly blnk_neg is delayed by 1.5 µs with reference to
vh_set. Thus the blnk_pos and blnk_neg signals ensure that the output from the A/D corresponds
to the sampled inductor voltage during on-time and off-time respectively. The 8-bit 2-to-1
multiplexer receiving the inputs from the ADC registers carries out the polarity switching
process by providing the on-time and off-time step values to the digital inverse timing generator
based on VPWM signal. The timing signals vh_set, vl_set, blnk_pos, blnk_neg, and VPWM are
113
indicated in Figure 4-4. The timing signals and the generation of the A/D outputs are also
indicated in Figure 4-12 with reference to the analog input voltages to the A/D converter.
The operational amplifier used in the experimental implementation is LT1022 [71] from
Linear Technology™. LT1022 is a JFET input, precision operational amplifier specifically
designed for instrumentation applications. The selection of the operational amplifier is greatly
influenced by the slew-rate of the opamp. The phase node voltage has steep rising edges with
slopes in the range of 50 V/µs. The slew-rate of LT1022 is 26 V/µs and sufficient enough to
sample the inductor voltage at a particular switching cycle and generate the duty ratio based on it
in the subsequent switching cycle. The digital SRM implementation allows a slower slewing
opamp to be used due to the fact that the generated duty ratio is based on the sampled inductor
voltage at the previous switching cycle. Thus, the digital implementation allows additional cost
savings. The asymmetry of the signal swing (3.5 V and -1.5 V) necessitates the need for the two-
stage scaling and difference implementation. The schematic representation of Figure 4-3 was
implemented in LTSpice/Switcher CAD and the associated waveforms are indicated in Figures
4-5, 4-6, 4-7, and 4-8.
The small-signal ac analysis (frequency response) of the amplifier indicating the loop gain
and phase margin is shown in Figure 4-5. In order to simulate the functionality of the signal
conditioning circuit, the DC-DC buck converter was driven under open-loop condition by
providing an external high-side gate drive for the UFET, namely the VPWM signal. The duty
ratio of the VPWM signal is 0.325 at a switching frequency of 300 kHz. The LFET is driven by
the complement of the VPWM signal. The command reference Vcmd was ramped up from 0V to
1.5V in 800 µs. The phase node voltage and its scaled value are plotted in Figure 4-6. The A/D
input voltages derived from the scaled phase voltage and output voltage are indicated in Figure
114
4-7.The reference voltage, output voltage, error between the output and reference voltage, and
the error input to the A/D converter are shown in Figure 4-8.
4.3 Hardware Implementation of DC-DC Buck Converter and A/D Signal Conditioning Circuit
The synchronous buck converter and the signal conditioning circuit are implemented on
hardware using a printed circuit board (PCB). The PCB layout for the board was developed using
Protel 99 SE® software. The PCB board was milled on a 0.059” (59 mil) 0.5 oz. two layer copper
board using Quick Circuit™ milling machine from T-Tech®. The layout of the buck converter
and the signal conditioning circuit from the gerber file are shown below. The top layer and
bottom layer of the PCB are indicated in Figure 4-9 and Figure 4-10 respectively. The layout of
the synchronous buck converter [72] is carefully designed to avoid unnecessary parasitics. The
traces between the outputs of the gate driver and the gate of the MOSFETs are kept short and
wide. The bypass capacitors are kept closer to the power supply (PVDD) and power ground
(PGND) pins of the gate driver. The source of the high-side MOSFET (UFET) and the drain of
the low-side MOSFET (LFET) are kept as close as possible since the phase node connecting
them exhibits a high dv/dt characteristic. DC-DC converters involve high switching currents
which can cause perturbations to the sensitive analog ground of signal conditioning circuits.
Hence proper care is taken to isolate the power ground (switching converter ground), signal
conditioning circuit ground, and the digital timing generator ground. The manufactured PCB
board with all the components is shown in Figure 4-11.
4.4 Experimental Implementation of the Digital Timing Generator
The digital timing generator was implemented using ALTERA UP2 board. The ALTERA
board has a configurable CPLD device from the FLEX10K™ family, namely FLEX10K70. The
on-board oscillator of 25.175 MHz was used as the clock input for the timing generator. In
115
Figure 4-12, the voltages at the input of the A/D converter are indicated with respect to the phase
node voltage (Vphase). As evident from the figure, there is a finite delay between the rising or
falling edge of Vphase to that of the A/D inputs. This delay arises due to the phase shift from the
opamps in the signal conditioning circuit. The finite delays are determined from the experimental
circuit and implemented using the counters described in section 4.2 in the ALTERA board. In
order to account for these delays, the ADC enable signals blnk_pos and blnk_neg in Figure 4-12
are delayed by 840 ns and 1.5 µs (determined from the experimental signal conditioning circuit)
respectively to sample the correct value of the scaled inductor voltage. The internal timing
signals vl_set and vh_set in Figure 4-12 determine the reference point from which the blnk_pos
and blnk_neg signals are delayed respectively. The Quartus II simulation outputs of the digital
timing generator implemented in ALTERA board are shown in Figure 4-13. The VPWM signal
indicating the on-time (965 ns) and the off-time (2.68 µs) is shown in the figure for the step
values derived from Equations 3-73 and 3-74. The time duration for the corresponding inductor
voltages are compared in Table 4-1 based on theoretical expression, Simulink, and ALTERA
board simulation.
4.5 Experimental Implementation of Digital Synthetic Ripple Modulator Controlling the DC-DC Buck Converter
The hardware implementation of the system architecture involving the buck converter,
signal conditioning circuit, A/D converters, and the ALTERA digital timing generator is shown
in Figure 4-14. The A/D outputs are interfaced to the digital controller through the 60-pin
through-hole connector. The output of the digital controller (VPWM) forming the input to the
synchronous buck gate driver is given through a Schmitt trigger (SN74AHC1G14DBVRG4).
The Schmitt trigger eliminates any high frequency noise due to the clock of the timing generator.
116
The testing and analysis of the digital SRM controlled buck converter is explained in
chapter 5 of the dissertation. The experimental implementation of the digital SRM controlled
buck converter involves the implementation of synchronous buck converter, signal conditioning
circuit, and the digital controller. The bill of materials for the experimental implementation of the
buck converter, signal conditioning circuit and the digital controller are indicated in Table 4-2,
Table 4-3, and Table 4-4 respectively.
117
Table 4-1. Comparison of time duration from simulations Parameter Theoretical Expression MATLAB/Simulink ALTERA board VLTon=3.66V 1.027µs 1.1µs 0.965µs VLToff= -1.54V 2.44µs 2.6µs 2.68µs
Table 4-2 Bill of materials for the synchronous buck DC-DC converter Synchronous buck DC-DC converter S.No Component or
Symbol name Part Number Specifications Qty
1 UFET and LFET IRF7455 (International Rectifier)
30V,rDSon=7.5mΩ 2
2 Inductor (L) PCV-1-472-10L (Coilcraft)
4.7µH ±15%, DCRmax=0.021Ω
1
3 Output Capacitor (C) 293D107X9020E (Vishay Electronics)
100µF, esr=10mΩ 5
4 MOSFET Gate driver
TPS2830 (Texas Instruments)
4.5V-15V, 2.4A peak output current, 50ns rise/fall times-3.3nF load
1
Table 4-3 Bill of materials for the A/D converter and signal conditioning circuit A/D Signal conditioning circuit S.No Component or Symbol
name Part Number(s) Specifications Qty
1 Opamps(A1,A2,A3, A4,A5)
LT1022 (Linear Techonology)
Slew rate 23V/µs; GBW=8.5MHz
5
2 A/D converter (ADC) ADS930 (Texas Instruments)
8-bit, 30MHz, 1Vp-p Full Scale
3
3 Resistors (660Ω,18kΩ,2.2kΩ, 1kΩ,2kΩ,150Ω)
P18KECT-ND P2.2KECT-ND P1.0KECT-ND (Digi-key)
1/8W 5% 1206 SMD 10
4 Capacitors ( 220pF, 82pF)
PCC221CGCT-ND 478-1479-1-1ND (Digi-key)
5% 50V 1206 SMD 5
5 Receptacle connector 4-1734005-0 (Tyco Electronics)
AMPMODU receptacle 40 positions, Dual rows
2
118
Table 4-4 Bill of materials for the FPGA based digital controller Digital SRM controller S.No Component or Symbol
name Part Number(s) Specifications Qty
1 Digital controller FPGA board
ALTERA UP-2 Evaluation board (Altera)
FLEX10k70 and MAX7000S CPLDs, 25.175MHz onboard oscillator
1
119
Vin
PWM switch Output L-C filter
, LL r
C
outV
VPWM
Liphasev outi
Cr
Cv
Digital SRM
Lv
UFET
LFET
LoadR
outV
cmdV
SYNCBUCKDRIVER
Figure 4-1. Schematic of synchronous buck DC-DC converter
Li
SDT ' SD T SDT
LiUFETi
( )t s
Figure 4-2. Current through the UFET in a switching cycle
120
Vin
µ= = Ω4.7 , 12LL H r m
µ=
500C
F
outVphaseV
Cr
Cv
Lv
VPWMVPWM
phaseV
_phase posV
1k2k
660
18k _ 1phase posV
cmdV
1.25LevelV V=
2.2k
outV
_ _err adc inputV2.2k
2.2k
2.2k
150220 pF
82pF150
1A
5A
IRF7455
IRF7455
PCV-1-472-10L
LT1022
LT1022930ADS
0D
7D
CLKf
outV
_out negV
1k2k
150660
18k _ 1out negV
220 pF
2A
LT1022
_ 1phase posV
82pF
_ 1out negV
_ _Lpos adc inputV
onInductor Voltage during T
2.2k
2.2k
2.2k
2.2k
1503A
1.0LevelV V=
LT1022
_ 1phase posV
_ 1out negV _ _Lneg adc inputV
offInductor Voltage during T
2.2k
2.2k2.2k
2.2k
150
82pF
4A
1.0LevelV V=
LT1022
[7..0
]VE
RR
930ADS
0D
7D
CLKf
[7..0
]VL
POS
930ADS
0D
7D
CLKf
[7..0
]VL
NEG
Figure 4-3. Schematic of signal conditioning circuit for the A/D converter with inclusion of the scaling factor
121
Figure 4-4. Block diagram of the experimental digital synthetic ripple modulator indicating the register enable and timing signals
122
10554
DCgain dBPhase Margin
== °
---------- : Gain- - - - - - : Phase
Figure 4-5. Frequency response of the signal conditioning circuit amplifier
123
_phase posV
_out negV
phaseV
outV
800 /ns div
Figure 4-6. Phase voltage, converter output voltage, and signal conditioning circuit scaled voltages for Vcmd=1.5V
124
_ 1phase posV
_ 1out negV
_ _Lpos adc inputV
_ _Lneg adc inputV
Figure 4-7. Inductor voltages at the input of the A/D converter for a duty cycle of D=0.325 and Vcmd=1.5V
125
_ _err adc inputV
cmdV
outV
Figure 4-8. Buck converter output voltages, error voltage and output A/D input voltage for Vcmd=1.5V
126
Figure 4-9. Gerber file indicating the top layer of the PCB board
127
Figure 4-10. Gerber file indicating the bottom layer of the PCB board
128
SYNC BUCKCONVERTER
.SIGNAL CONDTGCIRCUIT
/A DCONVERTER
Figure 4-11. Photograph of the manufactured PCB board indicating the buck converter and the signal conditioning circuit
129
ONT OFFT
10(100)= LposbinV
phaseV
ONT
_ _Lpos adc inputV
_blnk pos
_ _Lneg adc inputV
_blnk neg
10(100)= LposbinV
10(42)= LnegbinV 10(42)= LnegbinV
5inV V=
_ 0.2sync rectV V= −
0.388 1.0 ( ) 1.388V Level Shift V+ =
0.163 1.0 ( ) 1.163V Level Shift V+ =
840ns
1.5 sµ
Figure 4-12. Timing signals and A/D converter input voltages for the signal conditioning circuit
130
Figure 4-13. ALTERA board based digital synthetic ripple modulator outputs indicating VPWM outputs for step values (100)10 and (42)10
131
Figure 4-14. Experimental implementation of DSRM controlled buck converter system
132
CHAPTER 5 TESTING AND ANALYSIS OF DIGITAL SRM CONTROLLED BUCK CONVERTER
The DC-DC buck converter controlled by the digital synthetic ripple modulator consists of
three main components, namely the synchronous buck DC-DC converter; ALTERA FPGA based
digital timing generator, and the A/D signal conditioning circuit. Each of the major blocks was
tested at the module level to verify the functionality and extract key parameters used for
characterization. The system level testing was carried out to characterize the digital synthetic
ripple modulation technique when applied to the control of power converters.
5.1 DC-DC Buck Converter Testing and Measurement
The experimental test-bed used for measuring the various parameters of the buck-converter
is shown in Figure 5-1. The list of equipments used in the measurement of various parameters is
indicated in Table 5-1. The synchronous buck converter was driven by an externally generated
PWM signal with a specified duty ratio in the following test procedure. This test was used to
characterize the functionality of the buck converter and determine the various propagation delays
involved in the system. The test procedure is outlined below:
1. The current-limits of the voltage source (Agilent E3631A) supplying the gate driver and voltage source (HP6024A) supplying the input voltage of the buck converter was set to 5A and 4A respectively.
2 A power resistor of 1Ω (2Ω 5W || 2Ω 5W – part number DALE RH-5 5W 2Ω 1%) is connected across the output capacitor for setting the load current to 1.5A.
3 The PVDD pin of the TPS2830 gate driver was set to 5V by gradually increasing the voltage supply (Agilent E3631A) from 0 to 5V. The cooling fan can be turned on for higher load conditions to cool down the power MOSFETs.
4 A square wave with 5V amplitude, duty ratio of 30%, and a frequency of 300 kHz was applied to the PWM input of the TPS2830 gate driver.
5 The input voltage of the buck converter (Vin) was gradually increased from 0V to 5V by monitoring the output voltage and the input current.
133
6 The gate drive (vGS2) for the lower MOSFET (LFET) and the gate voltage at the upper MOSFET (UFET) were measured.
7 The phase or the switch node voltage (Vphase) was measured.
8 The output voltage (Vout) of the buck converter was measured.
9 The inductor current was measured using a current loop.
The measured waveforms from the buck converter are illustrated in Figures 5-2 to 5-8.
Figure 5-2 indicates that during the on-time when PWM input is high (VPWM=5V), the
UFET is turned ON and the switch node voltage is approximately equal to Vin. During the off-
time the LFET is ON and the switch node voltage is pulled to ground. During the turn ON of the
LFET, the body-diode of LFET conducts for a short duration to provide a continuous path for the
inductor current and to avoid DCM (Discontinuous Conduction Mode). Figure 5-3 indicates the
output voltage of the buck converter satisfying the steady-state duty ratio expression
Vout=DVin=0.3 X 5 = 1.5V.
Figure 5-4 and 5-5 indicates the sequential events of the high-side gate drive going high
followed by the phase-node voltage going high with the turn ON of UFET. The propagation
delay between the rising of the PWM input with that of the high-side drive and phase node
voltages are indicated in the respective figures.
In Figure 5-6, the PWM input and the low-side gate drive are indicated. Figure 5-7
indicates the dead-time between the falling of Vphase and the turn ON of the lower FET (LFET).
The dead-time ensures that both the FETs are not ON at the same time and prevents any shoot-
through currents between the MOSFETs.
The inductor voltage obtained from the difference between the phase node voltage and the
output voltage is shown in Figure 5-8.
134
5.2 Signal Conditioning Circuit Testing and Measurement
The functionality of the signal conditioning circuit was tested and the propagation delays
involved in the circuit were measured. The determination of these delays enables accurate
sampling of the scaled inductor voltages. The testing is carried out by operating the buck
converter in an open-loop condition and applying an external PWM input signal with duty ratio
D=0.25. The following waveforms were measured from the signal conditioning circuit shown in
Figure 4-3.
• Amplified phase and buck converter output voltages at the opamp outputs - Vphase_pos1 and Vout_neg1.
• A/D input voltages for sampling the inductor voltage - VLpos_adc_input and VLneg_adc_input. • A/D input voltages for sampling the error voltage between the command reference and
output voltage – Verr_adc_input.
Figures 5-9 to 5-12 depict the voltages associated with the signal conditioning circuit.
These voltages are obtained for an input voltage of Vin=5V with command reference at
Vcmd=1.38V. The measured buck converter output voltage was 1.28 V. In Fig 5-9, the scaled
phase voltage at the output of the opamp A1 in Fig 4-3 is plotted. The plotted outputs are verified
with Equations 5-1 and 5-2.
_ 1660 6603 5 3 0.531
660 18000 660 18000phase pos phaseV V V⎡ ⎤ ⎡ ⎤⎛ ⎞ ⎛ ⎞= × × = × × =⎜ ⎟ ⎜ ⎟⎢ ⎥ ⎢ ⎥+ +⎝ ⎠ ⎝ ⎠⎣ ⎦ ⎣ ⎦ (5-1)
In Figure 5-10, the scaled output voltage is plotted which satisfies the following relation,
_ 1660 6603 1.28 3 0.136
660 18000 660 18000out neg outV V V⎡ ⎤ ⎡ ⎤⎛ ⎞ ⎛ ⎞= × × = × × =⎜ ⎟ ⎜ ⎟⎢ ⎥ ⎢ ⎥+ +⎝ ⎠ ⎝ ⎠⎣ ⎦ ⎣ ⎦ (5-2)
In Figure 5-11, the scaled inductor voltage during the on-time (PWM=1) forming the A/D
input is shown which satisfies Eq. 5-3.
( ) ( )_ _ _ 1 _ 1 1.0 V= 0.531 0.136 1.0=1.395 VLpos adc input phase pos out negV V V= − + − + (5-3)
135
In Figure 5-12, the scaled inductor voltage during the off-time (PWM=0) forming the A/D
input is shown which satisfies Eq. 5-4.
( ) ( )_ _ _ 1 _ 1 1.0 V= 0.136 ( 0.1) 1.0 1.235 Lneg adc input out neg phase posV V V V= − + − − + = (5-4)
Figure 5-13 indicates the level shifted error between the output voltage and the command
reference satisfying the following relation.
( ) ( )_ _ 1 1.28 1.38 1.5 1.4 Verr adc input out cmdV V V= − + = − + = (5-5)
As evident from Figures 5-9 to 5-13, the delay between the rising edge of Vphase and the
instant at which VLpos_adc_input settles to the required scaled inductor voltage (during PWM=1) is
840 ns. Similarly the delay between the falling edge of Vphase and the instant at which
VLneg_adc_input settles to the required scaled inductor voltage (during PWM=0) is 1.5 µs.
5.3 Digital Synthetic Ripple Modulator Controlled Buck Converter Testing and Measurement
Digital synthetic ripple modulator utilizes the A/D outputs from the signal conditioning
circuit to determine the on-time or off-time of the power MOSFET switches and controls the
synchronous buck converter using the generated VPWM signal. Thus the output of the signal
conditioning circuit forms the feedback input to the digital modulator. The digital timing
generator in the digital modulator utilizes the propagation delay data from the open-loop tests to
generate input register enable signals. The register-enable signals blnk_pos and blnk_neg are
delayed by 840 ns and 1.5 µs from the rising and falling edges of Vphase respectively. The active
high enable signals are kept in logic high condition for 320 ns (8 clock counts) to accommodate
the A/D converter latency of 5 clock cycles. The clock frequency used in the A/D converter is
25.175 MHz (tCLK=40 ns). The closed loop operation of the digital modulator, buck converter
and the signal conditioning circuit is tested utilizing the test procedure outlined below:
136
1 The PVDD pin of the gate driver was set to 5V by gradually increasing the voltage supply from 0 to 5V.
2 The ALTERA board is powered and the power-on-reset and clk_en signals are enabled appropriately.
3 The signal conditioning circuit is powered by setting the VDD and VEE to 15V and -15V respectively
4 The input voltage of the buck converter (Vin) was gradually increased from 0V to 5V and the command reference (Vcmd) was simultaneously increased from 0V to 1.4V by monitoring the output voltage.
5 The Vcmd is adjusted until the output voltage settles to the required value and digital modulator outputs a PWM signal with constant switching frequency.
6 A power resistor of 1Ω (2Ω 5W || 2Ω 5W – part number DALE RH-5 5W 2Ω 1%) is connected across the output capacitor for setting the load current.
7 The phase or the switch node voltage (Vphase) was measured.
8 The gate drive ( 2GSv ) for the lower MOSFET (LFET) and the gate voltage at the upper MOSFET (UFET) was measured.
9 The output voltage ( OUTv ) of the buck converter was measured.
10 The inductor current is measured using the current loop.
The input of the A/D converters, the digital modulator inputs and the VPWM signal are
measured and plotted in the following figures. The scaled inductor voltage at the input of the
A/D converter during on-time and off-time are shown in Figure 5-14 and 5-15 respectively.
From Figure 5-14 and 5-15 the A/D input voltages can be determined to be
_ _ _ _( 1) 1.65 ( 0) 1.2Lpos adc input Lneg adc inputV VPWM V and V VPWM V= = = = (5-6)
The LSB equivalent of the A/D converters is given as
_ 930 8
1V 3.92 2 1 2 1LSB ADS N
Full ScaleV mV−= = =
− − (5-7)
The theoretical A/D output in each case can be derived as
137
( ) ( ) ( )10 2930
1.65 1166 10100110IDEAL
LSBADS
VLPOSV
−= = = (5-8)
( ) 210_ 930
(1.2 1) 51 (00110011)IDEALLSB ADS
VLNEGV
−= = = (5-9)
The measured A/D outputs as determined from Figures 5-16 and 5-17 for the inductor
voltage during the on-time and off-time are given as,
2 10[7 0] (10100001) (161)measuredVLPOS − = = (5-10)
2 10[7 0] (00111100) (60)measuredVLNEG − = = (5-11)
Thus the measured A/D outputs closely approximate the outputs predicted from the
theoretical expression. The A/D outputs, VLPOS [7-0] and VLNEG [7-0] forms the step value
for the successive accumulation process in the digital timing generator.
From figure 5-19, the error voltage A/D input can be determined to be 1.4 V. The
theoretical A/D output can be derived as,
10_ 930
1.4 1 (102)idealLSB ADS
VERRADV
−= = (5-12)
( ) 102[7 0] 01101110 (110)measuredVERRAD − = = (5-13)
The measured output approximately equals the theoretical output.
5.3.1 Digital Inverse Timing Generator Testing
The synthetic ripple modulator based on hysteretic control involves generation of on-time
and off-time duration for the power MOSFETs with inverse relation to the inductor voltage. The
inverse timing generator was implemented on the ALTERA UP2 board and tested over the entire
input range of 0.25 V to 5.25 V. The measured time duration from the ALTERA board is
compared with the time duration obtained from simulation and theoretical expression. The time
duration comparison plot is indicated in Figure 5-20.
138
The time duration comparison plot utilizes the following theoretical expression to compare
the measured digital timing generator output with that of the simulation and theory.
LON OFF
L L
L I Kt or tV V×∆
= = (5-14)
The percentage timing error between the digital and the theoretical approaches is plotted in
Figure 5-21. As evident from Figure 5-21, the error is less than 4% over the entire input range.
5.3.2 Command to Output Transfer Characteristic of Digital Synthetic Ripple Modulator Controlled Buck Converter
The property of the synthetic ripple modulator to linearly control the output variable with
the command reference was verified with the following test. The command voltage Vcmd is
varied from 1.25 V to 1.85 V and the corresponding buck converter output voltage is measured.
The linear plot of Vout vs Vcmd is obtained for various input voltages and load currents. The
linearity plots are indicated in Figures 5-22 to 5-26. As evident from these figures, the linear
control of the output variable, namely the output voltage using the synthetic ripple modulation
technique is proved with the experimental implementation.
5.3.3 Load transient response Step-Response of Digital Synthetic Ripple Modulator Controlled Buck Converter
The open-loop load transient response of the converter is tested by providing a load step of
1.5 A at the rate of 50 A/µs with a constant command voltage of 1.3 V. The load-step, inductor
current and the output voltage are indicated in Figure 5-27. The load transient is created by
including a load of 0.5 Ω to an already existing load of 1 Ω. It is evident from figure 5-27 that
the digital SRM responds instantaneously to the load transient even under open-loop condition
with a droop in output voltage. In Figure 5-28, with Vcmd=1.5 V a similar load transient is
applied. The figure depicts the fast response of the digital SRM wherein the upper MOSFET is
turned ON instantaneously, indicated by the VPWM signal.
139
5.3.4 Variation of Switching Frequency Based on Load Conditions
The variation of the switching frequency in hysteretic mode of control can be
advantageous under light load condition. Due to reduced switching frequency under light load
conditions, the associated switching losses are also reduced. The variation of the switching
frequency for the digital SRM control buck converter was investigated and associated results are
shown in Figure 5-28. As evident from the figure, the converter switches at a lower frequency for
load currents less than 1 A, thereby reducing the switching loss in the power MOSFETs and the
gate driver. The variations in the switching frequency can lead to a potential drawback caused by
the introduction of undesirable harmonics into the system. This complicates the design of the
buck converter output filter.
5.4 Future Directives for Research
The synthetic ripple modulation technique can be used in the control of motor drive
controllers requiring time duration inversely proportional to a control input. The synthetic ripple
modulation based on hysteretic control can provide efficient operation by operating at a lower
switching frequency under light loads. The synthetic ripple modulation technique can be applied
to the control of low-voltage VRM (Voltage Regulation Module) powering the modern
microprocessors.
140
Table 5-1 Equipment list and specifications S.No Equipment number Specifications 1 HP6263 Triple output power supply 0-6V,0-2.5A / 0±20V,0-0.5A 2 HPE3617A DC power supply 0-60V,0-1A 3 Agilent E3631A Triple Output power Supply 0-6V,5A / 0-±25V, 1A 4 Tektronix AM503 current probe amplifier
TM502A 20A (dc + peak ac) for current probe AM6302
5 Tektronix TDS460A 4-channel digitizing oscilloscope
400MHz, 100 MSa/s
6 PM 5192 programmable synthesizer, function generator
0.1mHz – 20MHz
7 HP6024A DC power supply 0-60V,0-10A, 200W
141
VPWM
Liphasev outi
Cv
Lv
AM503 Current-probeAmplifier
TEKTRONIX P5200High-VoltageDifferential-probe
1DSi
PAPST MOTOREN 4600X106 CFM Fan
46
04
TEK
TRO
NIX
TDS
Ach
anne
lD
igiti
zing
Stor
age
Osc
illos
cope
−
2GSv
TEKTRONIX TM502A
, LL r
C
CrinV
outV
UFET
LFET
460TEKTRONIXTDS A
Figure 5-1. Experimental test-bed setup used for characterizing the DC-DC synchronous buck
converter
Figure 5-2. Phase node voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3
142
Figure 5-3. Output voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3
Figure 5-4. PWM Input (CH2) and high-side gate drive (CH1) for Vin=5V and D=0.3
143
Figure 5-5. PWM input (CH2) and Vphase (CH1) for Vin=5V and D=0.3
Figure 5-6. PWM input (CH2) and low-side gate drive (CH1) for Vin=5V and D=0.3
144
Figure 5-7. Phase node voltage (CH1) and low-side gate drive (CH4) for Vin=5V and D=0.3
Figure 5-8. Phase node voltage (CH1), output voltage (CH2) and inductor voltage (Math2) for Vin=5V and D=0.3
145
Figure 5-9. Vphase_pos1 (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25
Figure 5-10. Vout_neg1 (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25
146
Figure 5-11. VLpos_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25
Figure 5-12. VLneg_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25
147
Figure 5-13. Verr_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.3
Figure 5-14. VLpos_adc_input (CH3), register-enable - blnk_pos (CH4) and VPWM from digital modulator (CH1) for Vin=5V and Vcmd=1.38
148
Figure 5-15. VLneg_adc_input (CH3), register-enable - blnk_neg (CH4) and VPWM from digital modulator (CH1) for Vin=5V and Vcmd=1.38
149
A
B
C
D
E F
G
H Figure 5-16. A/D converter output for inductor voltage during on-time-VLPOS [7-0] (CH3),
register enable-blnk_pos (CH4), and VPWM (CH1). A) VLPOS0 (LSB). B) VLPOS1. C) VLPOS2. D) VLPOS3. E) VLPOS4. F) VLPOS5. G) VLPOS6. H) VLPOS7 (MSB).
150
A
B
C D
E
F
G H Figure 5-17. A/D converter output for inductor voltage during off-time-VLNEG [7-0] (CH3),
register enable-blnk_neg (CH4), and VPWM (CH1). A) VLNEG0 (LSB). B) VLNEG1. C) VLNEG2. D) VLNEG3. E) VLNEG4. sF) VLNEG5. G) VLNEG6. H) VLNEG7 (MSB).
151
A
B
C
D
E F
G
H Figure 5-18. A/D output for error voltage between Vcmd and Vout – VERRAD [7-0] (CH3),
register enable-blnk_neg (CH4), and VPWM (CH1). A) VERRAD0 (LSB). B) VERRAD1. C) VERRAD2. D) VERRAD3. E) VERRAD4. F) VERRAD5. G) VERRAD6. H) VERRAD7 (MSB).
152
Figure 5-19. Verr_adc_input (CH1) and VPWM from digital modulator (CH4) for Vin=5V and Vcmd=1.38
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
2
4
6
8
10
12
14
16
18
20
Inductor Voltage VL (V)
Tim
e du
ratio
n ge
nera
ted
from
dig
ital i
nver
se ti
min
g ge
nera
tor (
us)
Measured dataSimulation dataTheoretical Expression
Figure 5-20. Timing generation comparison based on simulation, theory and experimental digital timing generation approach
153
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50.5
1
1.5
2
2.5
3
3.5
4
Inductor voltage VL (V)
Perc
enta
ge e
rror
bet
wee
n di
gita
l tim
ing
gene
rato
r and
theo
retic
al a
ppro
ach
(%)
Figure 5-21. Percentage timing error based on experimental digital timing generation approach
1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.60.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Command Input Vcmd (V)
Out
put V
olta
ge V
out (V
)
Vout
Linear Fit
inV = 4.5V
Figure 5-22. Linear plot of Vout Vs Vcmd for Vin=4.5V and load resistance RL=1Ω
154
1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.751
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
Command Input Vcmd(V)
Out
put V
olta
ge (V
)
Vin=4.96V RL=1ohm linear
Figure 5-23. Linear plot of Vout Vs Vcmd for Vin=4.96V and load resistance RL=1Ω
1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.650.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
Command Input Vcmd (V)
Out
put V
olta
ge V
out (
V)
Vin = 4.17V RL=1ohm linear
Figure 5-24. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=1Ω
155
1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Command Input Voltage (Vcmd (V) )
Out
put V
olta
ge V
out (
V)
VIn=5V RL=0.67ohm
linear
Figure 5-25. Linear plot of Vout Vs Vcmd for Vin=5V and load resistance RL=0.67Ω
1.25 1.3 1.35 1.4 1.45 1.5 1.550.9
0.95
1
1.05
1.1
1.15
1.2
1.25
Command Input Voltage(Vcmd) (V)
Out
put V
olta
ge (V
out (
V))
Vin=4.17V RL=0.67ohm linear
Figure 5-26. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=0.67Ω
156
2 ( ) outCH V Output Voltage−
4 (1 / ) CH Inductor Current A div−
3 (50 / ) CH Load transient step A sµ−
Figure 5-27. Load transient response of the digital SRM Vout (CH2), inductor current (CH4) and load current step (CH3)
157
0.5 1 1.5 2 2.5 3 3.5 4
640
650
660
670
680
690
700
Load Current Iout (A)
Switc
hing
freq
uenc
y (k
Hz)
Vin = 4.35VVin = 4.00VVin = 3.75V
Figure 5-28. Variation of switching frequency with respect to load current for Vin=3.75V, 4.00V and 4.35V
158
CHAPTER 6 CONCLUSION
6.1 Summary
Synthetic ripple modulation technique enables carrier signal generation from system
parameters. The SRM facilitates the controlled variable to be regulated with a tight tolerance
while providing sufficient ripple for PWM control. The modulation strategy superimposes the
controlled variable with the synthetic ripple and thereby allows direct control of the output
variable. The SRM scheme also provides the significant advantage of linear control of the output
variable with a command signal even under open-loop conditions. Since the synthetic ripple
modulation derives its principle from hysteretic mode of control, superior dynamic performance
is guaranteed. Thus the potential benefits of current mode control and hysteretic mode control
are achieved without the need for current sensing or a fast resolution PWM comparator.
The digital SRM based on the synthetic ripple modulation scheme generates duty ratio
with inverse relation to a sampled converter parameter. The digital duty ratio generation involves
a unique scaling process to eliminate the need for higher clock frequency and reduces power
consumption. The programmable scaling factor allows realization of various switching
frequencies and utilization of similar hardware for different applications. Since the carrier signal
is derived from the converter parameter, the modulation scheme offers natural input feed-
forward control. The principle of the digital SRM was validated with simulation and
experimental results. The application of the digital SRM to the control of a DC-DC synchronous
buck converter was tested and verified experimentally.
6.2 Future Work
The DC-DC buck converter application requires the design of a digital compensator to
account for the error between the output voltage and the command voltage. The design of digital
159
compensator ensures closed-loop operation and guarantees the regulation of the output voltage to
load transient conditions. The digital SRM strategy can be extended to the control of DC-AC
inverters and speed control of induction motor drives. These applications generally involve
hysteretic operation and require duty ratio generation with inverse relation to a given control
input.
160
APPENDIX A MATLAB FUNCTIONS
A.1 Inductor Voltage Quantization function MATLAB function to generate the quantized amplitude for a given inductor voltage using
NL=8, VLmax=5.25V.
function [GNL_cmplx]=GNL_amp(sg_in) NL=8; LF=4.7e-6; Ihys=0.64; a_max= 5.25; qsg_bin=dfn_quant_bin(sg_in,NL,a_max); % % Quantized Amplitude based delays if qsg_bin <= 44 t_NL=2; elseif qsg_bin >= 45 && qsg_bin <= 56 t_NL= 87.19 + 35.831 * ( qsg_bin - 46 ) ; elseif qsg_bin >= 57 && qsg_bin <= 70 t_NL= 50.41 + 17.25 * ( qsg_bin - 57 ) ; elseif qsg_bin >= 71 && qsg_bin <= 84 t_NL= 9.829 + 15.572 * ( qsg_bin - 71 ) ; elseif qsg_bin >= 85 && qsg_bin <= 91 t_NL= -5.043 + 20.143 * ( qsg_bin - 85 ) ; elseif qsg_bin >= 92 && qsg_bin <= 99 t_NL= 47.26 + 17.248 * ( qsg_bin - 92 ) ; elseif qsg_bin >= 100 && qsg_bin <= 105 t_NL= 1.349 + 18.655 * ( qsg_bin - 100 ) ; elseif qsg_bin >= 106 && qsg_bin <= 111 t_NL= 59.49 + 14.7367 * ( qsg_bin - 106 ) ; elseif qsg_bin >= 112 && qsg_bin <= 120 t_NL= -13.71 + 11.516 * ( qsg_bin - 112 ) ; elseif qsg_bin >= 121 && qsg_bin <= 127 t_NL= 22.13 + 10.212 * ( qsg_bin - 121 ) ; elseif qsg_bin >= 128 && qsg_bin <= 134 t_NL= 9.871 + 9.1318 * ( qsg_bin - 128 ) ; elseif qsg_bin >= 135 && qsg_bin <= 141 t_NL= 30.25 + 8.212 * ( qsg_bin - 135 ) ; elseif qsg_bin >= 142 && qsg_bin <= 148 t_NL= 4.914 + 7.4272 * ( qsg_bin - 142 ) ; elseif qsg_bin >= 149 && qsg_bin <= 155 t_NL= 14.13 + 6.748 * ( qsg_bin - 149 ) ; elseif qsg_bin >= 156 && qsg_bin <= 162 t_NL= 18.9 + 6.158 * ( qsg_bin - 156 ) ; elseif qsg_bin >= 163 && qsg_bin <= 170 t_NL= 19.81 + 4.702 * ( qsg_bin - 163 ) ; elseif qsg_bin >= 171 && qsg_bin <= 177 t_NL= 17.33 + 5.188 * ( qsg_bin - 171 ) ; elseif qsg_bin >= 178 && qsg_bin <= 184 t_NL= 11.87 + 4.788 * ( qsg_bin - 178 ) ; elseif qsg_bin >= 185 && qsg_bin <= 198
161
t_NL= 3.787 + 4.1525 * ( qsg_bin - 185 ) ; elseif qsg_bin >= 199 && qsg_bin <= 205 t_NL= 20.52 + 3.83 * ( qsg_bin - 199 ) ; elseif qsg_bin >= 206 && qsg_bin <= 216 t_NL= 6.127 + 3.252 * ( qsg_bin - 206 ) ; elseif qsg_bin >= 217 && qsg_bin <= 227 t_NL= 1.27 + 2.947 * ( qsg_bin - 217 ) ; elseif qsg_bin >= 228 && qsg_bin <= 245 t_NL= -6.854 + 2.6365 * ( qsg_bin - 228 ) ; elseif qsg_bin >= 246 && qsg_bin <= 255 t_NL= -0.02795 + 3.5935 * ( qsg_bin - 246 ) ; end t_NL=t_NL*1e-9; t_ana=(LF*Ihys) / sg_in ; % Determination of ideal analog time duration due to the quantized value amp_tdiff= (LF*Ihys) / ( t_ana + t_NL ) ; % Incrementing the quantized amplitude with the amplitude due % to timing error GNL_cmplx = amp_tdiff ;
A.2 Error Voltage Quantization function MATLAB function to generate the quantized amplitude for the error voltage between the
output voltage and command signal.
function [GNE_cmplx]=GNE_amp(sg_in) NE=5; a_max=300e-3; topamp=1000e-9; tclk=40e-9; GNE_amp=dfn_quant(sg_in,NE,a_max); % Input signal quantized amp and phase GNE_cmplx=abs(GNE_amp);
A.3 Dynamic system model transfer function MATLAB code for generating the command to output transfer function, command to duty
ratio transfer function, and duty ratio to output voltage transfer function. The code utilizes the
inductor voltage A/D converter quantization function, namely, GNL_amp(). It also utilizes the
error voltage A/D converter quantization function, namely, GNE_amp(). The functional
description for the quantization functions are indicated above.
% Frequency response of Digital SRM
162
clear clc NL=8; NC=4; NAD=3; Verrmax=1.5; Vinmax=5.25; Ihys=0.64; tclk=40e-9; topamp=840e-9; low_freq=1; high_freq=500e3; freq_values=linspace(low_freq,high_freq,10000); len_freq=length(freq_values); Vin=5; Vcmd=1.5; R=0.2; D=0.306; rL=15e-3; rC=10e-3; L=4.7e-6; Co=500e-6; Vout=1.51; NSC= ((2^NC)*(Vinmax/2^NL)*tclk)/(L*Ihys); Vhys=(2^NC)*(Vinmax/2^NL); Tsw=3.33e-6; for j=1:len_freq % Vcmd to Duty ratio function wf(j)=2*pi*freq_values(j); Num= GNL_amp(Vout)*(1-(2*D)) + D*(GNL_amp(Vin)) ; D_A1=Vhys*(GNL_amp(Vin)); D_B1=((GNL_amp(Vin))*(GNE_amp(Vout-Vcmd))) + (2*GNL_amp(Vout)*(GNE_amp(Vcmd-Vout))); D_C1= D*(GNL_amp(Vin)) + ( D*(GNE_amp((2*Vcmd)-(4*Vout))) ) - (GNL_amp(Vhys)) - (GNE_amp(Vcmd-Vout)) + GNL_amp(Vout) ; PDV = (L*Co)*( 1 + (rC/R) ); QDV = (rC*Co) + (L/R); GDV = (Vin * (rC*Co)) / PDV ; pl_1 = (-QDV/(2* PDV)) + (0.5*((((QDV/PDV)^2)-(4/PDV))^0.5)); po_1 = complex(real(pl_1),imag(pl_1)); pl_2 = (-QDV/(2* PDV)) - (0.5*((((QDV/PDV)^2)-(4/PDV))^0.5)); po_2 = complex(real(pl_2),imag(pl_2)); zr_1 = (-1)/(rC*Co); Num_b3(j) = Num * complex(0,(-1)*((wf(j))^3)); Num_b2(j) = Num * ( (4/Tsw) - (po_1+po_2) ) * (-1) * (((wf(j))^2)); Num_b1(j) = Num * ((po_1 * po_2)-((4/Tsw)*(po_1+po_2))) * complex(0,wf(j)); Num_b0(j) = Num * (4/Tsw) * (po_1 * po_2); Den_a3(j) = (D_A1 - D_B1)* complex(0,(-1)*((wf(j))^3)); Den_a2(j) = ((D_A1*((4/Tsw)-(po_1+po_2))) + (D_C1 * GDV) + (D_B1*((4/Tsw)+(po_1+po_2))))*((-1)*((wf(j))^2)); Den_a1(j) = ( (D_A1 * ((po_1 * po_2)-((4/Tsw)*(po_1+po_2))))+ ((D_C1 * GDV)*((4/Tsw)+zr_1)) - (D_B1 * ((po_1 * po_2)+((4/Tsw)*(po_1+po_2)))) ) * complex(0,wf(j));
163
Den_a0(j) = (D_A1*((4/Tsw)*(po_1*po_2))) + ((D_C1 * GDV)*((4/Tsw)*zr_1)) + (D_B1*((4/Tsw)*(po_1*po_2))) ; d_vcmd_num(j) = Num_b3(j) + Num_b2(j) + Num_b1(j) + Num_b0(j) ; d_vcmd_den(j) = Den_a3(j) + Den_a2(j) + Den_a1(j) + Den_a0(j) ; samp_hold1(j) = complex(1,((-1)*wf(j)*(Tsw/4))) /complex(1,(wf(j)*(Tsw/4))); d_vcmd_trfn(j) = ( d_vcmd_num(j) / d_vcmd_den(j) ) ; d_vcmd_mag(j) = 20*log10(d_vcmd_trfn(j)) ; d_vcmd_phase(j) = ( ((angle(d_vcmd_trfn(j))) * (180/pi)) ) ; % Duty ratio to output function gvd_num(j) = complex(Vin,(wf(j)*rC*Co)); gvd_den(j) = complex((1-(((wf(j))^2)*PDV)),(wf(j)*QDV)); gvd_trfn(j) = gvd_num(j) / gvd_den(j); gvd_mag(j)=20*log10(gvd_trfn(j)); gvd_phase(j)=angle(gvd_trfn(j)) *(180/pi); % Command to Output transfer function vo_vcmd_mag(j) = gvd_mag(j) + d_vcmd_mag(j); vo_vcmd_phase(j) = gvd_phase(j) + d_vcmd_phase(j) ; end
164
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[69] Texas Instruments, Dallas, TX: TPS2830 Non-inverting Fast Synchronous Buck MOSFET Drivers with Enable.
[70] Texas Instruments, Dallas, TX: ADS930 8-Bit, 30 MSPS Analog-to-Digital Converter SE/Diff Inputs w/ Internal Ref. and Low Power, Powerdown.
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[71] Linear Technology, Milpitas, CA: LT1022 High-speed Precision JFET Input Operational Amplifier.
[72] Maxim, Sunnyvale, CA, “Basic switching regulator layout techniques,” Appln. Note AN2997. Jan 15, 2004.
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BIOGRAPHICAL SKETCH
Bharath Balaji Kannan was born on February 18, 1980, in Chennai, India. He did his
schooling in SBOA School and Junior College and D.A.V Matriculation Higher Secondary
School. He received his bachelor’s degree in electrical and electronics engineering from College
of Engineering, Anna University, Guindy. He completed his master’s in electrical and computer
engineering at the University of Florida during the summer of 2003. He has been pursuing his
doctoral research in digital control of power converters at the University of Florida since August
2003. His research interests include mixed signal IC design with focus on analog/digital PWM
control of power converters. He is also interested in the field of digital signal processing and
computer networks. His hobbies include listening to music, drawing and painting.
