Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: CMOS circuits, construction Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET The abstraction level of our study: SYSTEM MODULE + GATE CIRCUIT DEVICE n+ SD G V out V in Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET The CMOS inverter recall V DD GND OUT IN n p V DD GND OUT=0 IN=1 V DD GND OUT=1 IN=0 In steady-state only on transistor is "on", the other one is always "off" Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET basic cases, depending on the supply voltage and threshold voltages of the transistors 1. small supply voltage: V DD < V Tn + |V Tp | only one transistor is "on" at a time 2. larger supply voltage V DD > V Tn + |V Tp | when switching over, both transistors are "on" at the same time U IN U V Tn V V Tp V DD V pMOS is "on" 0 0 nMOS is "on" pMOS is V Tp "on" nMOS is "on" Characteristic of the CMOS inverter Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET Characteristic of the CMOS inverter 1. small supply voltage: V DD < V Tn + |V Tp | the characteristics: = DD OUT V U < TnIN VUif V Tn + |V Tp | Switching over? - "mutual conduction" Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET Design for symmetrical operation: If U IN =U inv logic threshold voltage, both transistors have equal current: U GSp =V DD -U K U GSn =U K The CMOS inverter The inverter logic threshold voltage depends on the ratio of the current constants of the transistors. To have U inv at V DD /2 and V Tn =|V Tp |, then K n =K p has to be set. since hole mobility is times less The logic threshold voltage can be set by the W/L ratios 22 )()( TpinvDDpTninvn VUUKVUK pn pnTnTpDD inv KK KKVVU U /1 / Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET The CMOS inverter / dynamic char. Calculation of the switching times What do they depend on? the current driving capability of the output the capacitive load on the output If the characteristics of the two transistors are exactly complementary (K n =K p and V Tn =|V Tp |), rising and falling times will be equal out Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET The capacitnces Intrinsic capacitances of the driving stage Input capacitance of the loading stage (next gate) extrinsic or fanout capacitances wiring (interconnect) capacitance V out1 V in M2M2 M1M1 M4M4 M3M3 V out2 C DB2 C DB1 C GD12 intrinsic MOS transistor capacitances C G4 C G3 extrinsic MOS transistor (fanout) capacitances CwCw wiring (interconnect) capacitance Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET The capacitnces The intrinsic capacitances: S-G G-D overlap capacitances the MOS capacitance of the channel capacitances of pn junctions The wiring capacitance depends on the interconnect geometry (width, length) with the advance of manufacturing processes this capacitance tends to increase See later Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET The CMOS inverter / dynamic char. Calculation of switching times identical times, integration for the extreme values of the voltage of the load capacitance: V LM minimal voltage of the load capacitance If then Can be reduced by increasing the supply voltage or the W/L ratio out Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET Power consumption of CMOS inv.: There is no static consumption since there is no static current There is dynamic consumption during switching which consists of 2 parts: Mutual conduction: During the rise of the input voltage both transistors are "on" V Tn 3.9) L Interconnect - substrate: parallel plate capacitance Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET Interconnect capacitances C wire = C pp + C fringe + C interwire = ( di /t di )WL + (2 di )/log(t di /H) + ( di /t di )HL interwire fringe paralell plate H Budapest University of Technology and Economics Department of Electron Devices CMOS circuits Andrs Poppe, BME-EET Other issues of interconnects Series resistance Distributed parameter RC line (see transmission lines) Sort of a representation of the diffusion equation