Brushless DC Motor Flash MCU HT66FM5230 - Holtek...Co pa e Mat h Output Mode..... 70 Ti e /Counte Mode ..... 73 PWM Output Buzze Cont ol ..... 75 Standard Type TM

Brushless DC Motor Flash MCU

HT66FM5230

Revision: V1.10 Date: De�e��e� �1� �01�De�e��e� �1� �01�

Rev. 1.10 � De�e��e� �1� �01� Rev. 1.10 3 De�e��e� �1� �01�

HT66FM5230Brushless DC Motor Flash MCU

Table of Contents

Features ............................................................................................................ 7CPU Featu�es ......................................................................................................................... 7Pe�iphe�al Featu�es ................................................................................................................. 7

General Description ......................................................................................... 8Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 9Pin Descriptions ............................................................................................ 10Absolute Maximum Ratings .......................................................................... 12D.C. Characteristics ....................................................................................... 12A.C. Characteristics ....................................................................................... 13

HIRC F�equen�y A��u�a�y ove� Devi�e VDD and Te�pe�atu�e ............................................. 13

A/D Converter Characteristics ...................................................................... 14D/A Converter Characteristics ...................................................................... 148-bit R-2R D/A Converter (Analog Conditon VDD=5V, CL=10pF) ................. 15Operational Amplifier Characteristics ......................................................... 15Comparator Electrical Characteristics ........................................................ 16Power on Reset Electrical Characteristics .................................................. 16System Architecture ...................................................................................... 17

Clo�king and Pipelining ......................................................................................................... 17P�og�a� Counte� ................................................................................................................... 18Sta�k ..................................................................................................................................... 19A�ith�eti� and Logi� Unit – ALU ........................................................................................... 19

Flash Program Memory ................................................................................. 20St�u�tu�e ................................................................................................................................ �0Spe�ial Ve�to�s ..................................................................................................................... �0Look-up Ta�le ........................................................................................................................ �0Ta�le P�og�a� Exa�ple ........................................................................................................ �1In Ci��uit P�og�a��ing ......................................................................................................... ��On-Chip De�ug Suppo�t – OCDS ......................................................................................... �3

RAM Data Memory ......................................................................................... 23St�u�tu�e ................................................................................................................................ �3

Special Function Register Description ........................................................ 25Indi�e�t Add�essing Registe�s – IAR0� IAR1 ......................................................................... �5Me�o�y Pointe�s – MP0� MP1 .............................................................................................. �5Bank Pointe� – BP ................................................................................................................. ��A��u�ulato� – ACC ............................................................................................................... ��P�og�a� Counte� Low Registe� – PCL .................................................................................. ��Look-up Ta�le Registe�s – TBLP� TBHP� TBLH ..................................................................... ��Status Registe� – STATUS .................................................................................................... �7

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EEPROM Data Memory .................................................................................. 29EEPROM Data Me�o�y St�u�tu�e ........................................................................................ �9EEPROM Registe�s .............................................................................................................. �9Reading Data f�o� the EEPROM ........................................................................................ 31W�iting Data to the EEPROM ................................................................................................ 31W�ite P�ote�tion ..................................................................................................................... 31EEPROM Inte��upt ................................................................................................................ 31P�og�a��ing Conside�ations ................................................................................................ 31

Oscillator ........................................................................................................ 33Os�illato� Ove�view ............................................................................................................... 33System Clock Configurations ................................................................................................ 33Inte�nal �0MHz RC Os�illato� – HIRC ................................................................................... 34Inte�nal 3�kHz Os�illato� – LIRC ........................................................................................... 34Supple�enta�y Clo�ks .......................................................................................................... 34

Operating Modes and System Clocks ......................................................... 35Syste� Clo�ks ...................................................................................................................... 35Syste� Ope�ation Modes ...................................................................................................... 3�Cont�ol Registe� .................................................................................................................... 37Ope�ating Mode Swit�hing ................................................................................................... 39NORMAL Mode to SLOW Mode Swit�hing ........................................................................... 39SLOW Mode to NORMAL Mode Swit�hing .......................................................................... 39Ente�ing the SLEEP Mode .................................................................................................... 41Ente�ing the IDLE0 Mode ...................................................................................................... 41Ente�ing the IDLE1 Mode ...................................................................................................... 41Stand�y Cu��ent Conside�ations ........................................................................................... 4�Wake-up ................................................................................................................................ 4�

Watchdog Timer ............................................................................................. 43Wat�hdog Ti�e� Clo�k Sou��e .............................................................................................. 43Wat�hdog Ti�e� Cont�ol Registe� ......................................................................................... 43Wat�hdog Ti�e� Ope�ation ................................................................................................... 44

Reset and Initialisation .................................................................................. 45Reset Fun�tions .................................................................................................................... 45Reset Initial Conditions ......................................................................................................... 47

Input/Output Ports ......................................................................................... 51I/O Registe� List .................................................................................................................... 51Pull-high Resisto�s ................................................................................................................ 51Po�t A Wake-up ..................................................................................................................... 5�I/O Po�t Cont�ol Registe�s ..................................................................................................... 53Pin-sha�ing Fun�tions ........................................................................................................... 54Pin-�e�apping Fun�tions ...................................................................................................... 5�Pin-�e�apping Registe�s ....................................................................................................... 5�I/O Pin St�u�tu�es .................................................................................................................. 57P�og�a��ing Conside�ations ................................................................................................ 58

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Timer Modules – TM ...................................................................................... 58Int�odu�tion ........................................................................................................................... 58TM Ope�ation ........................................................................................................................ 59TM Clo�k Sou��e ................................................................................................................... 59TM Inte��upts ......................................................................................................................... 59TM Exte�nal Pins ................................................................................................................... 59P�og�a��ing Conside�ations ................................................................................................ �0

Compact Type TM – CTM .............................................................................. 61Co�pa�t TM Ope�ation ......................................................................................................... �1Co�pa�t Type TM Registe� Des��iption................................................................................ ��Co�pa�t Type TM Ope�ating Modes .................................................................................... 70Co�pa�e Mat�h Output Mode ............................................................................................... 70Ti�e�/Counte� Mode ............................................................................................................. 73PWM Output Mode ................................................................................................................ 73Buzze� Cont�ol ...................................................................................................................... 75

Standard Type TM – STM .............................................................................. 76Standa�d TM Ope�ation ......................................................................................................... 7�Standa�d Type TM Registe� Des��iption ............................................................................... 77Standa�d Type TM Ope�ating Modes .................................................................................... 81Co�pa�e Output Mode .......................................................................................................... 81Ti�e�/Counte� Mode ............................................................................................................. 84PWM Output Mode ................................................................................................................ 84Single Pulse Mode ................................................................................................................ 87Captu�e Input Mode .............................................................................................................. 87

Capture Timer Module – CAPTM .................................................................. 90Captu�e Ti�e� Ove�view ....................................................................................................... 90Captu�e Ti�e� Registe� Des��iption ..................................................................................... 90Captu�e Ti�e� Ope�ation ....................................................................................................... 94Captu�e Mode Ope�ation ....................................................................................................... 94Co�pa�e Mode Ope�ation ..................................................................................................... 94Noise Filte� ............................................................................................................................ 95Noise Filte� Registe�s Des��iption ......................................................................................... 95

Comparators .................................................................................................. 96Co�pa�ato�s Blo�k Diag�a� ................................................................................................. 9�Co�pa�ato� Ope�ation .......................................................................................................... 97

Analog to Digital Converter .......................................................................... 98A/D Ove�view ........................................................................................................................ 98A/D Conve�te� Registe� Des��iption ...................................................................................... 99A/D Conve�te� Data Registe�s – ADRL� ADRH ................................................................... 100A/D Conve�te� Cont�ol Registe�s – ADCR0� ADCR1� ADCR�� ADDL ................................. 100A/D Conve�te� Bounda�y Registe�s – ADLVDL� ADLVDH� ADHVDL� ADHVDH ................. 10�A/D Ope�ation ..................................................................................................................... 103Su��a�y of A/D Conve�sion Steps ..................................................................................... 104

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P�og�a��ing Conside�ations .............................................................................................. 105A/D T�ansfe� Fun�tion ......................................................................................................... 105A/D P�og�a��ing Exa�ples ............................................................................................... 10�

Over-current Detection ................................................................................ 108Ove�-�u��ent Fun�tional Des��iption ................................................................................... 108Ove�-�u��ent Registe� Des��iption ....................................................................................... 108

BLDC Motor Control Circuit .........................................................................110Fun�tional Des��iption ..........................................................................................................110PWM Counte� Cont�ol Ci��uit ..............................................................................................111Mask Fun�tion ......................................................................................................................115Othe� Fun�tions ................................................................................................................... 1�0Hall Senso� De�ode� ........................................................................................................... 1��Moto� P�ote�tion Fun�tion ................................................................................................... 130

I2C Interface ................................................................................................. 135I�C Inte�fa�e Ope�ation ....................................................................................................... 135I�C Registe�s ....................................................................................................................... 13�I�C Bus Co��uni�ation ..................................................................................................... 139I�C Bus Sta�t Signal ............................................................................................................ 140Slave Add�ess .................................................................................................................... 140I�C Bus Read/W�ite Signal ................................................................................................. 140I�C Bus Slave Add�ess A�knowledge Signal ...................................................................... 141I�C Bus Data and A�knowledge Signal .............................................................................. 141I�C Ti�e-out Cont�ol ............................................................................................................ 14�

Interrupts ...................................................................................................... 143Inte��upt Registe�s ............................................................................................................... 143Inte��upt Ope�ation .............................................................................................................. 149Exte�nal Inte��upt 0 .............................................................................................................. 151Exte�nal Inte��upt 1 .............................................................................................................. 151Co�pa�ato� Inte��upt ........................................................................................................... 151Ti�e Base Inte��upt ............................................................................................................. 151Multi-fun�tion Inte��upt ........................................................................................................ 15�A/D Conve�te� Inte��upt ....................................................................................................... 153PWM Module Inte��upts ...................................................................................................... 153CAPTM Module Inte��upt .................................................................................................... 153TM Inte��upt ......................................................................................................................... 153EEPROM Inte��upt .............................................................................................................. 154LVD Inte��upt ....................................................................................................................... 154I�C Inte��upt ......................................................................................................................... 154Inte��upt Wake-up Fun�tion ................................................................................................. 154P�og�a��ing Conside�ations .............................................................................................. 155

Low Voltage Detector – LVD ....................................................................... 156LVD Registe� ....................................................................................................................... 15�LVD Ope�ation ..................................................................................................................... 157

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Application Circuits ..................................................................................... 158Th�ee Phase BLDC Hall Senso� Solution (VB=�4V) ............................................................ 158Th�ee Phase BLDC Hall Senso�less Solution (VB=�4V) ..................................................... 158Single Phase BLDC Hall Senso� Solution (VB=1�V) ........................................................... 159Single Phase BLDC Hall Senso�less Solution (VB=1�V) ..................................................... 159

Instruction Set .............................................................................................. 160Int�odu�tion ......................................................................................................................... 1�0Inst�u�tion Ti�ing ................................................................................................................ 1�0Moving and T�ansfe��ing Data ............................................................................................. 1�0A�ith�eti� Ope�ations .......................................................................................................... 1�0Logi�al and Rotate Ope�ation ............................................................................................. 1�1B�an�hes and Cont�ol T�ansfe� ........................................................................................... 1�1Bit Ope�ations ..................................................................................................................... 1�1Ta�le Read Ope�ations ....................................................................................................... 1�1Othe� Ope�ations ................................................................................................................. 1�1Inst�u�tion Set Su��a�y ..................................................................................................... 1��

Instruction Definition ................................................................................... 164Package Information ................................................................................... 173

1�-pin NSOP (150�il) Outline Di�ensions ......................................................................... 174�0-pin SSOP (150�il) Outline Di�ensions ......................................................................... 175

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Features

CPU Features• OperatingVoltage:

fSYS=32kHz~20MHz:4.5V~5.5V

• Upto0.2μsinstructioncyclewith20MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Oscillators:Internal20MHz–HIRCInternal32kHz–LIRC

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• 6-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:2K×16

• RAMDataMemory:256×8

• TrueEEPROMMemory:32×8

• WatchdogTimerfunction

• Upto18bidirectionalI/Olines

• Fourpin-sharedexternalinterrupts

• Single10-bitCTM

• Single16-bitCTM

• Single10-bitSTM

• Single16-bitCAPTMformotorprotect

• 3-channel10-bitPWMwithcomlementaryoutputsforBLDCapplication

• 6-channel10-bitresolutionA/Dconverter

• Time-Basefunctionforgenerationoffixedtimeinterruptsignal

• SingleoperationalAmplifierforcurrentdetection

• Fourcomparatorswithinterruptfunctions

• Single8-bitD/AConverter

• I2Cinterface

• Lowvoltageresetfunction

• Lowvoltagedetectfunction

• Packagetypes:16-pinNSOP-A,20-pinSSOP-A

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General DescriptionThisdeviceisFlashMemorywith8-bithighperformanceRISCarchitecturemicrocontrollerdevicewhichincludesahostoffullyintegratedspecialfeaturesspecificallydesignedforthebrushlessDCmotorapplications.

Theadvantagesoflowpowerconsumption,I/Oflexibility,MultipleandextremelyflexibleTimerModules,oscillatoroptions,multi-channelA/DandD/AConverter,PulseWidthModulationfunction,16-bitCaptureTimerModulefunction,comparatorfunctions,MotorProtectModule,TimeBasefunction,LVD,TrueEEPROM,power-downandwake-upfunctions,CommunicationwiththeoutsideworldiscateredforbyincludingfullyintegratedI2Cinterfacefunctions,althoughespeciallydesignedforbrushlessDCmotorapplications,theenhancedversatilityofthisdevicealsomakesitapplicableforusinginawiderangeofA/Dapplicationpossibilitiessuchassensorsignalprocessing,motordriving,industrialcontrol,consumerproducts,subsystemcontrollers,etc.

Block Diagram

VDD

VSS

PositionDetectionCKT

ADC10-bitx6

PA3/TCK1/H1/C1P

I2C

PB0/HAO/AN3

PB3/TCK0/C1N

STM-10bitx1CTM-10bitx1CTM-16bitx1

PB1/CTIN/HBO/AN4

MCU(1)ROM:2KW(2)RAM:256x8(3)EEPROM:32x8(4)Stack:6

MotorControlCKT

ProtectionCKT

CurrentSenseCKT

PA1/TCK2/AN2/AP

HIRC=20MHzLIRC=32KHz

WDTLVRLVD

PC0/TP0_0/GATPC1/TP0_1/GABPC2/TP1_0/GBTPC3/TP1_1/GBBPC4/TP2_0/GCTPC5/TP2_1/GCB

AVDD

AVSS

PA7/NFIN/AN1

PA2/SCL/OCDSCK/ICPCK

PA0/SDA/OCDSDA/ICPDA

PB2/HCO/AN5

PA4/H2/[SDA]/C2P/[C1N]

PA5/H3/[SCL]/C3P

PA6/[C1N]/AN0

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Pin Assignment

PA5/H3/[SCL]/C3PPA�/[CIN]/AN0PA7/NFIN/AN1

VSS/AVSSVDD/AVDD

PA1/TCK�/AN�/APPC0/TP0_0/GATPC1/TP0_1/GAB

PA4/H�/[SDA]/C�P/[C1N]PA3/TCK1/H1/C1PPA�/SCL/OCDSCK/ICPCKPA0/SDA/OCDSDA/ICPDAPC5/TP�_1/GCBPC4/TP�_0/GCTPC3/TP1_1/GBBPC�/TP1_0/GBT

HT66FM523016NSOP-A

1�345�78

1�1514131�11109

HT66FM523020SSOP-A

1�345�789

�01918171�1514131�1110

PA�/[CIN]/AN0PA7/NFIN/AN1

VSS/AVSSVDD/AVDD

PA1/TCK�/AN�/APPB0/HAO/AN3

PB1/CTIN/HBO/AN4PB�/HCO/AN5

PC0/TP0_0/GATPC1/TP0_1/GAB

PA5/H3/[SCL]/C3PPA4/H�/[SDA]/C�P/[C1N]PA3/TCK1/H1/C1PPB3/TCK0/C1NPA�/SCL/OCDSCK/ICPCKPA0/SDA/OCDSDA/ICPDAPC5/TP�_1/GCBPC4/TP�_0/GCTPC3/TP1_1/GBBPC�/TP1_0/GBT

Note:1.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,itspinnamesattherightsideofthe"/"signcanbeusedforhigherpriority

2.VDD&AVDDmeanstheVDDandAVDDarethedoublebonding.

3.VSS&AVSSmeanstheVSSandAVSSarethedoublebonding.

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Pin DescriptionsPin Name Function OP I/T O/T Description


PA0 PAWU PAPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up and

wake-up.SDA PAPS0 ST NMOS I�C data

OCDSDA — ST CMOS On-�hip de�ug suppo�t data/add�ess pinICPDA — ST CMOS In-�i��uit p�og�a��ing suppo�t data/add�ess pin

PA1/TCK�/AN�/AP

PA1 PAPUPAWU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up and

wake-up.

TCK� PAPS0 ST — TM� input

AN� PAPS0 AN — A/D �hannel �

AP PAPS0 ST — Operational amplifier input

PA�/SCL/OCDSCK/ICPCK

PA� PAPUPAWU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up and

wake-up.

SCL PAPS0 ST NMOS I�C �lo�kOCDSCK — ST — On-�hip de�ug p�og�a��ing �lo�k pin

ICPCK — ST — In-�i��uit p�og�a��ing �lo�k pin

PA3/TCK1/H1/C1P


wake-up.TCK1 PAPS0 ST — TM1 input

H1 PAPS0 ST — HALL Senso� input

C1P PAPS0 AN — Co�pa�ato� 1 input

PA4/H�/[SDA]/C�P/[C1N]


wake-up.H� PAPS1 ST — HALL Senso� input

SDA PAPS1 ST NMOS I�C dataC�P PAPS1 AN — Co�pa�ato� � inputC1N PAPS1 AN — Co�pa�ato� 1 input

PA5/H3/[SCL]/C3P


wake-up.H3 PAPS1 ST — HALL Senso� input

SCL PAPS1 ST NMOS I�C �lo�k

C3P PAPS1 — CMOS Co�pa�ato� 3 input

PA�/[C1N]/AN0PA� PAPU

PAWU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up and wake-up.

C1N PAPS1 AN — Co�pa�ato� 1 inputAN0 PAPS1 AN — A/D �hannel 0

PA7/NFIN/AN1


wake-up.

NFIN PAPS1 ST — Exte�nal inte��upt 1 input

AN1 PAPS1 AN — A/D �hannel 1

PB0/HAO/AN3PB0 PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.HAO PBPS0 — CMOS Test pin fo� SAAN3 PBPS0 AN — A/D �hannel 3

PB1/CTIN/HBO/AN4

PB1 PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.CTIN PBPS0 — — CAPTM inputHBO PBPS0 — CMOS Test pin fo� SBAN4 PBPS0 AN — A/D �hannel 4

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Pin Name Function OP I/T O/T Description

PB�/HCO/AN5PB� PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.HCO PBPS0 — CMOS Test pin fo� SCAN5 PBPS0 AN — A/D �hannel 5

PB3/TCK0/C1NPB3 PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

TCK0 PBPS0 ST — TM1 inputC1N PBPS0 ST — Co�pa�ato� 1 input

PC0/TP0_0/GATPC0 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

TP0_0 PCPS0 ST CMOS TM0 I/OGAT PCPS0 — CMOS Pulse Width Modulation �o�pli�enta�y output

PC1/TP0_1/GABPC1 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

TP0_1 PCPS0 ST CMOS TM0 I/OGAB PCPS0 — CMOS Pulse Width Modulation �o�pli�enta�y output

PC�/TP1_0/GBTPC� PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

TP1_0 PCPS0 ST CMOS TM1 I/OGBT PCPS0 — CMOS Pulse Width Modulation �o�pli�enta�y output

PC3/TP1_1/GBBPC3 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

TP1_1 PCPS0 ST CMOS TM1 I/OGBB PCPS0 — CMOS Pulse Width Modulation �o�pli�enta�y output

PC4/TP�_0/GCTPC4 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

TP�_0 PCPS1 ST CMOS TM� I/OGCT PCPS1 — CMOS Pulse Width Modulation �o�pli�enta�y output

PC5/TP�_1/GCBPC5 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

TP�_1 PCPS1 ST CMOS TM� I/OGCB PCPS1 — CMOS Pulse Width Modulation �o�pli�enta�y output

VSS VSS — PWR — Negative powe� supply� g�ound

AVSS AVSS — PWR — G�ound �onne�tion fo� A/D �onve�te�. The VSS and AVSS a�e the sa�e pin at pa�kage

VDD VDD — PWR — Positive powe� supply

AVDD AVDD — PWR — Powe� supply �onne�tion fo� A/D �onve�te�. The VDD and AVDD a�e the sa�e pin at pa�kage

Note:I/T:Inputtype O/T:OutputtypeOP:Optionalbyconfigurationoption(CO)orregisteroptionPWR:Power ST:SchmittTriggerinputCMOS:CMOSoutput;AN:AnaloginputpinVDDisthedevicepowersupplywhileAVDDistheADCpowersupply.VSSisthedevicegroundpinwhileAVSSistheADCgroundpin.AsthePinDescriptionSummarytableappliestothepackagetypewiththemostpins,notalloftheabovelistedpinsmaybepresentonpackagetypeswithsmallernumbersofpins.

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Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOHTotal....................................................................................................................................-80mAIOLTotal..................................................................................................................................... 80mATotalPowerDissipation........................................................................................................ 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. CharacteristicsTa=�5°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD Ope�ating Voltage — fSYS=3� ~ �0000kHz 4.5 — 5.5 V

IDDOpe�ating Cu��ent(HIRC OSC) 5V No load� fH=�0MHz� ADC off�

WDT ena�le� Moto�_CTL off — 9 1� �A

ISTB Stand�y Cu��ent — LIRC and LVR on� LVD off� WDT ena�le — �0 100 μA

VILInput Low Voltage fo� I/O Po�ts� TCKn� H1� H�� H3 and NFIN — — 0 — 0.3VDD V

VIHInput High Voltage fo� I/O Po�ts� TCKn� H1� H�� H3 and NFIN — — 0.7VDD — VDD V

VLVR LVR Voltage Level — LVR Ena�le� 3.15V option -5% 3.15 +5% VVLVD LVD Voltage Level — LVDEN=1� VLVD=3.�V -5% 3.� +5% VVOL Output Low Voltage fo� I/O Po�ts 5V IOL=�0�A — — 0.5 VVOH Output High Voltage fo� I/O Po�ts 5V IOH=-7.4�A 4.5 — — VRPH Pull-high Resistan�e fo� I/O Po�ts 5V — 10 30 50 kΩ

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A.C. CharacteristicsTa=�5°C



fSYS Syste� Clo�k — 4.5V~5.5V 3� — �0000 kHz

fHIRC Syste� Clo�k (HIRC) 4.5V~5.5VTa=-40˚C~85˚C -1�% �0 +4% MHzTa=-20˚C~85˚C -9% �0 +4% MHzTa=25˚C -�% �0 +�% MHz

fTIMER Ti�e� Input Pin F�equen�y — — — — 4 fSYS

tINT Inte��upt Pulse Width — — 1 — — tSYS

tLVR Low Voltage Width to Reset — — 1�0 �40 480 μstLVD Low Voltage Width to Inte��upt — — �0 45 90 μstLVDS LVDO sta�le ti�e — — 15 — — μstEERD EEPROM Read Ti�e — — — 45 90 μstEEWR EEPROM W�ite Ti�e — — — � 4 �s

tSSTSyste� Sta�t-up Ti�e� Pe�iod(Wake-up f�o� HALT) — fSYS=HIRC — 15~1� — tSYS

tRSTD

Syste� Reset Delay Ti�e(Powe� On Reset) — — �5 50 100 �s

Syste� Reset Delay Ti�e(Any Reset ex�ept Powe� On Reset)

— — 8.3 1�.7 33.3 �s

Note:1.tSYS=1/fSYS

2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

HIRC Frequency Accuracy over Device VDD and Temperature

-1�%~+4%

85℃ ─

70℃ ─

25℃ ─

0℃ ─

-40℃ ─4.5

|5.5

±�%

-9%~+4%

Tem

pera

ture

(℃

)

VDD (V)

-20℃ ─

-9%~+4%

+-�%

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A/D Converter CharacteristicsTa=�5°C


Min. Typ. Max. UnitVDD Condition

AVDD A/D Conve�te� Ope�ating Voltage — — VLVR 5.0 5.5 V

IOP A/D Conve�te� Ope�ating Cu��ent3V — — 0.8 — �A5V — — 1 — �A

ISTBY ADC Stand�y Cu��ent — digital input no �hange — — 1 μA

VREF A/D Conve�te� Refe�en�e Voltage — — � AVDDAVDD

+0.1 V

T�onv A/D Conve�sion Ti�e — — 14 Tad�k

DNL A/D Diffe�ential Non-linea�ity

4.5V VREF=AVDD=VDD� tAD=0.2μs

-3 — 3 LSB

5.5V VREF=AVDD=VDD� tAD=0.2μs4.5V VREF=AVDD=VDD� tAD=6.4μs5.5V VREF=AVDD=VDD� tAD=6.4μs4.5V VREF=AVDD=VDD� tAD=12.8μs5.5V VREF=AVDD=VDD� tAD=12.8μs

INL A/D Integ�al Non-linea�ity

4.5V VREF=AVDD=VDD� tAD=0.2μs

-4 — 4 LSB

5.5V VREF=AVDD=VDD� tAD=0.2μs4.5V VREF=AVDD=VDD� tAD=6.4μs5.5V VREF=AVDD=VDD� tAD=6.4μs4.5V VREF=AVDD=VDD� tAD=12.8μs5.5V VREF=AVDD=VDD� tAD=12.8μs

Ge�� Gain E��o� — — — — ±� LSBTad�k ADCLK Pe�iod — — — 0.� — μsT�kh ADCLK High Width — — — 83 — nsT�kl ADCLK Low Width — — — 83 — nsTst1 Setup Ti�e fo� ADON — — � — — nsTst� Setup Ti�e fo� START lat�h — — � — — nsTsth START High Width — — �5 — — nsTdeo� EOCB Output Delay — AVDD=5V — 3 — nsTdout Output Delay — AVDD=5V — 3 — nsTon ADC Wake Up Ti�e — — � — — μsToff ADC Sleep Ti�e — — — — 5 ns

D/A Converter CharacteristicsTa=�5°C



VDD D/A Ope�ating Cu��ent — — VLVR — 5.5 V

VDA D/A Output Voltage — 00h ~ FFh� no load 0.01 — 0.99 VDD

tDAC D/A Conve�sion Ti�e — VDD=5V� CL=10pF — — � μsRO D/A Output Resistan�e — — — 10 — kΩ

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8-bit R-2R D/A Converter (Analog Conditon VDD=5V, CL=10pF)Model Corner TT SF FS SS FF

Te�pe�atu�e 25˚C 25˚C 25˚C 90˚C -40˚COpe�ating Ave�age Cu��ent(VDD=5V� CL=10pF) 352μA 330μA 374μA 297μA 413μA

Analog Output00000000 (B) ~11111111 (B) 0~4.98V 0~4.981V 0~4.98V 0~4.98V 0~4.981V

Conve�sion Ti�e ≤2μs ≤2μs ≤2μs ≤2μs ≤2μs

Operational Amplifier CharacteristicsTa=�5°C



VOPR1 Ope�ating Voltage 3.3V — �.7 3.3 5.5 VIOFF1 Powe� Down Cu��ent 3.3V — — — 0.1 μA

VOPOS1 Input Offset Voltage 3.3V Without �ali��ation� AOF[4:0]=10000B -15 — +15 �V

VOPOS� Input Offset Voltage 3.3V By �ali��ation -� — +� �V

VCM Co��on Mode Voltage Range 3.3V — VSS — VDD-1.4V V

PSRR Powe� Supply Reje�tion Ratio 3.3V — 90 — 9� dBCMRR Co��on Mode Reju�tion Ratio 3.3V VCM=0~VDD-1.4V — 10� — dBSR Slew Rate+� Slew Rate- 3.3V RL=600Ω, CL=100pF 1.�9 �.18 �.5 V/μsGBW Gain Band Width 3.3V RL=600Ω, CL=100pF �.05 3.70 7.1� MHzAOL Open Loop Gain 3.3V RL=600Ω, CL=100pF — 9� — dBPM Phase Ma�gin 3.3V RL=600Ω, CL=100pF — 90 — —



VOPR1 Ope�ating Voltage 5V — �.7 3.3 5.5 VIOFF1 Powe� Down Cu��ent 5V — — — 0.1 μA

VOPOS1 Input Offset Voltage 5V Without �ali��ation� AOF[4:0]=10000B -15 — +15 �V

VOPOS� Input Offset Voltage 5V By �ali��ation -� — +� �V

VCM Co��on Mode Voltage Range 5V — VSS — VDD-1.4V V

PSRR Powe� Supply Reje�tion Ratio 5V — TBD TBD TBD dBCMRR Co��on Mode Reju�tion Ratio 5V VCM=0 ~ VDD-1.4V TBD TBD TBD dBSR Slew Rate+� Slew Rate- 5V RL=600Ω, CL=100pF TBD TBD TBD V/μsGBW Gain Band Width 5V RL=600Ω, CL=100pF TBD TBD TBD MHzAOL Open Loop Gain 5V RL=600Ω, CL=100pF TBD TBD TBD dBPM Phase Ma�gin 5V RL=600Ω, CL=100pF TBD TBD TBD —

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Comparator Electrical CharacteristicsTa=�5°C



VCMP Co�pa�ato� Ope�ating Voltage 5V — �.� 5.0 5.5 VICMP Co�pa�ato� Ope�atiing Cu��ent 5V — — 300 450 μAIOFF Co�pa�ato� Powe� Down Cu��ent 5V Co�pa�ato� disa�le — — 0.1 μAVCMPOS Co�pa�ato� Input Offset Voltage 5V — -10 — +10 �VVHYS0 Hyste�esis Width 5V Co�pa�ato� 0 TBC 100 TBC �VVHYS1 Hyste�esis Width 5V Co�pa�ato� 1��3 �0 40 �0 �V

VCMInput Co��on Mode Voltage Range — — VSS — VDD-1.4 V

AOL Co�pa�ato� Open Loop Gain — — 100 1�0 — dB

tPD1 Co�pa�ato� Response Ti�e 5V VM= 0~(VDD-1.4)VWith 10�V ove�d�ive — — 1 μs

tPD� Co�pa�ato� Response Ti�e 5V *With 100�V ove�d�ive (note) — — �00 ns

*Note:MeasuredwithcomparatoroneinputpinatVM=(VDD-1.4)/2whiletheotherpininputtransitionfromVSS

to(VM+100mV)orfromVDDto(VM-100mV).

Power on Reset Electrical CharacteristicsTa=�5°C



VPOR VDD Sta�t Voltage to Ensu�e Powe�-on Reset — — — — 100 �VRRVDD VDD Rise Rate to Ensu�e Powe�-on Reset — — 0.035 — — V/�s

tPORMini�u� Ti�e fo� VDD to �e�ain at VPOR to Ensu�e Powe�-on Reset — — 1 — — �s

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System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicetakesadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increasedspeedofoperationandPeriodicperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcall instructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.The internaldatapath issimplifiedbymovingdata throughtheAccumulatorandtheALU.Certain internalregistersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheranHIRCorLIRCoscillator issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

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System Clock and Pipelining

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For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas"JMP"or"CALL" thatdemanda jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program CounterProgram Counter High byte PCL Register

PC10~PC8 PCL7~PCL0

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

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StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

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Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrementINCA,INC,DECA,DEC

• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

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Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdevicetheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberof times,allowing theuser theconvenienceofcodemodificationon thesamedevice.Byusing theappropriateprogramming tools, thisFlashdeviceoffersusers the flexibility toconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof2K×16bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

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Program Memory Structure

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe"TABRDC[m]"or"TABRDL[m]"instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas"0".

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

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InstructionTable Location Bits

b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0TABRDC [�] @10 @9 @8 @7 @� @5 @4 @3 @� @1 @0TABRDL [�] 1 1 1 @7 @� @5 @4 @3 @� @1 @0

Table LocationNote:b10~b0:Tablelocationbits

@7~@0:Tablepointer(TBLP)bits@10~@8:Tablepointer(TBHP)bits

Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis"700H"whichreferstothestartaddressofthelastpagewithinthe2KwordsProgramMemoryofthedevice.Thetablepointerissetupheretohaveaninitialvalueof"06H".ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress"706H"or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthepresentpageifthe"TABRDC[m]"instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe"TABRDC[m]"instructionisexecuted.Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2::mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a mov a,07h ; initialise high table pointermov tbhp,a::tabrdc tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "706H" transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrdc tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "705H" transferred to tempreg2 and TBLH in this ; example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2::org 700h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::

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In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:

Holtek Write Pins MCU Programming Pins FunctionICPDA PA0 P�og�a��ing Se�ial Data/Add�essICPCK PA� P�og�a��ing Se�ial Clo�kVDD VDD Powe� SupplyVSS VSS G�ound

During theprogrammingprocess, theusermust there takecare toensure thatnootheroutputsareconnected to these twopins.TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefortheclock.Twoadditionallinesarerequiredforthepowersupply.The technicaldetails regardingthe in-circuitprogrammingof thedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

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Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitanceof*mustbelessthan1nF.

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On-Chip Debug Support – OCDSAnEVchipexists for thepurposesofdeviceemulation.ThisEVchipdevicealsoprovidesan"On-ChipDebug" function todebug thedeviceduring thedevelopmentprocess.TheEVchipandtheactualMCUdevicesarealmostfunctionallycompatibleexceptfor the"On-ChipDebug"function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinistheOCDSData/Address input/outputpinwhile theOCDSCKpin is theOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpinsintheactualMCUdevicewillhavenoeffectintheEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpins for ICP.ForamoredetailedOCDSdescription, refer to thecorrespondingdocumentnamed"Holteke-Linkfor8-bitMCUOCDSUser’sGuide".

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSDA OCDSDA On-�hip De�ug Suppo�t Data/Add�ess input/outputOCDSCK OCDSCK On-�hip De�ug Suppo�t Clo�k input

VDD VDD Powe� SupplyGND VSS G�ound

RAM Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.TheRAMDataMemorycapacityisupto256×8bits.

StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

TheoverallDataMemoryissubdividedintotwobanks.TheSpecialPurposeDataMemoryregistersareaccessibleinallbanks,withtheexceptionof theEECregisterataddress40H,whichisonlyaccessibleinBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforthedeviceistheaddress00H.

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Data Memory Structure

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Special Purpose Data Memory Structure

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Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof"00H"andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ? code .section at 0 code´org00hstart: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM addressloop: clr IAR0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

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Bank Pointer – BPFor thisdevice, theDataMemory isdivided into twobanks,Bank0andBank1.Selecting therequiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0~1.

TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetinthePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.DirectlyaddressingtheDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafromBank1mustbeimplementedusingIndirectAddressing.

BP Register Bit 7 6 5 4 3 2 1 0

Na�e — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 DMBP0:SelectDataMemoryBanks

0:Bank01:Bank1

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe"INC"or"DEC"instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

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Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe"CLRWDT"or"HALT"instruction.ThePDFflagisaffectedonlybyexecutingthe"HALT"or"CLRWDT"instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVisset ifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe"CLRWDT"instruction.PDFissetbyexecutingthe"HALT"instruction.

• TOisclearedbyasystempower-uporexecutingthe"CLRWDT"or"HALT"instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

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STATUS RegisterBit 7 6 5 4 3 2 1 0

Na�e — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 × × × ×

"×" unknownBit7~6 Unimplemented,readas"0"Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe"CLRWDT"or"HALT"instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe"CLRWDT"instruction1:Byexecutingthe"HALT"instruction

Bit3 OV:Overflowflag0:nooverflow1:anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:noauxiliarycarry1:anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:nocarry-out1:anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

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EEPROM Data MemoryOneofthespecialfeaturesinthedeviceisitsinternalEEPROMDataMemory.EEPROM,whichstandsforElectricallyErasableProgrammableReadOnlyMemory,isbyitsnatureanon-volatileformofmemory,withdataretentionevenwhenitspowersupply is removed.Byincorporatingthiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproduct identificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithintheproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityisupto32×8bits.UnliketheProgramMemoryandRAMDataMemory, theEEPROMDataMemoryisnotdirectlymappedandis thereforenotdirectlyaccessible in the samewayas theother typesofmemory.ReadandWriteoperations to theEEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinBank0andasinglecontrolregisterinBank1.

EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewayasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbedirectlyaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

EEPROM Control Registers List

NameBit

7 6 5 4 3 2 1 0EEA — — — D4 D3 D� D1 D0EED D7 D� D5 D4 D3 D� D1 D0EEC — — — — WREN WR RDEN RD

EEA RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — D4 D3 D� D1 D0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas"0"Bit4~0 DataEEPROMaddress

DataEEPROMaddressbit4~bit0

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EED RegisterBit 7 6 5 4 3 2 1 0

Na�e D7 D� D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 DataEEPROMdataDataEEPROMdatabit7~bit0

EEC RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesetto"1"atthesametimeinoneinstruction.TheWRandRDcannotbesetto"1"atthesametime.

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Reading Data from the EEPROM ToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethigh toenable thewritefunction.TheEEPROMaddressof thedata tobewrittenmust thenbeplacedintheEEAregisterandthedataplacedintheEEDregister.IftheWRbitintheEECregisterisnowsethigh,aninternalwritecyclewillthenbeinitiated.SettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates, theWRbitwillbeautomaticallyclearedtozerobythemicrocontroller,informingtheuserthatthedatahasbeenwrittentotheEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainstinadvertentwriteoperationisprovidedinseveralways.Afterthedeviceispowered-ontheWriteEnablebit inthecontrolregisterwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willberesettozero,whichmeansthatDataMemoryBank0willbeselected.As theEEPROMcontrolregister is located inBank1, thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheEPWEbitintherelevantinterruptregister.WhenanEEPROMwritecycleends,theEPWFrequestflagwillbeset.IftheglobalandEEPROMinterruptsareenabledandthestackisnotfull,ajumptotheassociatedInterruptvectorwilltakeplace.Whentheinterruptisserviced,theEEPROMinterruptflagwillbeautomaticallyreset.MoredetailscanbeobtainedintheInterruptsection.

Programming ConsiderationsCaremustbetakenthatdataisnotinadvertentlywrittentotheEEPROM.ProtectioncanbePeriodicbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrol register exist.Althoughcertainlynotnecessary, considerationmightbegiven in theapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.Theglobal interruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.

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Programming Examples

Reading data from the EEPROM - polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, ASET IAR1.1 ; set RDEN bit, enable read operationsSET IAR1.0 ; start Read Cycle - set RD bitBACK:SZ IAR1.0 ; check for read cycle endJMP BACKCLR IAR1 ; disable EEPROM writeCLR BPMOV A, EED ; move read data to registerMOV READ_DATA, A

Writing Data to the EEPROM - polling methodCLR EMIMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, EEPROM_DATA ; user defined dataMOV EED, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, ASET IAR1.3 ; set WREN bit, enable write operationsSET IAR1.2 ; start Write Cycle - set WR bitSET EMIBACK:SZ IAR1.2 ; check for write cycle endJMP BACKCLR IAR1 ; disable EEPROM writeCLR BP

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OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupts.Fullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock,thedevicehastheflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq.Inte�nal High Speed RC HIRC �0MHzInte�nal Low Speed RC LIRC 3�kHz

Oscillator Types

System Clock ConfigurationsThereare twomethodsofgeneratingthesystemclock,ahighspeedoscillatoranda lowspeedoscillator.Thehighspeedoscillatoristheinternal20MHzRCoscillator.Thelowspeedoscillatoristheinternal32kHz(LIRC)oscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

Theactualsourceclockusedforthehighspeedandthelowspeedoscillatorsischosenviaregisters.ThefrequencyoftheslowspeedorhighspeedsystemclockisalsodeterminedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.Notethattwooscillatorselectionsmustbemadenamelyonehighspeedandone lowspeedsystemoscillators. It isnotpossible tochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.

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System Clock Configurations

Internal 20MHz RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillator has a fixed frequencyof 20MHz.Device trimmingduring themanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethat theinfluenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25˚Cdegrees,thefixedoscillationfrequencyof20MHzwillhaveatolerancewithin2%.

Internal 32kHz Oscillator – LIRCTheInternal32kHzSystemOscillatorisalowfrequencyoscillatorchoice.It isafullyintegratedRCoscillatorwitha typicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationson theoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25˚Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin10%.

Supplementary ClocksThelowspeedoscillator,inadditiontoprovidingasystemclocksourcearealsousedtoprovideaclocksourcetootherdevicefunctions.ThesearetheWatchdogTimerandtheTimeBaseInterrupt.

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Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovided thisdevicewithbothhighand lowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,or lowfrequency,fL,source,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromtheHIRCoscillator.ThelowspeedsystemclocksourcecanbesourcedfromtheLIRCoscillator.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

Therearetwoadditionalinternalclocksfortheperipheralcircuits,thesubstituteclock,fSUB,andtheTimeBaseclock,fTBC.EachoftheseinternalclocksissourcedbytheLIRCoscillator.

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System Clock Configurations

Note:WhenthesystemclocksourcefSYSisswitchedtofLfromfH,thehighspeedoscillationwillstoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

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System Operation ModesThere are fivedifferentmodesofoperation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingthreemodes, theSLEEP,IDLE0andIDLE1ModeareusedwhenthemicrocontrollerCPUisswitchedofftoconservepower.

OperatingMode

DescriptionCPU fSYS fSUB fS fTBC

NORMAL �ode On fH~fH/�4 On On OnSLOW �ode On fL On On OnIDLE0 �ode Off Off On On OnIDLE1 �ode Off On On On OnSLEEP �ode Off Off On On Off

NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbythehighspeedoscillator.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromthehighspeedoscillator,HIRC.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromfL.Running themicrocontroller in thismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregister is low.IntheSLEEPmodetheCPUwillbestopped.HoweverthefLclockswillcontinuetooperate.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimer,TMsandIIC.IntheIDLE0Modethesystemoscillatorwillbestopped,theWatchdogTimerclock,fS,willbeon.

IDLE1 ModeTheIDLE1ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimerandTMs.IntheIDLE1Modethesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModethelowfrequencyclockfSwillbeon.

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Control RegisterTheSMODregisterisusedtocontroltheinternalclockswithinthedevice.

SMOD RegisterBit 7 6 5 4 3 2 1 0

Na�e CKS� CKS1 CKS0 — LTO HTO IDLEN HLCLKR/W R/W R/W R/W — R R R/W R/WPOR 0 0 0 — 0 0 1 1

Bit7~5 CKS2 ~ CKS0:ThesystemclockselectionwhenHLCLKis"0"000:fL(fLIRC)001:fL(fLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbeLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4 Unimplemented,readas"0".Bit3 LTO:LIRCSystemOSCSSTreadyflag

0:Notready1:Ready

ThisisthelowspeedsystemoscillatorSSTreadyflagwhichindicateswhenthelowspeedsystemoscillatorisstableafterpoweronresetorawake-uphasoccurred.Theflagwillchangetoahighlevelafter1~2cyclesiftheLIRCoscillatorisused.

Bit2 HTO:HIRCSystemOSCSSTreadyflag0:Notready1:Ready

ThisisthehighspeedsystemoscillatorSSTreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstableafterawake-uphasoccurred.Thisflagisclearedto"0"byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas"1"bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterpoweronresetorawake-uphasoccurred,theflagwillchangetoahighlevelafter15~16clockcyclesiftheHIRCoscillatorisused.

Bit1 IDLEN:IDLEModeControl0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

Bit0 HLCLK:SystemClockSelection0:fH/2~fH/64orfL1:fH

Thisbit isusedtoselectif thefHclockorthefH/2~fH/64orfLclockisusedasthesystemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~fH/64orfLclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefLclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

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CTRL Register Bit 7 6 5 4 3 2 1 0

Na�e FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — × 0 0

Bit7 FSYSON:fSYSControlinIDLEMode0:Disable1:Enable

Bit6~3 Unimplemented,readas0.Bit2 LVRF:LVRfunctionresetflag

0:Notoccur1:Occurred

Thisbitissetto1whenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit1 LRF:LVRCControlregistersoftwareresetflag0:Notoccur1:Occurred

Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit0 WRF:WDTControlregistersoftwareresetflag0:Notoccur1:Occurred

Thisbit is set to1by theWDTControl register software resetandclearedby theapplicationprogram.Notethatthisbitcanonlybeclearedto0bytheapplicationprogram.

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Operating Mode Switching Thedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionof theIDLENbit in theSMODregisterandFSYSONintheCTRLregister.

WhentheHLCLKbitswitches toa lowlevel,whichimplies thatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfL.IftheclockisfromthefL,thehighspeedclocksourcewillstoprunningtoconservepower.Whenthishappens itmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofother internalfunctionssuchas theTMs.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.

NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower, thesystemclockcanswitch to run in theSLOWModebysetting theHLCLKbitto"0"andsettingtheCKS2~CKS0bitsto"000"or"001"intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequiresthisoscillator tobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

SLOW Mode to NORMAL Mode Switching InSLOWModethesystemusesLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,where thehighspeedsystemoscillator isused, theHLCLKbit shouldbeset to"1"orHLCLKbitis"0",butCKS2~CKS0issetto"010","011","100","101","110"or"111".Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

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Entering the SLEEP ModeThereisonlyonewayforthedevicetoentertheSLEEPModeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"0".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction.buttheWDTorLVDwillremainwiththeclocksourcecomingfromthefLclock.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecounting.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"1"andtheFSYSONbitinCTRLregisterequalto"0".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• The systemclockwill be stoppedand the applicationprogramwill stop at the "HALT"instruction,buttheTimeBaseclockfTBCandthelowfrequencyfLclockwillbeon.





Entering the IDLE1 ModeThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"1"andtheFSYSONbitinCTRLregisterequalto"1".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockandfTBCandthe lowfrequencyfLwillbeonandtheapplicationprogramwillstopatthe"HALT"instruction.





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Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobe takenwith the loads,whichareconnected to I/Opins,whichare setupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.IntheIDLE1Modethesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator, theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

IfthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Theactualsourceof thewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe"HALT"instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

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Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksource isprovidedbythe internalfsclockwhichis in turnsuppliedbytheLIRCoscillator.TheWatchdogTimersourceclockis thensubdividedbyaratioof28 to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.

NotethattheWatchdogTimerfunctionisalwaysenabled,itcanbecontrolledbyWDTCregister.

Watchdog Timer Control RegisterAsingleregister,WDTC,controlstherequiredtimeoutperiodaswellastheenableoperation.TheWDTCregister is initiatedto01010011Batanyresetbutkeepsunchangedat theWDTtime-outoccurrenceinapowerdownstate.

WDTC RegisterBit 7 6 5 4 3 2 1 0

Na�e WE4 WE3 WE� WE1 WE0 WS� WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4 ~ WE0:WDTfunctionsorgwarecontrol10101or01010:EnabledOthervalues:ResetMCU(Resetwillbeactiveafter1~2LIRCclockfordebouncetime.)

Whenthesebitsarechangedbytheenvironmentalnoisetoresetthemicrocontroller,theWRFbitintheCTRLregisterwillbesetto1.

Bit2~0 WS2 ~ WS0:WDTTime-outperiodselection000:28/fS

001:210/fS

010:212/fS

011:214/fS

100:215/fS

101:216/fS

110:217/fS

111:218/fS

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

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CTRL RegisterBit 7 6 5 4 3 2 1 0


Bit7 FSYSON:fSYSControlIDLEModeDescribeelsewhere

Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

DescribeelsewhereBit1 LRF:LVRControlregistersoftwareresetflag

DescribeelsewhereBit0 WRF:WDTControlregistersoftwareresetflag


Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theclearWDTinstructionwillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.Therearefivebits,WE4~WE0,intheWDTCregistertoenabletheWDTfunction.WhentheWE4~WE0bitsvalueisequalto01010Bor10101B,theWDTfunctionisenabled.However,iftheWE4~WE0bitsarechangedtoanyothervaluesexcept01010Band10101B,whichiscausedbytheenvironmentalnoise,itwillresetthemicrocontrollerafter2~3LIRCclockcycles.

WE4 ~ WE0 Bits WDT Function

01010B o� 10101B Ena�le

Any othe� values Reset MCU

Watchdog Timer Enable/Disable Control

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueiswrittenintotheWE4~WE0bitfiledexcept01010Band10101B,thesecondisusingtheWatchdogTimersoftwareclear instructionandthethirdisviaaHALTinstruction.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle"CLRWDT"instructiontocleartheWDT.

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Themaximumtime-outperiodiswhenthe218divisionratioisselected.Asanexample,witha32kHzLIRCoscillatoras itssourceclock, thiswillgiveamaximumwatchdogperiodofaround8secondsforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

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Watchdog Timer

Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsTherearefourwaysinwhichamicrocontrollerresetcanoccur,througheventsoccurringinternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

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Note:tRSTDispower-ondelay,typicaltime=50ms

Power-On Reset Timing Chart

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Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltage,VLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheCTRLregisterwillalsobesetto1.ForavalidLVRsignal,alowvoltage, i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreaterthanthevaluetLVRspecifiedintheA.C.characteristics.Ifthelowvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRisfixedatavoltagevalueof3.15VbytheLVSbitsintheLVRCregister.IftheLVS7~LVS0bitsarechangedtosomecertainvaluesbytheenvironmentalnoise,theLVRwillresetthedeviceafter2~3LIRCclockcycles.Whenthishappens,theLRFbitintheCTRLregisterwillbesetto1.Afterpowerontheregisterwillhavethevalueof01010101B.

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Note:tRSTDispower-ondelay,typicaltime=16.7msLow Voltage Reset Timing Chart

• LVRC Register Bit 7 6 5 4 3 2 1 0

Na�e LVS7 LVS� LVS5 LVS4 LVS3 LVS� LVS1 LVS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 LVS7 ~ LVS0:LVRVoltageSelectcontrol01010101:3.15V00110011:3.15V10011001:3.15V10101010:3.15VOthervalues:MCUreset–(resetwillbeactiveafter2~3LIRCclockfordebouncetime)

Note:S/Wcanwrite00H~FFHtocontrolLVRvoltage,eventoS/WresetMCU.IftheMCUresetcausedLVRCsoftwarereset,theLRFflagofCTRLregisterwillbeset.

• CTRL RegisterBit 7 6 5 4 3 2 1 0


Bit7 FSYSON:fSYSControlIDLEModeDescribeelsewhere

Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag


Thisbitissetto1whenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit1 LRF:LVRControlregistersoftwareresetflag0:Notoccur1:Occurred

Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit0 WRF:WDTControlregistersoftwareresetflagDescribeelsewhere

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Watchdog Time-out Reset during Normal OperationtheWatchdogtime-outflagTOwillbeset to"1"whenWatchdogtime-outResetduringnormaloperation.

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Note:tRSTDispower-ondelay,typicaltime=16.7ms

WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto"0"andtheTOflagwillbesetto"1".RefertotheA.C.CharacteristicsfortSSTdetails.

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Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbytheHIRC.ThetSSTis1~2clockfortheLIRC.

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Powe�-on �esetu u LVR �eset du�ing NORMAL o� SLOW Mode ope�ation1 u WDT ti�e-out �eset du�ing NORMAL o� SLOW Mode ope�ation1 1 WDT ti�e-out �eset du�ing IDLE o� SLEEP Mode ope�ation

Note:"u"standsforunchanged

Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETP�og�a� Counte� Reset to ze�oInte��upts All inte��upts will �e disa�ledWDT Clea� afte� �eset� WDT �egins �ountingTi�e� Modules Ti�e� Modules will �e tu�ned offInput/Output Po�ts I/O po�ts will �e setup as inputs and AN0~AN5 as A/D input pinsSta�k Pointe� Sta�k Pointe� will point to the top of the sta�k

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Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.

Register Reset(Power On)

WDT Time-out(Normal Operation) LVR Reset WDT Time-out

(SLEEP/IDLE)MP0 x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uMP1 x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uBP - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - uACC x x x x x x x x u u u u u u u u x x x x x x x x u u u u u u u uPCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x u u u u u u u u x x x x x x x x u u u u u u u uTBLH x x x x x x x x u u u u u u u u x x x x x x x x u u u u u u u uTBHP - - - - - x x x - - - - - u u u - - - - - x x x - - - - - u u uSTATUS - - 0 0 x x x x - - 1 u u u u u - - u u x x x x - - 1 1 u u u uSMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 u u u u u u u uLVDC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u – u u uLVRC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 u u u u u u u uWDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u uTBC 0 0 1 1 - - - - 0 0 1 1 - - - - 0 0 1 1 - - - - u u u u - - - -INTC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uINTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uINTC� - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - u u u - u u uMFI0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI4 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uPAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPBPU - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uPB - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uPBC - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uPCPU - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uPC - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPCC - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uINTEG - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uIICC0 - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u u -IICC1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 u u u u u u u uIICD x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uIICA x x x x x x x - x x x x x x x - x x x x x x x - u u u u u u u -I�CTOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uNF_VIH 0 0 - 1 1 0 0 1 0 0 - 1 1 0 0 1 0 0 - 1 1 0 0 1 u - - u u u u uNF_VIL 0 0 - 0 1 0 1 0 0 0 - 0 1 0 1 0 0 0 - 0 1 0 1 0 0 0 - u u u u uHCHK_NUM - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u uHNF_MSEL - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uCAPTC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

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(SLEEP/IDLE)CAPTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMDH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMAH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMCL x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uCAPTMCH x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uOPOMS 0 0 - - - 0 1 0 0 0 - - - 0 1 0 0 0 - - - 0 1 0 u u - - - u u uOPCM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCPC 1111 0 0 0 0 1111 0 0 0 0 1111 0 0 0 0 u u u u u u u uCTRL 0 - - - - x 0 0 0 - - - - x 0 0 0 - - - - x 0 0 u - - - - u u uEEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uEEA - - - x x x x x - - - x x x x x - - - x x x x x - - - u u u u uEED x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uADRL x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uADRH - - - - - - x x - - - - - - x x - - - - - - x x - - - - - - u uADCR0 0 11 - 0 0 0 0 0 11 - 0 0 0 0 0 11 - 0 0 0 0 u u u - u u u uADCR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uADCR� - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uADDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uADLVDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uADLVDH x x x x x x 0 0 x x x x x x 0 0 x x x x x x 0 0 u u u u u u u uADHVDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uADHVDH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPWMC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uDUTR0L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uDUTR0H - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uDUTR1L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uDUTR1H - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uDUTR�L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uDUTR�H - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPRDRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPRDRH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPWMRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPWMRH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uMCF 0 - - - 0 1 0 0 0 - - - 0 1 0 0 0 - - - 0 1 0 0 0 - - - u u u uMCD - - 0 0 0 1 1 1 - - 0 0 0 1 1 1 - - 0 0 0 1 1 1 - - u u u u u uDTS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPLC - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCR 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 u u u u u u u uHDCD - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u uHDCT0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT1 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT� - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT3 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT4 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT5 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u

Rev. 1.10 50 De�e��e� �1� �01� Rev. 1.10 51 De�e��e� �1� �01�




(SLEEP/IDLE)HDCT� - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT7 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT8 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT9 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT10 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT11 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uMPTC1 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u - -MPTC� - - - 1 0 0 1 1 - - - 1 0 0 1 1 - - - 1 0 0 1 1 - - - u u u u uTM1C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -TM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1AH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1RP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uOPACAL - 0 0 1 0 0 0 0 - 0 0 1 0 0 0 0 - 0 0 1 0 0 0 0 - u u u u u u uPWMME - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uPWMMD - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uTM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM�C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM�C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM�DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM�DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM�AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM�AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPAPS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAPS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPBPS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPCPS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPCPS1 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uPRM - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

Note:"-"notimplement

"u"standsfor"unchanged"

"x"standsfor"unknown"

Rev. 1.10 50 De�e��e� �1� �01� Rev. 1.10 51 De�e��e� �1� �01�


Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectionalinput/outputlineslabeledwithportnamesPA,PBandPC.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.AlloftheseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction"MOVA,[m]",wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

I/O Register List

RegisterName

Bit7 6 5 4 3 2 1 0

PA D7 D� D5 D4 D3 D� D1 D0PAC D7 D� D5 D4 D3 D� D1 D0

PAPU D7 D� D5 D4 D3 D� D1 D0PAWU D7 D� D5 D4 D3 D� D1 D0

PB — — — — D3 D� D1 D0PBC — — — — D3 D� D1 D0

PBPU — — — — D3 D� D1 D0PC — — D5 D4 D3 D� D1 D0

PCC — — D5 D4 D3 D� D1 D0PCPU — — D5 D4 D3 D� D1 D0

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternalresistor.Toeliminate theneedfor theseexternalresistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU~PCPU,andare implementedusingweakPMOStransistors.

PAPU RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 I/OPortAbit7~bit0Pull-HighControl0:Disable1:Enable

Rev. 1.10 5� De�e��e� �1� �01� Rev. 1.10 53 De�e��e� �1� �01�


PBPU RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — D3 D� D1 D0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~0 I/OPortBbit3~bit0Pull-HighControl

0:Disable1:Enable

PCPU RegisterBit 7 6 5 4 3 2 1 0

Na�e — — D5 D4 D3 D� D1 D0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5~0 I/OPortCbit5~bit0Pull-HighControl

0:Disable1:Enable

Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

PAWU RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 I/OPortAbit7~bit0WakeUpControl0:Disable1:Enable

Rev. 1.10 5� De�e��e� �1� �01� Rev. 1.10 53 De�e��e� �1� �01�


I/O Port Control RegistersEach I/Oporthas itsowncontrol registerknownasPAC~PCC, to control the input/outputconfiguration.With this control register, eachCMOSoutput or input canbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa"1".Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa"0",theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

PAC RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 I/OPortAbit7~bit0Input/OutputControl0:Output1:Input

PBC RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — D3 D� D1 D0R/W — — — — R/W R/W R/W R/WPOR — — — — 1 1 1 1

Bit7~4 Unimplemented,readas"0"Bit3~0 I/OPortBbit3~bit0Input/OutputControl

0:Output1:Input

PCC RegisterBit 7 6 5 4 3 2 1 0

Na�e — — D5 D4 D3 D� D1 D0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 1 1 1 1 1 1

Bit7~6 Unimplemented,readas"0"Bit5~0 I/OPortCbit5~bit0Input/OutputControl

0:Output1:Input

Rev. 1.10 54 De�e��e� �1� �01� Rev. 1.10 55 De�e��e� �1� �01�


Pin-sharing Functions

PAPS0 RegisterBit 7 6 5 4 3 2 1 0

Na�e PA3S1 PA3S0 PA�S1 PA�S0 PA1S1 PA1S0 PA0S1 PA0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PA3S1~PA3S0:PA3PinShareSetting00:PA3/TCK2/H101:C1P10:PA3/TCK2/H111:PA3/TCK2/H1

Bit5~4 PA2S1~PA2S0:PA2PinShareSetting00:PA201:SCL10:PA211:PA2

Bit3~2 PA1S1~PA1S0:PA1PinShareSetting00:PA1/TCK301:AN2/AP10:PA1/TCK311:PA1/TCK3

Bit1~0 PA0S1~PA0S0:PA0PinShareSetting00:PA001:SDA10:PA011:PA0

PAPS1 RegisterBit 7 6 5 4 3 2 1 0

Na�e PA7S1 PA7S0 PA�S1 PA�S0 PA5S1 PA5S0 PA4S1 PA4S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PA7S1~PA7S0:PA7PinShareSetting00:PA7/NFIN01:AN110:PA7/NFIN11:PA7/NFIN

Bit5~4 PA6S1~PA6S0:PA6PinShareSetting00:PA601:[C1N]ifpin-remapenabled10:AN011:PA6

Bit3~2 PA5S1~PA5S0:PA5PinShareSetting00:PA5/H301:[SCL]ifpin-remapenabled10:C3P11:PA5/H3

Bit1~0 PA4S1~PA4S0:PA4PinShareSetting00:PA4/H201:[SDA]ifpin-remapenabled10:C2P11:[C1N]ifpin-remapenabled

Rev. 1.10 54 De�e��e� �1� �01� Rev. 1.10 55 De�e��e� �1� �01�


PBPS0 RegisterBit 7 6 5 4 3 2 1 0

Na�e PB3S1 PB3S0 PB�S1 PB�S0 PB1S1 PB1S0 PB0S1 PB0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PB3S1~PB3S0:PB3PinShareSetting00:PB3/TCK101:C1Nifpin-remapdisabled10:PB3/TCK111:PB3/TCK1

Bit5~4 PB2S1~PB2S0:PB2PinShareSetting00:PB201:HCO10:AN511:PB2

Bit3~2 PB1S1~PB1S0:PB1PinShareSetting00:PB1/CTIN01:HBO10:AN411:PB1/CTIN

Bit1~0 PB0S1~PB0S0:PB0PinShareSetting00:PB001:HAO10:AN311:PB0

PCPS0 RegisterBit 7 6 5 4 3 2 1 0

Na�e PC3S1 PC3S0 PC�S1 PC�S0 PC1S1 PC1S0 PC0S1 PC0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PC3S1~PC3S0:PC3PinShareSetting00:PC301:TP1_110:GBB11:PC3

Bit5~4 PC2S1~PC2S0:PC2PinShareSetting00:PC201:TP1_010:GBT11:PC2

Bit3~2 PC1S1~PC1S0:PC1PinShareSetting00:PC101:TP0_110:GAB11:PC1

Bit1~0 PC0S1~PC0S0:PC0PinShareSetting00:PC001:TP0_010:GAT11:PC0

Rev. 1.10 5� De�e��e� �1� �01� Rev. 1.10 57 De�e��e� �1� �01�


PCPS1 RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — PC5S1 PC5S0 PC4S1 PC4S0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~2 PC5S1~PC5S0:PC5PinShareSetting

00:PC501:TP2_110:GCB11:PC5

Bit1~0 PC4S1~PC4S0:PC4PinShareSetting00:PC401:TP2_010:GCT11:PC4

Pin-remapping FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.

Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Thewayinwhichthepinfunctionofeachpinisselectedisdifferentforeachfunctionandapriorityorderisestablishedwheremorethanonepinfunctionisselectedsimultaneously.AdditionallythereareaseriesofPRMregistertoestablishcertainpinfunctions.

Pin-remapping RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.SomedevicesincludePRMregisterwhichcanselectthefunctionsofcertainpins.

PRM RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — C1NPS1 C1NPS0 SDAPS SCLPSR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~2 C1NPS1~C1NPS0:

00:C1NonPB301:C1NonPA610:C1NonPA411:C1NReserved

Bit1 SDAPS:0:SDAonPA01:SDAonPA4

Bit0 SCLPS:0:SCLonPA21:SCLonPA5

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I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

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Generic Input/Output Structure

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A/D Input/Output Structure

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Programming ConsiderationsWithintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregisters,PAC~PCC,arethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregisters,PA~PC,arefirstprogrammed.Selectingwhichpinsare inputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvaluesintotheappropriateportcontrolregisterorbyprogrammingindividualbits intheportcontrolregisterusingthe"SET[m].i"and"CLR[m].i"instructions.Notethatwhenusingthesebitcontrol instructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhastheadditionalcapabilityofprovidingwake-upfunctions.WhenthedeviceisintheSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevice includesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualCompactandStandardTMsection.

IntroductionThedevicecontainsthreeTMs,a10-bitCompactTM,a16-bitCompactTManda10-bitStandardTM,eachTMhavingareferencenameofTM0,TM1andTM2.Althoughsimilar innature, thedifferentTMtypesvary in their featurecomplexity.Thecommonfeatures to theCompactandStandardTMswillbedescribed in thissectionand thedetailedoperationwillbedescribed incorrespondingsections.Themain featuresanddifferencesbetween the two typesofTMsaresummarisedintheaccompanyingtable.

Function CTM STMTi�e�/Counte� √ √I/P Captu�e — √Co�pa�e Mat�h Output √ √PWM Channels 1 1Single Pulse Output — √PWM Align�ent Edge EdgePWM Adjust�ent Pe�iod & Duty Duty o� Pe�iod Duty o� Pe�iod

TM Function SummaryTM0 TM1 TM2

10-�it CTM 1�-�it CTM 10-�it STM

TM Name/Type Reference

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TM OperationThetwodifferenttypesofTMsofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrives themaincounter ineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingtheTnCK2~TnCK0bitsintheTMcontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH,thefTBCclocksourceortheexternalTCKnpin.TheTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsThetwodifferenttypesofTMshavetwointernalinterrupts,theinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerated,itcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

TM External PinsEachoftheTMs,irrespectiveofwhattype,hasoneTMinputpin,withthelabelTCKn.TheTMinputpin,isessentiallyaclocksourcefortheTMandisselectedusingtheTnCK2~TnCK0bitsintheTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingtheTnCK2~TnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.

TheTMseachhavetwooutputpins.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalTPnoutputpin isalso thepinwhere theTMgenerates thePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunction,theTMoutputfunctionmustfirstbesetupusingregisters.AsinglebitinoneoftheregistersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeisdifferent,thedetailsareprovidedintheaccompanyingtable.

AllTMoutputpinnameshavean"_n"suffix.Pinnamesthatincludea"_0"or"_1"suffixindicatethattheyarefromaTMwithmultipleoutputpins.ThisallowstheTMtogenerateacomplimentaryoutputpair,selectedusingtheI/Oregisterdatabits.

TM0 TM1 TM2TP0_0� TP0_1 TP1_0� TP1_1 TP�_0� TP�_1

TM Output Pins

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Programming ConsiderationsTheTMCounterRegisters,theCapture/CompareCCRAregister,beingeither16-bitor10-bit,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

AstheCCRAregister is implementedinthewayshowninthefollowingdiagramandaccessingtheseregisterpairsiscarriedoutinaspecificwaydescribedabove,it isrecommendedtousethe"MOV"instructiontoaccess theCCRAlowbyteregisters,namedTMxAL,usingthefollowingaccessprocedures.AccessingtheCCRAlowbyteregisterwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

Data Bus

8-�it Buffe�

TMxDHTMxDL

TMxAHTMxAL

TM Counte� Registe� (Read only)

TM CCRA Registe� (Read/W�ite)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRA♦ Step1.WritedatatoLowByteTMxAL–notethatheredataisonlywrittentothe8-bitbuffer.

♦ Step2.WritedatatoHighByteTMxAH–heredataiswrittendirectlytothehighbyteregistersandsimultaneouslydataislatchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRA♦ Step1.ReaddatafromtheHighByteTMxDHorTMxAH–heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydatais latchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowByteTMxDLorTMxAL–thisstepreadsdatafromthe8-bitbuffer.

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Compact Type TM – CTMAlthoughthesimplestformoftheTMtypes, theCompactTMtypestillcontainsthreeoperatingmodes,whichareCompareMatchOutput,Timer/EventCounterandPWMOutputmodes.TheCompactTMcanalsobecontrolledwithanexternalinputpinandcandrivetwoexternaloutputpins.Thesetwoexternaloutputpinscanbethesamesignalortheinversesignal.

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Compact Type TM Block Diagram (n=0, 1)

Compact TM OperationAtitscoreisa10-bitor16-bitcount-upcounterwhichisdrivenbyauserselectable internalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.Thesecomparatorswillcompare thevalue in thecounterwithCCRPandCCRAregisters.TheCCRPisthreebitswidewhosevalueiscomparedwiththehighestthreebitsoreightbits inthecounterwhiletheCCRAisthetenbitsorsixteenbitsandthereforecompareswithallcounterbits.

Theonlywayofchangingthevalueofthe10-bitor16-bitcounterusingtheapplicationprogram,istoclearthecounterbychangingtheTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheCompactTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

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Compact Type TM Register DescriptionOveralloperationoftheCompactTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitor16-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitor16-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeoreightCCRPbits.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TM0C0 T0PAU T0CK� T0CK1 T0CK0 T0ON T0RP� T0RP1 T0RP0TM0C1 T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLRTM0DL D7 D� D5 D4 D3 D� D1 D0TM0DH — — — — — — D9 D8TM0AL D7 D� D5 D4 D3 D� D1 D0TM0AH — — — — — — D9 D8

10-bit Compact TM Register ListName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TM1C0 T1PAU T1CK� T1CK1 T1CK0 T1ON — — —TM1C1 T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLRTM1DL D7 D� D5 D4 D3 D� D1 D0TM1DH D15 D14 D13 D1� D11 D10 D9 D8TM1AL D7 D� D5 D4 D3 D� D1 D0TM1AH D15 D14 D13 D1� D11 D10 D9 D8TM1RP D7 D� D5 D4 D3 D� D1 D0

16-bit Compact TM Register List

TM0DL Register – 10-bit CTMBit 7 6 5 4 3 2 1 0

Na�e D7 D� D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TM0DL:TM0CounterLowByteRegisterbit7~bit0TM010-bitCounterbit7~bit0

TM0DH Register – 10-bit CTMBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM0DH:TM0CounterHighByteRegisterbit1~bit0

TM010-bitCounterbit9~bit8

TM0AL Register(n=0) – 10-bit CTMBit 7 6 5 4 3 2 1 0


Bit7~0 TM0AL:TM0CCRALowByteRegisterbit7~bit0TM010-bitCCRAbit7~bit0

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TM0AH Register – 10-bit CTMBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM0AH:TM0CCRAHighByteRegisterbit1~bit0

TM010-bitCCRAbit9~bit8

TM1DL Register – 16-bit CTMBit 7 6 5 4 3 2 1 0



TM1DH Register – 16-bit CTMBit 7 6 5 4 3 2 1 0


Bit7~0 TM1DH:TM1CounterHighByteRegisterbit7~bit0TM116-bitCounterbit15~bit8

TM1AL Register – 16-bit CTMBit 7 6 5 4 3 2 1 0



TM1AH Register – 16-bit CTMBit 7 6 5 4 3 2 1 0


Bit7~0 TM1AH:TM1CCRAHighByteRegisterbit7~bit0TM116-bitCCRAbit15~bit8

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TM0C0 Register – 10-bit CTMBit 7 6 5 4 3 2 1 0

Na�e T0PAU T0CK� T0CK1 T0CK0 T0ON T0RP� T0RP1 T0RP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 T0PAU:TM0CounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 T0CK2~T0CK0:SelectTM0Counterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:Reserved110:TCK0risingedgeclock111:TCK0fallingedgeclock

These threebits areused to select theclock source for theTM0.Selecting theReservedclockinputwilleffectivelydisable the internalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 T0ON:TM0CounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM0.Settingthebithighenablesthecounter torun,clearingthebitdisables theTM0.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theTM0whichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwill retain its residualvalue. If theTM0is in theCompareMatchOutputModethentheTM0outputpinwillberesettoitsinitialcondition,asspecifiedbytheT0OCbit,whentheT0ONbitchangesfromlowtohigh.

Bit2~0 T0RP2~T0RP0: TM0CCRP3-bitregister,comparedwiththeTM0Counterbit9~bit7ComparatorPMatchPeriod000:1024TM0clocks001:128TM0clocks010:256TM0clocks011:384TM0clocks100:512TM0clocks101:640TM0clocks110:768TM0clocks111:896TM0clocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT0CCLRbit isset tozero.SettingtheT0CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

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Na�e T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T0M1~T0M0: SelectTM0OperatingMode00:CompareMatchOutputMode01:Undefined10:PWMMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheT0M1andT0M0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T0IO1~T0IO0:SelectTP0_0,TP0_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Undefined

Timer/counterModeunused

ThesetwobitsareusedtodeterminehowtheTM0outputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTM0isrunning.IntheCompareMatchOutputMode,theT0IO1andT0IO0bitsdeterminehowtheTM0outputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTM0outputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTM0outputpinshouldbesetupusingtheT0OCbit intheTM0C1register.NotethattheoutputlevelrequestedbytheT0IO1andT0IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheT0OCbitotherwisenochangewilloccurontheTM0outputpinwhenacomparematchoccurs.AftertheTM0outputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT0ONbitfromlowtohigh.In thePWMMode, theT0IO1andT0IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevaluesof theT0IO1andT0IO0bitsonlyafter theTM0hasbeen switchedoff.UnpredictablePWMoutputswilloccuriftheT0IO1andT0IO0bitsarechangedwhentheTMisrunning.

Rev. 1.10 �� De�e��e� �1� �01� Rev. 1.10 �7 De�e��e� �1� �01�


Bit3 T0OC: TP0_0,TP0_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTM0outputpin. ItsoperationdependsuponwhetherTM0isbeingusedintheCompareMatchOutputModeorinthePWMMode.Ithasnoeffect if theTM0is in theTimer/CounterMode. In theCompareMatchOutputModeitdetermines the logic levelofheTM0outputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesif thePWMsignal isactivehighoractivelow.

Bit2 T0POL:TP0_0,TP0_1OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP0_0orTP0_1outputpin.Whenthebit issethightheTM0outputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTM0isintheTimer/CounterMode.

Bit1 T0DPX: TM0PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 T0CCLR:SelectTM0Counterclearcondition0:TM0ComparatorPmatch1:TM0ComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theCompactTM0containstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theT0CCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheT0CCLRbitisnotusedinthePWMMode.

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Na�e T1PAU T1CK� T1CK1 T1CK0 T1ON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —




010:fH/16011:fH/64100:fTBC101:Reserved110:TCK1risingedgeclock111:TCK1fallingedgeclock

These threebits areused to select theclock source for theTM1.Selecting theReservedclockinputwilleffectivelydisable the internalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.


Thisbitcontrolstheoverallon/offfunctionoftheTM1.Settingthebithighenablesthecounter torun,clearingthebitdisables theTM1.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theTM1whichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwill retain its residualvalue. If theTM1is in theCompareMatchOutputModethentheTM1outputpinwillberesettoitsinitialcondition,asspecifiedbytheT1OCbit,whentheT1ONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas"0"

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Na�e T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T1M1~T1M0:SelectTM1OperatingMode00:CompareMatchOutputMode01:Undefined10:PWMMode11:Timer/CounterMode



PWMMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Undefined


ThesetwobitsareusedtodeterminehowtheTM1outputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTM1isrunning.IntheCompareMatchOutputMode,theT1IO1andT1IO0bitsdeterminehowtheTM1outputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTM1outputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTM1outputpinshouldbesetupusingtheT1OCbit intheTM1C1register.NotethattheoutputlevelrequestedbytheT1IO1andT1IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheT1OCbitotherwisenochangewilloccurontheTM1outputpinwhenacomparematchoccurs.AftertheTM1outputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT1ONbitfromlowtohigh.In thePWMMode, theT1IO1andT1IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevaluesof theT1IO1andT1IO0bitsonlyafter theTM1hasbeen switchedoff.UnpredictablePWMoutputswilloccuriftheT1IO1andT1IO0bitsarechangedwhentheTMisrunning.

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Bit3 T1OC:TP1_0,TP1_1OutputcontrolbitCompareMatchoutputMode0:Initiallow1:Initialhigh

PWMMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTM1outputpin. ItsoperationdependsuponwhetherTM1isbeingusedintheCompareMatchOutputModeorinthePWMMode.Ithasnoeffect if theTM1is in theTimer/CounterMode. In theCompareMatchOutputModeitdetermines the logic levelofheTM1outputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesif thePWMsignal isactivehighoractivelow.

Bit2 T1POL:TP1_0,TP1_1outputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP1_0orTP1_1outputpin.Whenthebit issethightheTM1outputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMnisintheTimer/CounterMode.

Bit1 T1DPX:TM1PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period




TM1RP Register – 16-bit CTMBit 7 6 5 4 3 2 1 0


Bit7~0 TM1RP:TM1CCRPRegisterbit7~bit00:65536TM1clocks1~255:256×(1~255)TM1clocks

TM1CCRP8-bitregister,comparedwiththeTM1Counterbit15~bit8ComparatorPMatchPeriodThesethreebitsareusedtosetupthevalueontheinternalCCRP8-bitregister,whichare thencomparedwith the internalcounter’shighesteightbits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT1CCLRbit isset tozero.SettingtheT1CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighesteightcounterbits, thecomparevaluesexist in256clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.10 70 De�e��e� �1� �01� Rev. 1.10 71 De�e��e� �1� �01�


Compact Type TM Operating ModesTheCompactTypeTMcanoperateinoneofthreeoperatingmodes,CompareMatchOutputMode,PWMModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.

Compare Match Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1register,shouldbesetto"00"respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothTnAFandTnPFinterruptrequestflagsfortheComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,or16-bit,FFFFHex,value,howeverheretheTnAFinterruptrequestflagwillnotbegenerated.

As thenameof themodesuggests,afteracomparison ismade, theTMoutputpinwillchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaTnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1andTnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.10 70 De�e��e� �1� �01� Rev. 1.10 71 De�e��e� �1� �01�


Counte� Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin

Ti�e

CCRP=0

CCRP > 0

Counte� ove�flowCCRP > 0Counte� �lea�ed �y CCRP value

Pause

Resu�e

Stop

Counte� Resta�t

TnCCLR = 0; TnM [1:0] = 00

Output pin set to initial Level Low if TnOC=0

Output Toggle with TnAF flag

Note TnIO [1:0] = 10 A�tive High Output sele�tHe�e TnIO [1:0] = 11

Toggle Output sele�t

Output not affe�ted �y TnAF flag. Re�ains High until �eset �y TnON �it

Output PinReset to Initial value

Output �ont�olled �y othe� pin-sha�ed fun�tion

Output Inve�tswhen TnPOL is high

0x3FFo� 0xFFFF

Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter

2.TheTMoutputpiniscontrolledonlybytheTnAFflag

3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge

4.n=0,1

Rev. 1.10 7� De�e��e� �1� �01� Rev. 1.10 73 De�e��e� �1� �01�


CCRP

CCRA

0x3FF o� 0xFFFF

CCRA = 0Counte� ove�flows

CCRP Int.Flag TnPF

CCRA Int.Flag TnAF

CCRA > 0 Counte� �lea�ed �y CCRA value

TM O/P Pin

TnON �it

Pause Counte�Reset

Output PinReset to initial value

Output Pin set to Initial LevelLow if TnOC = 0

Output Togglewith TnAF flag

He�e TnIO1� TnIO0 = 11Toggle Output Sele�t

Now TnIO1� TnIO0 = 10 A�tive High Output Sele�t

TnPAU �it

Resu�eStop

Ti�e

TnPF notgene�ated

No TnAF flaggene�ated on CCRA ove�flow

Output doesnot �hange

CCRA = 0

Output inve�tswhen TnPOL is high

TnPOL �it

TnCCLR = 1; TnM[1� 0] = 00

Output �ont�olled �yothe� pin-sha�ed fun�tion

Output not affe�ted �yTnAF flag �e�ains Highuntil �eset �y TnON �it

Counte� Value


Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter

2.TheTMoutputpiniscontrolledonlybytheTnAFflag

3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge

4.TheTnPFflagisnotgeneratedwhenTnCCLR=1

5.n=0,1

Rev. 1.10 7� De�e��e� �1� �01� Rev. 1.10 73 De�e��e� �1� �01�


Timer/Counter ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMmode, theTnCCLRbithasnoeffectonthePWMoperation.Bothof theCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycle isdeterminedusing theTnDPXbit in theTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

10-bit CTM, PWM Mode, Edge-aligned Mode, T0DPX=0CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 1�8 �5� 384 51� �40 7�8 89� 10�4Duty CCRA

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,

TheCTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

10-bit CTM, PWM Mode, Edge-aligned Mode, T0DPX=1CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod CCRADuty 1�8 �5� 384 51� �40 7�8 89� 10�4

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

Rev. 1.10 74 De�e��e� �1� �01� Rev. 1.10 75 De�e��e� �1� �01�


16-bit CTM, PWM Mode, Edge-aligned Mode, T1DPX=0CCRP 1~255 0Pe�iod CCRP×�5� �553�Duty CCRA

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=2andCCRA=128,TheCTMPWMoutput frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125 kHz, duty=128/(2×256)=25%.IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

16-bit CTM, PWM Mode, Edge-aligned Mode, T1DPX=1CCRP 1~255 0Pe�iod CCRADuty CCRP×�5� �553�

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbythe(CCRP×256)exceptwhentheCCRPvalueisequalto0.

Counte� Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e

Counte� �lea�ed �y CCRP

Pause Resu�e Counte� Stop if TnON �it low

Counte� Reset when TnON �etu�ns high

TnDPX = 0; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRA

PWM �esu�es ope�ation

Output �ont�olled �y othe� pin-sha�ed fun�tion Output Inve�ts

when TnPOL = 1PWM Pe�iod set �y CCRP

TM O/P Pin(TnOC=0)

PWM Mode – TnDPX=0Note:1.HereTnDPX=0–CounterclearedbyCCRP

2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0,1

Rev. 1.10 74 De�e��e� �1� �01� Rev. 1.10 75 De�e��e� �1� �01�


Counte� Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e

Counte� �lea�ed �y CCRA



TnDPX = 1; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRP



when TnPOL = 1PWM Pe�iod set �y CCRA

TM O/P Pin(TnOC=0)

PWM Mode – TnDPX=1Note:1.HereTnDPX=1–CounterclearedbyCCRA

2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0,1

Buzzer Control

Buzze�

HT��FM5�30

10-Bit CTMTM0

The10-bitCTMcandriveanexternalbuzzerusingitsPWMmodetoprovidevolumecontrol.

Rev. 1.10 7� De�e��e� �1� �01� Rev. 1.10 77 De�e��e� �1� �01�


Standard Type TM – STMTheStandardTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanalsobecontrolledwithanexternalinputpinandcandrivetwoexternaloutputpins.

Name TM No. TM Input Pin TM Output Pin

10-�it STM � TCK� TP�_0� TP�_1

� � � �

� � � �

� � � � � �

� � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � �

� � � � � � � � � �

� � � � � � �

� � � � � �

� � � � � � � � � � � � � � � � � �

� � � � � � � � � � � ��

� � � � � � � � � � � � ��

� � � � � � � � � � � � � �

� � � � � � � � � � � � � �

� � � � � � ��

� � � � � �

� ��

� � � � � � � � � �

� � � � � � � � � ��

� � � �

� � �

� � � � � � � ��

� � � � ��

� � � � �

� � � � �

� � � � � � �

� � ��

� � � � � ��

��

��

� � � � � � � � � � � � � ��

Standard Type TM Block Diagram (n=2)

The10-bitSTMcancapture theNoiseFliterDat_Outsignal timebetweentheraisingedgeandfallingedge.

10 �it STM (TM�)

CINS

0O�iginal TP� Captu�e in(Ex. TP�_0 o� TP�_1)

Captu�e in 1Noise Filte� Dat_Out

TM2 in Capture Mode Signal Select

Standard TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealso twointernalcomparatorswith thenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPis3-bitswidewhosevalueiscomparedwiththehighest3bitsinthecounterwhiletheCCRAisthe10bitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theT2ONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.10 7� De�e��e� �1� �01� Rev. 1.10 77 De�e��e� �1� �01�


Standard Type TM Register DescriptionOveralloperationoftheStandardTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TM�C0 T�PAU T�CK� T�CK1 T�CK0 T�ON T�RP� T�PR1 T�PR0TM�C1 T�M1 T�M0 T�IO1 T�IO0 T�OC T�POL T�DPX T�CCLRTM�DL D7 D� D5 D4 D3 D� D1 D0TM�DH — — — — — — D9 D8TM�AL D7 D� D5 D4 D3 D� D1 D0TM�AH — — — — — — D9 D8

10-bit Standard TM Register List

TM2C0 Register – 10-bit STMBit 7 6 5 4 3 2 1 0

Na�e T�PAU T�CK� T�CK1 T�CK0 T�ON T�RP� T�PR1 T�PR0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0




010:fH/16011:fH/64100:fTBC101:fTBC110:TCK2risingedgeclock111:TCK2fallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM2.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.


Thisbitcontrolstheoverallon/offfunctionoftheTM2.Settingthebithighenablesthecounter torun,clearingthebitdisables theTM2.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theTM2whichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTM2isintheCompareMatchOutputModethentheTM2outputpinwillberesettoitsinitialcondition,asspecifiedbytheT2OCbit,whentheT2ONbitchangesfromlowtohigh.

Rev. 1.10 78 De�e��e� �1� �01� Rev. 1.10 79 De�e��e� �1� �01�


Bit2~0 T2RP2~T2RP0: TM2CCRP3-bitregister,comparedwiththeTM2Counterbit9~bit7ComparatorPMatchPeriod000:1024TM2clocks001:128TM2clocks010:256TM2clocks011:384TM2clocks100:512TM2clocks101:640TM2clocks110:768TM2clocks111:896TM2clocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT2CCLRbit isset tozero.SettingtheT2CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue

TM2C1 Register – 10-bit STMBit 7 6 5 4 3 2 1 0

Na�e T�M1 T�M0 T�IO1 T�IO0 T�OC T�POL T�DPX T�CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T2M1~T2M0: SelectTM2OperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode



PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTP2_0,TP2_101:InputcaptureatfallingedgeofTP2_0,TP2_110:Inputcaptureatfalling/risingedgeofTP2_0,TP2_111:Inputcapturedisabled


ThesetwobitsareusedtodeterminehowtheTM2outputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTM2isrunning.

Rev. 1.10 78 De�e��e� �1� �01� Rev. 1.10 79 De�e��e� �1� �01�


IntheCompareMatchOutputMode,theT2IO1andT2IO0bitsdeterminehowtheTM2outputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTM2outputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTM2outputpinshouldbesetupusingtheT2OCbit intheTM2C1register.NotethattheoutputlevelrequestedbytheT2IO1andT2IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheT2OCbitotherwisenochangewilloccurontheTM2outputpinwhenacomparematchoccurs.AftertheTM2outputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT2ONbitfromlowtohigh.In thePWMMode, theT2IO1andT2IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevaluesof theT2IO1andT2IO0bitsonlyafter theTM2hasbeen switchedoff.UnpredictablePWMoutputswilloccuriftheT2IO1andT2IO0bitsarechangedwhentheTMisrunning.

Bit3 T2OC: TP2_0,TP2_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode//SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTM2outputpin. ItsoperationdependsuponwhetherTM2isbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTM2isintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelofheTM2outputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 T2POL:TP2_0,TP2_1OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP2_0orTP2_1outputpin.Whenthebit issethightheTM2outputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTM2isintheTimer/CounterMode.

Bit1 T2DPX: TM2PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period




Rev. 1.10 80 De�e��e� �1� �01� Rev. 1.10 81 De�e��e� �1� �01�


TM2DL Register – 10-bit STMBit 7 6 5 4 3 2 1 0



TM2DH Register – 10-bit STMBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM2DH:TM2CounterHighByteRegisterbit1~bit0

TM210-bitCounterbit9~bit8

TM2AL Register – 10-bit STMBit 7 6 5 4 3 2 1 0



TM2AH Register – 10-bit STMBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM2AH:TM2CCRAHighByteRegisterbit1~bit0

TM210-bitCCRAbit9~bit8

Rev. 1.10 80 De�e��e� �1� �01� Rev. 1.10 81 De�e��e� �1� �01�


Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheT2M1andT2M0bitsintheTM2C1register.

Compare Output ModeToselectthismode,bitsT2M1andT2M0intheTM2C1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheT2CCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecounter tooverflow.HerebothT2AFandT2PFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheT2CCLRbitintheTM2C1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theT2AFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenT2CCLRishighnoT2PFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto"0".

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaT2AFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheT2PFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theT2IO1andT2IO0bitsintheTM2C1register.TheTMoutputpincanbeselectedusingtheT2IO1andT2IO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theT2ONbitchangesfromlowtohigh,issetupusingtheT2OCbit.NotethatiftheT2IO1andT2IO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.10 8� De�e��e� �1� �01� Rev. 1.10 83 De�e��e� �1� �01�


CCRA

CCRP

0x3FF

Counte� ove�flow

CCRA Int.Flag TnAF

CCRP Int.Flag TnPF

CCRP > 0Counte� �lea�ed �y CCRP value

TM O/P Pin

TnON




He�e TnIO [1:0] = 11Toggle Output Sele�t

Now TnIO [1:0] = 10 A�tive High Output Sele�t

Output not affe�ted �yTnAF flag. Re�ains Highuntil �eset �y TnON �it

TnCCLR = 0; TnM[1:0] = 00

TnPAU

Resu�eStop

Ti�e

CCRP > 0

CCRP = 0

TnAPOL



Output �ont�olled�y othe� pin-sha�ed fun�tion

Counte� Value


Note:1.WithTnCCLR=0aComparatorPmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheTnAFflag

3.TheoutputpinresettoinitialstatebyaTnONbitrisingedge

4.n=2

Rev. 1.10 8� De�e��e� �1� �01� Rev. 1.10 83 De�e��e� �1� �01�


CCRP

CCRA

0x3FF

CCRA = 0Counte� ove�flows

CCRP Int.Flag TnPF

CCRA Int.Flag TnAF

CCRA > 0 Counte� �lea�ed �y CCRA value

TM O/P Pin

TnON





He�e TnIO [1:0] = 11Toggle Output Sele�t

Now TnIO [1:0] = 10 A�tive High Output Sele�t

TnPAU

Resu�eStop

Ti�e

TnPF notgene�ated

No TnAF flaggene�ated on CCRA ove�flow

Output doesnot �hange

CCRA = 0


TnPOL

TnCCLR = 1; TnM [1:0] = 00

Output �ont�olled �yothe� pin-sha�ed fun�tion

Output not affe�ted �yTnAF flag �e�ains Highuntil �eset �y TnON �it

Counte� Value


Note:1.WithTnCCLR=1aComparatorAmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheTnAFflag

3.TheoutputpinresettoinitialstatebyaTnONrisingedge

4.TheTnPFflagsisnotgeneratedwhenTnCCLR=1

5.n=2

Rev. 1.10 84 De�e��e� �1� �01� Rev. 1.10 85 De�e��e� �1� �01�


Timer/Counter ModeToselectthismode,bitsT2M1andT2M0intheTM2C1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsT2M1andT2M0intheTM2C1registershouldbesetto10respectivelyandalso theT2IO1andT2IO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible. In thePWMmode, theT2CCLRbithasnoeffectas thePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.WhichregisterisusedtocontroleitherfrequencyordutycycleisdeterminedusingtheT2DPXbitintheTM2C1register.

ThePWMwaveformfrequencyanddutycyclecan thereforebecontrolledby thevalues in theCCRAandCCRPregisters.An interrupt flag,one foreachof theCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheT2OCbitIntheTM2C1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoT2IO1andT2IO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheT2POLbitisusedtoreversethepolarityofthePWMoutputwaveform.

10-bit STM, PWM Mode, Edge-aligned Mode, T2DPX=0CCRP 001 010 011 100 101 110 111 000Pe�iod 1�8 �5� 384 51� �40 7�8 89� 10�4Duty CCRA

IffSYS=4MHz,TMclocksourceisfSYS,CCRP=2andCCRA=128,

TheSTMPWMoutputfrequency=fSYS/(2×256)=fSYS/512=7.8125kHz,duty=128/(2×256)=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

10-bit STM, PWM Mode, Edge-aligned Mode, T2DPX=1CCRP 001 010 011 100 101 110 111 000Pe�iod CCRADuty 1�8 �5� 384 51� �40 7�8 89� 10�4

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

Rev. 1.10 84 De�e��e� �1� �01� Rev. 1.10 85 De�e��e� �1� �01�


Counte� Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e




TnDPX = 0; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRA



when TnPOL = 1PWM Pe�iod set �y CCRP

TM O/P Pin(TnOC=0)

PWM Mode – TnDPX=0

Note:1.HereTnDPX=0-CounterclearedbyCCRP

2.AcounterclearsetsPWMPeriod

3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or01

4.TheTnCCLRbithasnoinfluenceonPWMoperation

5.n=2

Rev. 1.10 8� De�e��e� �1� �01� Rev. 1.10 87 De�e��e� �1� �01�


Counte� Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e

Counte� �lea�ed �y CCRA



TnDPX = 1; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRP



when TnPOL = 1PWM Pe�iod set �y CCRA

TM O/P Pin(TnOC=0)

PWM Mode – TnDPX=1

Note:1.HereTnDPX=1-CounterclearedbyCCRA

2.AcounterclearsetsPWMPeriod

3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or01

4.TheTnCCLRbithasnoinfluenceonPWMoperation

5.n=2

Rev. 1.10 8� De�e��e� �1� �01� Rev. 1.10 87 De�e��e� �1� �01�


Single Pulse ModeToselectthismode,bitsT2M1andT2M0intheTM2C1registershouldbesetto10respectivelyandalsotheT2IO1andT2IO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheT2ONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theT2ONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalTCK2pin,whichwillinturninitiatetheSinglePulseoutput.WhentheT2ONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheT2ONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheT2ONbit isclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

� � � � � � � � � � � �

� � � � � � � ��

� � � � � � � ��

� ��

� � � � � � � ��

� � � � � � � ��

� � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � �

� � � � � � � � � � � � � �

Single Pulse Generation (n=2)HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheT2ONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaTMinterrupt.ThecountercanonlyberesetbacktozerowhentheT2ONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheT2CCLRandT2DPXbitsarenotusedinthisMode.

Capture Input ModeToselectthismodebitsT2M1andT2M0intheTM2C1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheTP2_0orTP2_1pin,whoseactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheT2IO1andT2IO0bits in theTM2C1register.Thecounter isstartedwhentheT2ONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.When therequirededge transitionappearson theTP2_0orTP2_1pin thepresentvalue in thecounterwillbelatchedintotheCCRAregistersandaTMinterruptgenerated.IrrespectiveofwhateventsoccurontheTP2_0orTP2_1pinthecounterwillcontinuetofreerununtil theT2ONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;in thiswaytheCCRPvaluecanbeusedtocontrol themaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheT2IO1andT2IO0bitscanselecttheactivetriggeredgeontheTP2_0orTP2_1pintobearisingedge,fallingedgeorbothedgetypes.If theTnIO1andT2IO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheTP2_0orTP2_1pin,howeveritmustbenotedthatthecounterwillcontinuetorun.AstheTP2_0orTP2_1pinispinsharedwithotherfunctions,caremustbetakeniftheTMisintheInputCaptureMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheT2CCLRandT2DPXbitsarenotusedinthisMode.

Rev. 1.10 88 De�e��e� �1� �01� Rev. 1.10 89 De�e��e� �1� �01�


Counte� Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e

Counte� stopped �y CCRA

PauseResu�e Counte� Stops

�y softwa�e


TnM [1:0] = 10 ; TnIO [1:0] = 11

Pulse Width set �y CCRA

Output Inve�tswhen TnPOL = 1

No CCRP Inte��upts gene�ated

TM O/P Pin(TnOC=0)

TCKn pin

Softwa�e T�igge�

Clea�ed �y CCRA �at�h

TCKn pin T�igge�

Auto. set �y TCKn pin

Softwa�e T�igge�

Softwa�e Clea�

Softwa�e T�igge�Softwa�e

T�igge�

Single Pulse ModeNote:1.CounterstoppedbyCCRAmatch

2.CCRPisnotused3.ThepulseistriggeredbytheTCKnpinorsettingtheTnONbithigh4.ATCKnpinactiveedgewillautomaticallysettheTnONbithigh5.IntheSinglePulseMode,TnIO[1:0]mustbesetto"11"andcannotbechanged.6.n=2

Rev. 1.10 88 De�e��e� �1� �01� Rev. 1.10 89 De�e��e� �1� �01�


Counte� Value

YY

CCRP

TnON

TnPAU

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

CCRA Value

Ti�e


PauseResu�e

Counte� Reset

TnM [1:0] = 01

TM �aptu�e pin TPn_x

XX

Counte� Stop

TnIO [1:0] Value

XX YY XX YY

A�tive edge A�tive

edgeA�tive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disa�le Captu�e

Capture Input Mode

Note:1.TnM[1:0]=01andactiveedgesetbytheTnIO[1:0]bits

2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA

3.TheTnCCLRbitisnotused

4.Nooutputfunction-TnOCandTnPOLbitsarenotused

5.CCRPdetermines thecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

6.n=2

Rev. 1.10 90 De�e��e� �1� �01� Rev. 1.10 91 De�e��e� �1� �01�


Capture Timer Module – CAPTMTheCaptureTimerModule isa timingunitspecificallyusedforMotorControlpurposes.TheCAPTMiscontrolledbyaprogramselectableclocksourceandbythreeinterruptsourcesfromthemotorpositioninghallsensors.

Capture Timer OverviewAtthecoreoftheCaptureTimerisa16-bitcount-upcounterwhichisdrivenbyauserselectableinternalclocksourcewhichissomemultipleofthesystemclockorbythePWM.Thereisalsoaninternalcomparatorwhichcompares thevalueof this16-bitcounterwithapre-programmed16-bitvaluestoredin tworegisters.Thereare twobasicmodesofoperation,aCompareModeandaCaptureMode,eachofwhichcanbeusedtoresettheinternalcounter.Whenacomparematchsituationisreachedasignalwillbegeneratedtoresettheinternalcounter.Thecountercanalsobeclearedwhenacapturetriggerisgeneratedbythethreeexternalsources,H1,H2andH3.

Rising/Falling/Dou�le edge

Dete�to�

NoiseFilte�

x3

Rising/Falling/Dou�le edge

Dete�to�

Co�pa�e Registe�CAPTMAH/CAPTMAL

�o�pa�e

CAPTMCH/CAPTMCL

Clea� �aptu�e �ounte�

CLRCapTM_Ove�

CapTM_C�p

H1

H�

H3

CAPS1/CAPS0

1�-�itCAPTM

CLK

CAPTCK[�:0]

PWMOfSYS/�

fSYS/1�8fSYS/�4

Ha_Int H�_Int H�_Int

HaH�H�

Capture Timer Block Diagram

Capture Timer Register Description Overalloperationof theCaptureTimer iscontrolledusingeightregisters.Areadonlyregisterpairexists tostore the internalcounter16-bitvalue,whilea read/write registerpairexists tostore theinternal16-bitcomparevalue.Anadditionalreadonlyregisterpairisusedtostorethecapturevalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0CAPTC0 CAPTPAU CAPTCK� CAPTCK1 CAPTCK0 CAPTON — CAPS1 CAPS0CAPTC1 CAPEG1 CAPEG0 CAPEN CAPNFT CAPNFS CAPFIL CAPCLR CAMCLR

CAPTMDL D7 D� D5 D4 D3 D� D1 D0CAPTMDH D15 D14 D13 D1� D11 D10 D9 D8CAPTMAL D7 D� D5 D4 D3 D� D1 D0CAPTMAH D15 D14 D13 D1� D11 D10 D9 D8CAPTMCL D7 D� D5 D4 D3 D� D1 D0CAPTMCH D15 D14 D13 D1� D11 D10 D9 D8

Capture Timer Register List

Rev. 1.10 90 De�e��e� �1� �01� Rev. 1.10 91 De�e��e� �1� �01�


CAPTC0 RegisterBit 7 6 5 4 3 2 1 0

Na�e CAPTPAU CAPTCK� CAPTCK1 CAPTCK0 CAPTON — CAPS1 CAPS0R/W R/W R/W R/W R/W R/W — R/W R/WPOR 0 0 0 0 0 — 0 0

Bit7 CAPTPAU:CAPTMCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheCAPTMwillremainpowerupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 CAPTCK2~CAPTCK0:SelectCAPTMCounterclock000:PWMO001:fH/2010:fH/4011:fH/8100:fH/16101:fH/32110:fH/64111:fH/128

ThesethreebitsareusedtoselecttheclocksourcefortheCAPTM.TheclocksourcefHisthehighspeedsystemoscillator.

Bit3 CAPTON:CAPTMCounterOn/OffControl0:Off1:On

Thisbitcontrols theoverallon/off functionof theCAPTM.Setting thebithighenablesthecountertorun,clearingthebitdisablestheCAPTM.Clearingthisbit tozerowillstopthecounterfromcountingandturnofftheCAPTMwhichwillreduceitspowerconsumption.When thebitchangesstate fromlowtohigh the internalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalue.

Bit2 Unimplemented,readas"0"Bit1~0 CAPS1~CAPS0:capturesourceselect

00:H101:H210:H311:CTIN

Rev. 1.10 9� De�e��e� �1� �01� Rev. 1.10 93 De�e��e� �1� �01�


CAPTC1 RegisterBit 7 6 5 4 3 2 1 0

Na�e CAPEG1 CAPEG0 CAPEN CAPNFT CAPNFS CAPFIL CAPCLR CAMCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 CAPEG1~CAPEG0:DefinesCAPTMcaptureactiveedge00:DisabledCAPTMcapture01:Risingedgecapture10:Fallingedgecapture11:Dualedgecapture

Bit5 CAPEN:CAPTMCaptureinputcontrol0:Disable1:Enable

Thisbitenables/disablestheCAPTMcaptureinputsource.Bit4 CAPNFT:DefinesCAPTMNoiseFiltersampletimes

0:Twice1:4times

TheCAPTMNoiseFiltercircuit requiressampling twiceor4 timescontinuously,when theyareall thesame, thesignalwillbeacknowledged.Thesample time isdecidedbyCAPNFS.

Bit3 CAPNFS:CAPTMNoiseFilterclocksourceSelect0:tSYS

1:4tSYS

TheclocksourceforCaptureTimerModuleCounterisprovidedbyfSYSorfSYS/4.Bit2 CAPFIL:CAPTMcaptureinputfilterControl

0:Disable1:Enable

Thisbitenables/disablestheCAPTMcaptureinputfilter.Bit1 CAPCLR:CAPTMCountercaptureauto-resetControl

0:Disable1:Enable

Thisbit enables/disables the automatic reset of the counterwhen thevalue inCAPTMDLandCAPTMDHhave been transferred into the capture registersCAPTMCLandCAPTMCH.

Bit0 CAMCLR:CAPTMCountercomparematchauto-resetControl0:Disable1:Enable

Thisbitenables/disablestheautomaticresetofthecounterwhenacomparematchhasoccurred.

CAPTMDL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 CAPTMDL:CAPTMCounterLowByteRegisterbit7~bit0CAPTM16-bitCounterbit7~bit0

Rev. 1.10 9� De�e��e� �1� �01� Rev. 1.10 93 De�e��e� �1� �01�


CAPTMDH RegisterBit 7 6 5 4 3 2 1 0

Na�e D15 D14 D13 D1� D11 D10 D9 D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 CAPTMDH:CAPTMCounterHighByteRegisterbit7~bit0CAPTM16-bitCounterbit15~bit8.

CAPTMAL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 CAPTMAL:CAPTMCompareLowByteRegisterbit7~bit0CAPTM16-bitCompareRegisterbit7~bit0.

CAPTMAH RegisterBit 7 6 5 4 3 2 1 0

Na�e D15 D14 D13 D1� D11 D10 D9 D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 CAPTMAH:CAPTMCompareHighByteRegisterbit7~bit0CAPTM16-bitCompareRegisterbit15~bit8.

CAPTMCL RegisterBit 7 6 5 4 3 2 1 0

Na�e D7 D� D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR x x x x x x x x

"x"unknownBit7~0 CAPTMCL:CAPTMCaptureLowByteRegisterbit7~bit0

CAPTM16-bitCaptureRegisterbit7~bit0

CAPTMCH RegisterBit 7 6 5 4 3 2 1 0

Na�e D15 D14 D13 D1� D11 D10 D9 D8R/W R R R R R R R RPOR x x x x x x x x

"x"unknownBit7~0 CAPTMCH:CAPTMCaptureHighByteRegisterbit7~bit0

CAPTM16-bitCaptureRegisterbit15~bit8.

Rev. 1.10 94 De�e��e� �1� �01� Rev. 1.10 95 De�e��e� �1� �01�


Capture Timer OperationTheCaptureTimerisusedtodetectandmeasureinputsignalpulsewidthsandaperiods.ItcanbeusedinbothaCaptureorCompareMode.ThetimerinputsarethefourcaptureinputsH1,H2andH3.Eachofthesecaptureinputshasitsownedgedetectorselection,tochoosebetweenhigh,loworbothedgetriggertypes.

TheCAPTONbitisusedtocontroltheoverallCaptureTimerenable/disablefunction.DisablingtheCaptureModulewhennotusedwillreducethedevicepowerconsumption.Additionallythecaptureinputcontrolisenabled/disabledusingtheCAPENcontrolbit.ThetriggeredgeoptionsaresetupusingtheCAPEG1andCAPEG0bits,toselecteitherpositiveedge,negativeedgeorbothedges.

ThetimeralsoincludesanoiseFilterwhichisusedtofilteroutunwantedglitchesorpulsesontheH1,H2,H3andNFINinputpins.ThisfunctionisenabledusingtheCAPFILbit.Ifthenoisefilterisenabled,thecaptureinputsignalsmustbesampledeither2or4times,inordertorecognizeanedgeasavalidcaptureevent.Thesampling2or4timeunitsarebasedoeithertSYSor4×tSYSdeterminedusingtheCAPNFSbit.

I/P

O/P

Noise Filte�

Sa�pling

Noise Filter with CAPNFT and CATNFS = 0

Capture Mode OperationThecapturetimermodulecontains2captureregisters,CAPTMCLandCAPTMCH,whichareusedtostorethepresentvalueinthecounter.WhentheCaptureModuleisenabled,theneachtimeanexternalpinreceivesavalidtriggersignal,thecontentofthefreerunning16-bitcounter,whichiscontainedintheCAPTMDLandCAPTMDHregisters,willbecapturedintothecaptureregisters,CAPTMCLandCAPTMCH.When thisoccurs, theCAPOF interrupt flagbit in the interruptcontrolregisterwillbeset.Ifthisinterruptisenabledbysettingtheinterruptenablebit,CAPOE,high,aninterruptwillbegenerated.IftheCAPCLRbitissethigh,thenthe16-bitcounterwillbeautomaticallyresetafteracaptureeventoccurs.

Compare Mode OperationWhenthetimerisusedinthecomparemode,theCAPTMALandCAPTMAHregistersareusedtostorethe16-bitcomparevalue.Whenthefreerunningvalueofthecount-up16-bitcounterreachesavalueequaltotheprogrammedvaluesinthesecompareregisters,theCAPCFinterruptflagwillbesetwhichwillgenerateaninterruptifitsrelatedinterruptenablebitisset.IftheCAMCLRbitissethigh, thenthecounterwillbereset tozeroautomaticallywhenacomparematchconditionoccurs.Therotorspeedorastalledmotorconditioncanbedetectedbysettingthecompareregisterstocomparethecapturedsignaledgetransitiontime.Ifarotorstallconditionoccurs,thenacompareinterruptwillbegenerated,afterwhichthePWMmotordrivecircuitcanbeshutdowntopreventamotorburnoutsituation.

Rev. 1.10 94 De�e��e� �1� �01� Rev. 1.10 95 De�e��e� �1� �01�


Noise FilterTheexternalNFINpinisconnectedtoaninternalfiltertoreducethepossibilityofunwantedeventcountingeventsorinaccuratepulsewidthmeasurementsduetoadversenoiseorspikesontheNFINinputsignalandthenoutputtoSTMcapturecircuit.Inordertoensurethatthemotorcontrolcircuitworksnormally.

ThenoisefiltercircuitisanI/Ofilteringsurgecomparewhichcanfiltermicro-secondgradesharp-noise.

Antinoise pulsewidthmaximum: (NF_VIH[4:0]-NF_VIL[4:0])×5μs, (NF_VIH[4:0]-NF_VIL[4:0])>1

Dat_In

Dat_Out

Noise Filte�Dat_In Dat_Out

NF_VIH[4:0] NF_VIL[4:0]

STM

Noise Filter Registers Description

NF_VIH RegisterBit 7 6 5 4 3 2 1 0

Na�e NF_BYPS CINS — D4 D3 D� D1 D0R/W R/W R/W — R/W R/W R/W R/W R/WPOR 0 0 — 1 1 0 0 1

Bit7 NF_BYPS:BypassNoiseFilterEnable0:Disable1:Enable,Dat_Out=Dat_In

Bit6 CINS:STMcapturesourceselection0:NoselectNoiseFilterDat_Out(remainstheoriginalSTMpath)1:SelectNoiseFilterDat_Out

Bit5 Unimplemented,readas"0"Bit4~0 NF_VIHregisterBit4~Bit0

Rev. 1.10 9� De�e��e� �1� �01� Rev. 1.10 97 De�e��e� �1� �01�


NF_VIL RegisterBit 7 6 5 4 3 2 1 0

Na�e NFIS1 NFIS0 — D4 D3 D� D1 D0R/W R/W R/W — R/W R/W R/W R/W R/WPOR 0 0 — 0 1 0 1 0

Bit7~6 NFIS1~NFIS0:NFINInterruptedgecontrol00:Disable01:Risingedgetrigger10:Fallingedgetrigger11:Dualedgetrigger

Bit5 Unimplement,readas"0"Bit4~0 NF_VILregisterBit4~Bit0

ComparatorsFour independentanalogcomparatorsarecontainedwithin thesedevices.Thesefunctionsofferflexibilityviatheirregistercontrolledfeaturessuchaspower-down,polarityselect,hysteresisetc.InsharingtheirpinswithnormalI/OpinsthecomparatorsdonotwastepreciousI/Opinsiftherefunctionsareotherwiseunused.

Comparators Block Diagram

C3P C3X

C�P C�X

+ -

Co�pa�ato� 1 C1X

C0X

C1P

OPA output

Pin sha�e �ont�ol

DAC output

C1N

+ -

Co�pa�ato� 0

+ -

Co�pa�ato� �

+ -

Co�pa�ato� 3

Rev. 1.10 9� De�e��e� �1� �01� Rev. 1.10 97 De�e��e� �1� �01�


Comparator OperationThedevicecontainsfourcomparatorfunctionswhichareused tocompare twoanalogvoltagesandprovideanoutputbasedontheirdifference.Additionalcomparatorfunctionsinclude,outputpolarity,hysteresis functionsandpowerdowncontrol.Anypull-highresistorsconnected to thesharedcomparatorinputpinswillbeautomaticallydisconnectedwhenthecomparatorpin-shareisenabled.Asthecomparatorinputsapproachtheirswitchinglevel,somespuriousoutputsignalsmaybegeneratedonthecomparatoroutputduetotheslowrisingorfallingnatureoftheinputsignals.

Thiscanbeminimisedbyselectingthehysteresisfunctionwillapplyasmallamountofpositivefeedbacktothecomparator.Ideallythecomparatorshouldswitchatthepointwherethepositiveandnegativeinputssignalsareat thesamevoltagelevel,however,unavoidableinputoffsetsintroducesomeuncertaintieshere.Thehysteresisfunction,ifenabled,alsoincreasestheswitchingoffsetvalue.

CPC RegisterBit 7 6 5 4 3 2 1 0

Na�e C3HYEN C�HYEN C1HYEN C0HYEN C3EN C�EN C1EN C0ENR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 0 0 0 0

bit7 C3HYEN:Comparator3HysteresisControl0:Off1:On

This is thehysteresis controlbit and if sethighwill applya limitedamountofhysteresistothecomparator,asspecifiedintheComparatorElectricalCharacteristicstable.Thepositive feedback inducedbyhysteresis reduces theeffectofspuriousswitchingnearthecomparatorthreshold.







bit3 C3EN:Comparator3On/Offcontrol0:Off1:On

This is theComparatoron/offcontrolbit. If thebit iszero thecomparatorwillbeswitchedoffandnopowerconsumedevenifanalogvoltagesareappliedtoitsinputs.ForpowersensitiveapplicationsthisbitshouldbeclearedtozeroifthecomparatorisnotusedorbeforethedeviceentersthePower-downmode.

Rev. 1.10 98 De�e��e� �1� �01� Rev. 1.10 99 De�e��e� �1� �01�








Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.ThisdevicealsoincludessomespecialA/Dfeaturesforspecificuseinmotorcontrolapplications.

A/D OverviewThisdevicecontainsa6-channelanalogtodigitalconverter,6-channelcanbedirectlyinterfacetoexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoeithera10-bitdigitalvalue.Anadditionalchannelisconnectedtotheexternalcurrentsense inputpin,AP,viaan internaloperationalamplifier forsignalamplification,beforebeingtransferredtotheA/Dconverterinput.Asetofwhatareknownashighandlowboundaryregisters,allowtheA/Dconverterdigitaloutputvaluetobecomparedwithupperandlowerlimitvaluesandacorrespondinginterrupttobegenerated.AnadditionaldelayfunctionallowsadelaytobeinsertedintothePWMtriggeredA/Dconversionstartprocesstoreducethepossibilityoferroneousanalogvaluesamplingwhentheoutputpowertransistorsareswitchinglargemotorcurrents.

Input Channels A/D Channel Select Bits Input Pins�+1 ACS�~ACS0 AN0~AN5� AP

Rev. 1.10 98 De�e��e� �1� �01� Rev. 1.10 99 De�e��e� �1� �01�


TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

ADRH

ADRL

ADHVDH

ADHVDL

ADLVDH

ADLVDL

ADCHVE

ADCLVE

High Bounda�y Value

Low Bounda�y Value

Co�pa�ison Type Cont�ol Bits

Int_AHL_Li�Inte��upt Signal

ADC

Int_AD_EOC

EOCB �it

Co�pa�e Conve�tedValue with Uppe� and

Lowe� Li�its

ADDL

Delay Registe�

MUX

ADSTS �it

Sta�t Conve�tDelay Ti�e

ADSTR �it

PWM Pe�iodInte��upt signal

PWM dutyInte��upt signal

MUX

PWIS �it

A/D Conve�sionSta�t Signal

DLSTR �itDelay on/off �ont�ol

P�og�a��a�le Gain A�plifie�

AP

OPAVS0

OPAVS�Gain Cont�ol Bits

Gain = X1/X5/X10/X�0

ACS�~ACS0

PB0/AN3

PB�/AN5

PA�/AN0

PA7/AN1

PA1/AN�

PB1/AN4AD

HL/LVT�igge�

A/D Converter Structure

A/D Converter Register DescriptionOveralloperationoftheA/Dconverteriscontrolledusingseveralregisters.AreadonlyregisterpairADRL/ADRHexiststostoretheADCdata10-bitvalue.TheADLVDL/ADLVDHandADHVDL/ADHVDHregistersareusedtostoretheboundarylimitvaluesoftheADCinterrupttriggerwhiletheADDLregister isused tosetup thestartconversiondelay time.TheremainingregistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.

Register Name

Bit7 6 5 4 3 2 1 0

ADRL D7 D� D5 D4 D3 D� D1 D0ADRH — — — — — — D9 D8ADCR0 ADSTR EOCB ADOFF — — ACS� ACS1 ACS0ADCR1 ADSTS DLSTR PWIS ADCHVE ADCLVE ADCK� ADCK1 ADCK0ADCR� — — — — — — PWDIS1 PWDIS0ADDL D7 D� D5 D4 D3 D� D1 D0

ADLVDL D7 D� D5 D4 D3 D� D1 D0ADLVDH — — — — — — D9 D8ADHVDL D7 D� D5 D4 D3 D� D1 D0ADHVDH — — — — — — D9 D8

A/D Converter Register List

Rev. 1.10 100 De�e��e� �1� �01� Rev. 1.10 101 De�e��e� �1� �01�


A/D Converter Data Registers – ADRL, ADRHAsthisdevicecontainsaninternal10-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.After theconversionprocess takesplace, these registerscanbedirectly readby themicrocontrollertoobtainthedigitisedconversionvalue.

ADRL RegisterBit 7 6 5 4 3 2 1 0

Na�e D7 D� D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR x x x x x x x x

"x"unknownBit7~0 A/DLowByteRegisterBit7~Bit0

ADRH RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — x x

"x"unknownBit7~2 Unimplemented,readas"0"Bit1~0 A/DHighByteRegisterBit1~Bit0

A/D Converter Control Registers – ADCR0, ADCR1, ADCR2, ADDLTocontrolthefunctionandoperationoftheA/Dconverter,fourcontrolregistersknownasADCR0,ADCR1andADCR2areprovided.These8-bitregistersdefinefunctionssuchastheselectionofwhichanalogchannel isconnectedtotheinternalA/Dconverter, thedigitiseddataformat, theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.TheACS2~ACS0bits intheADCR0registerdefinetheADCinputchannelnumber.Asthedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit,eachoftheindividual6analoginputsmustberoutedtotheconverter.ItisthefunctionoftheACS2~ACS0bitstodeterminewhichanalogchannelinputpinsorAPpinisactuallyconnectedtotheinternalA/Dconverter.

TheADDLregisterexiststostoretheADCdelaystarttime.

ADCR0 Register Bit 7 6 5 4 3 2 1 0

Na�e ADSTR EOCB ADOFF — — ACS� ACS1 ACS0R/W R/W R R/W — — R/W R/W R/WPOR 0 1 1 — — 0 0 0

Bit7 ADSTR:StarttheA/Dconversion0→1→0:start0→1:resettheA/DconverterandsetEOCBto"1"

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.WhenthebitissethightheA/Dconverterwillbereset.

Bit6 EOCB:EndofA/Dconversionflag0:A/Dconversionended1:A/Dconversioninprogress

ThisreadonlyflagisusedtoindicatewhenanA/Dconversionprocesshascompleted.Whentheconversionprocessisrunningthebitwillbehigh.

Rev. 1.10 100 De�e��e� �1� �01� Rev. 1.10 101 De�e��e� �1� �01�


Bit5 ADOFF:ADCmodulepoweron/offcontrolbit0:ADCmodulepoweron1:ADCmodulepoweroff

Thisbitcontrols thepowerto theA/Dinternalfunction.ThisbitshouldbeclearedtozerotoenabletheA/Dconverter.IfthebitissethighthentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.AstheA/Dconverterwillconsumealimitedamountofpower,evenwhennotexecutingaconversion,thismaybeanimportantconsiderationinpowersensitivebatterypoweredapplications.Note:1.itisrecommendedtosetADOFF=1beforeenteringIDLE/SLEEPModefor savingpower.2.ADOFF=1willpowerdowntheADCmodule.

Bit4~3 Unimplemented,readas"0"Bit2~0 ACS2 ~ ACS0:SelectA/Dchannel

000:AN0001:AN1010:AN2011:AN3100:AN4101:AN5110:OPAoutput111:Undefined

ThesearetheA/Dchannelselectcontrolbits.AsthereisonlyoneinternalhardwareA/DconvertereachofthesixA/Dinputsmustberoutedtotheinternalconverterusingthesebits.

ADCR1 RegisterBit 7 6 5 4 3 2 1 0

Na�e ADSTS DLSTR PWIS ADCHVE ADCLVE ADCK� ADCK1 ADCK0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 ADSTS:SelectADCtriggercircuit0:SelectADSTRtriggercircuit1:SelectDELAYtriggercircuit

Bit6 DLSTR:Delaystartfunctioncontrol0:DisablebutneedtosetADDLto"0"1:EnablebutneedtosetADDLtononzerovalue

Bit5 PWIS:SelectPWMModuleinterruptsource0:SelectPWMperiodinterrupt1:SelectPWMdutyinterrupt

Bit4~3 ADCHVE, ADCLVE:SelectADCinterrupttriggersource00:ADLVD[9:0]<ADR[9:0]<ADHVD[9:0]01:ADR[9:0]<=ADLVD[9:0]10:ADR[9:0]>=ADHVD[9:0]11:ADR[9:0]<=ADLVD[9:0]orADR[9:0]>=ADHVD[9:0]

Bit2~0 ADCK2 ~ ADCK0:SelectADCclocksource000:fSYS

001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:Undefined

ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.

Rev. 1.10 10� De�e��e� �1� �01� Rev. 1.10 103 De�e��e� �1� �01�


ADCR2 RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — — — PWDIS1 PWDIS0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 PWDIS1~PWDIS0:PWIS=1,selectPWMndutycycleinterrupttriggersource

00:PWM001:PWM110:PWM211:Reseved(selectPWM2dutycycleinterrupttriggersource)

ADDL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 ADCDelay-TimeregisterBit7~Bit0Delay-TimeValue(countbysystemclock)

A/D Converter Boundary Registers – ADLVDL, ADLVDH, ADHVDL, ADHVDH ThedevicecontainswhatareknownasboundaryregisterstostorefixedvaluesforcomparisonwiththeA/DconverterconvertedvaluestoredinADRLandADRH.Thereare twopairsofregisters,ahighboundarypair,knownasADHVDLandADHVDHanda lowboundarypairknownasADLVDLandADLVDH.

ADLVDL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 ADCLowBoundaryLowByteRegisterBit7~Bit0

ADLVDH RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0


Bit1~0 ADCLowBoundaryHighByteRegisterBit9~Bit8

ADHVDL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 ADCHighBoundaryLowByteRegisterBit7~Bit0

Rev. 1.10 10� De�e��e� �1� �01� Rev. 1.10 103 De�e��e� �1� �01�


ADHVDH RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0


Bit1~0 ADCHighBoundaryHighByteRegisterBit9~Bit8

A/D OperationTherearetwowaystoinitiateanA/DConverterconversioncycle,selectedusingtheADSTSbit.Thefirstof theseis tousetheADSTRbit intheADCR0registerusedtostartandreset theA/Dconverter.Whenthemicrocontrollerprogramsets thisbit fromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.WhentheADSTRbit isbroughtfromlowtohighbutnotlowagain,theEOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.

Thesecondmethodof initiatingaconversion is touse thePWMinterruptsignal.ThiscanbesourcedfromeitherthePWMperiodordutyinterruptsignal,selectedusingthePWISbit.IfselectsPWMdutyinterruptsignal,interrupttriggersourcecanbeselectedbyPWDIS1andPWDIS2intheADCR2register.TheDLSTRbitcanactivateadelayfunctionwhichinsertsadelaytimebetweenthe incomingPWMinterruptsignalandtheactualstartof theA/Dconversionprocess,with theactualtimebeingsetupusingtheADDLregister.Theactualdelaytimeiscalculatedbytheregistercontentmultipliedbythesystemclockperiod.ThedelaybetweenthePWMinterruptandthestartoftheA/Dconversionistoreducethepossibilityoferroneousanalogsamplesbeingtakenduringthetimeoflargetransientcurrentswitchingbythemotordrivetransistors.NotethatiftheDLSTRbitselectsnodelaytheADDLregistermustbeclearedtozeroandvice-versaifthedelayisselected,thenanon-zerovaluemustbeprogrammedintotheADDLregister.

TheEOCBbit in theADCR0register isused to indicatewhentheanalogtodigitalconversionprocess iscomplete.Thisbitwillbeautomatically set tozeroby themicrocontroller afteraconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andif theinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theADCK2~ADCK0bitsintheADCR1register.AlthoughtheA/Dclocksourceisdeterminedbythesystemclocky,fSYS,andbybitsADCK2~ADCK0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstheminimumvalueofpermissibleA/Dclockperiod,tADCK,is0.2μs,caremustbetakenforsystemclockfrequenciesgreaterthan5MHz.Forexample,if thesystemclockoperatesatafrequencyof5MHz,theADCK2~ADCK0bitsshouldnotbesetto"000"and"001".DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.

Refer to thefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

Rev. 1.10 104 De�e��e� �1� �01� Rev. 1.10 105 De�e��e� �1� �01�


fSYS

A/D clock Period (tAD)ADCK2,ADCK1,ADCK0

=000(fSYS)

ADCK2,ADCK1,ADCK0

=001(fSYS/2)

ADCK2,ADCK1, ADCK0

=010(fSYS/4)

ADCK2,ADCK1, ADCK0

=011(fSYS/8)

ADCK2,ADCK1,ADCK0

=100(fSYS/16)

ADCK2,ADCK1,ADCK0

=101(fSYS/32)

ADCK2,ADCK1,ADCK0

=110(fSYS/64)

ADCK2,ADCK1,ADCK0

=111

5MHz �00ns 400ns 800ns 1.6μs 3.2μs 6.4μs 12.8μs Undefined10MHz 100ns* �00ns 400ns 800ns 1.6μs 3.2μs 6.4μs Undefined�0MHz 50ns* 100ns* �00ns 400ns 800ns 1.6μs 3.2μs Undefined

A/D Clock Period Examples

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theADOFFbit in theADCR0register.Thisbitmustbezero topoweron theA/Dconverter. if theADOFFbit iszerothensomepowerwillstillbeconsumed.Inpowerconsciousapplicationsit isthereforerecommendedthat theADOFFissethightoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

Theboundaryregisterpairs,ADHVDL/ADHVDHandADLVDL/ADLVDHcontainpresetvalueswhichcanbecomparedwith theA/Dconvertedvalues in theADRL/ADRHregisters.VarioustypesofcomparisonscanbemadeasdefinedbytheADCLVEandADCHVEbitsandaninterruptgeneratedtoinformthesystemthateither thelowerorhigherboundaryhasbeenexceeded.Thisfunctioncanbeusedtoensurethatthemotorcurrentoperateswithinsafeworkinglimits.

Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCK2~ADCK0intheADCR1register.

• Step2EnabletheA/DbyclearingtheADOFFbitintheADCR0registertozero.

• Step3SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS2~ACS0bitswhicharealsocontainedintheADCR0register.

• Step4SelectwhichpinsaretobeusedasA/Dinputsandconfigurethembycorrectlyprogrammingthecorrectbitsinthepinshareregisters.

• Step5Selectwhich triggercircuit is tobeusedbycorrectlyprogramming theADSTSbits in theADCR1.

• Step6If theinterruptsare tobeused, theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbit,AEOCE,mustbothbesethightodothis.

• Step7Ifthestep5selectsADSTRtriggercircuit,theanalogtodigitalconversionprocesscanbeinitialisedbysettingtheADSTRbitintheADCR0registerfromlowtohighandthenlowagain.Notethatthisbitshouldhavebeenoriginallyclearedtozero.Ifthestep5selectsPWMinterrupttriggerDelaycircuit,theDelaystartfunctioncanbeenabledbysettingtheDLSTRbitintheADCR1register.

Rev. 1.10 104 De�e��e� �1� �01� Rev. 1.10 105 De�e��e� �1� �01�


• Step8Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheADCR0registercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregisterADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethod,iftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.

Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheEOCBbitintheADCR0registerisused,theinterruptenablestepabovecanbeomitted.

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKwheretADCKisequaltotheA/Dclockperiod.

0 1 2 3 4 10 11 12

Tdeo�

ADCLK

START

EOCB

D[5:0]

TdoutADON

T�kl T�kh TadckTst

Tsta�t

Ton

000H

Toff

A/D Conversion Timing

Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,bysettingbitADOFFhigh in theADCR0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAsthedevicecontainsa10-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal to3FFH.Sincethefull-scaleanaloginputvalueisequal to theVDDvoltage, thisgivesasinglebitanaloginputvalueofVDDdividedby1024.

1LSB=VDD/1024

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×VDD/1024

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDlevel.

Rev. 1.10 10� De�e��e� �1� �01� Rev. 1.10 107 De�e��e� �1� �01�


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� �

� �

� �

� � � � � �

� � � � � � � � � � � � � � ��

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Ideal A/D Transfer Function

A/D Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheEOCBbit intheADCR0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an EOCB polling method to detect the end of conversionclr AEOCE ; disable ADC interruptmov a,03Hmov ADCR1,a ; select fSYS/8 as A/D clockclr ADOFFmov a,0C0h ; setup PAPS1 to configure pins AN0~AN1mov PAPS1,a mov a,00hmov ADCR0 ; enable and connect AN0 channel to A/D converter:start_conversion: clr ADSTR ; high pulse on start bit to initiate conversion set ADSTR ; reset A/D clr ADSTR ; start A/Dpolling_EOC: sz EOCB ; poll the ADCR0 register EOCB bit to detect end ; of A/D conversion jmp polling_EOC ; continue polling mov a,ADRL ; read low byte conversion result value mov ADRL_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov ADRH_buffer,a ; save result to user defined register::jmp start_conversion ; start next a/d conversion

Rev. 1.10 10� De�e��e� �1� �01� Rev. 1.10 107 De�e��e� �1� �01�


xample: using the interrupt method to detect the end of conversionclr MF1E ; disable ADC interruptclr AEOCEmov a,03Hmov ADCR1,a ; select fSYS/8 as A/D clockclr ADOFFmov a,0C0h ; setup PAPS1 to configure pins AN0~AN1mov PAPS1,a mov a,00hmov ADCR0,a ; enable and connect AN0 channel to A/D converterStart_conversion: clr ADSTR ; high pulse on START bit to initiate conversion set ADSTR ; reset A/D clr ADSTR ; start A/D clr AEOCF ; clear ADC interrupt request flag set AEOCE ; enable ADC interrupt set MF1E ; enable Multi_interrupt 1 set EMI ; enable global interrupt:: ; ADC interrupt service routineADC_ISR: mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory:: mov a,ADRL ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register::EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti

Rev. 1.10 108 De�e��e� �1� �01� Rev. 1.10 109 De�e��e� �1� �01�


Over-current DetectionThedevice contains an fully integratedover-current detect circuitwhich isused formotorprotection.

+_

OPCM

Int_IsAP

OPA : Av=1/5/10/�0

DAC8-�it

OP & Co�pa�e CKT

APInt_Is

OPA

Co�pa�ato� 0

Int_AD_EOC

Int_AHL_ Li�ADC

ADR

EOC

AD HL/LVT�igge�

Int_AHL_ Li�

IntT�igge�

C0E

ADLVD/ADHVD

Over-current Detector Block Diagram

Over-current Functional DescriptionTheover-currentfunctionalblockincludesanamplifier,10-bitA/DConverter,8-bitD/AConverterandcomparator.Ifanover-currentsituationisdetectedthenthemotorexternaldrivecircuitcanbeswitchedoff immediately topreventdamagetothemotor.Twokindsof interruptsaregeneratedwhichcanbeusedforover-currentdetection.

• A/DConverterinterrupt-Int_AHL_Lim

• Comparator0interrupt-Int_Is

Over-current Register DescriptionTherearethreeregisterstocontrolthefunctionandoperationoftheovercurrentdetectioncircuits,knownasOPOMS,OPCMandOPACAL.These8-bitregistersdefinefunctionssuchastheOPAoperationmodeselection,OPAcalibrationandcomparison.OPCMisan8-bitDACregisterusedforOPAcomparison.

Rev. 1.10 108 De�e��e� �1� �01� Rev. 1.10 109 De�e��e� �1� �01�


OPOMS RegisterBit 7 6 5 4 3 2 1 0

Na�e CMP0_EG1 CMP0_EG0 — — — OPAVS� OPAVS1 OPAVS0R/W R/W R/W — — — R/W R/W R/WPOR 0 0 — — — 0 1 0

Bit7~6 CMP0_EG1~CMP0_EG0:DefinesComparatoractiveedge00:DisableComparator0andDAC01:Risingedge10:Fallingedge11:Dualedge

Bit5~3 Unimplemented,readas"0"Bit2~0 OPAVS2~OPAVS0:OPAAvmodeselect

000:DisableOPA001:Av=5010:Av=10011:Av=20111:AV=1

Note:ItisneedtoenableAN2/APbysettingpinshareregisterwhenusingOPAfunction.

OPCM RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 8-bitOPAcomparisonregisterbit7~bit0

OPACAL RegisterBit 7 6 5 4 3 2 1 0

Na�e — ARS AOFM AOF4 AOF3 AOF� AOF1 AOF0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 1 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 ARS:Comparatorinputoffsetcalibrationreferenceselect

0:Comparatornegativeinput1:Comparatorpositiveinput

Bit5 AOFM: NormalorCalibrationModeselect0:OpamporComparatorMode1:OffsetCalibrationMode

Bit4~0 AOF4~AOF0:Comparatorinputoffsetvoltagecalibrationcontrol00000:Minimum10000:Center11111:Maximum

Rev. 1.10 110 De�e��e� �1� �01� Rev. 1.10 111 De�e��e� �1� �01�


BLDC Motor Control CircuitThissectiondescribeshowthedevicecanbeused tocontrolBrushlessDCMotors,otherwiseknownasBLDCMotors.Itshighleveloffunctionalintegrationandflexibilityofferafullrangeofdrivingfeaturesformotordriving.

Functional DescriptionThePWMcountercircuitoutputPWMOishasanadjustablePWMDutytocontroltheoutputmotorpowerthuscontrollingthemotorspeed.ChangingthePWMfrequencycanbeusedtoenhancethemotordriveefficiencyortoreducenoiseandresonancegeneratedduringphysicalmotoroperation.

The internalMaskcircuit isused todeterminewhichPWMmodulationsignalsareenabledordisabledfor themotorspeedcontrol.ThePWMmodulationsignalcanbeoutputboththeupperarms,GAT/GBT/GCTandthelowerarms,GAB/GBB/GCB,oftheexternalGateDriverTransistorPairsundersoftwarecontrol.

TheDead-TimeinsertioncircuitisusedtoensuretheupperandlowerGateDriverTransistorPairsarenotenabledsimultaneouslytopreventtheoccurrenceofavirtualpowershortcircuit.Thedeadtimeisselectedundersoftwarecontrol.

TheStaggeredcircuitcanforceall theoutputs toanoffstatus if thesoftwaredetectsanerrorconditionwhichcouldbeduetoexternalfactorssuchasESDproblemsorbothupperandlowerexternalGateDriverTransistorpairsbeingsimultaneouslyon.ThePolaritycircuitcanselect theoutputpolarityoftheBLDCmotoroutputcontrolporttosupportmanydifferenttypesofexternalMOSgatedrivedevicecircuitcombinations.

TheMotorProtectcircuit includesmanydetectioncircuits for functionssuchasamotorstallcondition,overcurrentprotection,externaledgetriggeredPausepin,external level triggerFaultpinetc.TheHallSensorDecodercircuitisasix-stepsystemwhichcanbeusedcontrolthemotordirection.

Twelveregisters,eachusing6bits,areusedtocontrolthedirectionofthemotor.Themotorforward,backward,brakeandfreefunctionsarecontrolledbytheHDCD/HDCRregisters.TheHA/HB/HCorSHA/SHB/SHCcanbeselectedastheHallSensorDecodercircuitinputs.

Rev. 1.10 110 De�e��e� �1� �01� Rev. 1.10 111 De�e��e� �1� �01�


10-�it PWM �ounte�

CKT

PWMR

Fpw�

PWMOx3PWMP_Int

PWMD_Int x3

MPTC1

Mask

GAT

GAB

GBT

GBB

GCT

GCB

Ove� Cu��ent P�ote�tion

Stall P�ote�tion

S/W

PWMBx3

MCF DTSPWMCDUTRx3 PRDR

PLC

HDCD

HC

HB

HA

SHA

SHB

SHC

SA

SB

SC

HDMS

0

1

Hall Senso� D�ode�1�x� Registe�

HDCRFRS

BRKE

Moto�P�ote�t

CKT

HATHABHBT HBBHCTHCB

PROTECT

HD_EN

PWMCo�ple�ent Pola�ity

DeadTi�eInse�t

Stagge�edCi��uit

AT�

AB�

BT�

BB�

CT�

CB�

AT0

AB0

BT0

BB0

CT0

CB0

AT1

AB1

BT1

BB1

CT1

CB1

BRKE

MCD

MPTC�

Hall Noise Filte�

Hall DelayCKT

HCHK_NUM HNF_MSEL

CTM1�-Int

HDLY_MSEL CTM_SEL[1:0]

PWMMDPWMME

BLDC Motor Control Block Diagram

Note:GAT,GAB,GBT,GBB,GCT,GCB==PWM0H,PWM0L,PWM1H,PWM1L,PWM2H,PWM2L.

PWM Counter Control Circuit Thedeviceincludesa10-bitPWMgenerator.ThePWMsignalhasbothadjustabledutycycleandfrequencythatcanbesetupbyprogramming10-bitvaluesintothecorrespondingPWMregisters.

10-�it PWM up/down �ounte�

CKT

PWMR

fPWM

PWM0~�

PWMP_Int

PWMD0~�_Int

PWMCDUTR0~� PRDR

PWM Block Diagram

Rev. 1.10 11� De�e��e� �1� �01� Rev. 1.10 113 De�e��e� �1� �01�


PWMP(Old)

PWMD_CH0(Old)

PWMD_CH0(New)

PWMP(New)

PWMEdge-Aligned Mode

PWMD_CH0(New) PWMP(New)

New PWM Duty

New PWM Pe�iod

PWMO

PWM Edge-Aligned mode Timing Diagram

PWMP(Old)

PWMD_CH0(Old)

PWMD_CH0(New)

PWMP(New)

PWMCente�-Aligned Mode

PWMD_CH0(New) PWMP(New)

New PWM Duty

New PWM Pe�iod

PWMO

Cente�-align �ode 1

Cente�-align �ode �

PWM Center-Aligned mode Timing Diagram

PWM Register DescriptionOverallPWMoperationiscontrolledbyaseriesofregisters.TheDUTRnL/DUTRnHregisterpairisusedforPWMdutycontrol foradjustmentof themotoroutputpower.ThePRDRL/PRDRHregisterpairareusedtogethertoforma10-bitvaluetosetupthePWMperiodforPWMFrequencyadjustment.BeingabletochangethePWMfrequencyisusefulformotorcharacteristicmatchingforproblemssuchasnoisereductionandresonance.ThePWMRL/PWMRHregistersareusedtomonitorthePWMcounterdynamically.ThePWMONbitinthePWMCregisteristhe10-bitPWMcounteron/offbit.ThePWMclocksourceforthePWMcountercanbeselectedbyPCKS1~PCKS0bitsinthePWMCregister.ThePWMMSbitsinthePWMCregisterdeterminethePWMalignmenttype,whichcanbeeitheredgeorcentretype.ItshouldbenotedthattheorderofwritingdatatoPWMregisterisMSB.

Rev. 1.10 11� De�e��e� �1� �01� Rev. 1.10 113 De�e��e� �1� �01�


• PWMC RegisterBit 7 6 5 4 3 2 1 0

Na�e PWMMS1 PWMMS0 PCKS1 PCKS0 PWMON ITCMS1 ITCMS0 PWMLDR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PWMMS:PWMmodeselectbit0x:Edge-alignedmode,10:Centre-alignedmode111:Centre-alignedmode2

Bit5~4 PCKS1, PCKS0:ClocksourceofthePWMcounterselect000:fPWM,PWMfrequencyMin.=20kHz,fPWMbaseon20MHz001:fPWM/2,PWMfrequencyMin.=10kHz010:fPWM/4,PWMfrequencyMin.=5kHz011:fPWM/8,PWMfrequencyMin.=2.5kHz

Bit3 PWMON:PWMCircuitOn/Offcontrol0:Off1:On

Thisbitcontrolstheoverallon/offfunctionofthePWM.Settingthebithighenablesthecounter torun,clearingthebitdisablesthePWM.Clearingthisbit tozerowillstopthecounterfromcountingandturnoff thePWMwhichwill reduceitspowerconsumption.

Bit2~1 ITCMS1~ITCMS0: 00:disablecenter-alignedmodedutyinterrupt01:center-alignedmodedutyinterruptonlyincounterupcondition10:center-alignedmodedutyinterruptonlyincounterdowncondition11:center-alignedmodedutyinterruptbothincounterupordowncondition

Bit0 PWMLD:PWMPRDR&DUTRx,x=0~2registerupdatebit0:TheregistersvalueofPRDRandDUTRx,x=0~2areneverloadedtocounterandComparatorregisters.

1:ThePRDRregisterwillbeloadvaluetocounterregisteraftercounterunderflow,andhardwarewillclearbynextclockcycle.

• DUTR0L RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 10-bitPWM0Dutyregisterlowbyteregister10-bitDUTR0registerbit7~bit0

• DUTR0H RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 10-bitPWM0Dutyregisterhighbyteregister

10-bitDUTR0registerbit9~bit8

Rev. 1.10 114 De�e��e� �1� �01� Rev. 1.10 115 De�e��e� �1� �01�






Na�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0







Na�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0



• PRDRL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 10-bitPWMPeriodregisterlowbyteregister10-bitPRDRregisterbit7~bit0

• PRDRH RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 10-bitPWMPeriodregisterhighbyteregister

10-bitPRDRregisterbit9~bit8

Rev. 1.10 114 De�e��e� �1� �01� Rev. 1.10 115 De�e��e� �1� �01�


• PWMRL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 10-bitPWMcounterregisterlowbyteregister10-bitPWMcounterbit7~bit0

• PWMRH RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 10-bitPWMCounterhighbyteregister

10-bitPWMCounterbit9~bit8

Mask FunctionThedeviceincludesaMotorControlMaskFunctionforincreasedcontrolflexibility.

Polarity

PWMB

IR2101x3GateDriver

MAT

MAB

MBT

MBB

MCT

MCB

PWMO

HallSensorDecoder12x6

HAT/HAB/HBT/HBB/HCT/HCB

Mask

GAT

GAB

GBT

GBB

GCT

GCB

MCF DTS PLC

DeadTimeInsert

Staggeredcircuit

AT2

AB2

BT2

BB2

CT2

CB2

AT0

AB0

BT0

BB0

CT0

CB0

AT1

AB1

BT1

BB1

CT1

CB1

MCD

BRKE PROTECT

PWMMDPWMME

Mask Function Block Diagram

Moto�

U

V

W

Powe� MOS

Moto HV

MAT MBT MCT

MAB MBB MCB

Mask Switching

Rev. 1.10 11� De�e��e� �1� �01� Rev. 1.10 117 De�e��e� �1� �01�


Functional DescriptionTheinternalMASKcircuithasthreeoperationmodes,whichareknownastheNormalMode,BrakeModeandMotorProtectMode.

• Normal ModeIntheNormalMode,themotorspeedcontrolmethodisdeterminedbythePWMS/MPWEbitsintheMCFregister.WhenPWMS=0, thebottomportPWMoutputselects transistorpairbottomarmGAB/GBB/GCB.WhenPWMS=1,thetopportPWMoutputselectstransistorpairtoparm,GAT/GBT/GCT.WhenMPWE=0,thePWMoutputisdisabledandAT0/BT0/CT0/AB0/BB0/CB0areallon.WhenMPWE=1, thePWMoutput isenabledandAT0/BT0/CT0/AB0/BB0/CB0canoutputavariablePWMsignalforspeedcontrol.WhenMPWMS=0,thePWMhasaComplementaryoutput.WhenMPWMS=1,thePWMhasaNon-complementaryoutput.MSKMS=0:theMaskModeselectsH/W.MSKMS=1:theMaskModeselectsS/W.

• H/W Mask ModeComplementarycontrol,MPWMS=0

PWMS=0

HAT HAB AT0 AB0

PWMS=1

HAT HAB AT0 AB00 0 0 0 0 0 0 0

0 1 PWMB PWMO 0 1 0 1

1 0 1 0 1 0 PWMO PWMB

1 1 0 0 1 1 0 0

PWMS=0

HBT HBB BT0 BB0

PWMS=1

HBT HBB BT0 BB00 0 0 0 0 0 0 0

0 1 PWMB PWMO 0 1 0 1

1 0 1 0 1 0 PWMO PWMB

1 1 0 0 1 1 0 0

PWMS=0

HCT HCB CT0 CB0

PWMS=1

HCT HCB CT0 CB00 0 0 0 0 0 0 0

0 1 PWMB PWMO 0 1 0 1

1 0 1 0 1 0 PWMO PWMB

1 1 0 0 1 1 0 0

Non-complementarycontrol,MPWMS=1

PWMS=0

HAT HAB AT0 AB0

PWMS=1

HAT HAB AT0 AB00 0 0 0 0 0 0 0

0 1 0 PWMO 0 1 0 1

1 0 1 0 1 0 PWMO 0

1 1 0 0 1 1 0 0

Rev. 1.10 11� De�e��e� �1� �01� Rev. 1.10 117 De�e��e� �1� �01�


PWMS=0

HBT HBB BT0 BB0

PWMS=1

HBT HBB BT0 BB00 0 0 0 0 0 0 0

0 1 0 PWMO 0 1 0 1

1 0 1 0 1 0 PWMO 0

1 1 0 0 1 1 0 0

PWMS=0

HCT HCB CT0 CB0

PWMS=1

HCT HCB CT0 CB00 0 0 0 0 0 0 0

0 1 0 PWMO 0 1 0 1

1 0 1 0 1 0 PWMO 0

1 1 0 0 1 1 0 0

• S/W Mask ModeTocontrol theMaskcircuit, tworegistersknownasPWMME,PWMMD,MCFandMCDareprovided.PWMMEregisterisusedforcontrolPWMsignalandPWMMDisusedtodeterminetheMOSGateDriverCircuitisonoroff.NotethatSettingPWMSandMPWMSoranythingrelatedtoPWMfunctioniseffectivetoH/WorS/Wmode.

0

1

�

3

4

5

3-phase inve�te� Sy��ol

Mask Co�ple�ent ModeExa�ple

Mask Independent Mode Exa�ple

Cu��ent Path (3�0)

PWMO

PWMB

A B C

A B C

A B C A B C A B C

PWMO

PWMB


PWMO

PWMB

Cu��ent Path (5��)

PWMO

PWMB


1

1

0

0

1

1

PMEN

1

0

x

x

0

0

PMD

1

1

1

1

0

0

PMEN

1

0

0

0

x

x

PMD

1

1

1

1

0

0

PMEN

0

0

1

0

x

x

PMD

0

0

1

1

1

1

PMEN

x

x

1

0

0

0

PMD


PWMO

A B C A B C A B C A B C

PWMO


PWMO


PWMO


1

1

1

0

1

1

PMEN

1

0

0

x

0

0

PMD

1

1

1

1

1

0

PMEN

1

0

0

0

0

x

PMD

1

1

1

1

1

0

PMEN

0

0

1

0

0

x

PMD

1

0

1

1

1

1

PMEN

0

x

1

0

0

0

PMD

Mask S/W Mode circuit

Note:1.Duringmaskingenabled,whenPWMxHandPWMxLaremaskedsimultaneously,thetwopinsofeachpaircannotbesetto"1"simultaneously,PMD.0andPMD.1,PMD.2andPMD.3,PMD.4andPMD.5.Iftheyareallhighinthesametime,switch2nandswitch2n+1willoutput"0".

2. IfPWMandcomplementaryPWMareenabledsimultaneously,oneof the tworegistersPWMxHandPWMxLoutputPWMandtheotheronecannotbemaskedto"1"butoutput"0"automaticallybyhardware.

3.IfthePWMxHandPWMxLareconfiguredasI/Ofunction,thenPWMMASKfunctionwillbeinvalid.

Rev. 1.10 118 De�e��e� �1� �01� Rev. 1.10 119 De�e��e� �1� �01�


S/W Mask Register Description• PWMME Register

Bit 7 6 5 4 3 2 1 0Na�e — — PME5 PME4 PME3 PME� PME1 PME0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

bit7~6 unimplemented,readas"0"bit5~0 PME5~PME0:PWMMaskenableregister

0:PWMgeneratorsignalisoutputtonextstage.1:PWMgeneratorsignalismaskedandPMDnisoutputtonextstage.

ThePWMgeneratorsignalwillbemaskedwhenthisbitisenabled.ThecorrespondingPWMnchannelwillbeoutputwithPMD.ndata.

• PWMMD RegisterBit 7 6 5 4 3 2 1 0

Na�e — — PMD5 PMD4 PMD3 PMD� PMD1 PMD0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

bit7~6 unimplemented,readas"0"bit5-0 PMD5~PMD0:PWMMaskDatabit

0:OutputlogiclowtoPWMn.1:OutputlogichightoPWMn.

ThisdatabitcontrolthestateofPWMnoutputpin,ifcorrespondingPMEn=1.

• Brake ModeTheBrakeModehasthehighestpriority.Whenactivated,theexternalGateDriverTransistorPairToparmwillbeoffandtheBottomarmwillbeon.TheBrakeTruthdecodetableisshownbelow.

BRKE=1AT0 BT0 CT0 AB0 BB0 CB0

0 0 0 1 1 1

• Motor Protect ModeWhentheMotorProtectModeisactivated,theexternalGateDriverTransistorPaircanselectthebrake,wherethetoparmisoffandthebottomarmison,orselectfreerunningwherethetopandbottomarmarebothoff.Theprotectiondecodetableisshownbelow.

PROTECT =1 GAT GBT GCT GAB GBB GCB

FMOS=0 0 0 0 0 0 0FMOS=1 0 0 0 1 1 1

For6-Stepcommunication,iftheUwindingandWwindingareonthenturnofftheVwinding.IfGAT=1andGAB=0,turnontheUwindingIfGBT=0andGBB=0,turnofftheVWinding.IfGCT=PWMDandGCB=PWM,turnontheWwindingandadjusttheoutputpowerofthemotorusingtheDUTRregistertocontrolthespeed.

Rev. 1.10 118 De�e��e� �1� �01� Rev. 1.10 119 De�e��e� �1� �01�


HT��FM5�30

MAT

MAB

MBTMBB

MCT

MCB

IR�101x3

GAT

GAB

GBT

GBB

GCT

GCB

Drive Signal Block Diagram

v

v

U

V W

Moto HV

MAT

MBT MCT

MAB

MBB MCB

Moto HVMoto HV

1

0

0

0

PWMD

PWM

Cu��ent di�e�tion

Moto�

Motor Winding Connection

Register DescriptionThedevicehastworegistersconnectedwiththeMaskFunctioncontrol.ThesearetheMCFregisterwhichisusedforcontrolandtheMCDregisterwhichisusedtoreadthestatusofthegatedriveroutputs.

• MCF RegisterBit 7 6 5 4 3 2 1 0

Na�e MSKMS — — — MPWMS MPWE FMOS PWMSR R/W — — — R/W R/W R/W R/W

POR 0 — — — 0 1 0 0

bit7 MSKMS:MaskModeSelect0:H/WMaskMode1:S/WMaskMode

bit6~4 unimplemented,readas"0"Bit3 MPWMS:MaskPWMModeselect

0:Complementary1:Non-complementary

Rev. 1.10 1�0 De�e��e� �1� �01� Rev. 1.10 1�1 De�e��e� �1� �01�


Bit2 MPWE:PWMoutputcontrol0:PWMoutputdisable(AT0/BT0/CT0/AB0/BB0/CB0cannotoutputPWM)1:PWMoutputenable(AT0/BT0/CT0/AB0/BB0/CB0canoutputPWMtocontrolspeed)

Bit1 FMOS:FaultMaskoutputselect0:AT0/BT0/CT0=0,AB0/BB0/CB0=01:AT0/BT0/CT0=0,AB0/BB0/CB0=1

Bit0 PWMS:Topport/BottomportPWMselect0:SelectBottomportPWMoutput1:SelectTopportPWMoutput

• MCD RegisterBit 7 6 5 4 3 2 1 0

Na�e — — GAT GAB GBT FHC FHB FHAR/W — — R R R R R RPOR — — 0 0 0 0 0 0

bit7~6 unimplemented,readas"0"Bit5~3 GAT/GAB/GBT:GatediveroutputmonitorBit2~0 FHC/FHB/FHA:HC/HB/HAfilteredoutputs

ThesesignalsarederivedfromtheHC/HB/HAsignalsandfilteredbytheHallNoiseFilter.

Other FunctionsSeveralotherfunctionsexistforadditionalmotorcontroldrivesignalflexibility.ThesearetheDeadTimeFunction,StaggeredFunctionandPolarityFunction.

Pola�ity

PWMBIR �101 x 3

Gate D�ive�

MAT

MAB

MBT

MBB

MCT

MCB

PWMO

Hall Senso� De�ode�1� x � HAT /

HAB /

HBT /

HBB /

HCT /

HCB

Mask

GAT

GAB

GBT

GBB

GCT

GCB

MCF DTS PLC

Dead

Ti�e

Inse�t

Stagge�ed

Ci��uit

AT �

AB �

BT �

BB �

CT �

CB �

AT 0

AB 0

BT 0

BB 0

CT 0

CB 0

AT 1

AB 1

BT 1

BB 1

CT 1

CB 1

MCD

BRKE PROTECT

PWMMDPWMME

Dead Time, Staggered and Polarity Function Block Diagram

Dead Time FunctionDuringtransistorpairswitching,theDeadTimefunctionisusedtopreventbothupperandlowertransistorpairsfromconductingat thesametimethuspreventingavirtualshortcircuitconditionfromoccurring.Theactualdeadtimevaluecanbesetuptobewithinavaluefrom0.3μs to5μswhichisselectedbytheapplicationprogram.

TheDeadTimeInsertioncircuitrequiressixindependentoutputcircuits:

When theAT0/AB0/BT0/BB0/CT0/CB0outputsexperiencea risingedge, thenaDeadTime isinserted.

WhentheAT0/AB0/BT0/BB0/CT0/CB0outputsexperienceafallingedge,thentheoutputsremainunchanged.

Rev. 1.10 1�0 De�e��e� �1� �01� Rev. 1.10 1�1 De�e��e� �1� �01�


TheDead-TimeInsertionCircuitisonlyduringmotorcontrol.TheDeadTimefunctionisenabled/disabledbytheDTEbitintheDTSregister.

AT0�AB0�BT0�BB0�CT0�CB0

Dead-Ti�e Inse�tion



Dead-Ti�e Inse�tion1.Rising Add Dead-Ti�e Inse�tion�.Falling Un�hange

AT1�AB1�BT1�BB1�CT1�CB1

Dead Time Insertion Timing

Asingleregister,DTS,isdedicatedforusebytheDeadTimefunction.

• DTS RegisterBit 7 6 5 4 3 2 1 0

Na�e DTCKS1 DTCKS0 DTE D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

bit7~6 DTCKS1, DTCKS0:Dead-Timeclocksourceselection00:fDTisfSYS,fSYSbasedon20MHz01:fDTisfSYS/210:fDTisfSYS/411:fDTisfSYS/8

Bit5 DTE:DeadTimeEnable0:Dead-Time=01:Dead-Time=(DTS[4:0]+1)/fDT

Bit4~0 D4~D0:DeadTimeRegisterbit4~bit0Dead-Timecounter.5-bitDead-TimevaluebitsforDead-TimeUnit.Dead-Time=(DTS[4:0]+1)/fDT

Staggered FunctionTheStaggeredFunction isused to forcealloutputdrive transistors toanoffconditionwhenasoftwareerroroccursorduetoexternalfactorssuchasESD.

AT1 AB1 AT2 AB20 0 0 00 1 0 11 0 1 01 1 0 0

ThedefaultconditionfortheBLDCmotorcontrolcircuitisdesignedfordefaultN-typetransistorpairs.Thismeansa"1"valuewillswitchthetransistoronanda"0"valuewillswitchitoff.

Rev. 1.10 1�� De�e��e� �1� �01� Rev. 1.10 1�3 De�e��e� �1� �01�


Polarity FunctionThis functionallowssetupof theexternalgatedrive transistorOn/Offpolaritystatus.Asingleregister,PLC,isusedforoverallcontrol.

• PLC RegisterBit 7 6 5 4 3 2 1 0

Na�e — — PCBC PCTC PBBC PBTC PABC PATCR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 PCBC: CpairBottomportGateoutputinversecontrolBit4 PCTC: CpairTopportGateoutputinversecontrolBit3 PBBC: BpairBottomportGateoutputinversecontrolBit2 PBTC: BpairTopportGateoutputinversecontrolBit1 PABC: ApairBottomportGateoutputinversecontrolBit0 PATC: ApairTopportGateoutputinversecontrol

Bit Value Status0 Output not inve�ted1 Output inve�ted

PLC Register Values

NotethatthedefaultoutputpinGAT/GAB/GBT/GBB/GCT/GCBstatusishighimpedance.

Hall Sensor DecoderThisdevicecontainsafullyintegratedHallSensordecoderfunctionwhichinterfacestotheHallSensorsintheBLDCmotorfordirectionalandspeedcontrol.

Hall Senso� De�ode�1�x� Registe�s

HDCD

HC

HB

HA

SHA

SHB

SHC

SA

SB

SC

HDMS

HDCR

FRS

BRKE

HAT

HAB

HBT

HBB

HCT

HCB

Mask

AT0

AB0

BT0

BB0

CT0

CB0

0

1

HDCEN

PWMO

PWMB

BRKE PROTECT

HallNoise Filte�

HallDelayCKT

HCHK_NUM HNF_MSEL

CTM-Int x3

HDLY_MSEL CTM_SEL[1:0]

Hall Sensor Decoder Block Diagram

TheHallSensorinputsignalsareselectedbysettingtheHDMSbithigh.IftheHDMSbitiszerothenSHA/SHB/SHCwillbeusedinsteadoftheactualHallSensorsignals.

Rev. 1.10 1�� De�e��e� �1� �01� Rev. 1.10 1�3 De�e��e� �1� �01�


Hall Sensor Noise FilterThisdeviceincludesaHallNoiseFilterfunctiontofilterouttheeffectsofnoisegeneratedbythelargeswitchingcurrentsofthemotordriver.ThisgeneratednoisemayaffecttheHallSensorinputs(H1/H2/H3),whichinturnmayresultinincorrectHallSensoroutputdecoding.

HC

HB

HA

+_

+_

+_

CMP �

CMP 3

Ha1H�1H�1

CMP 1

HSEL

Hall

Noise

Filte�

HNF_MSEL

FHC

FHB

FHA

HALA INT� HALB INT� HALC INT

C1EN

C3EN

C�EN

HCHK_NUMINTEG

H1

H�

H3

Ha0H�0H�0

Hall Sensor Noise Fliter Blick Diagram

Severalregistersareusedtocontrolthenoisefilter.TheHNF_ENbit intheHNF_MSELregisterisusedastheoverallenable/disablebitforthenoisefilter.ItisnecessarytoenableCMP1,CMP2andCMP3hysteries functionbefore thecamparators isusedduringmotorcontrol sensorlessapplications.

HNF_EN bit Status0 Noise Filte� Off – HA/HB/HC not used1 Noise Filte� On

Hall Sensor Noise Filter Enable

ThesamplingfrequencyoftheHallnoisefilterissetupusingtheHFR_SEL[3:0]bits.

TheHCHK_NUM[4:0]bitsareusedtosetuptheHallSensorinputcomparenumbers.

HCHK_NUM[4:0]×Samplingspace=Anti-noiseability=HallDelay-Time.

Itshouldbenoted that longerHalldelay timeswill result inhigherrotorspeedfeedbacksignaldistortion.

Rev. 1.10 1�4 De�e��e� �1� �01� Rev. 1.10 1�5 De�e��e� �1� �01�


Hall Sensor Delay FunctionTheHallsensorfunctioninthedeviceincludesaHalldelayfunctionwhichcanimplementasignalphaseforwardorphasebackwardoperation.Thefollowingsteps,whichshouldbeexecutedbeforetheHallDecoderisenabled,showhowthisfunctionisactivated.

• Step1SettheHallDecodetabletoselecteitherthephaseforwardorphasebackwardfunction.

• Step2SelectwhichTMisused togenerate theDelayTimeandset theselectedTMto run in theCompareMatchModebyprogrammingtheCTM_SEL1~CTM_SEL0bits.

• Step3UsetheHDLY_MSELbittoselecttheHallDelaycircuitoperatingmode.ThedefaultvalueofHDLY_MSELiszerowhichwilldisabletheHallDelaycircuit.If theHDLY_MSELbit issethigh,thentheHallDelaycircuitwillbeenabled.

• Step4EnabletheHallDecoderusingtheHDCENbit.

ThefollowingpointsshouldbenotedregardingtheHDLY_MSELbit.

• Whenthisbitislow,BUF1[2:0]andBUF2[2:0]willbeclearedtozero.

• Whenthisbitislow,TM0/TM1/TM2retaintheiroriginalTMfunctions.

• Whenthebitishigh,theTMwhichisselectedbytheDelayfunctionwillbededicatedforusebytheHallDelaycircuit.

TheoriginalTMfunctionswillstillremainactiveexceptfortheTnONbitwhichwillbecontrolledautomaticallybythehardware.

WithregardtotheTMfunctionsthefollowingstepsshouldbetakenbeforetheDelayfunctionisenabled.

• KeepTnONandTnPAU=0

• TheTMshouldbesetupintheCompareMatchMode

• TnCCLR=1,thereforetheTMisclearedwithacomparatorAmatchcondition.

• SetuptheDelaytimeusingTMnAandTnCKx.

AftertheDelayfunctionisenabled,HDLY_MSELwillchangefromlowtohigh.TheDelaytimemustnotbemorethanonesteptimeoftheHallinput,whichhassixsteps,otherwisetheoutputcannotbeanticipated,willdropoutofstep.

Rev. 1.10 1�4 De�e��e� �1� �01� Rev. 1.10 1�5 De�e��e� �1� �01�


HallSenso�

De�ode�1�x� Registe�

BUF�[�:0]BUF1[�:0]

D

D

D

CTM-1�(TM1)

CTM-10(TM0)

STM-10(TM�)

HallNoiseFilte�

HDCD

HAHBHC

HDLY_MSEL

HATHABHBTHBBHCTHCB

CTM_SEL[1:0]

SHASHBSHC

HDMS

Hall DELAY Ci��uit

HDCEN

HA0

HB0

HC0

HA1

HB1

HC1

HA�HB�HC�

SASBSC

FHAFHBFHC

Delay Function Block Diagram

HA0

HB0

HC0

SA

SB

SC

Delay ti�e

Delay Function Timing

Rev. 1.10 1�� De�e��e� �1� �01� Rev. 1.10 1�7 De�e��e� �1� �01�


Motor Control Drive SignalsThedirectionoftheBLDCmotoriscontrolledusingtheHDCR,HDCDregistersandaseriesofHDCTregisters,HDCT0~HDCT11.WhenusingtheHallSensorDecoderfunction, thedirectioncanbedeterminedusingtheFRSbitandthebrakecanbecontrolledusingtheBRKEbit.BothbitsareintheHDCRregister.SixbitsintheHDCT0~HDCT5registersareusedfortheMotorForwardtable,andsixbitsintheHDCT6~HDCT11registersareusedfortheMotorBackwardtable.

Theaccompanyingtablesshowthetruthtablesforeachoftheregisters.

Fo�wa�d(HDCEN=1�

FRS=0�BRKE=0)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCB1 0 0 1 0 0 HDCT0[5:0]1 1 0 1 1 0 HDCT1[5:0]1 1 1 0 1 0 HDCT�[5:0]0 1 1 0 1 1 HDCT3[5:0]0 0 1 0 0 1 HDCT4[5:0]0 0 0 1 0 1 HDCT5[5:0]

Hall Sensor Decoder Forward Truth Table

Ba�kwa�d(HDCEN=1�

FRS=1�BRKE=0)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCB1 0 0 1 0 0 HDCT�[5:0]1 1 0 1 1 0 HDCT7[5:0]1 1 1 0 1 0 HDCT8[5:0]0 1 1 0 1 1 HDCT9[5:0]0 0 1 0 0 1 HDCT10[5:0]0 0 0 1 0 1 HDCT11[5:0]

Hall Sensor Decoder Backward Truth Table

Thetruthtablesforthebrakefunction,halldecoderdisablefunctionandhalldecodererrorfunctionarealsoshownbelow.

B�ake(BRKE=1�

HDCEN=X�FRS=X)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCB

V V V V V V 0 1 0 1 0 1

Brake Truth Table

Hall De�ode� disa�le

(HDCEN=0)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCBV V V V V V 0 0 0 0 0 0

Hall Decoder Disable Truth Table

Hall De�ode� e��o�

(HDCEN=X)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCB1 0 1 1 1 1 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 0 0

Hall Decoder Error Truth Table

Therelationshipbetween thedata in the truth tablesandhowtheyrelate toactualmotordrivesignalsisshownintheaccompanyingtimingdiagram.Thefull6stepcycleforbothforwardandbackwardmotorrotationisprovided.

Rev. 1.10 1�� De�e��e� �1� �01� Rev. 1.10 1�7 De�e��e� �1� �01�


S1 S� S3 S4 S5 S�S1 S� S3 S4 S5 S�

HAT

SA

SB

SC

Hall senso� :1�0 deg�ee Moto� Fo�wa�d

N S

Ha

H� H�

�-pole Moto�

Moto�

U

V

W

Moto HV

MAT MBT MCT

MAB MBB MCB

P�esent Powe� MOS

MBT

MBB

MCT

MCB

MAT

MAB

HT66FM5230 IR2101x3

HBT

HCT

HBB

HCB

HAB

Motor Drive Signal Timing Diagram – Forward Direction

S1 S� S3 S4 S5 S�S1 S� S3 S4 S5 S�

Hall senso� :1�0 deg�ee Moto� Ba�kwa�d

N S

Ha

H� H�

�-pole Moto�

Moto�

U

V

W

Moto HV

MAT MBT MCT

MAB MBB MCB

P�esent Powe� MOS

MBT

MBB

MCT

MCB

MAT

MAB

HT66FM5230 IR2101x3HAT

HBT

HCT

HBB

HCB

HAB

SA

SB

SC

Motor Drive Signal Timing Diagram – Backward Direction

Rev. 1.10 1�8 De�e��e� �1� �01� Rev. 1.10 1�9 De�e��e� �1� �01�


Hall Sensor Decoder Register DescriptionTheHDCRregisteristheHallSensorDecodercontrolregister,HDCDistheHallSensorDecoderinputdataregister,andHDCT0~HDCT11aretheHallSensorDecodertables.TheHCHK_NUMregister is theHallNoiseFilterchecknumberregisterandHNF_MSELis theHallNoiseFilterModeselectregister.

• INTEG RegisterBit 7 6 5 4 3 2 1 0

Na�e — HSEL INTCS1 INTCS0 INTBS1 INTBS0 INTAS1 INTAS0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

bit7 Unimplemented,readas"0"Bit6 HSEL:HA/HB/HCsourceselect

0:H1/H2/H31:CMP1/CMP2/CMP3output

bit5~4 INTCS1, INTCS0: FHCInterruptedgecontrolforINTC00:disable01:risingedgetrigger10:fallingedgetrigger11:dualedgetrigger

bit3~2 INTBS1, INTBS0: FHBInterruptedgecontrolforINTB00:disable01:risingedgetrigger10:fallingedgetrigger11:dualedgetrigger

bit1~0 INTAS1, INTAS0:FHAInterruptedgecontrolforINTA00:disable01:risingedgetrigger10:fallingedgetrigger11:dualedgetrigger

• HDCR RegisterBit 7 6 5 4 3 2 1 0

Na�e CTM_SEL1 CTM_SEL0 HDLY_MSEL HALS HDMS BRKE FRS HDCENR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 1 0 0 0 0

Bit7~6 CTM_SEL1~CTM_SEL0:TMselectoftheHallDelayCircuit00:TM0(10-bitCTM)01:TM1(16-bitCTM)10:TM2(10-bitSTM)11:Unused

Bit5 HDLY_MSEL:HallDelayCircuitselect0:Selectoriginalpath1:SelectHallDelayCircuit

Bit4 HALS:HallSensorDecoderModeselect0:HallSensor60degree1:HallSensor120degree

Bit3 HDMS:HallSensorDecoderModeselect0:S/WMode1:HallSensorMode

Bit2 BRKE:motorbrakecontrol0:AT/BT/CT/AB/BB/CB=V1:AT/BT/CT=0,AB/BB/CB=1

Rev. 1.10 1�8 De�e��e� �1� �01� Rev. 1.10 1�9 De�e��e� �1� �01�


Bit1 FRS:MotorForward/Backwardselect0:Forward1:Backward

Bit0 HDCEN:HallSensorDecoderenable0:Disable1:Enable

• HDCD RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — — SHC SHB SHAR/W — — — — — R/W R/W R/WPOR — — — — — 0 0 0

Bit7~3 Unimplemented,readas"0"Bit2 SHC:S/WHallCBit1 SHB:S/WHallBBit0 SHA:S/WHallA

• HDCTn Register n=0~11Bit 7 6 5 4 3 2 1 0

Na�e — — HATDn HABDn HBTDn HBBDn HCTDn HCBDnR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 HATDn:GAToutputstatecontrolBit4 HABDn:GABoutputstatecontrolBit3 HBTDn:GBToutputstatecontrolBit2 HBBDn:GBBoutputstatecontrolBit1 HCTDn:GCToutputstatecontrolBit0 HCBDn:GCBoutputstatecontrol

Bit value Status0 Output is low1 Output is high

Output Status

• HCHK_NUM RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — HCK_N4 HCK_N3 HCK_N� HCK_N1 HCK_N0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas"0"Bit4~0 HCK_N4 ~ HCK_N0:HallNoiseFilterchecknumber

Rev. 1.10 130 De�e��e� �1� �01� Rev. 1.10 131 De�e��e� �1� �01�


• HNF_MSEL RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — HNF_EN HFR_SEL�

HFR_SEL1

HFR_SEL0

R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3 HNF_EN:Hallnoisefilterenable

0:Disable(bypass)1:Enable

Bit2~0 HFR_SEL2 ~ HFR_SEL0:Hallnoisefilterclocksourceselect000:fSYS/2001:fSYS/4010:fSYS/8011:fSYS/16100:fSYS/32101:fSYS/64110:fSYS/128111:Unused

Motor Protection FunctionMotorsnormallyrequire largecurrentsfor theiroperationandassuchneedtobeprotectedfromtheproblemsofexcessivedrivecurrents,motorstallingetctoreducemotordamageorforsafetyreasons.Thisdeviceincludesarangeofprotectionandsafetyfeatures.

Mask

AT0

AB0

BT0

BB0

CT0

CB0

Moto� P�ote�tCKT

OPA &

Co�pa�e CKTAP

CAPTM

H1

MPTC1

H�

H3

PROTECT

Int_AHL_Li�

Int_Is

CapTM_C�p

CapTM_Ove�

MPTC�

Protection Function Block Diagram

Rev. 1.10 130 De�e��e� �1� �01� Rev. 1.10 131 De�e��e� �1� �01�


PSWD

D

�eset

OPA &

Co�pa�e CKT

AHLHE

Int_AHL_Li�

ISHE

PROTECT

Q

Int_Is

CapTM_C�p

CapCHE

CAPTM CapOHE

CapTM_Ove�

CA

CP

S=1

CA

PO

PS

=1ISPS=0

PSWPS=1

PSWE PSWPS=0

AHLPS=1

DelayCKT

AHLPS=0

Protection Function Control

Motor Protection Function DescriptionThisdeviceprovidesthreekindsofprotectionfeatures,allowingactiontobetakentoprotectthemotorfromdamageortoprovideadditionalsafety.

Theprotectionfeaturesare:

• Stalldetectionfunction

• Overcurrentprotection

• Turnoffthemotorusingsoftware

Whenthemotorprotectioncircuitison,theexternalGateDrivetransistorpaircanbeputintotwodifferentprotectionmodes.ThefirstistheBrakeModewhichiswherethetoparmisoffandthebottomarmison,andthesecondistheFreeRunningModewherebothtopandbottomarmsareoff.TheFMOSbitintheMCFregisterdetermineswhichtypeisused.

Themotorprotectioncircuitoperatesintwomodes,whichisselectedbytheMPTC2register.Onemodeis theFaultModeandtheother isPauseMode.In theFaultMode,activatingtheprotectfunctionisdeterminedbythetriggersourcestartingstatus.Endingtheprotectfunctionisdeterminedby the trigger sourcedisarmingstatus. In thePauseMode, turningon theprotect function isdeterminedbythetriggersource.Endingtheprotectionfunctionisdeterminedbysoftware.

Rev. 1.10 13� De�e��e� �1� �01� Rev. 1.10 133 De�e��e� �1� �01�


Current Protection FunctionThedeviceusesaninternalOPAwithagainof10,ahighspeed10-bitA/DConverter,an8-bitD/AConverterandacomparator tomeasure themotorcurrentand todetect forexcessivecurrentvalues.Ifanovercurrentsituationshouldoccur,thentheexternaldrivecircuitmustbeshutdownimmediatelytopreventmotordamage.

AsthemotordriverPCBwillhaveratherlargeamountsofnoise,andasthisnoisewillbeamplifiedbytheOPA,thiscaneasilyleadtofalsetriggering.Forthisreasonthefaultmodemustbeused.

FortheMOScurrentlimitingmechanismInt_AHL_Li:WhenAHLHE=0thenthehardwaremodeisdisabled,andwhenAHLHE=1thehardwareisenabled.Thecurrentlimitingcircuitisahardwarecircuit, forwhich theA/Dconverterchannelmust select theoperationamplifier if it is tobeeffective.

AHLPS=0→TheprotectioncircuitwillallowthePWMoutputtoimmediatelyrestartoncetheInt_AHL_Liminterrupthasbeenreset.

AHLPS=1→TheprotectioncircuitwillonlyallowthePWMoutputtorestartonthenextPWMperiodoncetheInt_AHL_Liminterrupthasbeenreset.

MOSover-currentmechanismInt_Is:whenISHE=0 thehardwaremode isdisabledandwhenISHE=1thehardwaremodeisenabled.ISPS=0thenselecttheFaultMode

PWM �ounte�

HAT~HCB x�

S1 S� S3 S4 S5 S�

15KHz~�4 us

GAT~GCB (x�)(PWMO)

Ti�eInt_ADC

MOS li�ited �u��ent p�ote�t: (AHLHE=1;AHLPS=1)Sta�t the next �y�le of the PWM output auto�ati�ly �y ha�dwa�e

Int_ADC

PWM �ounte�

HAT~HCB x�

S1 S� S3 S4 S5 S�

15KHz~�4 us

GAT~GCB (x�)(PWMO)

Ti�eInt_CMP

MOS ove� �u��ent p�ote�tion: (ISHE=1;ISPS=0)Resta�t the PWM output �ust �y softwa�e

Int_CMP

Over Current

Rev. 1.10 13� De�e��e� �1� �01� Rev. 1.10 133 De�e��e� �1� �01�


Motor Stall Detection FunctionFor 3-phase BLDC applications with Hall Sensors, the 16-bit CAPTM can be used to monitor INT0A,

INT0B and INT0C for rotor speed detection. The software will setup the CAPTMAH and CAPTMAL

registers to monitor the Hall sensor inputs INT0A, INT0B and INT0C for motor speed control. If an

abnormal situation exists, then a CapTM_Cmp or CapTM_Over interrupt will be generated.

Stall Detect Mechanism CapTM_Cmp: when CapCHE=0 disable the hardware mode and when CapCHE

=1 enable the hardware mode. The stall detect mechanism must use the Pause Mode.

CAPCPS=1. then select the Pause Mode.

Stall Detect Mechanism CapTM_Over: when CapOHE=0 disable the hardware mode and when

CapOHE=1, enable the hardware mode.

CAPOPS=1, then select the Pause Mode.

Motor Protection Circuit Register DescriptionThereare tworegisters,MPTC1andMPTC2,whichareusedfor themotorprotectioncontrolfunction.

• MPTC1 RegisterBit 7 6 5 4 3 2 1 0

Na�e PSWD PSWE CapOHE CapCHE ISHE AHLHE — —R/W R/W R/W R/W R/W R/W R/W — —POR 0 0 0 0 0 0 — —

Bit7 PSWD:ProtectS/WModedata0:PSWD=01:PSWD=1

Bit6 PSWE: ProtectS/WModeenable0:Disable1:Enable

Bit5 CapOHE: CapTM_OverH/WModeenable0:Disable1:Enable

Bit4 CapCHE:CapTM_CmpH/WModeenable0:Disable1:Enable

Bit3 ISHE:Int_IsH/WModeenable0:Disable1:Enable

Bit2 AHLHE:Int_AHL_LimH/WModeenable0:Disable1:Enable


Rev. 1.10 134 De�e��e� �1� �01� Rev. 1.10 135 De�e��e� �1� �01�


• MPTC2 RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — PSWPS AHLPS ISPS CAPCPS CAPOPSR/W — — — R/W R/W R/W R/W R/WPOR — — — 1 0 0 1 1

Bit7~5 Unimplemented,readas"0"Bit4 PSWPS:Pause/FaultModeselect

0:SelectFaultMode1:SelectPauseMode

Bit3 AHLPS:Int_AHL_LimPause/FaultModeSelection0:ProtectioncircuitallowsimmediaterestartofPWMoutputwhentheInt_AHL_Liminterrupthasbeenreset.

1:ProtectioncircuitonlyallowsrestartofPWMoutputwhenonthenextPWMperiodwhentheInt_AHL_Liminterrupthasbeenreset.

Bit2 ISPS:Int_IsPause/FaultModeselect0:undefined,cannotbeselected1:SelectPauseMode

Bit1 CAPCPS:CapTM_CmpPause/FaultModeselect0:SelectFaultMode1:SelectPauseMode

Bit0 CAPOPS:CapTM_OverPauseModeselect0:undefined,cannotbeselected1:SelectPauseMode

Rev. 1.10 134 De�e��e� �1� �01� Rev. 1.10 135 De�e��e� �1� �01�


I2C Interface The I2C interface isused to communicatewith externalperipheraldevices suchas sensors,EEPROMmemoryetc.OriginallydevelopedbyPhilips,it isatwolinelowspeedserialinterfaceforsynchronousserialdatatransfer.Theadvantageofonlytwolinesforcommunication,relativelysimplecommunicationprotocolandtheabilitytoaccommodatemultipledevicesonthesamebushasmadeitanextremelypopularinterfacetypeformanyapplications.

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I2C Master/Slave Bus Connection

I2C Interface Operation TheI2Cserialinterfaceisatwolineinterface,aserialdataline,SDA,andserialclockline,SCL.Asmanydevicesmaybeconnectedtogetheronthesamebus,theiroutputsarebothopendraintypes.Forthisreasonitisnecessarythatexternalpull-highresistorsareconnectedtotheseoutputs.Notethatnochipselectlineexists,aseachdeviceontheI2CbusisidentifiedbyauniqueaddresswhichwillbetransmittedandreceivedontheI2Cbus.

WhentwodevicescommunicatewitheachotheronthebidirectionalI2Cbus,oneisknownasthemasterdeviceandoneas theslavedevice.Bothmasterandslavecantransmitandreceivedata,however, it is themasterdevice thathasoverallcontrolof thebus.For thisdevice,whichonlyoperatesinslavemode,therearetwomethodsoftransferringdataontheI2Cbus,theslavetransmitmodeandtheslavereceivemode.

It issuggested that theusershallnotenter themicroprocessor toHALTmodebyapplicationprogramduringprocessingI2Ccommunication.

IfthepinisconfiguredtoSDAorSCLfunctionofI2Cinterface,thepinisconfiguredtoopen-collectInput/Outputportanditspull-upfunctioncanbeenabledbyprogrammingtherelatedGenericPull-upControlRegister.

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Rev. 1.10 13� De�e��e� �1� �01� Rev. 1.10 137 De�e��e� �1� �01�


I2C RegistersTherearefourcontrolregistersassociatedwiththeI2Cbus,IICC0,IICC1,IICAandI2CTOCandonedataregister,IICD.TheIICDregister,isusedtostorethedatabeingtransmittedandreceivedontheI2Cbus.BeforethemicrocontrollerwritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheIICDregister.AfterthedataisreceivedfromtheI2Cbus,themicrocontrollercanreaditfromtheIICDregister.AnytransmissionorreceptionofdatafromtheI2CbusmustbemadeviatheIICDregister.

Register Name

Bit

7 6 5 4 3 2 1 0

IICC0 — — — — I�CDBNC1 I�CDBNC0 I�CEN —

IICC1 IICHCF IICHAAS IICHBB IICHTX IICTXAK IICSRW IICRNIC IICRXAK

IICD IICDD7 IICDD� IICDD5 IICDD4 IICDD3 IICDD� IICDD1 IICDD0

IICA IICA� IICA5 IICA4 IICA3 IICA� IICA1 IICA0 —

I�CTOC I�CTOEN I�CTOF I�CTOS5 I�CTOS4 I�CTOS3 I�CTOS� I�CTOS1 I�CTOS0

I2C Registers List

IICC0 Register Bit 7 6 5 4 3 2 1 0

Na�e — — — — I�CDBNC1 I�CDBNC0 I�CEN —R/W — — — — R/W R/W R/W —POR — — — — 0 0 0 —

Bit7~4 unimplemented,readas"0"Bit3~2 I2CDBNC1~I2CDBNC0:I2CDebounceTimeSelection

00:Nodebounce01:2systemclockdebounce10:4systemclockdebounce11:4systemclockdebounce

Bit1 I2CEN:I2Cenable0:Disable1:Enable

Bit0 Unimplemented,readas"0"

SPIfunctioncouldbeturnedofforturnedonbycontrollingtherelatedpin-sharingcontrolbitwhichdecidesthefunctionoftheIOportspin-sharedthepinsSDAandSCL.WhentheIOportspin-sharedthepinsSDAandSCLarechosentothefunctionsotherthanSDAandSCLbypin-sharingcontrolbit,SPIfunction is turnedoffanditsoperatingcurrentwillbereducedtoaminimumvalue. Incontrary,SPIfunctionisturnedonwhentheIOportspin-sharedthepinsSDAandSCLarechosentothepinsSDAandSCLbycontrollingpin-sharingcontrolbit.

Rev. 1.10 13� De�e��e� �1� �01� Rev. 1.10 137 De�e��e� �1� �01�


IICC1 Register Bit 7 6 5 4 3 2 1 0

Na�e IICHCF IICHAAS IICHBB IICHTX IICTXAK IICSRW IICRNIC IICRXAKR/W R R R R/W R/W R R/W RPOR 1 0 0 0 0 0 0 1

Bit7 IICHCF:I2CBusdatatransfercompletionflag0:Dataisbeingtransferred1:Completionofan8-bitdatatransfer

TheIICHCFflagis thedatatransferflag.Thisflagwillbezerowhendataisbeingtransferred.Uponcompletionofan8-bitdata transfer theflagwillgohighandaninterruptwillbegenerated.Belowisanexampleoftheflowofatwo-byteIICdatatransfer.First,IICslavedevicereceiveastartsignalfromIICmasterandthenIICHCFbit isautomaticallyclearedtozero.Second,IICslavedevicefinishreceivingthe1stdatabyteandthenIICHCFbit isautomaticallysettoone.Third,userreadthe1stdatabytefromIICDregisterbytheapplicationprogramandthenIICHCFbitisautomaticallyclearedtozero.Fourth,IICslavedevicefinishreceivingthe2nddatabyteandthenIICHCFbit isautomaticallysettooneandsoon.Finally,IICslavedevicereceiveastopsignalfromIICmasterandthenIICHCFbitisautomaticallysettoone.

Bit6 IICHAAS:I2CBusaddressmatchflag0:Notaddressmatch1:Addressmatch

TheIICHASSflagistheaddressmatchflag.Thisflagisusedtodetermineiftheslavedeviceaddressisthesameasthemastertransmitaddress.Iftheaddressesmatchthenthisbitwillbehigh,ifthereisnomatchthentheflagwillbelow.

Bit5 IICHBB:I2CBusbusyflag0:I2CBusisnotbusy1:I2CBusisbusy

TheIICHBBflagistheI2Cbusyflag.Thisflagwillbe"1"whentheI2CbusisbusywhichwilloccurwhenaSTARTsignalisdetected.Theflagwillbesetto"0"whenthebusisfreewhichwilloccurwhenaSTOPsignalisdetected.

Bit4 IICHTX:SelectI2Cslavedeviceistransmitterorreceiver0:Slavedeviceisthereceiver1:Slavedeviceisthetransmitter

Bit3 IICTXAK:I2CBustransmitacknowledgeflag0:Slavesendacknowledgeflag1:Slavedonotsendacknowledgeflag

TheIICTXAKbitisthetransmitacknowledgeflag.Aftertheslavedevicereceiptof8-bitsofdata, thisbitwillbetransmittedtothebusonthe9thclockfromtheslavedevice.TheslavedevicemustalwayssetIICTXAKbit to"0"beforefurtherdataisreceived.

Bit2 IICSRW:I2CSlaveRead/Writeflag0:Slavedeviceshouldbeinreceivemode1:Slavedeviceshouldbeintransmitmode

TheIICSRWflag is the I2CSlaveRead/Write flag.This flagdetermineswhetherthemasterdevicewishes to transmitor receivedata fromthe I2Cbus.When thetransmittedaddressandslaveaddressismatch,thatiswhentheIICHAASflagissethigh,theslavedevicewillchecktheIICSRWflagtodeterminewhetheritshouldbeintransmitmodeorreceivemode.IftheIICSRWflagishigh,themasterisrequestingtoreaddatafromthebus,sotheslavedeviceshouldbeintransmitmode.WhentheIICSRWflagiszero,themasterwillwritedatatothebus,thereforetheslavedeviceshouldbeinreceivemodetoreadthisdata.

Rev. 1.10 138 De�e��e� �1� �01� Rev. 1.10 139 De�e��e� �1� �01�


Bit1 IICRNIC:I2CrunningusingInternalClockControl0:I2Crunningusinginternalclock1:I2CrunningnotusingInternalClock

TheI2Cmodulecanrunwithoutusinginternalclock,andgenerateaninterruptiftheIICinterrupt isenabled,whichcanbeusedinSLEEPMode,IDLE(SLOW)Mode,NORMAL(SLOW)Mode.

Bit0 IICRXAK:I2CBusReceiveacknowledgeflag0:Slavereceiveacknowledgeflag1:Slavedonotreceiveacknowledgeflag

TheIICRXAKflagisthereceiveracknowledgeflag.WhentheIICRXAKflagis"0",itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsofdatahavebeentransmitted.Whentheslavedevice in the transmitmode, theslavedevicecheckstheIICRXAKflagtodetermineifthemasterreceiverwishestoreceivethenextbyte.TheslavetransmitterwillthereforecontinuesendingoutdatauntiltheIICRXAKflagis"1".Whenthisoccurs,theslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.

TheIICDregisterisusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethedevicewritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheIICDregister.AfterthedataisreceivedfromtheI2Cbus,thedevicecanreaditfromtheIICDregister.AnytransmissionorreceptionofdatafromtheI2CbusmustbemadeviatheIICDregister.

IICD RegisterBit 7 6 5 4 3 2 1 0

Na�e IICDD7 IICDD� IICDD5 IICDD4 IICDD3 IICDD� IICDD1 IICDD0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR x x x x x x x x

"x" unknownBit7~0 IICDD7~IICDD0:IICDataBufferbit7~bit0

IICA RegisterBit 7 6 5 4 3 2 1 0

Na�e IICA� IICA5 IICA4 IICA3 IICA� IICA1 IICA0 —

R/W R/W R/W R/W R/W R/W R/W R/W —

POR x x x x x x x —

"x" unknownBit7~1 IICA6~IICA0:I2Cslaveaddress

IICA6~IICA0istheI2Cslaveaddressbit6~bit0.TheIICAregister is the locationwhere the7-bitslaveaddressof theslavedeviceisstored.Bits7~1oftheIICAregisterdefinethedeviceslaveaddress.Bit0isnotdefined.Whenamasterdevice,whichisconnectedtotheI2Cbus,sendsoutanaddress,whichmatchestheslaveaddressintheIICAregister,theslavedevicewillbeselected.

Bit0 Unimplemented,readas"0"

Rev. 1.10 138 De�e��e� �1� �01� Rev. 1.10 139 De�e��e� �1� �01�


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I2C Block Diagram

I2C Bus Communication CommunicationontheI2Cbusrequiresfourseparatesteps,aSTARTsignal,aslavedeviceaddresstransmission,adatatransmissionandfinallyaSTOPsignal.WhenaSTARTsignalisplacedontheI2Cbus,alldevicesonthebuswillreceivethissignalandbenotifiedoftheimminentarrivalofdataonthebus.ThefirstsevenbitsofthedatawillbetheslaveaddresswiththefirstbitbeingtheMSB.Iftheaddressoftheslavedevicematchesthatofthetransmittedaddress, theIICHAASbitintheIICC1registerwillbesetandanI2Cinterruptwillbegenerated.Afterenteringtheinterruptserviceroutine,theslavedevicemustfirstchecktheconditionoftheIICHAASbittodeterminewhethertheinterruptsourceoriginatesfromanaddressmatchorfromthecompletionofan8-bitdatatransfer.Duringadatatransfer,notethatafterthe7-bitslaveaddresshasbeentransmitted,thefollowingbit,whichisthe8thbit,istheread/writebitwhosevaluewillbeplacedintheSRWbit.Thisbitwillbecheckedbytheslavedevicetodeterminewhethertogointotransmitorreceivemode.BeforeanytransferofdatatoorfromtheI2Cbus,themicrocontrollermustinitialisethebus,thefollowingarestepstoachievethis:

• Step1SetConfigurethepin-sharedI/OportstoI2Cpinfunction.(SCLandSAD).

• Step2SetI2CENbitintheIICC0registerto"1"toenabletheI2Cbus.

• Step3WritetheslaveaddressofthedevicetotheI2CbusaddressregisterIICA.

• Step4SettheIICEinterruptenablebitoftheinterruptcontrolregistertoenabletheI2CinterruptandMulti-functioninterrupt.

Rev. 1.10 140 De�e��e� �1� �01� Rev. 1.10 141 De�e��e� �1� �01�


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I2C Bus Initialisation Flow Chart

I2C Bus Start Signal TheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI2Cbusandnotbytheslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI2Cbus.Whendetected,thisindicatesthattheI2CbusisbusyandthereforetheIICHBBbitwillbeset.ASTARTconditionoccurswhenahightolowtransitionontheSDAlinetakesplacewhentheSCLlineremainshigh.

Slave Address ThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI2Cbus.Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslavedevicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceivingthis7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutbythemastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI2Cbusinterruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,definestheread/writestatusandwillbesavedtotheIICSRWbitoftheIICC1register.Theslavedevicewillthentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.TheslavedevicewillalsosetthestatusflagIICHAASwhentheaddressesmatch.

Asan I2Cbus interrupt cancome from two sources,when theprogramenters the interruptsubroutine, theIICHAASbitshouldbeexamined toseewhether the interruptsourcehascomefromamatchingslaveaddressorfromthecompletionofadatabytetransfer.Whenaslaveaddressismatched,thedevicemustbeplacedineitherthetransmitmodeandthenwritedatatotheIICDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheIICDregistertoreleasetheSCLline.

I2C Bus Read/Write Signal TheIICSRWbitintheIICC1registerdefineswhethertheslavedevicewishestoreaddatafromtheI2CbusorwritedatatotheI2Cbus.Theslavedeviceshouldexaminethisbittodetermineifit istobeatransmitterorareceiver.IftheIICSRWflagis"1"thenthisindicatesthatthemasterdevicewishestoreaddatafromtheI2Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI2Cbusasatransmitter.IftheIICSRWflagis"0"thenthisindicatesthatthemasterwishestosenddatatotheI2Cbus,thereforetheslavedevicemustbesetuptoreaddatafromtheI2Cbusasareceiver.

Rev. 1.10 140 De�e��e� �1� �01� Rev. 1.10 141 De�e��e� �1� �01�


I2C Bus Slave Address Acknowledge Signal After themasterhas transmittedacallingaddress,anyslavedeviceon theI2Cbus,whoseowninternaladdressmatchesthecallingaddress,mustgenerateanacknowledgesignal.Theacknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.IfnoacknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemastertoendthecommunication.WhentheIICHAASflagishigh,theaddresseshavematchedandtheslavedevicemustchecktheIICSRWflagtodetermineifitistobeatransmitterorareceiver.IftheIICSRWflagishigh,theslavedeviceshouldbesetuptobeatransmittersotheIICHTXbitintheIICC1registershouldbesetto"1".IftheIICSRWflagislow,thenthemicrocontrollerslavedeviceshouldbesetupasareceiverandtheIICHTXbitintheIICC1registershouldbesetto"0".

I2C Bus Data and Acknowledge Signal The transmitteddata is8-bitswideand is transmittedafter theslavedevicehasacknowledgedreceiptofitsslaveaddress.TheorderofserialbittransmissionistheMSBfirstandtheLSBlast.Afterreceiptof8-bitsofdata,thereceivermusttransmitanacknowledgesignal, level"0",beforeitcanreceivethenextdatabyte.Iftheslavetransmitterdoesnotreceiveanacknowledgebitsignalfromthemasterreceiver, thentheslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignal toreleasetheI2CBus.ThecorrespondingdatawillbestoredintheIICDregister.Ifsetupasatransmitter,theslavedevicemustfirstwritethedatatobetransmittedintotheIICDregister.Ifsetupasareceiver,theslavedevicemustreadthetransmitteddatafromtheIICDregister.

Whentheslavereceiver receives thedatabyte, itmustgenerateanacknowledgebit,knownasIICTXAK,on the9thclock.Theslavedevice,which is setupasa transmitterwillcheck theIICRXAKbitintheIICC1registertodetermineifitistosendanotherdatabyte,ifnotthenitwillreleasetheSDAlineandawaitthereceiptofaSTOPsignalfromthemaster.

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I2C Communication Timing Diagram

Note:*Whenaslaveaddressismatched,thedevicemustbeplacedineitherthetransmitmodeandthenwritedatatotheIICDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheIICDregistertoreleasetheI2CSCLline.

Rev. 1.10 14� De�e��e� �1� �01� Rev. 1.10 143 De�e��e� �1� �01�


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I2C Bus ISR Flow Chart

I2C Time-out ControlInordertoreducetheproblemofI2Clockupduetoreceptionoferroneousclocksources,atime-outfunctionisprovided.IftheclocksourcetotheI2Cisnotreceivedthenafterafixedtimeperiod,theI2Ccircuitryandregisterswillbereset.

The time-outcounterstartscountingonanI2Cbus"START"&"addressmatch"condition,andisclearedbyanSCLfallingedge.BeforethenextSCLfallingedgearrives,ifthetimeelapsedisgreater thanthetime-outsetupbytheI2CTOCregister, thenatime-outconditionwilloccur.Thetime-outfunctionwillstopwhenanI2C"STOP"conditionoccurs.

WhenanI2Ctime-outcounteroverflowoccurs, thecounterwillstopandtheI2CTOENbitwillbecleared tozeroandtheI2CTOFbitwillbesethighto indicate thata time-outconditionhasoccurred.Thetime-outconditionwillalsogenerateaninterruptwhichusestheI2Cinterruptvector.WhenanI2Ctime-outoccurs,theI2Cinternalcircuitrywillberesetandtheregisterswillberesetintothefollowingcondition:

Register After I2C Time-outIICD� IICA� IICC0 No �hange

IICC1 Reset to POR �ondition

I2C Registers After Time-out

Rev. 1.10 14� De�e��e� �1� �01� Rev. 1.10 143 De�e��e� �1� �01�


TheI2CTOFflagcanbeclearedbytheapplicationprogram.Thereare64time-outperiodswhichcanbeselectedusingbitsintheI2CTOCregister.Thetime-outtimeisgivenbytheformula:

((1~64)×32)/fSUB.

Thisgivesarangeofabout1msto64ms.NotealsothattheLIRCoscillatoriscontinuouslyenabled.

I2CTOC Register

Bit 7 6 5 4 3 2 1 0Na�e I�CTOEN I�CTOF I�CTOS5 I�CTOS4 I�CTOS3 I�CTOS� I�CTOS1 I�CTOS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 I2CTOEN:I2CTime-outControl0:disable1:enable

Bit6 I2CTOF:Time-outflag(setbytime-outandclearbysoftware)0:notime-out1:time-outoccurred

Bit5~0 I2CTOS5~I2CTOS0:Time-outDefinitionI2Ctime-outclocksourceisfSUB/32.I2Ctime-outtimeisgivenby:([I2CTOS5:I2CTOS0]+1)×(32/fSUB)

InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontroller todirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternalinterruptandinternalinterruptsfunctions.TheexternalinterruptisgeneratedbytheactionoftheexternalH1,H2,H3andNFINpins,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,Comparators,16-bitCAPTMModul,TimeBase,LVD,EEPROMandtheA/Dconverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Thenumberofregistersdependsuponthedevicechosenbutfall intothreecategories.ThefirstistheINTC0~INTC2registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI4registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran"E"forenable/disablebitor"F"forrequestflag.

Rev. 1.10 144 De�e��e� �1� �01� Rev. 1.10 145 De�e��e� �1� �01�


Function Enable Bit Request Flag NotesGlo�al EMI — —

Exte�nal inte��upt 0(Hall Senso� HA/HB/HC inte��upt)

HALLE HALLF MFI0HALAE HALAF Hall Noise Filte�edHALBE HALBF Hall Noise Filte�edHALCE HALCF Hall Noise Filte�ed

Exte�nal inte��upt 1(Noise Flite� Inte��upt) INT1E INT1F NFIN Inte��upt

Noise Filte�edCo�pa�ato� 0 C0E C0F —Ti�e Base TBE TBF —

A/D Conve�te�AEOCE AEOCF —ALIME ALIMF —

CAPTMCAPOE CAPOF —CAPCE CAPCF —

LVD LVDE LVDF —EEPROM w�ite EPWE EPWF —

PWMPWMDnE PWMDnF n=0�1��PWMPE PWMPF —

CTMTMnAE TMnAF n=0�1TMnPE TMnPF n=0�1

STMTMnAE TMnAF n=�TMnPE TMnPF n=�

I�C IICE IICF —Multifun�tion inte��upt MFnE MFnF n=0~4

Interrupt Register Bit Naming Conventions

Interrupt Register ContentsName Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0INTEG — HSEL INTCS1 INTCS0 INTBS1 INTBS0 INTAS1 INTAS0INTC0 — C0F INT1F HALLF C0E INT1E HALLE EMIINTC1 EPWF LVDF MF1F TBF EPWE LVDE MF1E TBEINTC� IICF MF4F MF3F MF�F IICE MF4E MF3E MF�EMFI0 — HALCF HALBF HALAF — HALCE HALBE HALAEMFI1 CAPCF CAPOF ALIMF AEOCF CAPCE CAPOE ALIME AEOCEMFI� PWMPF PWMD�F PWMD1F PWMD0F PWMPE PWMD�E PWMD1E PWMD0EMFI3 TM1AF TM1PF TM0AF TM0PF TM1AE TM1PE TM0AE TM0PEMFI4 — — TM�AF TM�PF — — TM�AE TM�PE

Rev. 1.10 144 De�e��e� �1� �01� Rev. 1.10 145 De�e��e� �1� �01�


INTEG Register

Bit 7 6 5 4 3 2 1 0Na�e — HSEL INTCS1 INTCS0 INTBS1 INTBS0 INTAS1 INTAS0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

bit7 Unimplemented,readas"0"Bit6 HSEL:HA/HB/HCsourceselect

0:H1/H2/H31:CMP1/CMP2/CMP3output

bit5~4 INTCS1, INTCS0: FHCInterruptedgecontrolforINTC00:disable01:risingedgetrigger10:fallingedgetrigger11:dualedgetrigger

bit3~2 INTBS1, INTBS0: FHBInterruptedgecontrolforINTB00:disable01:risingedgetrigger10:fallingedgetrigger11:dualedgetrigger

bit1~0 INTAS1, INTAS0:FHAInterruptedgecontrolforINTA00:disable01:risingedgetrigger10:fallingedgetrigger11:dualedgetrigger

INTC0 RegisterBit 7 6 5 4 3 2 1 0

Na�e — C0F INT1F HALLF C0E INT1E HALLE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 C0F:Comparator0interruptrequestflag

0:Norequest1:Interruptrequest

Bit5 INT1F:External1interruptrequestflag0:Norequest1:Interruptrequest

Bit4 HALLF:Hallsensorglobalinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 C0E:Comparator0interruptcontrol0:Disable1:Enable

Bit2 INT1E:External1interruptcontrol0:Disable1:Enable

Bit1 HALLE:Hallsensorglobalinterruptcontrol0:Disable1:Enable

Bit0 EMI:GlobalInterruptControl0:Disable1:Enable

Rev. 1.10 14� De�e��e� �1� �01� Rev. 1.10 147 De�e��e� �1� �01�



Na�e EPWF LVDF MF1F TBF EPWE LVDE MF1E TBER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 EPWF:DataEEPROMinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 LVDF:LVDinterruptrequestflag0:Norequest1:Interruptrequest

Bit5 MF1F:Multi-functionInterrupt1RequestFlag0:Norequest1:Interruptrequest

Bit4 TBF:TimeBaseinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 EPWE:DataEEPROMinterruptcontrol0:Disable1:Enable

Bit2 LVDE:LVDinterruptcontrol0:Disable1:Enable

Bit1 MF1E:Multi-functionInterrupt1Control0:Disable1:Enable

Bit0 TBE:TimeBaseinterruptcontrol0:Disable1:Enable


Na�e IICF MF4F MF3F MF�F IICE MF4E MF3E MF�ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 IICF: I2C InterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 MF4F:Multi-functioninterrupt4requestflag0:Norequest1:Interruptrequest



Bit3 IICE: I2C interruptcontrol0:Disable1:Enable

Bit2 MF4E:Multi-functioninterrupt4control0:Disable1:Enable



Rev. 1.10 14� De�e��e� �1� �01� Rev. 1.10 147 De�e��e� �1� �01�


MFI0 RegisterBit 7 6 5 4 3 2 1 0

Na�e — HALCF HALBF HALAF — HALCE HALBE HALAER/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas"0"Bit6 HALCF:HallSensorCinterruptrequestflag


Bit5 HALBF:HallSensorBinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 HALAF:HallSensorAinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 Unimplemented,readas"0"Bit2 HALCE:HallSensorCinterruptcontrol

0:Disable1:Enable

Bit1 HALBE:HallSensorBinterruptcontrol0:Disable1:Enable

Bit0 HALAE:HallSensorAinterruptcontrol0:Disable1:Enable


Na�e CAPCF CAPOF ALIMF AEOCF CAPCE CAPOE ALIME AEOCER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 CAPCF:CAPTMcomparematchinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 CAPOF:CAPTMcaptureoverflowinterruptrequestflag0:Norequest1:Interruptrequest

Bit5 ALIMF:A/DConverterEOCcompareinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 AEOCF:A/DConverterinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 CAPCE:CAPTMcomparematchinterruptcontrol0:Disable1:Enable

Bit2 CAPOE:CAPTMcaptureoverflowinterruptcontrol0:Disable1:Enable

Bit1 ALIME:A/DConverterEOCcompareinterruptcontrol0:Disable1:Enable

Bit0 AEOCE:A/DConverterinterruptcontrol0:Disable1:Enable

Rev. 1.10 148 De�e��e� �1� �01� Rev. 1.10 149 De�e��e� �1� �01�


MFI2 Register Bit 7 6 5 4 3 2 1 0

Na�e PWMPF PWMD�F PWMD1F PWMD0F PWMPE PWMD�E PWMD1E PWMD0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 PWMPF:PWMPeriodmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 PWMD2F:PWM2Dutymatchinterruptrequestflag0:Norequest1:Interruptrequest



Bit3 PWMPE:PWMPeriodmatchinterruptInterruptControl0:Disable1:Enable

Bit2 PWMD2E:PWM2DutymatchinterruptControl0:Disable1:Enable




Na�e TM1AF TM1PF TM0AF TM0PF TM1AE TM1PE TM0AE TM0PER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 TM1AF:TM1ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 TM1PF:TM1ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit5 TM0AF:TM0ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest


Bit3 TM1AE:TM1ComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit2 TM1PE:TM1ComparatorPmatchinterruptcontrol0:Disable1:Enable

Bit1 TM0AE:TM0ComparatorAmatchinterruptcontrol0:Disable1:Enable


Rev. 1.10 148 De�e��e� �1� �01� Rev. 1.10 149 De�e��e� �1� �01�



Na�e — — TM�AF TM�PF — — TM�AE TM�PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 TM2AF:TM2ComparatorAmatchinterruptrequestflag



Bit3~2 Unimplemented,readas"0"Bit1 TM2AE:TM2ComparatorAmatchinterruptcontrol

0:Disable1:Enable


Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparePorCompareAmatchorA/Dconversioncompletionetc,therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.If theenablebit issethighthentheprogramwill jumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea"JMP"whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha"RETI",whichretrieves theoriginalProgramCounteraddress fromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Rev. 1.10 150 De�e��e� �1� �01� Rev. 1.10 151 De�e��e� �1� �01�


Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

NFIN

HALLF

INT1F

HALLE

INT1E

04H

08H

CMP0 C0F C0E 0CH

Inte��upt Na�e

Request Flags

Ena�le Bits

Maste� Ena�le Vector

EMI auto disa�led in ISR

Low

HALBF HALBE

HALCF HALCE

H1 HALAF HALAE

Inte��upts �ontained within Multi-Fun�tion Inte��upts

P�io�ityHigh

XXE Ena�le Bits

xxF Request Flag� auto �eset in ISR

LegendxxF Request Flag� no auto �eset in ISR

�4H

�8HMF4F MF4E

MF3F MF3EMulti-Fun�tion 3

Multi-Fun�tion 4

EEPROM EPWF EPWE

H�

H3

1CH

I�C IICF IICE

�0HMF�F MF�EMulti-Fun�tion �PWMP PWMPF PWMPE

PWMD0 PWMD0F PWMD0E

PWMD1 PWMD1F PWMD1E

PWMD� PWMD�F PWMD�E

10HTi�e Base TBF TBE

14HMulti-Fun�tion 1 MF1F MF1E

AHL_Li� ALIMF ALIME

AEOCF AEOCE

CAPCF CAPCE

CapTM_Ove� CAPOF CAPOE

ADC EOC

CapTM_C�p

18HLVD LVDF LVDE

TM0 A TM0AF TM0AE

TM0 P TM0PF TM0PE

TM1 A TM1AF TM1AE

TM1 P TM1PF TM1PE

TM� A TM�AF TM�AE

TM� P TM�PF TM�PE

Multi-Fun�tion 0 EMI

EMI

EMI

EMI

EMI

EMI

EMI

EMI

EMI

EMI

�CHEMI

Interrupt Structure

Rev. 1.10 150 De�e��e� �1� �01� Rev. 1.10 151 De�e��e� �1� �01�


External Interrupt 0Theexternalinterrupt0,alsoknownastheHallSensorinterrupt, isaMulti-functionInterrupt.Itiscontrolledbysignaltransitionsonthepins,HallSensorinputpins,H1,H2andH3.Anexternalinterrupt requestwill takeplacewhen theexternal interrupt request flag,HALAF,HALBForHALCFisset,whichwilloccurwhenatransition,appearsontheexternalinterruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheMulti-functioninterruptcontrolledbit,HALLEmustfirstbeset.WhentheMulti-functioninterruptcontrolledbitHALLEisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecall tooneoftheMulti-functioninterruptvectorswill takeplace.Whentheinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterruptsandtherelatedMulti-Functionrequest flagHALLF,willbeautomatically reset,but theMulti-function interrupt request flags,HALAF,HALBF,HALCF,mustbemanuallyclearedbytheapplicationprogram.

External Interrupt 1Theexternalinterrupt1iscontrolledbysignaltransitionsonthepinNFIN.Anexternalinterruptrequestwill takeplacewhentheexternal interruptrequestflag,INT1F, isset,whichwilloccurswhena transitionappearson theexternal interruptpin.Toallow theprogramtobranch to itsrespective interruptvectoraddress, theglobal interruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INT1E,mustfirstbeset.Whentheinterruptisenabled, thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,INT1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinswillremainvalidevenifthepinisusedasanexternalinterruptinput.

Comparator InterruptThecomparatorinterruptiscontrolledbytheinternalcomparator0.Acomparatorinterruptrequestwill takeplacewhenthecomparator interruptrequestflag,C0F,isset,asituationthatwilloccurwhenthecomparatoroutputchangesstate.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andcomparatorinterruptenablebit,C0E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandthecomparatorinputsgenerateacomparatoroutputtransition,asubroutinecalltothecomparatorinterruptvector,willtakeplace.Whentheinterruptisserviced,thecomparatorinterruptrequestflag,C0F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Time Base InterruptThefunctionoftheTimeBaseInterruptistoprovideregulartimesignalintheformofaninternalinterrupt. It iscontrolledby theoverflowsignal fromits timerfunction.Whenthishappens itsinterruptrequestflag,TBFwillbeset.Toallowtheprogramtobranchtoitsinterruptvectoraddress,theglobal interruptenablebit,EMIandTimeBaseenablebit,TBE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflow,asubroutinecalltoitsvectorlocationwill takeplace.Whenthe interrupt isserviced, the interrupt request flag,TBF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.ItsclocksourceoriginatesfromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.

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TBC registerBit 7 6 5 4 3 2 1 0

Na�e TBON TBCK TB1 TB0 — — — —R/W R/W R/W R/W R/W — — — —POR 0 0 1 1 — — — —

Bit7 TBON:TBControl0:Disable1:Enable

Bit6 TBCK:SelectfTBClock0:fTBC1:fSYS/4

Bit5~4 TB1~TB0:SelectTimeBaseTime-outPeriod00:4096/fTB

01:8192/fTB

10:16384/fTB

11:32768/fTB


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Time Base Interrupt

Multi-function InterruptWithinthisdevicearefiveMulti-functioninterrupts.Unliketheotherindependentinterrupts,theseinterruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheHallSensorinterrupts,A/Dinterrupts,PWMModuleinterrupts,CAPTMInterrupts,TMInterrupts.

AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,HALLFandMF1F~MF4Fareset.TheMulti-functioninterruptflagswillbesetwhenanyoftheirincludedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterrupt isenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupts,namelytheHallSensor interrupts,A/Dinterrupts,PWMModule interrupts,CAPTMInterrupts,TMInterrupts,willnotbeautomatically resetandmustbemanually resetby theapplicationprogram.

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A/D Converter InterruptTheA/DConverterhastwointerrupts.AllofthemarecontainedinMulti-functioninterrupt.Theone iscontrolledby the terminationofanA/Dconversionprocess.AnA/DConverter interruptrequestwilltakeplacewhentheA/DConverterInterruptrequestflag,ALIMF,isset,whichoccurswhentheA/Dconversionprocessfinishes.TheotheriscontrolledbytheADCHVE/ADCLVEbitintheADCR1registerandthevalueintheADLVDH/ADLVDLandADHVDH/ADHVDLboundarycontrolregisters.AnA/DConverterInterruptrequestwilltakeplaceafterEOCcomparing.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,AEOCEorALIME,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/DconversionprocesshasendedorafterEOCcomparingasubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,AEOCForALIMF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

PWM Module InterruptsThePWMModulehasfourinterrups.AllofthemarecontainedinMulti-functioninterrupt,whichisknownasPWMDnandPWMP.TheyaretheDutyorthePeriodmachingofthePWMModule.APWMinterruptrequestwilltakeplacewhenthePWMinterruptrequestflag,PWMDnForPWMPF,isset,whichoccurswhenthePWMDutyorPWMPeriodmatches.Whentheinterruptisenabled,thestackisnotfullandPWMDutyorPWMPeriodmaches,asubroutinecalltothisvectorlocationwilltakeplace.Whentheinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableother interruptsand therelatedMulti-Functionrequest flagwillbeautomatically reset,but theinterruptrequestflag,PWMDnForPWMPF,mustbemanuallyclearedbytheapplicationprogram.

CAPTM Module InterruptTheCAPTMModulehas two interrupts.Allof themarecontainedwithin theMulti-functionInterrupt,whichareknownasCapTM_OverandCapTM_Cmp.ACAPTMInterruptrequestwilltakeplacewhentheCAPTMInterruptsrequestflag,CAPOForCAPCF,isset,whichoccurswhenCAPTMcaptureoverflowsorcomparemaches.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheCAPTMInterruptenablebit,andMuti-functioninterruptenablebit,mustfirstbeset.Whentheinterrupt isenabled, thestackisnotfullandCAPTMcaptureoverflowsorcomparematches,asubroutinecall totherespectiveMulti-functionInterruptvector,will takeplace.WhentheCAPTMInterruptisserviced,theEMIbitwillbeautomaticallycleared todisableother interrupts,howeveronly theMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheCAPOFandCAPCFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

TM InterruptTheCompactandStandardTypeTMshave two interruptseach.Allof theTMinterruptsarecontainedwithin theMulti-functionInterrupts.Foreachof theCompactTypeTMandStandardTypeTMsthereare twointerruptrequest flagsTnPFandTnAFand twoenablebitsTnPEandTnAE.ATMinterruptrequestwilltakeplacewhenanyoftheTMrequestflagsisset,asituationwhichoccurswhenaTMcomparatorPorAmatchsituationhappens.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,respectiveTMInterruptenablebit,andrelevantMulti-functionInterruptenablebit,MFnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecalltotherelevantMulti-functionInterruptvectorlocations,willtakeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

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EEPROM InterruptAnEEPROMInterruptwill takeplacewhentheEEPROMInterruptrequestflag,EPWF, isset,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMIandEEPROMInterruptenablebit,EPWE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveEEPROMInterruptvector,willtakeplace.WhentheEEPROMinterruptisserviced,theinterruptrequestflag,EPWF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts

LVD InterruptAnLVDInterruptrequestwilltakeplacewhentheLVDInterruptrequestflag,LVDF,isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andLowVoltageInterruptenablebit,LVDE,mustfirstbeset.Whentheinterruptisenabled, thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheLVDInterruptvector,willtakeplace.WhentheEEPROMinterruptisserviced,theinterruptrequestflag,LVDF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

I2C InterruptAI2CInterruptrequestwilltakeplacewhentheI2CInterruptrequestflag,IICF,isset,whichoccurswhenabyteofdatahasbeenreceivedortransmittedbytheI2Cinterface.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheSerialInterfaceInterruptenablebit,IICE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandabyteofdatahasbeentransmittedorreceivedbytheI2Cinterface,asubroutinecalltotherespectiveInterruptvector,willtakeplace.WhentheI2CInterfaceInterruptisserviced,theinterruptrequest flag, IICF,willbeautomatically resetand theEMIbitwillbecleared todisableotherinterrupts.

Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageorcomparatorinputchangemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremust thereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

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Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptservice routine is executed, asonly theMulti-function interrupt request flags,HALLFandMF1F~MF4F,willbeautomaticallycleared,theindividualrequestflagforthefunctionneedstobeclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe"CALL"instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

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Low Voltage Detector – LVDThedevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenablesthedevicetomonitorthepowersupplyvoltage,VDD,andprovidesawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebitsinthisregister,VLVD2~VLVD0,areusedtoselectafixedvoltagebelowwhichalowvoltageconditionwillbedetemined.Alowvoltageconditionis indicatedwhentheLVDObit isset. IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbitisusedtocontroltheoverallon/offfunctionofthelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebit tozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC RegisterBit 7 6 5 4 3 2 1 0

Na�e — — LVDO LVDEN — VLVD� VLVD1 VLVD0R/W — — R R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetect1:LowVoltageDetect

Bit4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable

Bit3 Unimplemented,readas"0"Bit2~0 VLVD2 ~ VLVD0:SelectLVDVoltage

000:3.6V001:3.6V010:3.6V011:3.6V100:3.6V101:3.6V110:3.6V111:3.6V

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LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasavoltageof3.6V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatingalowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.Whenthedeviceispowereddownthelowvoltagedetectorwillremainactiveif theLVDENbit ishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

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LVD Operation

TheLowVoltageDetectoralsohasitsowninterruptwhichiscontainedwithinoneoftheMulti-functioninterrupts,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.WhenthedeviceispowereddowntheLowVoltageDetectorwillremainactiveif theLVDENbit ishigh.Inthiscase, theLVDFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPorIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVDFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPorIDLEMode.

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Application Circuits

Three Phase BLDC Hall Sensor Solution (VB=24V)

PC0/TP0_0/GAT

PC1/TP0_1/GABPC�/TP1_0/GBT

PC3/TP1_1/GBB

PA1/TCK3/AN�/AP

PA3/TCK1/H1/C1P

PA7/NFIN/AN1



HT66FM5230(16NSOP)

VDD/AVDD

+5V

VSS/AVSS

PC4/TP�_0/GCT

PC5/TP�_1/GCB

Speed Cont�ol

Hall O/P

GND

VOVI 7815+15VVB=�4V

Gate D�ive�(T�. x1�)

+�4V

Powe� MOSSwit�h

(P�804x3)

+�4V

VB

RS

Moto�

VB Volt. Det.

Speed Out

GND

VOVI 7805+5V

+15V

PA4/H�/[SDA]/C�P/[C1N]PA5/H3/[SCL]/C3P

PA�/[C1N]/AN0

Three Phase BLDC Hall Sensorless Solution (VB=24V)

PC0/TP0_0/GAT


PC3/TP1_1/GBB

PA1/TCK�/AN�/AP

PA3/TCK1/H1/C1P

PA7/NFIN/AN1

PB0/HAO/AN3

PB1/CTIN/HBO/AN4

HT66FM5230(20SSOP)

VDD/AVDD

+5V

VSS/AVSS

PC4/TP�_0/GCT

PC5/TP�_1/GCB

Speed Cont�ol

GND

VOVI 7815+15VVB=�4V

Gate D�ive�(T�. x1�)

+�4V

Powe� MOSSwit�h

(P�804x3)

+�4V

VB

RS

Moto�

VB Volt. Det.

Speed Out

GND

VOVI 7805+5V

+15V

Senso�less

Bias and RC filte� �i��uit

Mot

o�

U/V

/W PB3/TCK1/C1N

PB�/HCO/AN5



U/V/W

PA4/H�/[SDA]/C�P/[C1N]PA5/H3/[SCL]/C3P

PA�/[C1N]/AN0

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Single Phase BLDC Hall Sensor Solution (VB=12V)

PC0/TP0_0/GAT


PC3/TP1_1/GBB

PA1/TCK�/AN�/AP

PA3/TCK1/H1/C1P

PA7/NFIN/AN1



HT66FM5230(16NSOP)

VDD/AVDD

+5V

VSS/AVSS

Speed Cont�ol

GND

VOVI 7805

Gate D�ive�(T�. x�)

Powe� MOS(H-B�idge)

RS

VB Volt. Det.

Speed Out

+5V

+1�V

VB

VBS

+1�V

Hall

+5V

PC4/TP�_0/GCT

PC5/TP�_1/GCB

+1�V

PA4/H�/[SDA]/C�P/[C1N]

PA�/[C1N]/AN0

PA5/H3/[SCL]/C3P

Single Phase BLDC Hall Sensorless Solution (VB=12V)

PC0/TP0_0/GAT


PC3/TP1_1/GBB

PA3/TCK1/H1/C1P

PA7/NFIN/AN1

PB0/HAO/AN3

PB1/CTIN/HBO/AN4

HT66FM5230(20SSOP)

VDD/AVDD

+5V

VSS/AVSS

Speed Cont�ol

VB Volt. Det.

Speed Out PB3/TCK0/C1N

PB�/HCO/AN5



GND

VOVI 7805+5V

VB

VBS

+1�V

OUT1

+5V

OUT0

Gate D�ive�(T�. x�)

+1�V

Powe� MOS(H-B�idge)

+1�V

PA1/TCK�/AN�/AP

RS

PC4/TP�_0/GCT

PC5/TP�_1/GCB

OUT1

OUT0

PA�/[C1N]/AN0

PA4/H�/[SDA]/C�P/PC1N]

PA5/H3/[SCL]/C3P

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Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

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Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

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Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A�[�] Add Data Me�o�y to ACC 1 Z� C� AC� OVADDM A�[�] Add ACC to Data Me�o�y 1Note Z� C� AC� OVADD A�x Add i��ediate data to ACC 1 Z� C� AC� OVADC A�[�] Add Data Me�o�y to ACC with Ca��y 1 Z� C� AC� OVADCM A�[�] Add ACC to Data �e�o�y with Ca��y 1Note Z� C� AC� OVSUB A�x Su�t�a�t i��ediate data f�o� the ACC 1 Z� C� AC� OVSUB A�[�] Su�t�a�t Data Me�o�y f�o� ACC 1 Z� C� AC� OVSUBM A�[�] Su�t�a�t Data Me�o�y f�o� ACC with �esult in Data Me�o�y 1Note Z� C� AC� OVSBC A�[�] Su�t�a�t Data Me�o�y f�o� ACC with Ca��y 1 Z� C� AC� OVSBCM A�[�] Su�t�a�t Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y 1Note Z� C� AC� OVDAA [�] De�i�al adjust ACC fo� Addition with �esult in Data Me�o�y 1Note CLogic OperationAND A�[�] Logi�al AND Data Me�o�y to ACC 1 ZOR A�[�] Logi�al OR Data Me�o�y to ACC 1 ZXOR A�[�] Logi�al XOR Data Me�o�y to ACC 1 ZANDM A�[�] Logi�al AND ACC to Data Me�o�y 1Note ZORM A�[�] Logi�al OR ACC to Data Me�o�y 1Note ZXORM A�[�] Logi�al XOR ACC to Data Me�o�y 1Note ZAND A�x Logi�al AND i��ediate Data to ACC 1 ZOR A�x Logi�al OR i��ediate Data to ACC 1 ZXOR A�x Logi�al XOR i��ediate Data to ACC 1 ZCPL [�] Co�ple�ent Data Me�o�y 1Note ZCPLA [�] Co�ple�ent Data Me�o�y with �esult in ACC 1 ZIncrement & DecrementINCA [�] In��e�ent Data Me�o�y with �esult in ACC 1 ZINC [�] In��e�ent Data Me�o�y 1Note ZDECA [�] De��e�ent Data Me�o�y with �esult in ACC 1 ZDEC [�] De��e�ent Data Me�o�y 1Note ZRotateRRA [�] Rotate Data Me�o�y �ight with �esult in ACC 1 NoneRR [�] Rotate Data Me�o�y �ight 1Note NoneRRCA [�] Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC 1 CRRC [�] Rotate Data Me�o�y �ight th�ough Ca��y 1Note CRLA [�] Rotate Data Me�o�y left with �esult in ACC 1 NoneRL [�] Rotate Data Me�o�y left 1Note NoneRLCA [�] Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC 1 CRLC [�] Rotate Data Me�o�y left th�ough Ca��y 1Note C

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Mnemonic Description Cycles Flag AffectedData MoveMOV A�[�] Move Data Me�o�y to ACC 1 NoneMOV [�]�A Move ACC to Data Me�o�y 1Note NoneMOV A�x Move i��ediate data to ACC 1 NoneBit OperationCLR [�].i Clea� �it of Data Me�o�y 1Note NoneSET [�].i Set �it of Data Me�o�y 1Note NoneBranchJMP add� Ju�p un�onditionally � NoneSZ [�] Skip if Data Me�o�y is ze�o 1Note NoneSZA [�] Skip if Data Me�o�y is ze�o with data �ove�ent to ACC 1Note NoneSZ [�].i Skip if �it i of Data Me�o�y is ze�o 1Note NoneSNZ [�].i Skip if �it i of Data Me�o�y is not ze�o 1Note NoneSIZ [�] Skip if in��e�ent Data Me�o�y is ze�o 1Note NoneSDZ [�] Skip if de��e�ent Data Me�o�y is ze�o 1Note NoneSIZA [�] Skip if in��e�ent Data Me�o�y is ze�o with �esult in ACC 1Note NoneSDZA [�] Skip if de��e�ent Data Me�o�y is ze�o with �esult in ACC 1Note NoneCALL add� Su��outine �all � NoneRET Retu�n f�o� su��outine � NoneRET A�x Retu�n f�o� su��outine and load i��ediate data to ACC � NoneRETI Retu�n f�o� inte��upt � NoneTable ReadTABRD [�] Read ta�le to TBLH and Data Me�o�y �Note NoneTABRDL [�] Read ta�le (last page) to TBLH and Data Me�o�y �Note NoneMiscellaneousNOP No ope�ation 1 NoneCLR [�] Clea� Data Me�o�y 1Note NoneSET [�] Set Data Me�o�y 1Note NoneCLR WDT Clea� Wat�hdog Ti�e� 1 TO� PDFCLR WDT1 P�e-�lea� Wat�hdog Ti�e� 1 TO� PDFCLR WDT� P�e-�lea� Wat�hdog Ti�e� 1 TO� PDFSWAP [�] Swap ni��les of Data Me�o�y 1Note NoneSWAPA [�] Swap ni��les of Data Me�o�y with �esult in ACC 1 NoneHALT Ente� powe� down �ode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.

3.For the"CLRWDT1"and"CLRWDT2"instructions theTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDF flagsareclearedafterboth "CLRWDT1"and"CLRWDT2"instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

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CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

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RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

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RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

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SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRD [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

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Min. Nom. Max.A — 0.�3� BSC —B — 0.154 BSC —C 0.008 — 0.01� C’ — 0.341 BSC —D — — 0.0�9 E — 0.0�5 BSC —F 0.004 — 0.0098 G 0.01� — 0.05 H 0.004 — 0.01 α 0° — 8°

SymbolDimensions in mm

Min. Nom. Max.A — �.000 BSC —B — 3.900 BSC —C 0.�0 — 0.30 C’ — 8.��0 BSC —D — — 1.75 E — 0.�35 BSC —F 0.10 — 0.�5 G 0.41 — 1.�7 H 0.10 — 0.�5 α 0° — 8°

Rev. 1.10 17� De�e��e� �1� �01� Rev. 1.10 PB De�e��e� �1� �01�


Copy�ight© �01� �y HOLTEK SEMICONDUCTOR INC.

The info��ation appea�ing in this Data Sheet is �elieved to �e a��u�ate at the ti�e of pu�li�ation. Howeve�� Holtek assu�es no �esponsi�ility a�ising f�o� the use of the specifications described. The applications mentioned herein are used solely fo� the pu�pose of illust�ation and Holtek �akes no wa��anty o� �ep�esentation that su�h appli�ations will �e suita�le without fu�the� �odifi�ation� no� �e�o��ends the use of its p�odu�ts fo� appli�ation that �ay p�esent a �isk to hu�an life due to �alfun�tion o� othe�wise. Holtek's p�odu�ts a�e not autho�ized fo� use as ��iti�al �o�ponents in life suppo�t devi�es o� syste�s. Holtek �ese�ves the �ight to alte� its products without prior notification. For the most up-to-date information, please visit ou� we� site at http://www.holtek.�o�.

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