A VHDL TUTORIAL

Developed by

Syed Yawar Ali Shah

Supervisor: Dr. Asim J. Alkhalili

October, 1999

Department of Electrical and Computer Engineering

Concordia University, Montreal

TABLE OF CONTENTS

1- Introduction ................................................................................................................................ 2

2- Setting up the environment to run the Synopsys VHDL simulation tools .................................. 2

3- VHDL: Basic Language Organization ....................................................................................... 3

4- Examples .................................................................................................................................... 4

4.1- Full Adder ............................................................................................................................ 4

4.1.1- Structural Description ................................................................................................ 4

4.1.2- Behavioral Descriptions ........................................................................................... 15

4.1.3- Stimulator ................................................................................................................. 17

4.1.4- Test Bench for Full Adder ........................................................................................ 19

4.2- Register .............................................................................................................................. 21

4.2.1- Structural Description .............................................................................................. 21

4.2.2- Mixed Description .................................................................................................... 27

4.2.3- Behavioral Description ............................................................................................. 29

4.3- Counter ............................................................................................................................. 31

4.3.1- BCD Counter ............................................................................................................ 31

4.3.2- 3 Digit Counter ......................................................................................................... 38

4.4- Multiplier ........................................................................................................................... 43

4.4.1- Unsigned 4x4 Bit Multiplier .................................................................................... 43

4.4.2- Unsigned 8x8 Bit Multiplier .................................................................................... 44

4.4.3- Signed 8x8 Bit Multiplier ......................................................................................... 45

1- INTRODUCTION:

This tutorial deals with the basic structure of VHDL code, analysis of VHDL source files and VHDL simulation using the Synopsys VHDL System Simulator (VSS).

2- SETTING UP THE ENVIRONMENT TO RUN THE SYNOPSYS VHDL SIMULATION TOOLS:[1]

Section 2 will help you in setting up the environment , to run the Synopsys VHDL simulation tools. Section 3 gives some idea of VHDL basic language organization. Section 4 contains some examples of VHDL coding, starting with a simple combinational circuit, Full Adder, which has been constructed using different VHDL modeling styles. Next some advance aspects of VHDL have been introduced by constructing different VHDL descriptions of an 8 bit Register. In the next example, codes for a BCD Counter have been generated; which are upgraded to a 3 digit counter. In the end, signed and unsigned Multipliers are designed by using dataflow and algorithmic implementation styles.

2- SETTING UP THE ENVIRONMENT TO RUN THE SYNOPSYS VHDL SIMULATION TOOLS:[1]

To set up your environment refer to the following Tutorial : "Digital Logic Synthesis Using Synopsys and XilinxA Tutorial By Ted Obuchowicz" It can found in http://www.ece.concordia.ca -->documentation-->Other Tutorials-->Tutorials

A basic working knowledge of the UNIX operating system (using text editors, creating directories, copying files, printing, etc.) is needed to work on the tutorial.

Once your environment is set up you may follow the tutorial for for the analysis, simulation and elaboration of your VHDL code.

3- VHDL: BASIC LANGUAGE ORGANIZATION

Design entity is the basic construct in VHDL for modeling a digital system. A design entity can represent an arbitrarily complex digital system, ranging from a logic gate to an entire network of computers.

Design entity is composed of two parts: Interface and Body

Interface is denoted by the keyword entity.

Body is denoted by the keyword architecture

Interface defines the boundary between the design entity and the environment, such as signals that flow into and out of design entity. Body describes how the design operates (how the outputs respond to inputs). Body is separated from design entity Interface to allow different implementations of the same design entity. Different implementations are possible for the same design using different modeling styles.

There are two basic VHDL modeling styles: Structural and Behavioral.

Structural modeling (Structural Architectures) implicitly defines the input/output functions by describing components and their interconnections.

Behavioral modeling (Behavioral Architectures) explicitly defines the input/output functions by describing signal transformations.

There are two general kinds of Behavioral modeling: Dataflow modeling and Algorithmic modeling.

Dataflow modeling uses concurrent statements whereas Algorithmic modeling uses sequential statements. Algorithmic architecture is composed of one or more concurrent processes. The statements inside each process executes sequentially.

4- EXAMPLES

4.1- FULL ADDER

VHDL code for full adder is generated using three different modeling styles i.e Structural, Data-flow and Algorithmic. Thus three different architectures are written for the same design entity FULL_ADDER.

4.1.1- Structural Description:

In Structural description, Structural architecture of the design entity describes it in terms of interconnected components. Each component may be in turn described as interconnected subcomponents or behavioral in terms of built-in functions.

The first step in writing VHDL code for structural architectures is to write the codes for components in separate design entities and analyze them. Analysis creates simulation files in WORK directory. Using those files in the configuration commands of the design code of parent circuit, allows us to use those design entities as components in our parent circuit.

Fig 1: Full Adder Circuit

In the generation of the structural code for Full adder, we will generate VHDL code of all three components i.e XOR, AND and OR gates as shown in the figure 1, in the separate design entities.

4.1.1.1- XOR gate:

Using any text editor (xedit, emacs, etc.), write the VHDL code of XOR gate as given below and save it in file XOR2.vhd

entity XOR_2 is

port (

A, B : in BIT;

Z : out BIT);

end XOR_2;

architecture DATA_FLOW of XOR_2 is

begin

Z Full Fit from the top menu bar. Give new values and run the simulator for another time period. Figure 6 shows the result of the simulation.

You can print the results by selecting File -> Print. Click on Print to File in the Print Options window and then enter a name for the file with extension .ps, say XOR_SIM.ps. Click OK.

Fig 5: Synopsys Waveform Viewer

Fig 6: Simulation Result of XOR_2

At the UNIX prompt, enter:

% lpr -PPrinterName XOR_SIM.ps

Now exit the Synopsys VHDL Debugger (Vhdldbx) window by clicking on Execute -> Quit.

4.1.1.4- Elaboration:

Elaborate command is used to build a design from a VHDL entity and architecture or a VHDL configuration. To elaborate a design, enter the following command from your UNIX prompt:

% design_analyzer

Synopsys Design Analyzer window will open as shown in figure 7.

Fig 7: Synopsys Design Analyzer

Click on File -> Analyze. Analyze File window will appear. Select XOR2.vhd and click OK. Analyze window will appear. After some time if you receive a 1 at the end of analysis, its mean your analysis is successful. If you do not receive a 1, then there are some errors in your VHDL code. Go back and correct them.

From Synopsys Design Analyzer window, click on File -> Elaborate. Elaborate design window will appear as shown in figure 8. Select library WORK. Two designs will be displayed: XOR_2(ALGORITHM) and XOR_2(DATA_FLOW). Select XOR_2(ALGORITHM) and click OK. You will see entity name (XOR_2) with a box in the center of Synopsys Design Analyzer window. Double click on it. You will see XOR_2 gate with its input/output ports. Double click on it and you will see schematic diagram of XOR gate as shown in figure 9. Follow the same steps for XOR_2(DATA_FLOW). The gate level schematic diagram is shown in Figure 10. It can be seen that the DATA_FLOW architecture is implemented by a built-in XOR gate.

Fig 8: Elaborate Design

Fig 9: Synopsys Design Analyzer (ALGORITHM design of XOR_2)

Fig 10: Data_Flow Design of XOR_2

4.1.1.5- AND gate:

Generate and save the VHDL code of AND gate, as given below, in file AND2.vhd

entity AND_2 is

port (

A, B : in BIT;

Z : out BIT);

end AND_2;

architecture DATA_FLOW of AND_2 is

begin

Z SUM);

A1 : AND_2 port map (A => S1, B => C_IN, Z => S2);

A2 : AND_2 port map (A => A_IN, B => B_IN, Z => S3);

O1 : OR_2 port map (A => S2, B => S3, Z => C_OUT);

end STRUCTURE;

Components are first declared and then connected together by using port map command. Only ALGORITHM architectures of XOR_2, AND_2 and OR_2 entities are used in configuration specifications. You can also select DATA_FLOW architectures by just replacing DATA_FLOW with ALGORITHM in the configuration specification commands. Analyze the code and then elaborate it. You will see the design as shown in figure 11.

Fig 11: Structural Design of Full Adder

4.1.2- Behavioral Descriptions:

Two more VHDL descriptions (Data-flow and Algorithmic) of Full Adder are shown below. Save it in file FULL_ADDER_BEHAV.vhd.

entity FULL_ADDER is

port (

A_IN, B_IN, C_IN : in BIT;

SUM, C_OUT :out BIT);

end FULL_ADDER;

architecture DATA_FLOW of FULL_ADDER is

-- Signal declarations

signal S1, S2, S3 : BIT;

begin

S1