Basics of DACs

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    BLOCK DIAGRAM OF A DIGITAL-ANALOG CONVERTER

    b1 is the most significant bit (MSB)

    The MSB is the bit that has the most (largest) influence on the analog output

    bNis the least significant bit (LSB)

    The LSB is the bit that has the least (smallest) influence on the analog output

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    _____________________________________________________________________________________ CMOS Analog IC Design

    _____________________________________________________________________________________________________ Page 10.1-1

    Chapter 10 - DA and AD Converters (6/4/01) _ P.E. Allen, 2001

    10.1 - CHARACTERIZATION OF DIGITAL-ANALOG CONVERTERS

    STATIC CHARACTERISTICS

    OUTPUT-INPUT CHARACTERISTICS

    Ideal input-output characteristics of a 3-bit DAC

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    _____________________________________________________________________________________ CMOS Analog IC Design

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    Chapter 10 - DA and AD Converters (6/4/01) _ P.E. Allen, 2001

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    _____________________________________________________________________________________CMOS Analog IC Design

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    Chapter 10 - DA and AD Converters (6/4/01) _ P.E. Allen, 2001

    DEFINITIONS

    Resolutionof the DAC is equal to the number of bits in the applied digital input word.

    The full scale (FS):

    FS = Analog output when all bits are 1 - Analog output all bits are 0VREF

    FS = (VREF- 2N) - 0 = VREF 1 - 12N

    Full scale range(FSR) is defined as

    FSR =lim

    N FS =

    Quantization Noiseis the inherent uncertainty in digitizing an analog value with a finite resolution converter.

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    _____________________________________________________________________________________ CMOS Analog IC Design

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    Chapter 10 - DA and AD Converters (6/4/01) _ P.E. Allen, 2001

    max

    max FSR

    /2

    6

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    CMOS Analog IC Design ______________________________________________________________________________ Page 10.1-4

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    EVEN MORE DEFINITIONS

    Effective number of bits (ENOB)can be defined from the above as

    ENOB=SNRActual-1.76

    6.02where SNRActualis the actual SNRof the converter.

    Comment:

    TheDR is the amplitude range necessary to resolveNbits regardless of the amplitude of the output voltage.

    However, when referenced to a given output analog signal amplitude, theDR required must include 1.76 dB more

    to acount for the presence of quantization noise.

    Thus, for a 10-bit DAC, theDRis 60.2dB and for a full-scale, rmsoutput voltage, the signal must be approximately

    62dB above whatever noise floor is present in the output of the DAC.

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    CMOS Analog IC Design _______________________________________________________________________________Page 10.1-5

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    OFFSET AND GAIN ERRORS

    An offset erroris a constant difference between the actual finite resolution characteristic and the infinite

    resolution characteristic measured at any vertical jump.

    Again erroris the difference between the slope of an actual finite resolution and an infinite resolution

    characteristic measured at the right-most vertical jump.

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    7

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    CMOS Analog IC Design ____________________________________________________________________________ Page 10.1-12

    Chapter 10 - DA and ADConverters (6/4/01) __ P.E. Allen, 2001

    INFLUENCE OF THE OP AMP GAINBANDWIDTH

    Single-pole response:

    vout(t) =ACL[1 - e-Ht]vin(t)

    whereACL= closed-loop gain

    R 1 C2 H= GB R1+R2 or GB

    C1+C2

    To avoid errors in DACs (and ADCs), vout(t)must be within 0.5LSBof the final value by the end of the conversion

    time.

    Multiple-pole response:

    Typically the response is underdamped like the following (see Appendix C of text).

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    CMOS Analog IC Design ____________________________________________________________________________ Page 10.1-13

    Chapter 10 - DA and AD Converters(6/4/01) __ P.E. Allen, 2001

    =

    2) = 0.693

    3.141 0.693 = 1.986

    - 2

    GB

    Assume that a DAC uses a switched capacitor noninverting amplifier with = and = 1MHz. Find the

    conversion time of an 8-bit DAC if is 1V.

    From the analysis in Secs. 9.2 and 9.3, we know that

    + = (2(0.5)(10 ) =3.141x10

    and = 1. Assume that the ideal output is equal to .Therefore the value of the output voltage which is

    0.5LSB of is

    = 1 - - H

    or

    2 = H

    Solving for gives

    =

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    CMOS Analog IC Design ____________________________________________________________________________ Page 10.1-12

    Chapter 10 - DA and AD Converters(6/4/01) _ P.E. Allen, 2001

    TESTING OF DACs

    INPUT-OUTPUT TEST

    Test setup:

    Comments:

    Sweep the digital input word from 000...0 to 111...1.

    The ADC should have more resolution by at least 2 bits and be more accurate than the errors of the DAC

    INL will show up in the output as the presence of 1s in any bit.

    If there is a 1 in the Nth bit, theINLis greater than 0.5LSB

    DNLwill show up as a change between each successive digital error output.

    The bits which are greater thanNin the digital error output can be used to resolve the errors to less than 0.5LSB

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    SPECTRAL TEST

    Test setup:

    Comments:

    Digital input pattern is selected to have a fundamental frequency which has a magnitude of at least 6NdB above its

    harmonics.

    Length of the digital sequence determines the spectral purity of the fundamental frequency.

    All nonlinearities of the DAC (i.e.INLandDNL) will cause harmonics of the fundamental frequency

    The THD can be used to determine the SNR dB range between the magnitude of the fundamental and the THD. ThisSNR should be at least 6NdB to have anINLof less than 0.5LSBfor an ENOB ofN-bits.

    Note that the noise contribution of VREFmust be less than the noise floor due to nonlinearities.

    If the period of the digital pattern is increased, the frequency dependence ofINLcan be measured.