Bao Cao Tot Nghiep Hieu Bac 040608

8/8/2019 Bao Cao Tot Nghiep Hieu Bac 040608

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I HC BCH KHOA H NI

KHOA IN B MN IU KHIN T NG

THIT KH THNG X L NH S TRNNN FPGA

Nhm sinh vin thc hin: Ng Hi Bc Trung Hiu

Lp iu khin t ng 1 K48

Gio vin hng dn: Ts. Lu Hng Vit

H NI - 2008


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Li cm n

Trc ht, chng em xin gi li cm n su sc n thy gio TS. LuHng Vit, ngi gip rt nhiu v nh hng nghin cu, thit b thnghim phc v cho nghin cu.

Chng em xin chn thnh cm n cc thy c gio ging dy chngem, c bit l cc thy c gio trong B mn iu khin t ng Khoain, TS. Phm Ngc Nam Ph Trng b mn in t - Tin hc Khoain t Vin Thng Trng i hc Bch Khoa H Ni to iu kingip chng em hon thnh n tt nghip ny.

Xin chn thnh cm n Dave Vanden Bout, k s ca cng ty XESSCorporation tr li tn tnh nhng thc mc ca chng em vKIT XSA-3S1000 v XST-3.0.

V cui cng, chng em xin dnh tt c lng bit n v knh trng su scnht ti bm chng em, nhng ngi sinh thnh, nui dng chng emnn ngi, lo lng, chbo t nhng vic nh nht, to mi iu kincho chng em c sng v hc tp mt cch tt nht vn ti nhng c

m v hoi bo ca mnh.

Mc d rt n lc v cgng hon thnh lun vn tt nghip ny,song chc chn khng thtrnh khi sai st. V vy, chng em rt mong cs chbo ca thy c gio ti tt nghip ny hon thin hn.


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Mc lc

Li cm n.................................................................................................................................................. 2

Mc lc ....................................................................................................................................................... 3

Danh mc cc hnh v trong n tt nghip...................................................................................... 6

M u........................................................................................................................................................ 8

Phn 1 : C s l thuyt x l nh s................................................................................................... 10

1.1. Khi qut vh thng Th gic my tnh v Cm bin th gic........................................10

1.3. Cc thnh phn ca h thng x l nh: .............................................................................16

1.3.1. Thnh phn thu thp nh, Camera v vn nh dng nh..................................16

1.3.2. Thnh phn x l nh .................................................................................................... 17

1.3.2.1. Cc khi nim cbn ca x l nh s................................................................17

1.3.2.2. Cc thut ton x l nh s................................................................................... 18

1.4. Mt sgii php phn cng cho h thng th gic my ...................................................28

FPGA ................................................................................................................................................ 28

DSP Processor .................................................................................................................................28

Mainboard, laptop .........................................................................................................................29

Phn 2 : Khi qut v FPGA v mch pht trin XST 3S1000 ca XESS......................................31

2.1. Gii thiu chung v FPGA v ngn ng VHDL ..............................................................31

2.1.1. Khi nim v ng dng FPGA .................................................................................... 31

2.1.2. Kin trc FPGA...............................................................................................................32

2.1.2.1. Kin trc chung FPGA .......................................................................................... 32

Configurable Logic Blocks (CLBs)...................................................................................... 33

Configurable I/O Blocks .......................................................................................................34

Programmable Interconnect................................................................................................. 34

Mch ng h (Clock Circuitry )......................................................................................... 35

2.1.2.2. So snh gia cu trc nh v cu trc ln .........................................................36

2.1.2.3. So snh gia SDRAM Programming v Anti-fuse programming................36

2.1.2.4. Cu trc FPGA ca Spartan 3............................................................................... 37

2.1.3. Trnh t thit kmt chip ............................................................................................ 38


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Ghi cc c im k thut .....................................................................................................39

Chn cng ngh......................................................................................................................40

Chn mt hng tip cn thit k...................................................................................... 40

Chn cng c tng hp .........................................................................................................40

Thit kchip ...........................................................................................................................41

M phng ci nhn tng quan v thit k...................................................................... 41

Tng hp..................................................................................................................................41

Place and Route ......................................................................................................................41

M phng li tng quan cui cng.................................................................................. 42

Kim tra....................................................................................................................................42

2.1.4. Ngn ng m t phn cng VHDL.............................................................................42

Trnh t thit kmt chp da trn VHDL...........................................................................43

2.2. Gii thiu mch pht trin XST 3S 1000 ca hng XESS................................................44

2.2.1. XSA-3S1000......................................................................................................................45

2.2.2. XST-3.0 (XStend Board)................................................................................................. 46

2.3. Gii thiu hng Xilinx v cc cng c lp trnh: ..............................................................49

Hng Xilinx .....................................................................................................................................49

ISE 9.2 ...............................................................................................................................................49

LogicCore 9.2...................................................................................................................................49

EDK 9.2.............................................................................................................................................50

System Generator 9.2.....................................................................................................................50

Phn 3 : Xy dng h thng x l nh ng trn nn FPGA ..........................................................51

3.1. S cu trc h thng x l nh ng .............................................................................51

3.2. Xy dng h thng thu thp, lu tr, x l v hin th nh ..........................................53

3.2.1. Thnh phn thu thp nh Framegrabber................................................................... 53

3.2.2. Lu d liu t Framegrabber vo SDRAM ..............................................................55

3.2.3. Cc c ch ghi c SDRAM: SDRAM Controller, Dual Port SDRAM................55

SDRAM Controller ....................................................................................................................55

Pipeline Read Operation ......................................................................................................56

Pipeline Write Operation .....................................................................................................56

Dualport Module for the SDRAM Controller ...................................................................... 58


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3.2.4. Image Processing core ................................................................................................... 60

3.2.5. Hin th nh ln VGA: VGA Generator .................................................................... 67

VGA Color Signals ....................................................................................................................67

VGA Signal Timing...................................................................................................................68

Nguyn tc hot ng ca VGA Generator ..........................................................................69

3.2.6. Picoblaze v h thng iu khin trung tm ............................................................71

3.2.6.1. Khi qut PicoBlaze............................................................................................... 71

KCPSM3 Module ...................................................................................................................73

Kt ni vi b nh ROM chng trnh.............................................................................. 73

3.2.6.2. S cu trc ca khi x l trung tm ............................................................75

Thut ton ca chng trnh ................................................................................................. 753.3. Thit kgiao din iu khin h thng.............................................................................76

Chc nng ....................................................................................................................................77

3.4. M phng v kt qu.............................................................................................................77

Phng n m phng .....................................................................................................................77

Kt qu..............................................................................................................................................78

Kt lun .................................................................................................................................................... 79

Ti liu tham kho .................................................................................................................................82


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Danh mc cc hnh v trong n tt nghip

Hnh 1.1 Mt tay my thc hin gp i tng vi s tr gip ca h thng th gicmy tnh

Hnh 1.2 Cc bc c bn ca x l nh s.

Hnh 1.3 Nhng kiu lin kt gia cc im nh.Hnh 1.4 Nhng kiu ng lin kt gia cc im nh.Hnh 1.5 Kt qu ca php lc Gaussian vi ca s 3x3.Hnh 1.6 Kt qu thut ton d bin.Hnh 1.7 Phn ngng theo lc xm.Hnh 1.8 Loi b nhiu v khi phc i tng bng qu trnh lm mnh-lm y.Hnh 1.9 S thut ton gn nhn i tng.Hnh 2.1 Kin trc chung ca FPGA.Hnh 2.2 Mt Logic Block in hnh.Hnh 2.3 Configurable Logic Blocks.

Hnh 2.4 Programmable Interconnect.

Hnh 2.5 Cu trc cc thnh phn ca Spartan 3A.Hnh 2.6 Design Flow.

Hnh 2.7 Qui trnh thit kchip da trn VHDL.Hnh 2.8 KIT XSA-3S1000.

Hnh 2.9 S cu trc ca XSA-3S1000.Hnh 2.10 XST-3.0 Board.

Hnh 2.11 XST-3S1000.

Hnh 3.1 Mt nh cn c x l.Hnh 3.2 S chung ca h thng.Hnh 3.3 Pixel stream waveform.

Hnh 3.4 Framegrabber state machine.

Hnh 3.5 Pipelined Read Operation timing waveforms.

Hnh 3.6 Pipelined Write Operation timing waveforms.

Hnh 3.7 Ghp ni vi SDRAM Controller.Hnh 3.8 Ghp ni dualport vi SDRAM Controller.Hnh 3.9 Xy dng 4 ports SDRAM interface.Hnh 3.10 S khi x l nh.

Hnh 3.11 Khi ghi d liu t read_fifo vo Buffer.


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Hnh 3.12 Khi thut ton x l nh.Hnh 3.13 C ch ghi v c buffer.Hnh 3.14 Khi c d liu t buffer.Hnh 3.15 S khi thanh ghi dch Pixel registerHnh 3.16 Cu trc nhn chp.Hnh 3.17 Cu trc b x l ng cu nh nh phn.Hnh 3.18 Khi gn nhn i tng.Hnh 3.19 VGA Connection.

Hnh 3.20 8 mu c bn.Hnh 3.21 CRT Display Timing Example.

Hnh 3.22 640 x 480 Mode VGA Control Timing.

Hnh 3.23 S khi cu trc ca VGA Generator.Hnh 3.24 S khi cu trc ca PicoBlaze.

Hnh 3.25 S cu trc PicoBlaze Microcontroller.Hnh 3.26 S khi iu khin trung tm v giao tip UART.Hnh 3.27 Giao din iu khin.


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M u

Th gic my l mt lnh vc v ang rt pht trin. Khi nim th gic

my Computer vision c lin quan ti nhiu ngnh hc v hng nghin

cu khc nhau. T nhng nm 1970 khi m nng lc tnh ton ca my tnh

ngy cng tr nn mnh m hn, cc my tnh lc ny c th x l c

nhng tp d liu ln nh cc hnh nh, cc on phim th khi nim v k

thut vth gic my ngy cng c nhc n v nghin cu nhiu hn cho

ti ngy nay.

Th gic my bao gm l thuyt v cc k thut lin quan nhm mc ch

to ra mt h thng nhn to c thtip nhn thng tin t cc hnh nh thu

c hoc cc tp d liu a chiu.

Ngy nay, ng dng ca th gic my tr nn rt rng ln v a dng,

len li vo mi lnh vc t qun s, khoa hc, v tr, cho n y hc, sn xut,

v t ng ha ta nh.

Mc ch ca n ny l nghin cu cc khi nim c bn ca Th gicmy tnh v x l nh s. ng thi trn c s , chng em xy dng mt

h thng cm bin th gic trn nn phn cng vi mch kh trnh FPGA. Cm

bin ny thc hin cc chc nng c s ca mt cm bin th gic : l tip

nhn thng tin t hnh nh thu c x l v phc v cho cc qu trnh

phn tch cao hn.


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Phn 1 : C s l thuyt x l nh s

1.1. Khi qut v h thng Th gic my tnh v Cm bin th gic

Theo nh ngh a t [1] : H thng th gic - bao gm c th gic my(machine vision) v th gic my tnh (computer vision)- l nhng h thngtip nhn thng tin t cc cm bin th gic (vision sensor) vi mc ch chophp my mc a ra nhng quyt nh thng minh.

Th gic my tnh l mt ngnh khoa hc mi pht trin. Mc d cnhng ng dng ca x l nh strong nhng thp nin u ca thk XXvo mt slnh vc, nhng phi n nhng nm 1970, nhng nghin cu v

lnh vc ny mi c bt u khi my tnh c thqun l cc qu trnhx l mt lng ln d liu nh cc nh s.

Lnh vc nghin cu ca th gic my rt rng, v c im chung l ccbi ton vth gic my tnh u khng c mt bi chung v cch gii duynht. Mi gii php gii quyt vn u c mt kt qu nht nh chonhng trng hp c th. Ta c th thy s tng quan gia Computervision vi cc lnh vc khc nh sau:


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Qua s trn, ta c th thy th gic my tnh v th gic my c linquan n rt nhiu ngnh nh t ng iu khin, x l nh s, quang hc,sinh hc, ton hc, my hc. v Tr tu nhn to. S kt hp ca nhngngnh ny to cho Th gic my tnh mt kh nng ng dng ht sc rng

ln trong mi lnh vc ca khoa hc, sn xut v i sng. C thlit k mts ng dng ca th gic my tnh nh sau :

iu khin tin trnh (v d: trong cc robot cng nghip, hay cc thit b,xe t hnh).

Pht hin s kin (v d: cc thit b gim st)

T ng ha ta nh.

M hnh ho i tng (v d: qu trnh kim tra trong mi trng cngnghip, x l nh trong y hc).

Tng tc (ng vai tr lm u vo cho thit b trong qu trnh tngtc gia ngi v my).

Nhn dng

Qun s.

Trong l nh vc iu khin tin trnh, th gic my tnh ng vai tr cbit quan trng nh mt cm bin v tr cho robot cng nghip hoc xe thnh.

Trong h thng my CNC, hoc cc dy chuyn cng ngh, cc cm binth gic thu thp d liu nh v i tng cng nghip, x l v tch itng ra khi nh. Sau khi tch i tng, h thng th gic my tnh toncc c trng ca i tng, nh v tr, hng, gip cnh tay my carobot cng nghip thao tc chnh xc vic gp hoc gia cng i tng.

Vi nhng h thng th gic c tch hp cc camera c phn gii ln,c lp trnh chnh xc, c th iu khin tay my thao tc vi nhng vimch nh i hi chnh xc gn nh tuyt i.


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Hnh 1.1: Mt tay my thc hin gp i tng vi s tr gip ca h thng th gicmy tnh

Cng nh vy, vi xe t hnh i trong mi trng phc tp, nhiu vtcn, h thng th gic my gip cho xe pht hin ra nhng i tng, v tr vkhong cch ca chng i vi xe. Trong trng hp ny, h thng th gicmy khng ch ng vai tr nh mt cm bin th gic, m cn thc hin vicv bn i tng, cho php xe t hnh chn c ng i thch hp

nht.H thng th gic my cn c ng dng trong nhng l nh vc cng

nghip vi vai tr nh mt cm bin kim sot li bmt sn phm. Camerathu thp hnh nh vbmt sn phm, s truyn d liu vo cho h thng xl tm ra li trn sn phm, v tr li v kch thc li. Vi nhng h thngth gic s dng camera hng ngoi, ta cn c th o nhit sn phm v sphn bnhit trn sn phm.

Nh vy, c thni, trong lnh vc cng nghip, th gic my v cm binth gic c ththay thmt lng ln cc cm bin v tr thng thng, vncn rt nhiu trong mt dy chuyn sn xut hoc CNC, gip gim thiu chiph v cng sc lp t cm bin, v quan trng nht l to nn mt h thngx l thng nht nhng thng tin vqu trnh v i tng cng nghip.

Trong lnh vc t ng ha ta nh, h thng th gic my cng ng mtvai tr ngy cng quan trng.


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Vi s pht trin ca cc thut ton x l d liu nh, ng dng cc thnhtu mi nht ca cng ngh x l v tr tu nhn to, cc cm bin th gicngy nay c th thc hin nhng chc nng thng minh nh m s ngitrong phng, nhn dng i tng chuyn ng, nhn dng khun mt, cnh

bo s kin, nhn dng vn tay....

Cc hng nh ALTALS v SELTEC, cho ra i nhng my m sngi, da trn chui hnh nh. Bng cch quan st s di chuyn ca dngngi v s ngi , h thng th gic my s tnh ton tc v mt dngngi di chuyn. Bi ton ny c ng dng nhiu trong nhng khu cngcng nh nh ga, tu in ngm kim sot lu lng ngi ra vo nhma ra nhng quyt nh iu hnh chnh xc.[2]

H thng th gic my cn c ng dng rng ri trong vic nhn dng,chun on y hc, qun s ( xc nh v tr i phng) v v tr...

Xu thpht trin ca cc cm bin ngy nay, l chnh xc cao, kmvi tnh phn tn, thng minh, kh nng loi b li (fault tolerance). Cc hthng cm bin th gic ang chng t ngy cng p ng c xu th y.Cc h thng cm bin th gic ngy nay, c ththay th c mt lngln cm bin v tr trong nhng bi ton c th, ng thi, kh nng x l

thng tin khng cn n s i u khin ca b i u khin trung tm, chophp chng c thtch hp rng ri vo nhng h thng iu khin phn tn.Thm vo , cc cm bin th gic c tnh linh hot rt cao, c th ng dngtrong nhiu bi ton vi nhng yu cu o c v gim st khc nhau. Vcui cng, do c im hot ng ca mnh, cc cm bin th gic c thhotng tt trong nhng mi trng khc nghit, nh nhit cao, phng x,

bi, in trng, m ln...

Vi nhng l do , h thng th gic my v cm bin th gic ang ngycng c ng dng nhiu trong nhng h thng phc tp v hin i, hotng lin tc v i hi yu cu v chnh xc v x l thng tin cao.

1.2. Khi qut qu trnh x l nh s trong h thng th gic mytnh

H thng th gic my tnh bao gm nhiu lnh vc, trong x l nh s

ng mt vai tr quyt nh.


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H thng x l nh sbao gm mt phm vi rng cc kin thc vphncng, phn mm v c s l thuyt.

Cc bc c bn ca x l nh s c m t trong s di y:

X l vnhn dng

Biu din

Tin x l

Thu nhnnh

Phn vng,phn ngng

C s kin thc

Hnh 1.2 : Cc bc c bn ca x l nh s

Thu thp nh(image acquision) : nh s c thu thp bng mt cmbin nh c kh nng bin thng tin v cng sng v mc xm ca nhthc thnh tn hiu in p di dng analog. Tn hiu ny sau c sha tr thnh tn hiu s.

Hin nay c mt scm bin nh thc hin c vic thu nhn tn hiu v

cng sng ca nh v sha tn hiu. Trong trng hp cm bin khngc chc nng sha th cn phi c mt bbin i nh tng t thnh nhs(video decoder). Tn hiu nh sau khi c sha cn c m ha theonhng chun video (video format) nht nh trc khi c a vo qutrnh lu tr v x l. Cc chun video thng gp nh IUT-R-BT 656, 601...

Tin x l nh : Sau khi nh s c thu thp di dng tn hiu s, cnphi tri qua giai on tin x l. Chc nng ch yu ca tin x l l cithin nh, nng cao cc tnh cht ca nh gip cho cc qu trnh x l vsau


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c thun tin hn. Cc cng on c bn ca tin x l l : nng cao tng phn, lc nhiu...

Phn vng nh: Bc tip theo ca qu trnh x l l phn vng nh. nh

sau khi c ci thin, s tr nn thun tin hn cho vic phn ngng vphn vng. Nhim v chnh ca phn ngng v phn vng nh l tch nhu vo thnh cc i tng, vt thring bit. Kt qu ca qu trnh phnvng nh, ta s c mt tp hp cc im nh c lin kt vi nhau thnh cci tng, c nh s phn bit, thun tin cho cc qu trnh x l caohn.

u ra ca qu trnh phn vng nh l cc pixel cha c lc, bao gm

lin kt ca 1 vng hoc tt c cc im nh trong vng . S liu ny cnc bin i thnh dng thch hp cho my tnh x l.

Phn tch nh: y l giai on x l bc cao trong h thng x l nh s.nh sau khi c phn vng thnh cc i tng ring bit, c nh sphn bit, s c phn tch phc v nhng mc ch khc nhau nh:

Xc nh cc c trng hnh hc ca i tng: da trn c s i tng

c xc nh v phn bit, ta c th thc hin xc nh cc c trnghnh hc ca mi i tng y, nh : v tr, kch thc, hng, ... v s itng hay mt i tng trong nh. y l cc c trng c dngnhiu trong h thng th gic my (machine vision)

Nhn dng : cc i tng c th l cc vt thc hnh dng nht nh,hoc cc k t s, ch ci, du vn tay...nh sau khi c phn vng c thc nhn dng theo nhng phng php nht nh nh phng phpneural, tm ra mu hnh dng m i tng thuc v.

hng dn hot ng ca tng module x l, cn c mt h c s kinthc kim tra hot ng v tng tc gia cc module. H ny c nhimv kim sot hot ng ca tng module v sp xp trnh t hot ng cachng trong tng thi im, gii quyt bi ton xung t.


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1.3. Cc thnh phn ca h thng x l nh:

1.3.1. Thnh phn thu thp nh, Camera v vn nh dng nh.

Gii thiu chung vcamera : Trong h thng x l nh s, camera l mtthit b rt quan trng c chc nng quan st v thu nhn nh u vo cah thng. N thng c coi l hp en trong c cc qu trnh bin ichuyn mt nh thnh dng lu tr trong my tnh. Cc bc x l ny

bao gm s pht sng, thu knh, sensor, cc phn t quang in v b sho, mi thnh phn ny phi hp nhm a ra nh scui cng. im c

bit quan trng trong nhn dng nh l c tnh thi gian ca camera, v vyqu trnh x l nh c vai tr nh b ly mu trong h thng nhn dng nh.

Cm bin nhn chung gm 2 thnh phn chnh. Thnh phn th nht tora tn hiu in u ra t l vi mc nng lng m n nhn c. Thnhphn th 2 l b s ha(digitalize) , l phn t bin i tn hiu tng tthnh tn hiu s. Ty thuc vo thnh phn sha thc cht l b chuyni ADC, chng ta c cc tn hiu vi sbit khc nhau: 4 bit, 8bit, 10 bit, 12

bit..., tng ng ta s c cc nh c 16, 256....mc xm khc nhau.

Trc y, ngi ta s dng cc camera da trn thit b phng tia int, linh kin bn dn, tuy nhin nhng thit b ny thng cng knh, thiu

bn vng, n nh thp. T nhng nm 1980, bt u xut hin ccsensor nh trong cc camera nh sensor CMOS, CCD. Cc sensor ny chamt s lng phn t quang ri rc, hay cc im nh (pixel), mi phn tcha thng tin lin quan n sng chiu vo n.

phn gii ca cc sensor ph thuc vo s im nh trn n. S imnh ca cc sensor l a dng, t thp (32x32 im nh), n trung bnh(256x256 im nh) cho n cao (640x480 ) hoc cao hn na l 1280x1024im nh.

Trong ti ny, chng em s dng loi camera AVC 301D ca hngAVTech, y l mt loi camera quan st cho nh xm, s dng sensor c phn gii tng i ln (510x482 im nh), cho ra tn hiu nh dng tng

t v cn phi c s ha trc khi i vo qu tr nh x l. Tn hiu nh


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tng t c sha thnh nh sbi b video decoder TVP5150 theo chunITU-R-BT 601.

Mi frame nh thu v c biu din di dng I(x,y) trong x,y l ta

ca pixel trn frame v I l mc xm tng ng ca pixel .

Nh vy 1 frame nh thu c s c biu din di dng mt ma trn2 chiu n x m vi n l spixel trn 1 hng, m l shng trong 1 frame. Trong n ny, nh thu c t camera c kch thc 510x482, tuy nhin sau qutrnh s ha theo chun ITU 601 ta c nh s 8bit vi kch thc chun l720x525.

1.3.2. Thnh phn x l nh

1.3.2.1. Cc khi nim c bn ca x l nh s

Pixel v cc ln cn : Nh bit, mi frame nh c m t di dngma trn 2 chiu, trong mi phn t ca ma trn tng ng vi mc xmca 1 im nh (pixel). Mi im nh ny c cc ln cn xung quanh. Nuhin th mi pixel di dng mt vung, mi im c chung bin vi 4

im ln cn, v c chung gc vi 4 im ln cn khc.

Hai im ln cn gi l "lin kt 4" nu chng c chung bin vi nhau, v"lin kt 8" nu chung gc v chung bin vi nhau.

Hnh 1.3 : Nhng kiu lin kt gia cc im nh

ng lin kt: ng lin kt l ng ni t pixel 1, 1[ ]i j n pixel

,[ ]n ni j , qua mt chui cc pixel 1, 1[ ]i j , 2, 2[ ]i j ,... ,[ ]k ki j ..., trong mi pixel


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lin kt vi pixel trc n. Ta c ng lin kt 4 hoc lin kt 8 nu cc pixellin kt 4 hoc 8 vi nhau

a) Lin kt 4 b) Lin kt 8

Hnh 1.4 : Nhng kiu ng lin kt gia cc im nh.

C thd dng nhn thy, nu c mt ng lin kt gia 2 im ,[ ]a ai j ,

,[ ]b bi j , v gia 2 im ,[ ]a ai j , ,[ ]c ci j th cng s c ng lin kt gia 2

im [ ]b bi j v [ ]c ci j . Lin kt c tnh tng i.

i tng v nn : nh sau khi c nh phn ha ( cc im nh ch cgi tr 0 hoc 1) s phn bit c i tng v nn. Trong ti ny, ta ginh i tng l tp hp cc im nh c lin kt vi nhau v c mc xm l0 (en), ta k hiu l S, v nn l nhng im c mc xm 1 (trng) .

Bin:bin ca mt i tng S l tp cc im trn S v c lin kt 4 vi~S (phn b ca S) hay nn ca nh.

Min trong ca S : l cc im thuc S nhng khng nm trn bin can.

1.3.2.2. Cc thut ton x l nh s

Ton t ca s (windowing operator): Trong vic thc thi cc thut tonx l nh s c bn, ngi ta thng s dng mt ton t c bit gi l tont ca s. Ton t ca s l mt tp hp c hnh dng nht nh, gm ccpixel c lin kt vi mt pixel trung tm, l pixel ang c x l. Cc php


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ton trn cc pixel ny s c nh hng n cc pixel trung tm cng l ccpixel ang c x l trong mt thut ton x l nh.

Ton t ca sc nhiu hnh dng, ty thuc vo thut ton thc hin.

Tuy nhin thng dng nht l cc ton t c dng hnh vung vi cc cnhl mt sl, v d :3x3, 5x5, 7x7...

Trong n ny, chng em s dng thng xuyn ton t ca sc dng3x3, v y l kch thc hp l thc hin hiu qu tt c cc thut ton xl c bn v nng cao, ng thi li d thc hin v rt ngn ti a qu trnhx l. Nu s dng ca s5x5 v 7x7, thi gian x l s tng ln rt nhiu.

Tng tng phn : nh sau khi thu c t camera, c th do stng phn nh sng km, dn n chi qu cao, kh phn bit. cithin nh, h tr cc qu trnh x l cao hn, ta s dng cc phng phphiu chnh: hiu chnh min-max, hiu chnh histogram, hiu chnh Gamma, ...

y ta s dng phng php hiu chnh min-max v n dn u mcxm ca nh trong di cho php (khng nh hng n mc xm chung).Cng thc nng cp nh theo hiu chnh min-max:

min

max min

.256oldnewI I

II I

Trong : maxI , min - l cc mc xm cao nht v thp nht.

newI , oldI - l mc xm sau khi hiu chnh v trc khi hiu chnh.

Sau khi hiu chnh mc xm, ta s dn mc xm ca nh ra cc gi tr cchbit nhau hn, to thut tin cho vic x l v nhn dng sau ny.

Cc thut ton nhn chp

Nhn chp (convolution) : nhn chp khng phi l mt thut ton x lnh, m l php ton thng dng trong cc thut ton x l nh s dng ton


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t ca s. Nhn chp c s dng trong cc bi ton d bin (edgedetection) v lc tuyn tnh (linear filter).

Nhn chp tnh ton ra gi tr mi ca pixel trung tm ca ton t ca s,

bng cch thc hin php tnh vi cc pixel ln cn v chnh pixel trung tm.

Vic thc thi php nhn chp nh sau: cho mt ca svi pixel trung tmchy trn ton b frame nh, vi mi ca s 3x3 thu c, ta thc hin phpton :

11

1 1

( , ) ( , ). ( , )ji

n i m j

I i j c n m I n m

(1.1).

Kt qu tnh c cho ra gi tr mi ca pixel trung tm.

Trong (1.1), c(n,m) l cc phn t ca mt ma trn gi l mt n (mask).Mi thut ton x l khc nhau s dng mt mt n khc nhau tnh gi trca cc im nh.

Lc tuyn tnh, d bin: y l 2 thut ton c s s dng php nhn

chp.

Lc tuyn tnh(linear filter) c tc dng ci thin nh, loi b nhiu h trcho cc qu trnh x l cao hn.

Mi b lc khc nhau s dng mt mt n khc nhau, cho hiu qu khcnhau ty vo mc ch s dng v tnh trng ca nh sau khi thu thp. V di vi nh c nhiu phn b u, ngu nhin c lp vi mi pixel, ta c th

s dng mt n dnh cho lc trung bnh, mt n ny s lm gim nh hngca nhiu i vi pixel trung tm bng cch ly trung bnh cng cc pixel lncn trong ca s.

11 12 13

21 22 23

31 32 33

1 1 11

1 1 19

1 1 1

c c c

c c c c

c c c

Nu nh c nhiu Gaussian, ta s dng mt n


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11 12 13

21 22 23

31 32 33

1 2 11

2 4 216

1 1 1

c c c

c c c c

c c c

a) Trc khi lc b)Sau khi lc

Hnh 1.5 : Kt qu ca php lc Gaussian vi ca s 3x3

D bin : Bin ca mt i tng c xc nh ni mc xm ca ccpixel c s thay i t ngt. C nhiu cch xc nh bin, nh d bin theogradient, d bin bng cch ly o hm bc 2 ca mc xm theo ta pixel. Hu ht cc thut ton d bin s dng nhn chp, d khng phi ltt c . Thut ton d bin m chng em s dng trong n ny l thutton Laplacien.

Thut ton Laplacien d bin ch quan tm n s thay i t ngt camc xm ( ly o hm bc 2 ) m khng quan tm n hng ca bin.

Thut ton ny c thc thi bng cch s dng mt n:

11 12 13

21 22 23

31 32 33

1 1 1

1 8 1

1 1 1

c c c

c c c c

c c c

cho lin kt 8


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11 12 13

21 22 23

31 32 33

0 1 0

1 4 1

0 1 0

c c c

c c c c

c c c

cho lin kt 4

a) nh gc b) Kt qu d bin

Hnh 1.6 : Kt qu thut ton d bin

Phn ngng, phn vng v nh phn ha nh s: nh sau qu trnh tin

x l, nng cp, ti nhng qu trnh x l cao hn cn c nh phn ha,phn vng thnh cc i tng ring bit.

Tm ngng : y l qu tr nh tm ra ngng ca mt nh thc hinvic phn vng. Ngng ng vai tr quyt nh qu trnh nh phn ha nhsc hiu qu hay khng. Nu chn ngng khng tt, sb qua mt s itng, hoc cho i tng vi kch thc, v tr khng ng, hoc t hn llm cc i tng khng phn bit c vi nhau.

C nhiu thut ton tm ngng, cho kt qu khc nhau : Trong inhnh l tm ngng trung bnh v tm ngng theo histogram.

Tm ngng trung bnh, ngng c tnh theo cng thc:


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1 1

1( , )

.

n m

tb

i j

ng tb

I i jn m

I I

n x m - kch thc nh

tbI , ng, - mc xm trung bnh, gi tr ngng v sgia hiu chnh.

Tm ngng theo histogram: l phng php t m ngng da theo lc xm.

Hnh 1.7 : Phn ngng theo lc xm

Ngng tm c theo cng thc: ngI =( max1I + max2 )/2. Trong max1I

v max2 l 2 mc xm tng ng cc i trn histogram.

Phn vng v nh phn ha nh s: sau khi tm ngng, ta c th nhphn ha nh s v tch cc i tng. Trong nh xm ban u, ta coi itng l nhng vng nh c mc xm thp, nn l vng nh c mc xmcao. Ta c th tch i tng ra bng thut ton phn ngng:


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Ta s c i tng c mu en( mc xm 1) v nn c mu trng (mcxm 0).

X l ng cu nh nh phn

nh nh phn thu c sau khi phn ngng, phn vng nh thnh cci tng, vn c th cha hon chnh thc hin cc qu trnh phn tchtip theo. l do trn nh vn c thtn ti cc nhiu l cc chm en cha

b loi b sau cc thut ton nng cp nh v lc, hoc do ngng c chncha thc s tt tch hon ton cc i tng. gii quyt vn ny, tas dng cc thut ton x l ng cu nh nh phn (morphologicalalgorithms) .

C 2 phng php x l tiu biu : Thut ton lm y( dilation) v lmmnh (erosion).

2 phng php ny u s dng mt ca s- phn t cu trc(structureelement) qut qua nh. Da trn vic phn tch ca sny ta tnh ra gi trca pixel trung tm.

Lm y (dilation) ( , ) I i j = 0 ch khi tt c cc pixel trong phn tcu trc c gi tr bng 0 (ca s nm hon ton bn ngoi itng)

Lm mnh (erosion) ( , ) I i j = 1 ch khi tt c cc pixel trong phn t

cu trc c gi trbng 1 ( ca snm hon ton trong i tng )

Kt qu ca qu trnh lm mnh l nh s loi b bt c nhng nhiunh, ng thi lm nh bt i tng, tch cc i tng gn nhau ra. khi phc i tng tr li nh c, ta dng thut ton lm y. Sau qu trnhny cc nhiu b loi b s khng xut hin tr li. C thloi b hn ccnhiu tng i ln bng cch thc hin nhiu ln thut ton lm mnh vlm y. Tuy nhin sau hnh dng i tng khng c khi phc honton nh trc.


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Hnh 1.8 : Loi b nhiu v khi phc i tng bng qu trnh lm mnh-lm y.

Bi ton nh nhn i tng: vi phng php x l ng cu nh nhphn, ta c 1 nh nh phn vi cc i tng c tch ra r rt, v loi

b c cc nhiu. thc hin vic xc nh cc c trng hnh hc ca itng, phc v cho h thng nh v v nhn dng, cn phi phn bit cci tng (cc vng nh en) vi nhau bng cch gn cho chng cc nhnkhc nhau.

Thut ton gn nhn i tng cng s dng mt ca s3x3 chy khpframe. Pixel trung tm s c kim tra gn nhn, v cc pixel ln cnc dng xc nh nhn mi cho pixel trung tm. Thut ton thc hinnh sau:


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Hnh 1.9 : S thut ton gn nhn i tng

Thut ton gn nhn i tng c thc hin nh sau: ban u ta khi

to bin m i tng n_object=0. Ca s c t v tr xut pht (gc tri


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pha trn ca frame). Kim tra xem pixel trung tm c bng 0. Nu khc 0 thdch ca s. Nu bng 0, kim tra nhn ca pixel trung tm(pixel_index). Nukhc 0 th quay tr li. Nu bng 0 th kim tra nhn cc pixel ln cn(pixel_nei_index) v gn pixel_cen_index=min(pixel_nei_index). Nu

pixel_cen_index khc 0 th dch ca s. Nu bng 0 th pixel l thuc itng cha nh nhn. Ta tng bin m i tng n_object thm 1, ngthi gn pixel_cen_index = n_object. Sau quay tr li dch ca s.

Vi thut ton ny, ta s thc hin nh nhn i tng gm cc pixel clin kt 8 vi nhau. Nhn i tng c lu vo mt phn ca thng tin vpixel cha trong RAM.

Cc c trng hnh hc ca i tng

Sau khi nh c phn vng v nh nhn thnh cng, ta thc hinvic xc nh cc c trng ca i tng.

Cc c trng hnh hc ca i tng cn c xc nh bao gm :

-Din tch: bng spixel ca i tng :

1 1

( , )n m

i j

I i j

trong ( , )i j =1 hoc 0;

-Chu vi i tng: bng spixel nm trn bin i tng.

-V tr (ta ) ca i tng, cng l ta trng tm vt th,c tnhtheo cng thc :

1 1

1 1

1. ( , );

1. ( , );

n m

i j

n n

i j

x i I i jA

y j I i jA


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1.4. Mt s gii php phn cng cho h thng th gic my

C ththy, cc thut ton x l nh strong h thng th gic my u

tng i phc tp, vi khi lng tnh ton rt ln (hng trm ngn pixel).

Do , tha mn yu cu vtc v hiu sut x l, i hi nhng nn

phn cng mnh vi kh nng x l v tnh thi gian thc cao.

Di y l mt sgii php phn cng thng c s dng cho mt h

thng x l nh s.

FPGA

y l gii php vphn cng m hay c s dng hin nay. Tn dng

c tnh ca FPGA l linh hot v tc x l nhanh (cng ho cc gii

thut), c bit vi kh nng x l song song, FPGA rt ph hp vi cc bi

ton x l nh i hi mt khi lng tnh ton phc tp.

DSP Processor

DSP Processor c gii thiu u tin vo nhng nm 1978, 1979 bi

Intel, Bell Labs. Cc b x l DSP c nhng c tnh ni bt nh sau:

Thch hp cho cc qu trnh cn x l theo thi gian thc

Hiu nng c ti u vi d liu dng lung Chng trnh v d liu c bch ring bit (kin trc Harvard)

Tch hp cc ch th lnh c bit SIMD (Single Instruction, Multiple

Data)

Khng h tr a nhim

Tng tc trc tip vi b nh ca thit b

Tch hp sn ADC v DAC


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DSP Processor ngy nay c tch hp nhiu thnh phn khc nhau,

lm tng kh nng linh hot v tc x l. c bit cc DSP Processor rt

thch hp cho nhng nhu cu cn tnh ton nhanh, x l sthc. c bit mt

scn c sn nhng ch th lnh gip cho vic tnh ton ma trn, tch chphay thm ch cc php bin i DCT trong qu tnh nn nh. Vi nhng u

im DSP Processor c dng trong nhiu thit b x l nh chuyn

nghip.

Mainboard, laptop

y l mt trong nhng phng php n gin nht. C thtn dng cc

mainboard my tnh hay thm ch cc my tnh xch tay vi chc nng l mt

n v x l nh, v a ra quyt nh. Vi vic kt ni mt camera hay

webcam ta hon ton ch ng trong qu trnh nhn/x l nh. Cc giao tip

ngoi vi phbin nh UART, Parallel, USB hay Keyboard.

Vic s dng mainboard, laptop s c nhng u/ nhc im sau:

u im

C tc x l cao

D dng lp trnh, kim li

H iu hnh quen thuc (windows/linux)

Cc cng c lp trnh/bin dch phbin (MSVC, gcc)

Nhc im

Kch thc, khi lng ln

D h hng do va p hay cc tc nhn khc

Gi thnh rt t (>600$)

C qu nhiu thnh phn khng s dng n


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Ch c th giao tip vi ngoi vi thng qua cc chun phbin nh

UART, USB

Ngoi cc gii php trn, cn nhiu nhng gii php phn cng khc cho

mt h thng x l nh s nh : Main cng nghip, Single Board

Computer(SBC) s dng Single on Chip (SoC)....

Trong n ny, chng em s dng gii php l vi mch kh trnh FPGA

xy dng ton b h thng x l nh v iu khin trung tm. Mc ch

ca ti l xy dng mt h thng x l nh trn nn FPGA, trong thc

hin c mt sthut ton c bn nh lc, phn ngng, phn vng, x l

ng cu nh nh phn, nh nhn i tng v cui cng l tnh ton cc

c trng ca i tng. (v tr, din tch...)

H thng c xy dng vi mc ch th nghim nhng thut ton x

l nh s c nghin cu, s dng cng ngh FPGA, ng thi to nn

tng cho h thng th gic my tnh vi nhng thut ton x l cao hn.


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Phn 2 : Khi qut v FPGA v mch pht trin XST 3S1000 caXESS

2.1. Gii thiu chung v FPGA v ngn ng VHDL

2.1.1. Khi nim v ng dng FPGA

Khi nim

FPGA (Field Programable Gate Arrays) l mt thit b bn dn bao gmcc khi logic lp trnh c gi l "Logic Block", v cc kt ni kh trnh. Cckhi logic c th c lp trnh thc hin cc chc nng ca cc khi logic

c bn nh AND, XOR, hoc cc chc nng kt hp phc tp hn nhdecoder hoc cc php tnh ton hc. Trong hu ht cc kin trc FPGA, cckhi logic cng bao gm c cc phn t nh. c thl cc Flip-Flop hocnhng b nh hon chnh hn.

Cc kt ni kh trnh cho php cc khi logic c thni vi nhau theo thitkca ngi xy dng h thng, ging nh mt bng mch kh trnh.

Mt kin trc khc tng t nhng n gin hn FPGA, l CPLD (Complex Programable Logic Device ). Thc cht y l tin thn ca FPGA.Nm 1984, Ross Freeman, mt ng sng lp ca Xilinx pht minh raFPGA. FPGA v CPLC u bao gm mt s lng kh ln cc phn t logickh trnh. Mt cng logic (Logic Gate) ca CPLD nm trong khon t vinghn cho n 10 nghn cng. Trong khi FPGA thng thng cha t 10nghn cho n vi triu cng.

Khc bit c bn gia FPGA v CPLD l kin trc ca chng. CPLD cmt kin trc b gii hn trong mt hoc mt vi dy logic kh trnh cng vimt lng nh thanh ghi nh thi. Do n km linh hot hn, nhng li cu im l kh nng d on tr ln hn v t l logic-kt ni cao hn.

Ngc li, trong kin trc ca FPGA li c s tri hn vs lng kt ni.iu ny lm cho n tr nn linh hot hn ( vs lng thit k c thc


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thi bn trong) nhng cng ng ngha vi vic phc tp hn trong qu trnhthit k.

Mt khc bit ng ch na gia FPGA v CPLD l : hu ht cc FPGA

hin nay u bao c cc phn t chc nng tch hp cao hn ( nh b cng,nhn tch hp) , v b nh tch hp.

Mt s kin trc FPGA hin nay cn c th cho php cu hnh li tngphn (partial re-configuration). C ngh a l cho php mt phn ca thit kc cu hnh li trong khi nhng thit kkhc vn tip tc hot ng.

Mt u im khc ca FPGA, l ngi thit kc thtch hp vo cc

b x l mm (soft processor) hay vi x l tch hp (embedded processor).Cc vi x l ny c th c thit k nh cc khi logic thng thng, m mngun do cc hng cung cp, thc thi cc lnh theo chng trnh c npring bit, v c cc ngoi vi c thit k linh ng ( khi giao tip UART,vo/ra a chc nng GPIO, ethernet...). Cc vi x l ny cng c th c lptrnh li (re-configurable computing) ngay trong khi ang chy.

ng dng.

FPGA c ng dng in hnh trong cc lnh vc nh: x l tn hiu s,x l nh, th gic my, nhn dng ging ni, m ha, m phng(emulation)...FPGA c bit mnh trong cc lnh vc hoc ng dng m kintrc ca n yu cu mt lng rt ln x l song song, c bit l m ha vgii m. FPGA cng c s dng trong nhng ng dng cn thc thi ccthut ton nh FFT, nhn chp (convolution), thay thcho vi x l.

Hin nay cng ngh FPGA ang c sn xut v h tr phn mm bicc hng nh :Xilinx, Altera, Actel, Atmel... Trong Xilinx v Altera l 2hng hng u. Xilinx cung cp phn mm min ph trn nn Windows,Linux, trong khi Altera cung cp nhng cng c min ph trn nn Windows,Linux v Solaris.

2.1.2. Kin trc FPGA

2.1.2.1. Kin trc chung FPGA


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Hnh 2.1 : Kin trc chung ca FPGA

Mi nh sn xut FPGA c ring cu trc FPGA , nhng nh n chung cutrc c thhin ging nh trong hnh bn trn. Cu trc FPGA bao gm cconfiguration logic blocks (CLBs), configurable I/O blocks (IOB), v

programmable interconnect. V tt nhin, chng c mch clock truyn tnhiu clock ti cc logic block, v thm vo c cc logic resources nhALUs, memory v c th c c decoders. Cc phn t lp trnh c caFPGA c 2 dng c bn l cc RAM tnh (Static RAM) v anti-fuses.

Configurable Logic Blocks (CLBs)

Configurable Logic Blocks (CLBs) bao gm cc Look-Up Tables (LUTs) rt

linh ng c chc nng thc thi cc logic v cc phn t nh dng nh l ccflip-flop hoc cc cht (latch). CLB thc hin phn ln cc chc nng logicnh l lu tr d liu,..


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Hnh 2.2 : Mt Logic Block in hnh

Configurable I/O Blocks

Input/Output Blocks (IOBs) iu khin dng d liu gia cc chn vo raI/O v cc logic bn trong ca FPGA. N bao gm c cc b m vo v ravi 3 trng thi v iu khin ng ra dng open collector. Phn ln l c trko ln ng ra v thnh thong li c tr ko xung.IOBs h tr lung dliu 2 chiu (bidirectional data flow) v hot ng logic 3 trng thi (3 state).H tr phn ln cc chun tn hiu, bao gm mt vi chun tc cao, nhDouble Data-Rate (DDR).

Hnh 2.3 : Configurable Logic Blocks

Programmable Interconnect


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Interconnect FPGA khc xa so vi CPLD, tuy nhin li ging vi cagate array ASIC. C mt line di c dng ni cc CLBs quan trng mchng li cch xa nhau m khng gy ra qu nhiu tr. Chng c th cdng nh l cc bus trong chip. C cc line ngn c dng lin kt cc

CLBs ring r nhng t gn nhau. V cng thng c vi ma trn chuyni (switch matrices), ging nh trong CPLD, ni gia cc line di v ngn livi nhau theo mt s cch c bit. Cc chuyn i lp trnh c(Programmable switches) bn trong chip cho php kt ni gia CLBs ti ccinterconnect line v gia interconnect line vi cc line khc v vi switchmatrix. Cc b m 3 trng thi c dng kt ni phn ln cc CLBs vicc line di (long line), to nn cc bus. Cc long line c bit, gi l cc line

clock ton cc (global clock lines) , c thit k c bit cho tr khng thpv nh m thi gian lan truyn nhanh hn. Chng c kt ni vi cc bm clock v vi mi phn t c clock trong mi CLB. l cch m clockc thphn phi bn trong FPGA.

Hnh 2.4 : Programmable Interconnect

Mch ng h (Clock Circuitry )

Cc khi vo ra vi b m clock high drive gi l cc clock driver,nm ri

rc xung quanh chip. Cc b m ny c ni vi cc chn clock vo v li


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cc tn hiu clock vo cc ng clock ton cc (global clock line) nh m tbn trn. Cc ng clock c thit ksao cho thi gian thi gian lch nhnht v thi gian lan truyn nhanh. Thit k ng b l yu cu bt buc viFPGA, t khi lch tuyt i v tr khng c bo m. Ch khi dng cc

tn hiu clock t cc b m clock th thi gian tr tng i v thi gian lchmi c m bo.

2.1.2.2. So snh gia cu trc nh v cu trc ln

FPGA c cu trc nh ging nh cc mng cng ca h ASIC vi cc CLBschbao gm cc phn t c bn rt nh nh cc cng NAND, cng NOR, Cc nh l lun cho rng cc phn t nh c thni vi nhau to ln cc chc

nng ln hn m khng tn nhiu cc phn t logic. Trong cc FPGA c cutrc ln, cc CLB c thbao gm 2 hoc nhiu flip-flop, cc thit km khngcn nhiu flip-flop s khin cho nhiu flip-flop khng c dng n. Ticrng, cc cu trc nh li yu cu kh nhiu ngun kt ni (routing resource),dn n tng khng gian v thm vo mt lng ln tr m khng thb lic hiu qu hn.

2.1.2.3. So snh gia SDRAM Programming v Anti-fuse programming

C 2 cch lp trnh FPGA. Cch u tin l SDRAM Programming, baogm mt vi bit Static RAM cho mi phn t lp trnh. Ghi mt bit vi gi tr0 s ngt switch, trong khi ghi gi tr 1 s ng switch. Cch cn li l anti-fuse bao gm cc cu trc rt nh , khng ging nh cc cu ch thngthng, bnh thng chng khng to ra mt kt ni no c. Mt dng inc cng nht nh trong khi lp trnh thit b s dn n vic hai bn ca

anti-fuse kt ni vi nhau.

Thun li ca cu trc FPGA da trn SRAM l chng dng mt qu trnhsn xut chun m cc khoch sn xut chip l gn nh ging nhau vlun lun c ti u cho kh nng hot ng. T khi m SRAM c thlptrnh li c th FPGA c th lp trnh li bt c khi no mun, thn chngay c khi chng ang trong h thng, n gin nh l ghi vo SRAMthng thng. Chng c nhc im l vng nh volatile nn mt vn v


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ngun c th thay i ni dung ca RAM. Cc thit b da trn SDRAM cngc thi gian tr ng truyn ln.

Thun li ca cu trc FPGA da trn anti-fuse l chng l non-volatile v

cc tr khi ni dy s rt nh v th nn chng c khuynh hng nhanh hn.Nhc im l chng yu cu mt b lp trnh bn ngoi lp trnh v mikhi lp trnh xong th khng th thay i c.

2.1.2.4. Cu trc FPGA ca Spartan 3

Cu trc tng quan ca Spartan 3 gm c 5 thnh phn c chc nng khtrnh c bn sau:

Configurable Logic Blocks (CLBs) bao gm cc Look-Up Tables (LUTs)rt linh ng c chc nng thc thi cc logic v cc phn t nh dng nh lcc flip-flop hoc cc cht (latch). CLB thc hin phn ln cc chc nng logicnh l lu tr d liu,..

Input/Output Blocks (IOBs) iu khin dng d liu gia cc chn vora I/O v cc logic bn trong ca FPGA. IOBs h tr lung d liu 2 chiu(bidirectional data flow) v hot ng logic 3 trng thi (3 state). H tr phn

ln cc chun tn hiu, bao gm mt vi chun tc cao, nh Double Data-Rate (DDR).

Block RAM cho php lu tr d liu di dng cc khi (block) dual-port 18-Kbit.

Multiplier Blocks cho php 2 snh phn 18bit lm u vo v d dngtnh ton tch ca chng.

Digital Clock Manager (DCM) Blocks cung cp kh nng t xc nh

xung clock, l gii php shon chnh cho cc tn hiu clock phn phi, tr,nhn, chia v dch bit.

Cc phn t ny c tchc nh trong hnh sau:


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.

Hnh 2.5 : Cu trc cc thnh phn ca Spartan 3A

T hnh v ta thy, cc IOBs bao quanh cc mng CLBs, ring Spartan-3Ech c mt vng cc IOBs. Mi ct block RAM bao gm mt vi block RAM18-Kbit, mi block RAM li gn lin vi mt multiplier dnh ring. Cc DCMc t cc v tr: 2 DCM pha trn v 2 ci pha di ca thit b, v ivi cc device ln hn th c thm cc DCM pha bn cnh.

c im chung mng Spartan-3 l kt ni lin thng gia 5 phn t cbn ny, v truyn tn hiu gia chng. Mi thnh phn chc nng ny c

mt switch matrix dnh ring cho php chn la kt ni cho vic i dytrong FPGA.

2.1.3. Trnh t thit kmt chip

Trnh t thit kmt h thng trn nn FPGA bao gm cc bc sau:


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Hnh 2.6. Design Flow

Ghi cc c im k thut

Tm quan trng ca cc c im k thut (specification) khng thphngi qu. N ch tuyt i cn c bit khi l mt hng dn chn cngngh ph hp v to nhng yu cu ca bn cho cc nh sn xut chip. Vcc c im k thut cho php mi k s hiu vthit kh thng chung vcng vic ca h trong h thng l g. V n cng cho php cc k s thit

kgiao din ng cho mt lot cc phn ca chip. Cc c im k thut cnggip tit kim thi gian v s hiu lm. S khng lm g c nu khng ccc bng ghi cc c im k thut.

Chi tit k thut nn bao gm cc thng tin sau y:

S khi bn ngoi ch ra chip c t vo trong h thngnh thno.

S khi bn trong ch r mi chc nng ca cc thnh phn.


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Miu t cc chn vo ra bao gm kh nng li u ra, mc ngngu vo.

Thi gian c lng bao gm thi gian thit lp v gi cc chn vo,thi gian lan truyn ra cc cng ra v thi gian chu k clock.

m xp x sgate Dng ng gi Tiu th ngun Gi c Cc th tc kim tra

Mt iu rt quan trng na l l cc ti liu trc tuyn. Rt nhiuphn s c d on tt nht trong , nhng s thay i trong qu trnh

chip c thit k.

Chn cng ngh

Mi khi mt chi tit miu t k thut c xut bn, n c th c dngchn nh sn xut chip tt nht vi cng ngh v cu trc gi c l tt nhtp ng c yu cu ca bn.

Chn mt hng tip cn thit k

Ti thi im ny bn phi quyt nh cch thc hin thit k m bnmong mun. i vi cc chip nh th cch tip cn bng s nguyn l(schematic) thng c chn, c bit l khi cc k s thit k quen thucvi cc cng c ny. Th nhng i vi cc thit kln hn, ngun ng miut phn cng (hardware description language) HDL nh Verilog v VHDLc dng bi kh nng mm do, d c, d chuyn giao. Khi dng ngnng cp cao, phn mm tng hp (synthesis software) s c yu cu tnghp (synthesize) thit k. C ngha rng phn mm ny s to ra cc cng cp thp t miu t cp cao hn.

Chn cng c tng hp

Ti im ny, bn phi quyt nh chn phn mm tng hp no s cdng nu bn c khoch thit k FPGA vi HDL. iu rt quan trng k


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t khi mi cng c tng hp c khuyn dng v s y thc ca cch thitkphn cng nn n c thhot ng tng hp ng hn.

Thit kchip

C mt s cch thit kchip

Top-down design (Thit kt trn xung di) Macros

Synchronous design

Protect against metastability

Avoid floating nodes

Avoid bus contention

M phng ci nhn tng quan v thit k

M phng l mt qu trnh lin tc khi m thit kxong. Tng phn nhca thit k nn c m phng trc khi kt hp chng thnh cc phn lnhn. iu ny rt l cn thit v s m phng theo th t s kim tra chcnng hot ng ng ca tng phn.

Mi khi thit kv m phng hon thnh, dn n mt ci nhn tng quankhc vthit kv ththit kc th c kim tra li. Tht l quan trng nhn cc kt qu khc cho php nhn qua cc m phng v chc chn rngkhng c iu g b qun v khng s tn hao no gp phi. l mt trongnhng khi qut quan trng nht bi v khi m phng ng v thnh cngth bn sbit c chip ca bn s hot ng ng trong h thng.

Tng hp

Nu thit k dng HDL, bc tip theo l tng hp chip, bao gm vicdng phn mm tng hp chuyn i tht ti u t thit k mc RTL(register transfer level) sang thit k mc gate m c th gn vo cc khilogic trong FPGA.

Place and Route


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Bc tip theo l sp t chip, kt qu trong vic thit kvt l cho chipthc. iu ny bao gm cc cng c ca nh sn xut ti u lp trnh chochip thc hin thit k. Sau , thit k c lp trnh vo cho chip.

M phng li tng quan cui cng

Sau khi sp t xong, th chip phi c m phng li vi cc con svthi gian to ra bi cc layout thc t. Nu mi th u tt n thi imny, th mt kt qu m phng mi s ng vi cc kt qu d on.

Kim tra

i vi cc thit b lp trnh c, n gin l lp trnh thit b v ngaylp tc c mu th. Sau bn c trch nhim t mu th ny vo trong hthng v xem xem h thng c lm vic ng khng. Nu bn lm ln ltcc bc bn trn th a phn l h thng s hot ng ng ch vi mtvi li rt nh. Cc li ny thng c lm vic xung quanh vi vic thayi h thng v thay i phn mm h thng. Cc li ny cn c kim trav trch dn li c th c sa cha trong phin bn tip theo ca chip.Kim tra h thng nhng l cn thit ti thi im ny a ra kt qu rng

mi phn ca h thng u hot ng ng khi kt hp vi nhau.

Khi cc chp c a vo sn xut, rt cn thit c mt vi kim tra cmt vi kim tra burn-in trong h thng test thng xuyn h thng quathi gian di. Nu mt chip c thit k ng, th n chb hng khi li inhc hoc li c hc s thng xuyn xy ra vi loi kim tra khc nghit ny.

2.1.4. Ngn ng m t phn cng VHDL

VHDL l mt ngn ng m t phn cng (hardware descriptionlanguage), m t hnh vi ca mch in hoc h thng, t mch in vtl hoc h thng c thc thc thi.

VHDL l vit tt ca VHSIC Hardware Description Language. Bn thnVHSIC l vit tt ca Very High Speed Integrated Circuits (mch tch hp tc cao), ln u tin c sng lp bi United State Department of Defensetrong nhng nm 80, sau to ra VHDL. Phin bn u tin l VHDL 87,


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ln nng cp sau c tn l VHDL 93. VHDL l ngn ng m t phn cngnguyn gc u tin c chun ha bi Institue of Electrical and ElectronicsEngineers (IEEE), ti chun IEEE 1076. Trong IEEE 1164, c mt chun cthm vo l gii thiu h thng logic a gi tr (multi-valued logic system).

ng c thc y c bn khi dng VHDL (hay dng Verilog) l VHDL lmt ngn ng c lp chun ca cc nh cng ngh, cc nh phn phi do chng c kh nng portable v ktha cao (reusable). Hai ng dng trc tipchnh ca VHDL l trong mng cc thit b logic lp trnh c (Programmable Logic Devices) (bao gm CPLDs Complex ProgrammableLogic Devices v FPGAs Field Programmable Gate Arrays). Mi khi mngun VHDL c vit, chng c th c dng thc thi mch in trongcc thit b lp trnh c (t Altera, Xilinx, Almel, ..) hoc c thgi n ccxng chto cc chp ASIC. Hin ny, rt nhiu cc chip thng mi phctp (v d nh cc microcontrollers ) c thit kda trn cch tip cn ny.

Mt iu ch v VHDL l tri ngc vi cc chng tr nh my tnhthng thng c thc hin tun t th cc cu lnh c thc hin songsong (concurrent). V l do , nn VHDL thng c coi l mt m ngun

hn l mt chng tr nh. Trong VHDL ch c cc cu lnh t trongPROCESS, FUNCTION, hay PROCEDURE c thc thi tun t.

Trnh t thit kmt chp da trn VHDL

Mt trong nhng tin ch ln ca VHDL l cho php tng hp mch inhoc h thng trong thit b kh lp trnh (programmable devide) (PLD hocFPGA) hoc trong mt h ASIC. Cc bc thc hin mt project c tng

kt nh trong hnh di:


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Hnh 2.7: Qui trnh thit kchip da trn VHDL

Chng ta bt u thit kbng cch vit m VHDL, c ghi trong cc filevi ui m rng .vhd v tn ging nh tn ca ENTITY (thc th). Bc

u tin trong qu trnh synthesis l bin dch. Bin dch l mt qu trnhchuyn i gia ngn ng VHDL bc cao ti Register Transfer Level (RTL)sang netlist mc gate level. Bc th 2 l ti u thc hin trn gate level netlist ti u vtc hoc cho din tch. Cui cng l mt phn mm place androute s to ra mt physical layout cho cc chp PLD/FPGA hoc to ra ccmt n cho mt h ASIC.

2.2. Gii thiu mch pht trin XST 3S 1000 ca hng XESS

Trang ch ca XESS Corp. : http://www.xess.com

X Engineering Software Systems Corporation (XESS) l cng ty ti phaBc Carolina (M) c thnh lp t nm 1990. XESS Corp. a ra nhngcng c pht trin logic lp trnh c vi gi phi chng v cc hng dncho ngi dng c vit bi cc k s, cc nh nghin cu, nh thit kvngay c ca sinh vin.


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XESS gii thiu 2 board chuyn dng cho x l nh v audio:

2.2.1. XSA-3S1000

Hnh 2.8 : KIT XSA-3S1000

KIT FPGA ny bao gm c 32 Mbyte DRAM ng b v 2 Mbyte Flash xy dng h thng vi iu khin RISC hon thin da trn phn mm (soft-core).

C thc ti 4 bitstream c lu tr trong Flash v ta c thdng switch la chn bitstream no c cu hnh cho FPGA khi p t ngun invo KIT. Hoc chng ta c thdownload trc tip vo FPGA nh cng songsong (parallel port) dng cng c XSTOOLS ( trong b cng c ca XESS).Giao din CPLD trn XSA-3S1000 cng h tr download dng XILINXiMPACT v circuit test/debug vi ChipScope dng cp download song songca Xilinx.


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Bsung thm vo cc chip FPGA, SDRAM v Flash, c thm cng VGA cth hin th ha vi 512 mu. Thm vo , cn c thm prototypingheader a cho ta 65 chn I/O xy dng cc giao din vi cc ngoi vikhc.

Hnh 2.9. S cu trc ca XSA-3S1000

2.2.2. XST-3.0 (XStend Board)


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Hnh 2.10 : XST-3.0 Board

Xstend Board l mch h tr cho XSA Board c th truy nhp qua giaodin prototype. Bo mch ny m rng kh nng ca XSA Board trn mt smt:

Cc pushbuttons, DIP switches, LEDs, v protopying area rt c chcho cc th nghim phng Lab.

Mch stereo v dual-chanel analog I/O dng cho x l m thanh kthp vi cc thnh phn DSP c synthesize vi phn mm COREgeneration ca Xilinx.

Video decoder (b gii m video) cho php s ha cc video dngNTSC/PAL/SECAM trong cc ng dng x l nh.

Giao din Ethernet 10/100 lm cho XSA Board c kh nng truy nhpTCP/IP v cc dng mng khc.

Giao din USB 1.1 lm cho XSA Board nh mt ngoi vi USB dng low-

speed hoc full-speed vi PC.


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Giao din RS-232 rt hu ch khi XSA Board cn phi gi thng tin qualin kt giao tip ni tip vi tc thp.

Giao din IDE cung cp cho XSA Board kh nng truy cp vo a

cng (hard disk) lu v phc hi d liu.

Cc module vi chc nng khc c ththm vo trong XST Board nhcc doughterboard connector.

Nh vy, kt hp gia XSA-3S1000 v XST-3.0 cho ta mt Board ng dngx l video rt hiu qu.

Hnh 2.11 : XST-3S1000

H tr k thut: XESS c mt group xsboard-user l mt mailing list, giip mi thc mc vthit kphn cng v h thng phn mm khi dng bomch logic kh trnh ca XESS Corp. Ngoi ra, cc phn mm v modulepht trin kh y .


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2.3. Gii thiu hng Xilinx v cc cng c lp trnh:

Hng Xilinx

Xilinx l nh pht trin hng u hin nay trong lnh vc chip kh trnh.c thnh lp bi Ross Freeman, Bernie Vonderschmitt, v Jim Barnett, vc tr s ti thung lng Silicon. Tr s chnh hin nay San Jose , California.L thnh vin ca nhm 100 cng ti hng u thgii hin nay do tp chFortune bnh chn.

Xilinx l nh pht trin FPGA, CPLD c s dng rng ri trong nhngng dng truyn thng, t ng ha, mt m...v cc lnh vc khc. Cc sn

phm phn cng ca Xilin gm c cc dng CPLD : CoolRunner, cc hFPGA nh Spartans, Virtex...

Xilinx cn cung cp cc phn mm h tr lp trnh FPGA, CPLD nh ISE,EDK, LogicCore, System Generator. Cc cng c ny h tr rt nhiu cho qutrnh lp trnh FPGA, gip gim thi gian v cng sc thit k. Cc phin bnphn mm trn c nng cp thng xuyn. (Hin gi c phin bn 10.1cho cc ng dng).

ISE 9.2

L cng c xy dng v lp trnh FPGA. ISE 9.2 thc s l mt mi trngtng hp v thc thi ton din cho cc chip kh trnh ca Xilinx. Vi ISE9.2,ngi thit kc th lp trnh, g ri, m phng, dch v np chng trnhmt cch nhanh chng v d dng. Ngi thit k cng c th thit k hthng ca mnh theo nhiu cch khc nhau : vi m vhd, vi s RTL, hoc

vi s trng thi (state machine)

LogicCore 9.2

LogicCore 9.2 l th vin ca ISE 9.2, trong cha cc m ngun cho cckhi logic c th c s dng cho vic xy dng nhng h thng khc nhau.Vi Logic Core, ngi thit kc thgim i rt nhiu cng sc thit k, bqua vic xy dng nhng thnh phn c sn v tp trung vo vic xydng h thng, ng thi cng ti u ha cc thit kca mnh.


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EDK 9.2

L cng c xy dng h thng c cc vi x l nhng trong FPGA nhMicroBlaze (cho tt c cc h FPGA ) v Power PC ( ch cho h Virtex).

EDK 9.2 khng ch gip to ra cc vi x l nhng m cn h tr thit kcc ngoi vi, giao din cho chng, vi mt th vin ngoi vi s, cho phpvi x l thc thi bt c mt nhim v no m cc vi x l thng thng cththc hin c : nh giao tip UART, Ethernet, cc b nh RAM, ROM,cc I/O,....Cc thit kvi x l nhng cng c ti u ha. Ngoi ra EDKcng c cng c m phng rt mnh.

System Generator 9.2

System Generator (sysgen)l cng c pht trin h thng cho FPGA, chophp thit kh thng dng cc khi, v h tr m phng, debug, to codenp vo FPGA hoc kt hp vo nhng ng dng ln hn.

Sysgen c xy dng nh mt Block Set ca Simulink trong Matlab. Do, sysgen tha hng tt c cc u im ca Simulink trong vic xy dng

h thng v m phng. Sysgen cn s dng th vin ca Logic Core xydng cc block ca mnh. Trong th vin ca Sysgen c tt c cc khi thchin cc chc nng t c bn nh cng, tr , nhn, cc khi logic,...cho nnhng thit kphc tp hn nh cc DSPs, b lc s, nhn chp, UART..., cc

b nh tch hp: Single Port, DualPort Ram, FIFOs, cc thanh ghi...

Sysgen cn cho php ngi thit k to ra cc khi thc hin nhngnhim v ring bng khi Black Box, ti y ngi thit ks to ra cc entity

v ci m ca n vo Black Box to ra cc thit kring ca mnh.

Nhng thit kca Sysgen c th c dch ra nhiu kiu d liu, c ththnh file bit np ngay vo phn cng, hoc thnh cc thit k ghpvo mt h thng ln hn.Vi vic kt hp vi Mathwork xy dngSysgen, Xilinx lm cho vic thit kh thng trn nn FPGA ca mnh trnn thun tin v n gin hn rt nhiu i vi ngi lm k thut. Trong n ny, chng em s dng Sysgen xy dng ton b phn thutton x l nh scho thit kca mnh.


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Phn 3 : Xy dng h thng x l nh ng trn nn FPGA

Yu cu h thng :

Trong phn ny, chng em trnh by chi tit vic thc thi h thng cmbin th gic trn nn FPGA. D liu nh thu c l ca mt tp hp cc itng tch ri nhau trn nn trng. Nhim v ca h thng l thu thp nhv x l bng cc thut ton x l nu, nhm loi b nhiu, tch cc itng ra khi nn, gn nhn cho i tng, ng thi xc nh cc c trngc bn ca i tng cho qu trnh x l cao hn hoc cho vic iu khintay my thao tc vi i tng.

ng thi, h thng cng c nhim v giao tip vi b x l trung tm (my tnh PC ) truyn thng tin c x l ( s i tng, kch thc, vtr, ...ca i tng ) v nhn tn hiu iu khin, trong khi iu khin giaotip VGA hin th hnh nh.

Hnh 3.1 : Mt nh cn c x l.

3.1. S cu trc h thng x l nh ng


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Hnh 3.2 : S chung ca h thng

Trn y l s cu trc ca h thng x l nh s. H thng gm c 3phn chnh sau:


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Khi thu thp d liu t Camera v ghi vo SDRAM: d liu t videodecoder c x l khi Framegrabber ch ly d liu luminance v ghivo FIFO, sau c ghi vo SDRAM. Chip Video decoder c kch hotnh tn hiu iu khin qua chun I2C trn PC qua cng Parallel Port (LPT).

Khi x l nh: c d liu t SDRAM vo FIFO, x l v sau lighi vo FIFO v ghi vo SDRAM qua dual port, SDRAM Controller. Chnthut ton v kch hot tng module x l tng thut ton c kch hottbn ngoi qua cc nt bm (button) v cc kha chuyn (switch).

Khi hin th nh ln VGA: hin th cc pixel ca nh trong SDRAM lnmn hnh my tnh CRT.

3.2. Xy dng h thng thu thp, lu tr, x l v hin th nh

3.2.1. Thnh phn thu thp nh Framegrabber

Nhim v: nhim v c bn ca khi Framegrabber l ng b vi chipVideo Decoder c cc pixel v ghi vo FIFO.

Phn tch cch thc thi

Framegrabber dng mt Finite State Machine gii m v cht thnhphn luminance (ch ly cc thnh phn xm grayscale) t pixel streamca ITU-R BT.656 4:2:2 ( nh dng xut ra mc nh ca video decoder).

Pixel stream c nh dng nh sau:

Hnh 3.3: Pixel stream waveform

u tin l cc byte nh du bt u mt frame (FF-00-00), tip theo lbyte ng b (embedded sync byte) ES. Theo sau l 1440 byte gm: 720 gi trluminance (Y), 360 gi trblue chromiance (Cb) v 360 gi tr red chrominace

(Cr) theo nhm c mt Cb v Cr th c 2 gi tr Y: 1b n r nC Y C Y .


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S cu trc ca State machine nh hnh v di y:

Hnh 3.4 : Framegrabber state machine

T hnh v ta thy 3 trng thi u: wait_for_embedded_sync,wait_embedded_sync_1, wait_embedded_sync_2 dng kim tra 3 bytenh du u tin (FF-00-00).

Ti trng thi check_embedded_sync kim tra cc tn hiu ng b gm cfield id, field change v ghi byte ng b vo FIFO phc v cho vic ghid liu vo FIFO v hin th VGA. Nu c tn hiu image_processing_start khi ng khi ny th tip tc chuyn sang cc trng thi tip theo nhnd liu v ghi vo FIFO, cn khng th quay li trng thi ban u kimtra cc byte nh du ca frame mi.

Sau khi ng b xong th lin tc thc hin cc trng thigrab_chromar v grab_luminance2. D liu lumincance c ly trng thigrab_luminance2. Qu trnh nhn d liu kt thc (tn hiu done) xy ra khi

trong cc trng thi ny nhn c byte c gi tr 0xFF.


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D liu ghi vo FIFO bao gm 16 bit c 2 bit u tin l cc bit ng b:field_id v field_change, theo sau l cc bit 0 v byte luminance:

Pixel_in


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Trong n ny, chng em dng read, write vi ch pipeline.

Hnh 3.5 : Pipelined Read Operation timing waveforms

Pipeline Read Operation

Trn y l dng sng cho hot ng c kiu pipeline. Hot ng c ch pipeline c thc hin bng cch gi cho tn hiu rd ln cao trongghi lin tc cung cp a ch cn c mi khi m tn hiu earlyOpBegun hocopBegun ln cao bo hiu hot ng c trc bt u. V d trn m t 3hot ng c truy nhp cc vng nh SDRAM ti bank v hng caSDRAM ang c active. Nu vic c thc hin bank hoc hng khcca SDRAM th SDRAM Controller s hon thnh qu trnh c hin ti vactive bank v row mi trc khi tn hiu earlyOpBegun v opBegun ln cao.

Pipeline Write Operation


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Hnh 3.6 : Pipelined Write Operation timing waveforms

Hot ng ghi ch pipeline c thc hin bng cch gi cho tnhiu wr ln cao trong khi th lin tc cung cp a ch mi mi khi tn hiuearlyOpBegun hay opBegun ln cao bo hiu rng qu trnh ghi trc btu. V d trn y thc hin 3 hot ng ghi vo b nh trong bank v rowhin ti ca SDRAM. Nu ghi vo a ch bank hoc row khc th SDRAMController s hon thnh vic ghi hin ti v sau kch hot bank v rowmi trc khi tn hiu earlyOpBegun v opBegun ln cao.

Nh m vic ghi, c SDRAM tr nn d dng hn, theo cu trc sau:


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Hnh 3.7 : Ghp ni vi SDRAM Controller

Dualport Module for the SDRAM Controller

Chc nng: Dualport module nh vo pha cc cng bn host-side ca biu khin XESS SDRAM Controller v chia thnh hai phn host-side ring

bit, mi phn c thhot ng nh cc cng ca host-side ban u do ng dng c thgm nhiu thnh phn truy nhp SDRAM nhng ch dng 1

b iu khin SDRAM Controller. Bt k ng dng no thc hin vic ghi cb nh SDRAM u c lp vi hot ng cc post khc. Bng thngtng cng ca SDRAM c th c phn phi gia 2 port cho khp vidata rate ca cc ng dng dng dual port. Dualport module c th xydng kiu tng xy dng giao din SDRAM vi 3 hay nhiu cng c lp.


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Hnh 3.8 : Ghp ni dualport vi SDRAM Controller

Hnh 3.9 : Xy dng 4 ports SDRAM interface

Phn phi bng thng SDRAM cho cc port ca mt dualport c thchin qua tham sPORT_TIME_SLOTS, l mt vector 16 bit vi mi bit tngng vi mt time slot trong khi mt hot ng c hoc ghi ca SDRAM c


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thxy ra. Thit lp bit bng 0 cu hnh time slot cho port0, v thit lpbng 1 dnh time slot cho port 1. Sau y l mt scch thit lp:

PORT_TIME_SLOTS => 1111000011110000 p dng 8 time slot cho mi

port, vi mi port c 4 ln truy cp lin nhau vo SDRAM trc khi dualport chuyn iu khin cho port kia. V th , mi port c phn phi mtna bng thng ca dual port.

Tham sPORT_TIME_SLOTS ch c tc ng ti hot ng ca dualportmodule khi cc ng dng trn c 2 port cng cgng truy nhp vo SDRAM.ng dng mt port s truy nhp trc tip vo SDRAM nu khng c hotng ghi v c ang tin hnh port kia. V th PORT_TIME_SLOTS =

1111111111111111 s cho php port 0 truy nhp SDRAM ch khi port 1khng truy cp, nhng khng ngn hon ton port 0 trong vic truy cpSDRAM.

PORT_TIME_SLOTS = 1111111100000000 cu hnh mt na bng thngcho mi port tuy nhin c thblock truy cp ca mt port ln ti 8 time slottrong khi port kia c u tin hn. gim tr ch cn gnPORT_TIME_SLOTS = 0101010101010101 tuy nhin s lng ph thi gian

bi v SDRAM Controller phi xa pipeline trc mi qu trnh chuyn port.V th, nhm cc bit lin nhau cng mt gi tr l gii php tt nht.

3.2.4. Image Processing core

Image Processing core l thnh phn quan trng nht ca h thng x lnh, trong thc thi tt c cc thut ton t c bn( lc, d bin, phnngng...) n nng cao ( gn nhn i tng, xc nh cc c trng ). Hotng ca thnh phn ny c iu khin bi b x l trung tm.

Nh thy trn, mi pixel c thu thp, x l v lu vo SDRAM cdng mt word 16bit cha thng tin nh sau :

'field_id' | 'field_change' | "000000" | "luminance"

Trong , field_id v field_change l nhng bit thng tin v frame v

pixel, khng c thay i trong qu trnh x l. Luminance l s8 bit biu


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th mc xm ca pixel, s c x l trong cc thut ton vsau. Cn li 6 bitcao sau field_change cha c s dng n, s c dng gn nhn itng.

Vic thit k Image Processing Core ch yu s dng cng c SystemGenerator. Vi cng c ny, ngi thit kc ths dng cc core c sn c cung cp bi Xilinx, gim thiu cng sc v thi gian thit k, ng thivn c tht to ra cc block ring cho mnh s dng cng c Black Box, vc bit, vic g ri v m phng h thng c ththc hin hon ton trnMatlab, vn rt quen thuc vi sinh vin iu khin t ng.

Hnh 3.10: S khi x l nh.

Khi x l nh giao tip vi SDRAM thng qua 2 FIFO l read_fifo vstore_fifo.

read_fifo c nhim v c tun t d liu t SDRAM vo khi x lnh lu vo buffer v x l. Vic c bt u khi tn hiu bo read_fifokhng cn trng (read_fifo_empty='0' hay read_fifo_avail='1') v dng khic ht mt frame. Vic c c th tm dng khi sp xy ra xung t qutrnh c v x l.


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store_fifo c nhim v ly d liu x l t khi x l nh v lu tunt tr li vo SDRAM ti v tr xc nh. Cng nh read_fifo, vic ghi castore_fifo iu khin qu trnh x l, khi store_fifo y th tm dng vic xl.

Cu trc ca Image Processing Core gm 2 thnh phn :

fifo_to_buffer : thc thi vic giao tip vi read_fifo v lu d liu vo mtb m. Thc cht b m d liu l mt Block Ram trong FPGA, c khnng lu n 27 dng ca frame. Vic lu d liu c iu khin sao chotrnh xung t vi thnh phn x l.

Hnh 3.11 : Khi ghi d liu t read_fifo vo Buffer

processing_algorithms : la chn, thc thi tt c cc thut ton x l nh,t lc, d bin, cc thut ton x l ng cu,... cho n phn ngng, phnvng v gn nhn i tng. ng thi thnh phn ny cn thc hin giaotip gia Image Processing Core trong vic giao tip vi store_fifo a dliu x l ra ngoi.


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Hnh 3.12 : Khi thut ton x l nh

Khi x l ny c d liu tb m theo cng mt phng php trongtt c cc thut ton x l. iu ny c thgy ko di thi gian x l i vimt st thut ton, nhng li gip tit kim rt nhiu ti nguyn v cngsc thit kcng nh gim thiu kh nng gy li hoc nhm ln trong qutrnh thit k.

Vic ghi v c d liu b m buffer nh sau:

Ban u ta c tun t d liu vo buffer cho n khi y 10 dng, ta liquay ngc tr li v tr ban u v tip tc c. ng thi, ca s ghi ra x l c dch tun t cho n ht 10 dng , ri cng quay ngc tr lidng u tin. Vic ghi v c c iu khin sao cho khng xy ra s xungt : ch ghi vo nhng dng x l v ch c khi ghi sdng cnthit x l.

Vic c v ghi nh trn cho php s dng mt cch hiu qu sblockram hu hn ca FPGA, trnh hon ton kh nng xung t c/ghi, ngthi loi gip cho vic c v ghi tr nn tng i c lp vi nhau, gimthiu sai st trong qu trnh x l.

Vic c v ghi cng c iu khin bi tn hiu bo t read_fifo vstore_fifo: dng ghi khi read_fifo trng (read_fifo_avail= 0) v dng x l khistore_fifo y (store_fifo_full = 1).


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C ththy, vi thanh ghi dch ny, ta c thtn dng ti a kh nng xl song song ca FPGA cho cc thut ton x l nh s.

Khi x l : Khi x l bao gm nhiu thut ton x l khc nhau. Tuy

nhin, cu trc ca cc thut ton l tng i ging nhau v ta c th tndng mt c ch c duy nht dng chung cho tt c cc thut ton.

Cu trc b lc tuyn tnh, d bin : B lc tuyn tnh v d bin theophng php Laplacien cng s dng php nhn chp vi 2 mt n khcnhau. Do ta c thghp chung li thnh mt khi. Php nhn chp c thc thc hin rt nhanh chng s dng cu trc song song. Di y l cutrc b nhn chp trong cc b x l ny :

Hnh 3.15 : Cu trc nhn chp

B x l ng cu nh nh phn : Khi ny ch yu tnh ra gi tr max,minca cc pixel trong ca s, do s dng cc block so snh. Cu trc nhsau:


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Hnh 3.17 : Khi gn nhn i tng

u vo khi gn nhn i tng l 9 pixel ca ca shin ti, vi pixel 5l trung tm, cn c xem xt gn nhn. Vic gn nhn cho pixel trung

tm thc hin nh thut ton trnh by phn 1.

3.2.5. Hin th nh ln VGA: VGA Generator

VGA Color Signals

C 3 tn hiu color l: red, green v blue gi tn hiu mu sc (colorinformation) n mn hnh VGA. Mi mt tn hiu iu khin mt sng bn

in t (electron gun) phng cc ht electron v ln mt mu c bn timt im trn mn hnh. Di ca tn hiu nm t t 0 V (tng ng vi muti hon ton) v 0.7V (sng hon ton) iu khin cng ca mi thnhphn mu v 3 thnh phn mu kt hp vi nhau to ln mu ca im nh(dot) hay phn t nh (pixel) trn mn hnh.

Hnh 3.19 : VGA Connection


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Mi tn hiu mu analog c thl mt trong 8 mc bng 3 tn hiu digitalbng cch dng b chuyn i digital to analog 3 bit (DAC 3 bit). Do , 8mc trn mi tn hiu analog kt hp vi nhau to nn phn t nh (pixel)vi 8 x 8 x 8 = 512 mu khc nhau. Tuy nhin trong n ny, chng em ch

dng camera en trng nn hin th trn mn hnh ch c 8 mu khc nhauhay 8 mc thi.

Hnh 3.20 : 8 mu c bn

VGA Signal Timing

Mi mt nh (hay frame) trn mn hnh hin th l kt hp ca h dng,mi dng c w pixel. Kch thc ca mi frame c biu din w x h di

cc dng tiu biu gm 640 x 480m 800 x 600, 1024 x 768 v 1280 x 1024.

Hnh 3.21 : CRT Display Timing Example


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sync generator c u ra l tn hiu gate mt chu k trng khp vi sn lnca xung ng b ngang ( horizontal sync pulse), tn hiu gate ny ni vitn hiu clock-enable ca b vertical sync generator v th nn clock-enablech cp nht b m thi gian sau mi dng pixel (line of pixels). Tn hiu

gate ca vertical sync generator c dng nh tn hiu bo kt thc mtframe cho cc khi d liu pixel bn ngoi , ng thi n cng reset v xaton b ni dung ca pixel buffer nn b VGA generator lun khi ng ttrng thi xa sch hon ton vi mi frame.

B to tn hiu ng b cng to ra cc tn hiu horizontal v verticalblanking. Khi dng php ton OR logic ta c tn hiu blanking ton cc.Cc tn hiu blanking c kt hp vi cc bit c trng sthp hn b m

horizontal pixel counter xc nh khi no c pixel tb m. V d, numi pixel c rng 16 bit, th mt t 16 bit s cn c c sau mi chu kclock. V thnn hot ng c c khi to bt c khi no tn hiu videokhng trng v 2 bit thp ca b m pixel u bng 0.

Hnh 3.23 : S khi cu trc ca VGA Generator


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Tn hiu full signal c gi ra ngun d liu pixel bn ngoi bo chobit khi no th dng vic in d liu vo b m. Vi b m FIFO 256, tnhiu full ln cao khi 5 bit cao ca tn hiu FIFO level bng 11111. Khin cho

b trng 7 bit trong FIFO in cc pixel khi cc ngun d liu bn ngoi

cht gi d liu vo trong pipe. y gi l c chb m an ton.

3.2.6. Picoblaze v h thng iu khin trung tm

3.2.6.1. Khi qut PicoBlaze

Vi iu khin PicoBlaze l vi iu khin nhng 8 bit c cu trc RISC cti u pht trin cho cc h FPGA nh Spartan 3, Virtex II v Virtex II Pro

ca Xilinx. Vi vi iu khin ny chng ta c thlm mt b iu khin datrn nn vi iu khin rt hiu qu, hay x l d liu n gin.

Vi iu khin PicoBlaze c ti u vmt hiu sut v chi ph pht trinthp. N chim khong 96 FPGA slices, hay ch 12.5% ca XC3S50 FPGA vchim mt phn rt nh mc 0.3% ca XC3S5000 FPGA. Bnh thng mi

block RAM ca FPGA c th lu tr ti 1024 cu lnh chng trnh (programinstructions) v cc lnh ny c t ng load trong khi cu hnh FPGA, khi

vi iu khin PicoBlaze c thhot ng t 44000 ti 100000 cu lnh trngiy (MIPS million instructions per second) ty thuc vo h FPGA cdng l loi g v tc ca h .

Nhn ca vi iu khin PicoBlaze c nhng hon ton trong FPGA vkhng cn mt ngun thm no. n gin l cc ngoi vi ca PicoBlaze c tht do la chn cho ph hp vi cc mc ch c bit, chc nng v yu cu

vgi c ca sn phm cui cng. PicoBlaze c nhng vo di dng mtm ngun VHDL v thn c th nhng vo cc i FPGA sau ny v do project ca chng ta s c tnh ktha cao. c nhng trong FPGA, vi iukhin PicoBlaze s gim kch thc mch, gi thit kv thc hin.

PicoBlaze FPC c h trbi mt scc cng c pht trin ph hp baogm assembler v mi trng pht trin ha tch hp (IDE integrateddevelopment environment), graphical instruction set simulator v m ngun


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VHDL v khi m phng. V rt n gin l vi iu khin PicoBlaze c htr trong mi trng pht trin Xilinx System Generator hay ISE.

Hnh 3.24 : S khi cu trc ca PicoBlaze

Vi iu khin PicoBlaze c cc c im sau:

16 thanh ghi d liu chc nng chung c rng 8 bit. Lu tr c 1K lnh trong chng trnh c th lp trnh c trong

chip v t ng np khi cu hnh FPGA hay khi khi ng FPGA. Khi tnh ton logic (Arithmetic Logic Unit ALU) vi cc c CARRY

v ZERO.

Mt bng RAM 64 byte. 256 u vo v 256 u ra d dng c thm rng thm. Automatic 31 location CALL/RETURN stack.

Predictable performance, lun lun dng 2 xung nhp h thng cho mt

cu lnh, c th t ti 200 MHz hoc 100 MIPS trong Virtex II Pro FPGA. p ng ngt nhanh; worst-case 5 clock cycles. c ti u cho cu truc Spartan 3, Virtex II, v Virtex II Pro FPGA

ca Xilinx ch chim 96 slices v 0.5 ti 1 block RAM. H tr m phng tp lnh assembler.

Vi iu khin PicoBlaze c cung cp di file ngun VHDL gi lKCPSM3.vhd, c ti u vvic thc thi hiu qu v chc chn trong cch Spartan-3, Virtex-II hay Vertex-II Pro. Cc m ngun ph hp vi c qutrnh tng hp v m phng v c pht trin v kim tra dng cng c


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Xilinx Synthesizs Tool (XST) cho tng hp logic v ModelSim cho m phng.Cc nh thit kcng thnh cng khi dng cc cng c tng hp logic v mphng khc. Cc m ngun VHDL khng nn b chnh sa trong bt k honcnh no.

KCPSM3 Module

Module KCPSM3 bao gm ALU, register file, scratchpad RAM, Ch duynht chc nng khng nm trong KCPSM3 l b nh chng trnh. Khai bocomponent v gn chn nh sau:

Kt ni vi b nh ROM chng trnh


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B nh ROM chng trnh ca PicoBlaze c dng trong thit kVHDL.T file assembler to ra file VHDL, nh ngha block RAM v khi to nidung cho RAM. File VHDL ny c th c dng cho c tng hp logic vm phng vi iu khin.

Sau y l khai bo component v gn cc thc th ca b nh chngtrnh trong FPGA:

Do , s cu trc ca vi iu khin PicoBlaze nh sau:

Hnh 3.25: S cu trc PicoBlaze Microcontroller

vit m lnh cho chng trnh (vi tn m rng l .psm) th chng tac th dng bt c trnh son tho no lp trnh da theo 31 lnh c

cung cp. V dng file thc thi KCPSM3.exe v cc form c nh ngha sn


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ca ROM di dng file .vhd, .coe, .v dch ra cc file .vhd, .v v cho vochng trnh FPGA.

phi hp hot ng ca tt c cc thnh phn trn, m bo h thng

hot ng chnh xc, ta phi c mt h thng iu khin trung tm. Trong n ny, chng em s dng mt vi x l nhng c tn l PicoBlaze iukhin hot ng ca cc khi x l trong FPGA, ng thi giao tip vi mytnh thng qua cng RS232 v khi iu khin giao tip RS232 : UARTController.

3.2.6.2. S cu trc ca khi x l trung tm

S cu trc ca khi x l dng PicoBlaze:

Hnh 3.26 : S khi iu khin trung tm v giao tip UART

Ngoi vi iu khin PicoBlaze, c s dng thm 2 component l UARTReceive v UART Transmit. Hai component c cung cp min ph biXilinx, bao gm b m v cc tn hiu trng thi giao tip vi cng RS232.

Vi iu khin PicoBlaze c nhim v nhn lnh iu khin t chngtrnh trn PC v ra cc lnh iu khin capture nh t camera v cc tnhiu la chn thut ton v kch hot khi x l frame nh lu trongSDRAM, ng thi nhn tn hiu done v bo vgiao din bit thut ton x l xong.

Thut ton ca chng trnh


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Chng trnh chnh lun lun nhn cc k t t giao din ngi dng vkim tra xem gi lnh vi c php g. V d: lnh bt u bng ch ci Cdng capture nh, bt u bng ch ci M chn thut ton x l nhM1 lc nhiu, M2 phn vng, v ra cc tn hiu iu khin tng

ng vo cc chn Algorithm Selection ca khi x l nh.

Khi x l ngt s c kch hot khi c tn hiu done tb x l nh vkhi xa tn hiu kch hot khi x l nh v gi messenger ln PC.

3.3. Thit kgiao din iu khin h thng

Giao din ca chng trnh c xy dng trn nn GUI (Graphic User

Interface) ca Matlab R2007a.

Giao din ca chng trnh iu khin nh h nh v di. Giao din nyc th thay i ti thi im bo v.

Hnh 3.27 : Giao din iu khin


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Chc nng

Chn thng sca cng RS232 thit lp giao tip RS232 vi mch phncng bn di. Mc nh chn cng COM1, tc 115200. C th la chn

kt ni hoc ngt kt ni vi RS232, c hp thoi hin th trng thi ca giaotip RS232.

Kch hot chip Video Decoder trn mch phn cng qua nt I2C giaotip I2C vi chip qua cng LPT. Mc nh chn cng LPT1, c thpht trinthm la chn cc cng LPT khc na.

Cho php download trc tip file cu hnh cho FPGA hoc Flash qua cng

LPT, nh cc nt bm phn LPT FPGA Programming.

Cho php la chn thut ton thc hin v c led hin th sth t thutton tng ng. Do cha c tn c thca tng thut ton c thnn mi cht tn l thut ton 1, thut ton 2, Mi khi kt thc thut ton u c bcin thng bo thc hin thnh cng.

Cho php kch hot capture nh t camera v t hin ln mn hnh

VGA. ang pht trin thc hin la chn gia capture mt nh v chplin tc khong 30 hnh/s.

3.4. M phng v kt qu

Phng n m phng

Yu cu ca bi ton m phng: thc hin tt cc thut ton x l nh

m svt trn mt frame, v nh v tng vt.

Phng n m phng y c thc hin nh sau: dng camera chiuvo mt tm bng mt mu (en) c cc vt c kch thc khc nhau. Khi ,dng chng trnh giao tip trn PC iu khin camera capture mt nhr nt, sau tin hnh thc hin tng thut ton theo trnh t nht nh vxc nh svt. Tng kt qu chy mi thut ton u hin th trc tip trnmn hnh VGA.


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Trnh t thc hin nh sau:

Thut ton 1 : Lc nh bng php lc Gausse, ng thi tnh ngngtrung bnh

Thut ton 2 : Phn ngng nh theo thut ton phn ngng, sdng ngng va tnh.

Thut ton 3 : Lm mnh.

Thut ton 4 : Lm y, khi phc nh.

Thut ton 5 : Thc hin gn nhn i tng, hin th s i tngtrong frame.

Thut ton 6 : Tnh ton cc c tnh ca ln lt tng i tng, ngthi hin i tng ln., hin th cc c tnh ca i tng cn xc nhra giao din. Hon thnh lt m phng.

Kt qu

Kt qu m phng cho thy vic thc thi cc thut ton v thit k hthng thc hin ng nh mong mun. Vic phn vng v nh nhn nhthnh cng. Tuy nhin, nu nh c nhng nhiu tng i ln ( dykhong hn 3 pixel ) th cn nhiu qu trnh lm mnh lin tip mi xa bhon ton c nhiu.


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Kt lunTrong cc gii php phn cng cho vic xy dng h thng th gic my

tnh, c th thy FPGA l mt trong nhng gii php ph hp nht. ViFPGA, chng ta c ththit kh thng theo tng khi hot ng song song,cho php tng tc x l ln nhiu ln so vi x l tun t. iu ny l rtquan trng i vi nhng h thng i hi tc x l nhanh, chng hnnh nhng cnh tay robot gp vt ang chuyn ng nhanh.

Trong n ny, chng em thc thi thnh cng mt h thng th gicmy vi nhim v l tch cc i tng trong mt nh, gn nhn v xc nhcc c trng hnh hc ca i tng. Vi kh nng x l nh vy, chng em

nhn thy hon ton c th m rng ti ra gii quyt cc bi ton x lnng cao nh :

Nhn dng : da trn cc c trng hnh hc ca i tng, ta cn cthnhn dng i tng, phc v cho bi ton nhn dng vt hoc chci v svsau. Vic nhn dng c thbng mng neural xy dng trc tiptrn FPGA, bng cch to ra cc neural nh cc n v x l kt ni vi nhau.

Xc nh i tng chuyn ng: i tng c x l y mi ch li tng tnh, trong khi camera truyn nh lin tc v i tng. Nu kthp cc qu trnh x l trong nhng thi im khc nhau, ta c thgii quyt

bi ton xc nh i tng chuyn ng v c tc chuyn ng ca n.Vic gii quyt bi ton ny c ngha thc tin rt ln i vi cc c cu

bm i tng chuyn ng.

Xc nh khong cch vt trong khng gian : Mch XST 3S 1000 c 2cng video. Thm vo , project ca chng ta cha chim ht mt na tinguyn ca h thng, trong khi nu thm mt project na, ta vn c thtndng nhng ti nguyn c. Do chng ta hon ton c ththc thi mt hthng vi 2 camera cng hot ng. iu ny cho php ta c thquan st cci tng trong khng gian 3D, thm ch xc nh hnh dng, kch thc vthtch ca chng. Ta cng c th xc nh khong cch gia cc i tngtrong khng gian nu kt hp kt qu x l c vi cc php tnh quang

hc chnh xc. Xa hn na, ta hon ton c thxy dng mt h thng th


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gic my gip cho vic di chuyn ca xe t hnh v cc thao tc ca h thngCNC i vi vt th3 chiu.

M rng kh nng giao tip ca cm bin th gic ph hp vi nhiu

chun ch khng ch ring RS232: chun Ethernet, USB, CAN, RS 485... gipcho thit b d dng tch hp vo cc h thng iu khin phn tn tht s.

Ci thin cc thut ton nhm lm tng kh nng x l, cht lng nhsau tin x l.

u l nhng ng dng rt c gi tr thc tin trong nhiu l nh vc,c bit l T ng iu khin, v c kh nng thc thi nu i su nghin

cu.

Qua qu trnh thc hin n ny, chng em cm thy hc c rtnhiu iu.

l k nng t nghin cu trong nhng lnh vc cn ht sc mi m ivi sinh vin iu khin t ng : l X l nh s , Th gic my tnh vcng ngh FPGA, trn nn tng nhng kin thc c s hc c nh

trng.

l k nng lm vic theo nhm : bng cch phn cng tng i hpl, chng em chia tch cng vic ra mt cch kh cn bng, m bo mingi pht huy ht s trng ca mnh, thc hin n mt cch tt nhttrong kh nng c th. y l mt trong nhng k nng quan trng nht chocng vic ca mt k s vsau

l k nng trnh by nhng tng , hiu bit v kin thc ca mnhvo mt n, nhm truyn ti mt cch y nht c thnhng g mnhhiu vlnh vc m mnh ang nghin cu.

Cui cng, cng phi ni rng d cgng rt nhiu, nhng chng emvn khng trnh khi nhng sai st, trong vic xy dng h thng, trong victrnh by lun vn. Nhng chng em vn lun thc c rng, nhng saist y cng l mt c hi cho chng em rn luyn k nng ca mnh : k

nng sa cha nhng sai st v khim khuyt, thc hin nhng ti, d


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n vsau mt cch hon chnh hn. tt c l nh s theo di, hng dn ,phn bin tn tnh v nghim tc ca cc thy, c trong hi ng bo v.

Chng em xin chn thnh cm n cc thy c v s tn ty y!


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Ti liu tham kho

[1]. Volnei A. Pedroni, Circuit Design with VHDL, MIT Press Cambridge,

Massachusetts London, England, 2004.

[2]. Texas Instruments, TVP5150PBS Ultralow-Power NTSC/PAL Video

Decoder, Texas Instruments Incorporated, May 2006.

[3]. D. Vanden Bout, XSA Board SDRAM Controller, XESS Corporation, July

12, 2005.

[4]. D. Vanden Bout, VGA Generator for the XSA Boards, XESS Corporation,

October 12, 2004.

[5]. D. Vanden Bout, Dualport Module for the SDRAM Controller, XESS

Corporation, July 12, 2005.

[6]. Karthikeyan Palanisamy, Interfacing Spartan-3 Devices with 166 MHz or

333 Mb/s DDR SDRAM Memories, Xilinx Corporation, October 14, 2004.

[7]. Anil K.Jail , Fundamentals Digital Image Processing, University of

California.

[8]. Xilinx Ltd, PicoBlaze 8-bit Embedded Microcontroller User Guide

UG129, www.xilinx.com, November 21, 2005.

[9]. Xilinx Ltd, Spartan-3E Starter Kit Board User Guide UG230 (v1.0),

www.xilinx.com, March 9, 2006.

[10]. Xilinx Ltd, Chapter 7 Implementing DDR SDRAM Controller MIG

User Guide UG086 (V2.0), www.xilinx.com, September 18, 2007.

[11]. Xilinx Ltd, System Generator for DSP Userguide Release 9.2.00,

www

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