46600  Landing  Parkway,  Fremont,  CA  94538  

Media  Contact:  Tim  Helms  (510)  438-­‐0148  X126  media@avalanche-­‐technology.com    

Company  Fact  Sheet  

Avalanche Non-Volatile Magnetic Memory To Revolutionize Enterprise Solid-State Storage

With  more  than  200  patents  filed  and  nearly  half  awarded  or  granted  for  its  work  in  cell,  circuit,  process  and  systems  implementation,  Avalanche  intends  to  become  the  market  leader  of  next  generation  enterprise-­‐class  solid-­‐state  storage  arrays,  built  from  the  ground  up  utilizing  its  own  Spin-­‐Transfer  Torque  Magnetic  RAM  (STT-­‐MRAM)  technology.  

Avalanche Memory – Application Everywhere

Avalanche’s  discrete  and  embedded  technology  also  finds  application  at  the  heart  of  any  electronics  device  requiring  non-­‐volatile  memory  –  everywhere.  

 

Avalanche Opportunity in Enterprise Storage

The  enterprise  storage  market  has  an  estimated  total  market  of  more  than  $35  billion  in  2014,  while  the  rapidly  growing  solid  state  array  segment  is  forecasted  by  Gartner  Group  to  reach  $4  billion  by  2016,  with  89%  CAGR,  growing  to  50%  of  the  overall  market  in  the  next  five  to  seven  years  to  around  $20  billion.  

 

Avalanche  is  vertically  integrating  its  STT-­‐MRAM  technology  into  enterprise  class  storage  array  systems  that  target  the  ultra-­‐  and  high-­‐performance  segments  of  the  enterprise  storage  market.      

By  next  year  Avalanche  will  release  a  fully  integrated  hardware  and  software  solid-­‐state  storage  array:    

• More  than  double  the  IOPs  and  reliability  and  using  half  the  power  of  current  solutions  

• Broad  set  of  features  required  for  widespread  enterprise  adoption  

• Significantly  reduced  COGs  than  existing  storage  arrays  

Avalanche Technology Facts:

Petro  Estakhri,  Founder,  President  and  CEO  leads  experienced  management  team Headquarters  in  Fremont,  California  

Privately  backed  by  Bessemer,  Leader  Ventures,  Qualcomm  Ventures,  Rogers  Venture  Partners,  Sequoia  Capital,  Thomvest  Ventures,  VTB  Capital  and  Vulcan  Capital  

   

 

 46600  Landing  Parkway,  Fremont,  CA  94538  

Media  Contact:  Tim  Helms  (510)  438-­‐0148  X126  media@avalanche-­‐technology.com    

Company  Fact  Sheet  

 

Avalanche Technology At Its Core

Avalanche’s  core  technology  is  non-­‐volatile  Magneto-­‐Resistive  Random  Access  Memory  (MRAM).  Unlike  early  instances  of  field  or  toggle  MRAM,  Avalanche  utilizes  a  revolutionary  spin  current  switching  technology  called  perpendicular  magnetic  tunnel  junction  (pMTJ),  allowing  for  lower  write  current,  smaller  cell  size,  with  excellent  scalability  to  future  technology  nodes  and  radiation  hard  applications.  The  Avalanche  cell  size  roadmap  begins  at  15F2  and  extends  below  1.0F2,  less  than  1/5th  the  size  of  any  current  memory  device.    This  will  lead  to  an  unprecedented  combination  of  low  cost  and  high  performance  features,  creating  numerous  application  opportunities  for  revolutionary  system  design.  

 Perpendicular  magnetic  tunnel  junction  (pMTJ)  cells  are  comprised  of  a  ferromagnetic  ‘pinned’  layer,  a  dielectric  barrier  layer  and  another  ferromagnetic  ‘free’  layer.    The  magnetic  orientation  of  the  pinned  layer  is  permanently  fixed  during  fabrication  and  the  free  layer  is  not,  so  it  can  change  direction  based  

on  the  direction  of  the  electrical  current  flowing  through  the  pMTJ  cell.    This  enables  two  binary  states  for  digital  data  storage.    The  resistance  of  the  pMTJ  cell  changes  from  low  to  high  when  the  magnetic  orientation  of  the  free  layer  is  changed.      

Avalanche  has  been  awarded  and  granted  extensive  patents  regarding  its  pMTJ  cells  and  STT-­‐MRAM  circuit  design.  

Targeting  gigabit  densities,  pMTJ  cell  size  can  extend  well  below  10nm.      The  switching  current  and  performance  variations  can  be  greatly  reduced  and  with  a  switching  speed  of  less  than  500  pico-­‐seconds,  it  is  ideally  suited  to  replace  high-­‐speed  SRAM.    The  TMR  ratio  (difference  between  high  and  low  resistance)  far  exceeds  100%,  making  it  an  excellent  medium  for  any  storage  application  requiring  data  read-­‐back  operations.  

A  fundamental  strength  of  Avalanche’s  discrete  memory  is  that  it  is  based  on  standard  CMOS  manufacturing.    Operating  on  a  fabless  basis  takes  advantage  of  existing  fab  capacity  and  equipment  to  deliver  lower  cost  products.    The  manufacturing  occurs  in  two  stages:  basic  CMOS  layers  and  pMTJ  layers.  Avalanche  utilizes  large  third-­‐party  foundries  for  the  CMOS  processing  while  the  proprietary  magnetic  processing  is  performed  either  at  the  foundry  or  at  Avalanche’s  own  facility.        

Avalanche  anticipates  delivering  its  first  SPMEMTM  (Spin  Programmable  Memory)  discrete  devices  and  licensing  its  first  AVRAMTM  embedded  SOC  applications  in  2014.    Avalanche’s  vertically  integrated  solid-­‐state  storage  array  solutions  are  expected  to  reach  the  market  in  2015.