August 12, 2005 Uppalapati et al.: VDAT'05 1

Glitch-Free Design of Low Power ASICs Using Customized Resistive

Feedthrough Cells

9th VLSI Design & Test Symposium – VDAT ’05Bangalore, August 10-13, 2005

Siri UppalapatiGDA Tech., Inc.

San Jose, CA 95131, USA

siri@gdatech.com

Michael L. BushnellRutgers University

Piscataway, NJ 08854, USA

bushnell@caip.rutgers.edu

Vishwani D. AgrawalAuburn University

Auburn, AL 36849, USA

vagrawal@eng.auburn.edu

August 12, 2005 Uppalapati et al.: VDAT'05 2

Motivation• Application Specific Integrated Circuit

(ASIC) chips employ standard cell design style.

• Dynamic power consumed by glitches in a CMOS circuit, though significant, can be reduced or eliminated by design.

• Existing glitch reduction techniques demand customized gate design, not suitable for a standard cell ASIC.

August 12, 2005 Uppalapati et al.: VDAT'05 3

Power Dissipation in CMOS Logic (0.25µ)

%75 %5%20

Ptotal (0→1) = CL VDD2

+ tscVDD Ipeak + VDDIleakage

CL

August 12, 2005 Uppalapati et al.: VDAT'05 4

Prior Work: Hazard Filtering

• Glitch is suppressed when the inertial delay of gate exceeds the differential input delay.

1 or 32

Filtering Effect of a gate

Reference: V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997.

or

2

2

August 12, 2005 Uppalapati et al.: VDAT'05 5

Prior Work: A Reduced Constraint Set LP Model for Glitch Removal

• Satisfy glitch suppression condition at all gates:Differential path delay at gate input < inertial delay

• Use a linear program (LP) to find delays– Path enumeration avoided– Reduced (linear) size of LP allows scalability

• Design gates with specified delays• 40-60% dynamic power savings in custom design• Procedure is not suitable for pre-designed cell

libraries

Reference: T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” VLSI Design 2003.

August 12, 2005 Uppalapati et al.: VDAT'05 6

Prior Work: ASIC• J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power

Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ’01– Transistor sizing results in 20 - 25% savings in power– Power optimized by minimizing parasitic capacitances– No glitch reduction attempted

• Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ’01– Mixed Integer Linear Program (MILP) to select from different

realizations of cells such that power consumption is minimized without violating delay constraints

– Sum of dynamic and leakage power is minimized– Library contains cells of varying sizes, supply voltages, and

threshold voltages– Achieved 79% power saving on an average– No glitch reduction attempted.

August 12, 2005 Uppalapati et al.: VDAT'05 7

New Glitch Removing Solution

• Balanced the differential delays at cell inputs:– Using delay elements called Resistive

Feedthrough cells

• Automated the delay element– Generation – Insertion into the circuit

August 12, 2005 Uppalapati et al.: VDAT'05 8

Comparison of Delay Elements

Delay

element

Average delay (ns)

Delay/Power

Delay/Area

I 0.28 0.22 .03

II 0.59 4.43 0.05

III 0.72 5.54 0.11

IV 0.63 1.05 0.16

II. n diffusion capacitor

III. Polysilicon resistor

IV. Transmission gate

I. Inverter pair

• Resistor shows– Maximum delay– Minimum power

and area per unit delay

– Hence, best delay element

• Resistive feed through cell– A fictitious buffer at

logic level

August 12, 2005 Uppalapati et al.: VDAT'05 9

Resistive Feedthrough Cell

• A parameterized cell

• Physical design is simple – easily automated

• No routing layers(M2 to M5) used – not an obstruction to the router

R□*(length of poly)

Width of polyR =

S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’sThesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004.

August 12, 2005 Uppalapati et al.: VDAT'05 10

RC Delay Model• CL varies during

transition (model not perfectly linear)

• Spectre simulation data stored as a 3D lookup table

• Average of signal rise and fall delays

• Linear interpolation used

TPLH + TPHL

2TP =

VinR

CL

Vout

CL R

TP

August 12, 2005 Uppalapati et al.: VDAT'05 11

Design Optimization Flow

Design Entry

Tech. Mapping

Layout

RemoveGlitches

Find delays from LP

Find resistor values from lookup table

Generate feed through cells and

modify netlist

August 12, 2005 Uppalapati et al.: VDAT'05 12

Results Circuit New Standard Cell Based Design Power saved (%)

in custom design Raja et al.

Area overhead (%)

Power saved (%)

4 bit ALU 29.5 23.7 N/A

c432 114.0 50.0 35.0

C499 86.0 32.0 29.0

C880 98.0 43.0 44.0

C1355 22.0 68.3 56.0

C2670 14.0 30.0 31.0

S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’sThesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004.

August 12, 2005 Uppalapati et al.: VDAT'05 13

Glitch Elimination on net86 in 4bit ALU

Source: Post layout simulation in SPECTRE

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Layouts of c880

Original layout of c880 Optimized layout of c880

Power saving = 43%Area increase= 98%

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Conclusion• Successfully devised a glitch removal method for the

standard cell based design style• Does not require redesign of the library cells• Does not increase the critical path delay• Modified design flow maintains the benefits of ASIC

• On an average • Dynamic power saving: 41%• Area overhead: 60%

• Possible ways to reduce area overhead• Cell replacements from existing library• On-the-fly-cell design• Adjust routing delays for glitch suppression