ATmega328PB Automotive Complete - Microchip Technology · The ATmega328PB Automotive is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing

ATmega328PB AutomotiveAVRreg Microcontroller with Core Independent Peripherals

and picoPowerreg Technology

Introduction

The picoPowerreg ATmega328PB Automotive is a low-power CMOS 8-bit microcontroller based on theAVRreg enhanced RISC architecture By executing powerful instructions in a single clock cycle theATmega328PB Automotive achieves throughputs close to 1 MIPSreg per MHz This empowers systemdesigners to optimize the device for power consumption versus processing speed

Features

High Performance Low-Power AVRreg 8-bit Microcontroller Familybull Advanced RISC Architecture

ndash 131 Powerful Instructionsndash Most Single Clock Cycle Executionndash 32 x 8 General Purpose Working Registersndash Fully Static Operationndash Up to 16 MIPS Throughput at 16 MHzndash On-Chip 2-Cycle Multiplier

bull High Endurance Nonvolatile Memory Segmentsndash 32 KB of In-System Self-Programmable Flash program memoryndash 1 KB EEPROMndash 2 KB Internal SRAMndash WriteErase Cycles 10000 Flash100000 EEPROMndash Optional Boot Code Section with Independent Lock Bits

bull In-System Programming by On-chip Boot Programbull True Read-While-Write Operation

ndash Programming Lock for Software Securitybull Peripheral Features

ndash Peripheral Touch Controller (PTC)bull Capacitive Touch Buttons Sliders and Wheelsbull 24 Self-Cap Channels and 144 Mutual Cap Channels

ndash Two 8-bit TimerCounters with Separate Prescaler and Compare Modendash Three 16-bit TimerCounters with Separate Prescaler Compare Mode and Capture Modendash Real-Time Counter with Separate Oscillatorndash Ten PWM Channelsndash 8-channel 10-bit ADC

copy 2018 Microchip Technology Inc Datasheet Complete DS40001980B-page 1

ndash Two Programmable Serial USARTsndash Two MasterSlave SPI Serial Interfacesndash Two Byte-Oriented Two-Wire Serial Interfaces (Philips I2C Compatible)ndash Programmable Watchdog Timer with Separate On-chip Oscillatorndash On-Chip Analog Comparatorndash Interrupt and Wake-Up on Pin Change

bull Special Microcontroller Featuresndash Power-On Reset and Programmable Brown-Out Detectionndash Internal 8 MHz Calibrated Oscillatorndash External and Internal Interrupt Sourcesndash Six Sleep Modes Idle ADC Noise Reduction Power-save Power-down Standby and Extended

Standbyndash Clock Failure Detection Mechanism and Switch to Internal 8 MHz RC Oscillator in case of Failurendash Individual Serial Number to Represent a Unique ID

bull IO and Packagesndash 27 Programmable IO Linesndash 32-pin TQFP and 32-pin Wettable Flank QFN

bull Operating Voltagendash 27 - 55V

bull Temperature Rangendash -40degC to 105degC

bull Speed Gradendash 0 - 16 MHz 45 ndash 55Vndash 0 - 8 MHz 27 ndash 55V

bull Power Consumption at 1 MHz 27V 25degCndash Active Mode 032 mAndash Power-Down Mode 02 μAndash Power-Save Mode 13 μA (Including 32 kHz RTC)

ATmega328PB Automotive

Table of Contents

Introduction1

Features 1

1 Description10

2 Configuration Summary 11

3 Ordering Information12

4 Block Diagram 13

5 Pin Configurations 1451 Pin Descriptions 15

6 IO Multiplexing18

7 Automotive Quality Grade 20

8 Resources 21

9 About Code Examples22

10 AVR CPU Core 23101 Overview 23102 ALU ndash Arithmetic Logic Unit 24103 Status Register24104 General Purpose Register File27105 Stack Pointer28106 Instruction Execution Timing 30107 Reset and Interrupt Handling 31

11 AVR Memories34111 Overview 34112 In-System Reprogrammable Flash Program Memory34113 SRAM Data Memory 35114 EEPROM Data Memory 36115 IO Memory37116 Register Description38

12 System Clock and Clock Options 47121 Clock Systems and Their Distribution 47122 Clock Sources 48123 Low-Power Crystal Oscillator 50124 Low Frequency Crystal Oscillator51125 Calibrated Internal RC Oscillator53

126 128 kHz Internal Oscillator 54127 External Clock 55128 Clock Output Buffer 55129 TimerCounter Oscillator561210 System Clock Prescaler561211 Register Description56

13 Clock Failure Detection (CFD)60131 Overview 60132 Features 60133 Operations60134 Timing Diagram 62135 Register Description62

14 PM - Power Management and Sleep Modes64141 Overview 64142 Sleep Modes 64143 BOD Disable65144 Idle Mode65145 ADC Noise Reduction Mode 65146 Power-Down Mode66147 Power-Save Mode66148 Standby Mode 67149 Extended Standby Mode671410 Power Reduction Registers671411 Minimizing Power Consumption671412 Register Description69

15 SCRST - System Control and Reset 74151 Resetting the AVR 74152 Reset Sources74153 Power-on Reset75154 External Reset76155 Brown-out Detection77156 Watchdog System Reset77157 Internal Voltage Reference77158 Watchdog Timer 78159 Register Description81

16 INT- Interrupts85161 Interrupt Vectors in ATmega328PB 85162 Register Description86

17 EXTINT - External Interrupts 89171 Pin Change Interrupt Timing89172 Register Description90

18 IO-Ports 100

181 Overview 100182 Ports as General Digital IO101183 Alternate Port Functions104184 Register Description 119

19 TC0 - 8-bit TimerCounter0 with PWM134191 Features 134192 Overview 134193 TimerCounter Clock Sources 136194 Counter Unit 136195 Output Compare Unit 137196 Compare Match Output Unit139197 Modes of Operation141198 TimerCounter Timing Diagrams 145199 Register Description147

20 TC1 3 4 - 16-bit TimerCounter1 3 4 with PWM159201 Features 159202 Overview 159203 Accessing 16-bit TimerCounter Registers160204 TimerCounter Clock Sources 163205 Counter Unit 163206 Input Capture Unit 164207 Compare Match Output Unit166208 Output Compare Units167209 Modes of Operation1692010 TimerCounter Timing Diagrams 1762011 Register Description178

21 TimerCounter 0 1 3 4 Prescalers215211 Internal Clock Source215212 Prescaler Reset215213 External Clock Source215214 Register Description217

22 TC2 - 8-bit TimerCounter2 with PWM and Asynchronous Operation219221 Features 219222 Overview 219223 TimerCounter Clock Sources 221224 Counter Unit 221225 Output Compare Unit 222226 Compare Match Output Unit224227 Modes of Operation225228 TimerCounter Timing Diagrams 229229 Asynchronous Operation of TimerCounter22302210 TimerCounter Prescaler 2322211 Register Description232

23 OCM - Output Compare Modulator 247231 Overview 247232 Description 247

24 SPI ndash Serial Peripheral Interface 249241 Features 249242 Overview 249243 SS Pin Functionality 253244 Data Modes253245 Register Description254

25 USART - Universal Synchronous Asynchronous Receiver Transceiver263251 Features 263252 Overview 263253 Block Diagram263254 Clock Generation264255 Frame Formats267256 USART Initialization 268257 Data Transmission ndash The USART Transmitter 269258 Data Reception ndash The USART Receiver 271259 Asynchronous Data Reception2742510 Multi-Processor Communication Mode 2782511 Examples of Baud Rate Setting 2792512 Register Description282

26 USARTSPI - USART in SPI Mode292261 Features 292262 Overview 292263 Clock Generation292264 SPI Data Modes and Timing293265 Frame Formats293266 Data Transfer295267 AVR USART MSPIM vs AVR SPI296268 Register Description297

27 TWI - Two-Wire Serial Interface 298271 Features 298272 Two-Wire Serial Interface Bus Definition298273 Data Transfer and Frame Format299274 Multi-Master Bus Systems Arbitration and Synchronization302275 Overview of the TWI Module304276 Using the TWI306277 Transmission Modes 309278 Multi-Master Systems and Arbitration 327279 Register Description328

28 AC - Analog Comparator 336

281 Overview 336282 Analog Comparator Multiplexed Input336283 Register Description337

29 ADC - Analog to Digital Converter341291 Features 341292 Overview 341293 Starting a Conversion343294 Prescaling and Conversion Timing344295 Changing Channel or Reference Selection346296 ADC Noise Canceler 348297 ADC Conversion Result 351298 Register Description352

30 PTC - Peripheral Touch Controller361301 Features 361302 Overview 361303 Block Diagram362304 Signal Description 363305 System Dependencies 363306 Functional Description364

31 DBG - debugWIRE On-chip Debug System365311 Features 365312 Overview 365313 Physical Interface365314 Software Break Points366315 Limitations of debugWIRE366316 Register Description366

32 BTLDR - Boot Loader Support ndash Read-While-Write Self-Programming 368321 Features 368322 Overview 368323 Application and Boot Loader Flash Sections368324 Read-While-Write and No Read-While-Write Flash Sections369325 Entering the Boot Loader Program371326 Boot Loader Lock Bits 372327 Addressing the Flash During Self-Programming373328 Self-Programming the Flash374329 Register Description382

33 MEMPROG - Memory Programming385331 Program And Data Memory Lock Bits385332 Fuse Bits 386333 Signature Bytes388334 Calibration Byte389335 Serial Number 389336 Page Size391

337 Parallel Programming Parameters Pin Mapping and Commands391338 Parallel Programming393339 Serial Downloading 400

34 Electrical Characteristics 406341 Absolute Maximum Ratings406342 DC Characteristics 406343 Power Consumption408344 Speed Grades 409345 Clock Characteristics409346 System and Reset Characteristics 410347 SPI Timing Characteristics 411348 Two-Wire Serial Interface Characteristics 413349 ADC Characteristics4153410 Parallel Programming Characteristics415

35 Typical Characteristics418351 Active Supply Current418352 Idle Supply Current421353 ATmega328PB Automotive Supply Current of IO Modules423354 Power-down Supply Current 424355 Pin Pull-Up 426356 Pin Driver Strength428357 Pin Threshold and Hysteresis 430358 BOD Threshold433359 Analog Comparator Offset4353510 Internal Oscillator Speed4363511 Current Consumption of Peripheral Units4393512 Current Consumption in Reset and Reset Pulse Width 442

36 Register Summary444

37 Instruction Set Summary 448

38 Packaging Information453381 32-Pin TQFP 453382 32-Pin VQFN454

39 Errata455391 Rev A455392 Rev C - D455393 Rev A - D 455

40 Revision History456

The Microchip Web Site 457

Customer Change Notification Service457

Customer Support 457

Microchip Devices Code Protection Feature 457

Legal Notice458

Trademarks 458

Quality Management System Certified by DNV459

Worldwide Sales and Service460

1 DescriptionThe ATmega328PB Automotive is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture By executing powerful instructions in a single clock cycle the ATmega328PBAutomotive achieves throughputs close to 1 MIPS per MHz This empowers system designer to optimizethe device for power consumption versus processing speed

The core combines a rich instruction set with 32 general purpose working registers All the 32 registersare directly connected to the Arithmetic Logic Unit (ALU) allowing two independent registers to beaccessed in a single instruction executed in one clock cycle The resulting architecture is more codeefficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers

The ATmega328PB Automotive provides the following features 32 KB of In-System Programmable Flashwith Read-While-Write capabilities 1 KB EEPROM 2 KB SRAM 27 general purpose IO lines 32general purpose working registers five flexible TimerCounters with compare modes internal andexternal interrupts two serial programmable USART two byte-oriented two-wire Serial Interface (I2C)two SPI serial ports an 8-channel 10-bit ADC in TQFP and QFNMLF package a programmableWatchdog Timer with internal Oscillator Clock failure detection mechanism and six software selectablepower saving modes The Idle mode stops the CPU while allowing the SRAM TimerCounters USARTtwo-wire Serial Interface SPI port and interrupt system to continue functioning PTC with enabling up to24 self-cap and 144 mutual-cap sensors The Power-Down mode saves the register contents but freezesthe Oscillator disabling all other chip functions until the next interrupt or hardware reset In Power-Savemode the asynchronous timer continues to run allowing the user to maintain a timer base while the restof the device is sleeping Also ability to run PTC in Power-Save modewake-up on touch and DynamicONOFF of PTC analog and digital portion The ADC Noise Reduction mode stops the CPU and all IOmodules except asynchronous timer PTC and ADC to minimize switching noise during ADCconversions In Standby mode the crystalresonator Oscillator is running while the rest of the device issleeping This allows very fast start-up combined with low power consumption

The device is manufactured using high-density non-volatile memory technology The On-chip ISP Flashallows the program memory to be reprogrammed In-System through an SPI serial interface by aconventional nonvolatile memory programmer or by an On-chip Boot program running on the AVR coreThe Boot program can use any interface to download the application program in the Application Flashmemory Software in the Boot Flash section will continue to run while the Application Flash section isupdated providing true Read-While-Write operation By combining an 8-bit RISC CPU with In-SystemSelf-Programmable Flash on a monolithic chip the ATmega328PB Automotive is a powerfulmicrocontroller that provides a highly flexible and cost-effective solution to many embedded controlapplications

The ATmega328PB Automotive is supported by a full suite of program and system development toolsincluding C Compilers Macro Assemblers Program DebuggerSimulators In-Circuit Emulators andEvaluation kits

ATmega328PB AutomotiveDescription

2 Configuration SummaryFeatures ATmega328PB Automotive

Pin count 32

Flash (KB) 32

SRAM (KB) 2

EEPROM (KB) 1

General Purpose IO pins 27

TWI (I2C) 2

USART 2

ADC 10-bit 15 ksps

ADC channels 8

AC propagation delay 400 ns (Typical)

8-bit TimerCounters 2

PWM channels 10

PTC Available

Clock Failure Detector (CFD) Available

Output Compare Modulator (OCM1C2) Available

ATmega328PB AutomotiveConfiguration Summary

3 Ordering InformationSpeed [MHz] Power Supply [V] Ordering Code Package (GPC)(1) Operational Range

16 27 - 55 ATMEGA328PB-ABTVAO TQFP (AUT) Automotive (-40degC to105degC)

16 27 - 55 ATMEGA328PB-MBTVAO VQFN (ZBS) Automotive (-40degC to105degC)

Note 1 Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances

(RoHS directive) Also Halide free and fully Green2 Tape amp Reel3 The above are generic ordering codes without dedicated PPAP

Package Type

AUT 32-lead (MA) 080 mm Pitch 7x7x100 mm Body size Thin Profile Plastic Quad Flat Package (TQFP)

ZBS 32-lead (21) 050 mm Pitch 50x50x09 mm Body size Very Thin Quad Flat No Lead Package (VQFN)Sawn Wettable Flanks

ATmega328PB AutomotiveOrdering Information

4 Block DiagramFigure 4-1 Block Diagram

USART 0

ADCADC[70]AREF

RxD0TxD0XCK0

MISO1MOSI1SCK1SS1

IOPORTS

DATABUS

GPIOR[20]

EXTINT

FLASHNVM

programming

debugWire

DATABUS

TC 0(8-bit)

ACAIN0AIN1ACO

EEPROM

EEPROMIF

PTCX[150]Y[230]

TC 1(16-bit)

OC1ABT1

TC 3(16-bit)

TC 4(16-bit)

OC3ABT3

OC4ABT4

TC 2(8-bit async)

SDA0SCL0

SDA1SCL1

USART 1RxD1TxD1XCK1

InternalReference

Watchdog Timer

Power management

and clock control

Clock generation8MHz

Calib RC

128kHz int osc

32768kHz XOSC

External clock

Power SupervisionPORBOD amp

XTAL2 TOSC2

XTAL1 TOSC1

16MHz LP XOSC

Crystal failure detection

PCINT[270]INT[10]

T0OC0AOC0B

MISO0MOSI0SCK0SS0

OC2AOC2B

PB[70]PC[6 0]PD[70]PE[30]

PE[32] PC[50]AREF

PB[50] PE[10] PD[70]PB[50] PE[10] PD[70] PE[32] PC[50]

PE[30] PD[70] PC[60] PB[70]PD3 PD2

PB1 PB2PD5PB0

PB3PD3

PD0 PD2PE3PE2

PD1 PD2PE1PE0

PD0PD1PD4

PC0PE3PC1PE2

PC4PC5

PE0PE1

PB4PB3PB5

PD4PD6PD5

PB4PB3PB5PB2

SPIPROG

PARPROG

PD6PD7PE0

ATmega328PB AutomotiveBlock Diagram

5 Pin ConfigurationsFigure 5-1 32 TQFP Pinout ATmega328PB Automotive

32 31 30 29 28 27 265

9 10 11 12 13 14 15 16

PC0 (ADC0PTCYMISO1)

PC1 (ADC1PTCYSCK1)

PE2 (ADC6PTCYICP3SS1)

PE3 (ADC7PTCYT3MOSI1)

(XCK0T0PTCXY) PD4

(SDA1ICP4ACOPTCXY) PE0

(SCL1T4PTCXY) PE1

(XTAL1TOSC1) PB6

(XTAL2TOSC2) PB7

(OC2BINT1PTCXY) PD3

Ground

Programmingdebug

Digital

Analog

CrystalCLK

PB5 (PTCXYXCK1SCK0)

ATmega328PB AutomotivePin Configurations

Figure 5-2 32 VQFN Pinout ATmega328PB Automotive

32 31 30 29 28 27 26

9 10 11 12 13 14 15 16

PC0 (ADC0PTCYMISO1)

PC1 (ADC1PTCYSCK1)

PE3 (ADC7PTCYT3MOSI1)(P

(XCK0T0PTCXY) PD4

(SCL1T4PTCXY) PE1

(XTAL1TOSC1) PB6

(XTAL2TOSC2) PB7

(OC2BINT1PTCXY) PD3

Bottom pad should be soldered to ground

PB5 (PTCXYXCK1SCK0)

51 Pin Descriptions

511 VCCDigital supply voltage

512 GNDGround

513 Port B (PB[70]) XTAL1XTAL2TOSC1TOSC2Port B is an 8-bit bi-directional IO port with internal pull-up resistors (selected for each pin) The Port Boutput buffers have symmetrical drive characteristics with both high sink and source capability As inputsPort B pins that are externally pulled low will source current if the pull-up resistors are activated The PortB pins are tri-stated during a reset condition even if the clock is not running

Depending on the clock selection fuse settings PB6 can be used as input to the inverting Oscillatoramplifier and input to the internal clock operating circuit

Depending on the clock selection fuse settings PB7 can be used as output from the inverting Oscillatoramplifier

If the Internal Calibrated RC Oscillator is used as chip clock source PB[76] is used as TOSC[21] inputfor the Asynchronous TimerCounter2 if the AS2 bit in ASSR is set

514 Port C (PC[50])Port C is a 7-bit bi-directional IO port with internal pull-up resistors (selected for each pin) The PC[50]output buffers have symmetrical drive characteristics with both high sink and source capability As inputsPort C pins that are externally pulled low will source current if the pull-up resistors are activated The PortC pins are tri-stated during a reset condition even if the clock is not running

515 PC6RESETIf the RSTDISBL Fuse is programmed PC6 is used as an IO pin Note that the electrical characteristicsof PC6 differ from those of the other pins of Port C

If the RSTDISBL Fuse is unprogrammed PC6 is used as a Reset input A low level on this pin for longerthan the minimum pulse length will generate a Reset even if the clock is not running Shorter pulses arenot guaranteed to generate a Reset

The various special features of Port C are elaborated in the Alternate Functions of Port C section

516 Port D (PD[70])Port D is an 8-bit bi-directional IO port with internal pull-up resistors (selected for each pin) The Port Doutput buffers have symmetrical drive characteristics with both high sink and source capability As inputsPort D pins that are externally pulled low will source current if the pull-up resistors are activated The PortD pins are tri-stated during a reset condition even if the clock is not running

517 Port E (PE[30])Port E is a 4-bit bi-directional IO port with internal pull-up resistors (selected for each pin) The Port Eoutput buffers have symmetrical drive characteristics with both high sink and source capability As inputsPort E pins that are externally pulled low will source current if the pull-up resistors are activated The PortE pins are tri-stated during a reset condition even if the clock is not running

518 AVCC

AVCC is the supply voltage pin for the AD Converter PC[30] and PE[32] It should be externallyconnected to VCC even if the ADC is not used If the ADC is used it should be connected to VCC througha low-pass filter Note that PC[64] use digital supply voltage VCC

519 AREFAREF is the analog reference pin for the AD Converter

5110 ADC[76] (TQFP and VFQFN Package Only)In the TQFP and VFQFN package ADC[76] serve as analog inputs to the AD converter These pins arepowered by the analog supply and serve as 10-bit ADC channels

6 IO MultiplexingEach pin is by default controlled by the PORT as a general purpose IO and alternatively it can beassigned to one of the peripheral functions

The following table describes the peripheral signals multiplexed to the PORT IO pins

Table 6-1 PORT Function Multiplexing

No PAD EXTINT PCINT ADCAC PTC X PTC Y OSC TC USART I2C SPI

1 PD[3] INT1 PCINT19 X3 Y11 OC2B

2 PD[4] PCINT20 X4 Y12 T0 XCK0

3 PE[0] PCINT24 ACO X8 Y16 ICP4 SDA1

6 PE[1] PCINT25 X9 Y17 T4 SCL1

7 PB[6] PCINT6 XTAL1TOSC1

9 PD[5] PCINT21 X5 Y13 OC0B T1

10 PD[6] PCINT22 AIN0 X6 Y14 OC0A

11 PD[7] PCINT23 AIN1 X7 Y15

12 PB[0] PCINT0 X10 Y18 CLKO ICP1

13 PB[1] PCINT1 X11 Y19 OC1A

14 PB[2] PCINT2 X12 Y20 OC1B SS0

15 PB[3] PCINT3 X13 Y21 OC2A TXD1 MOSI0

16 PB[4] PCINT4 X14 Y22 RXD1 MISO0

17 PB[5] PCINT5 X15 Y23 XCK1 SCK0

18 AVCC

19 PE[2] PCINT26 ADC6 Y6 ICP3 SS1

20 AREF

21 GND

22 PE[3] PCINT27 ADC7 Y7 T3 MOSI1

23 PC[0] PCINT8 ADC0 Y0 MISO1

24 PC[1] PCINT9 ADC1 Y1 SCK1

25 PC[2] PCINT10 ADC2 Y2

27 PC[4] PCINT12 ADC4 Y4 SDA0

28 PC[5] PCINT13 ADC5 Y5 SCL0

29 PC[6]RESET PCINT14

30 PD[0] PCINT16 X0 Y8 OC3A RXD0

ATmega328PB AutomotiveIO Multiplexing

31 PD[1] PCINT17 X1 Y9 OC4A TXD0

32 PD[2] INT0 PCINT18 X2 Y10 OC3B OC4B

7 Automotive Quality GradeThe devices have been manufactured according to the most stringent requirements of the internationalstandard ISOTS 16949 This data sheet contains limit values extracted from the results of extensivecharacterization (temperature and voltage)

The quality and reliability have been verified during regular product qualification as per AEC-Q100 grade2 (ndash40degC to +105degC)

Table 7-1 Temperature Grade Identification for Automotive Products

Temperature (degC) Temperature Identifier Comments

ndash40 to +105 B Automotive temperature grade 2

ATmega328PB AutomotiveAutomotive Quality Grade

8 ResourcesA comprehensive set of development tools application notes and datasheets are available for downloadon httpwwwmicrochipcomdesign-centers8-bitmicrochip-avr-mcus

ATmega328PB AutomotiveResources

9 About Code ExamplesThis documentation contains simple code examples that briefly show how to use various parts of thedevice These code examples assume that the part specific header file is included before compilation Beaware that not all C compiler vendors include bit definitions in the header files and interrupt handling in Cis compiler dependent Confirm with the C compiler documentation for more details

For IO Registers located in extended IO map ldquoINrdquo ldquoOUTrdquo ldquoSBISrdquo ldquoSBICrdquo ldquoCBIrdquo and ldquoSBIrdquo instructionsmust be replaced with instructions that allow access to extended IO Typically ldquoLDSrdquo and ldquoSTSrdquocombined with ldquoSBRSrdquo ldquoSBRCrdquo ldquoSBRrdquo and ldquoCBRrdquo

ATmega328PB AutomotiveAbout Code Examples

10 AVR CPU Core

101 OverviewThis section discusses the AVR core architecture in general The main function of the CPU core is toensure correct program execution The CPU must therefore be able to access memories performcalculations control peripherals and handle interrupts

Figure 10-1 Block Diagram of the AVR Architecture

Register file

Flash program memory

Program counter

Instruction register

Instruction decode

Data memory

ALUStatus register

R0R1R2R3R4R5R6R7R8R9

R10R11R12R13R14R15R16R17R18R19R20R21R22R23R24R25

R26 (XL)R27 (XH)R28 (YL)R29 (YH)R30 (ZL)R31 (ZH)

Stack pointer

In order to maximize performance and parallelism the AVR uses a Harvard architecture ndash with separatememories and buses for program and data Instructions in the program memory are executed with asingle level pipelining While one instruction is being executed the next instruction is pre-fetched from theprogram memory This concept enables instructions to be executed in every clock cycle The programmemory is In-System Reprogrammable Flash memory

The fast-access register file contains 32 x 8-bit general purpose working registers with a single clockcycle access time This allows single-cycle Arithmetic Logic Unit (ALU) operation In a typical ALUoperation two operands are output from the register file the operation is executed and the result isstored back in the register file ndash in one clock cycle

Six of the 32 registers can be used as three 16-bit indirect address register pointers for data spaceaddressing ndash enabling efficient address calculations One of these address pointers can be used as an

ATmega328PB AutomotiveAVR CPU Core

address pointer for lookup tables in Flash program memory These added function registers are the 16-bitX- Y- and Z-register described later in this section

The ALU supports arithmetic and logic operations between registers or between a constant and aregister Single register operations can also be executed in the ALU After an arithmetic operation theStatus register is updated to reflect information about the result of the operation

Program flow is provided by conditional and unconditional jump and call instructions able to directlyaddress the whole address space Most AVR instructions have a single 16-bit word format Everyprogram memory address contains a 16- or 32-bit instruction

Program Flash memory space is divided into two sections the Boot Program section and the ApplicationProgram section Both sections have dedicated Lock bits for write and readwrite protection The SPMinstruction that writes into the Application Flash memory section must reside in the Boot Program section

During interrupts and subroutine calls the return address Program Counter (PC) is stored on the StackThe Stack is effectively allocated in the general data SRAM and consequently the Stack size is onlylimited by the total SRAM size and the usage of the SRAM All user programs must initialize the StackPointer (SP) in the Reset routine (before subroutines or interrupts are executed) The SP is readwriteaccessible in the IO space The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture

The memory spaces in the AVR architecture are all linear and regular memory maps

A flexible interrupt module has its control registers in the IO space with an additional global interruptenable bit in the Status register All interrupts have a separate interrupt vector in the interrupt vector tableThe interrupts have priority in accordance with their interrupt vector position The lower the interruptvector address the higher the priority

The IO memory space contains 64 addresses for CPU peripheral functions as Control registers SPI andother IO functions The IO memory can be accessed directly or as the data space locations followingthose of the register file 0x20 - 0x5F In addition this device has extended IO space from 0x60 - 0xFF inSRAM where only the STSTSSTD and LDLDSLDD instructions can be used

102 ALU ndash Arithmetic Logic UnitThe high-performance AVR ALU operates in direct connection with all the 32 general purpose workingregisters Within a single clock cycle arithmetic operations between general purpose registers orbetween a register and an immediate are executed The ALU operations are divided into three maincategories ndash arithmetic logical and bit-functions Some implementations of the architecture also providea powerful multiplier supporting both signedunsigned multiplication and fractional format See InstructionSet Summary section for a detailed description

Related Links339 Serial Downloading

Name SPSR1Offset 0xAD [ID-000004d0]Reset 0x00

Bit 7 ndash SPIF1 SPI Interrupt Flag 1When a serial transfer is complete the SPIF Flag is set An interrupt is generated if SPIE in SPCR is setand global interrupts are enabled If SS is an input and is driven low when the SPI is in Master mode thiswill also set the SPIF Flag SPIF is cleared by hardware when executing the corresponding interrupthandling vector Alternatively the SPIF bit is cleared by first reading the SPI Status Register with SPIFset then accessing the SPI Data Register (SPDR)

Bit 6 ndash WCOL1 Write Collision Flag 1The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer The WCOL bit (andthe SPIF bit) are cleared by first reading the SPI Status Register with WCOL set and then accessing theSPI Data Register

Bit 0 ndash SPI2X1 Double SPI Speed Bit 1When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is inMaster mode (refer to Table 24-5) This means that the minimum SCK period will be two CPU clockperiods When the SPI is configured as Slave the SPI is only guaranteed to work at fosc4 or lower

2455 SPI Data Register 0

Name SPDR0Offset 0x4E [ID-000004d0]Reset 0xXXProperty When addressing as IO Register address offset is 0x2E

Bit 7 6 5 4 3 2 1 0 SPID[70]

Bits 70 ndash SPID[70] SPI DataThe SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be read

Name SPDR1Offset 0xAE [ID-000004d0]Reset 0xXX

Bit 7 6 5 4 3 2 1 0 SPID1[70]

Bits 70 ndash SPID1[70] SPI Data 1The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be read

25 USART - Universal Synchronous Asynchronous Receiver Transceiver

251 Featuresbull Two USART instances USART0 USART1bull Full Duplex Operation (Independent Serial Receive and Transmit Registers)bull Asynchronous or Synchronous Operationbull Master or Slave Clocked Synchronous Operationbull High-Resolution Baud Rate Generatorbull Supports Serial Frames with 5 6 7 8 or 9 data bits and 1 or 2 stop bitsbull Odd or Even Parity Generation and Parity Check Supported by Hardwarebull Data OverRun Detectionbull Framing Error Detectionbull Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filterbull Three Separate Interrupts on TX Complete TX Data Register Empty and RX Completebull Multi-processor Communication Modebull Double Speed Asynchronous Communication Modebull Start Frame Detection

252 OverviewThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highlyflexible serial communication device

The USART can also be used in Master SPI mode The Power Reduction USART bit in the PowerReduction Register (PRRPRUSARTn) must be written to 0 in order to enable USARTn USART 0 and 1are in PRR0

Related Links26 USARTSPI - USART in SPI Mode18 IO-Ports5 Pin Configurations14123 PRR0

253 Block DiagramIn the USART Block Diagram the CPU accessible IO Registers and IO pins are shown in bold Thedashed boxes in the block diagram separate the three main parts of the USART (listed from the top)Clock Generator Transmitter and Receiver Control Registers are shared by all units The ClockGeneration logic consists of synchronization logic for external clock input used by synchronous slaveoperation and the baud rate generator The XCKn (Transfer Clock) pin is only used by synchronoustransfer mode The Transmitter consists of a single write buffer a serial Shift Register Parity Generatorand Control logic for handling different serial frame formats The write buffer allows a continuous transferof data without any delay between frames The Receiver is the most complex part of the USART moduledue to its clock and data recovery units The recovery units are used for asynchronous data reception Inaddition to the recovery units the Receiver includes a Parity Checker Control logic a Shift Register and

ATmega328PB AutomotiveUSART - Universal Synchronous Asynchronous R

a two-level receive buffer (UDRn) The Receiver supports the same frame formats as the Transmitter andcan detect Frame Error Data OverRun and Parity Errors

Figure 25-1 USART Block Diagram

PARITYGENERATOR

UBRRn [HL]

UDRn(Transmit)

UCSRnA UCSRnB UCSRnC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER RxDn

TxDnPINCONTROL

UDRn (Receive)

PINCONTROL

DATARECOVERY

CLOCKRECOVERY

PINCONTROL

TXCONTROL

RXCONTROL

PARITYCHECKER

SYNC LOGIC

Clock Generator

Transmitter

Receiver

Note Refer to the Pin Configurations and the IO-Ports description for USART pin placement

254 Clock GenerationThe Clock Generation logic generates the base clock for the Transmitter and Receiver The USARTsupports four modes of clock operation Normal asynchronous Double Speed asynchronous Mastersynchronous and Slave synchronous mode The USART Mode Select bit 0 in the USART Control andStatus Register n C (UCSRnCUMSELn0) selects between asynchronous and synchronous operationDouble Speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA RegisterWhen using synchronous mode (UMSELn0=1) the Data Direction Register for the XCKn pin(DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode) TheXCKn pin is only active when using synchronous mode

Below is a block diagram of the clock generation logic

Figure 25-2 Clock Generation Logic Block Diagram

PrescalingDown-Counter 2

UBRRn+1

SyncRegister

XCKnPin

UMSELn

DDR_XCKn

DDR_XCKnrxclk

Detector

UCPOLn

Signal description

bull txclk Transmitter clock (internal signal)bull rxclk Receiver base clock (internal signal)bull xcki Input from XCKn pin (internal signal) Used for synchronous slave operationbull xcko Clock output to XCKn pin (internal signal) Used for synchronous master operationbull fosc System clock frequency

2541 Internal Clock Generation ndash The Baud Rate GeneratorInternal clock generation is used for the asynchronous and the synchronous master modes of operationThe description in this section refers to the Clock Generation Logic block diagram in the previous section

The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as aprogrammable prescaler or baud rate generator The down-counter running at system clock (fosc) isloaded with the UBRRn value each time the counter has counted down to zero or when the UBRRnLRegister is written A clock is generated each time the counter reaches zero This clock is the baud rategenerator clock output (= fosc(UBRRn+1)) The Transmitter divides the baud rate generator clock outputby 2 8 or 16 depending on the mode The baud rate generator output is used directly by the Receiverrsquosclock and data recovery units However the recovery units use a state machine that uses 2 8 or 16states depending on the mode set by the state of the UMSEL U2Xn and DDR_XCK bits

The table below contains equations for calculating the baud rate (in bits per second) and for calculatingthe UBRRn value for each mode of operation using an internally generated clock source

Table 25-1 Equations for Calculating Baud Rate Register Setting

Operating Mode Equation for Calculating BaudRate(1)

Equation for Calculating UBRRnValue

Asynchronous Normal mode(U2Xn = 0) BAUD = OSC16 + 1 = OSC16BAUD minus 1Asynchronous Double Speedmode (U2Xn = 1) BAUD = OSC8 + 1 = OSC8BAUD minus 1Synchronous Master mode BAUD = OSC2 + 1 = OSC2BAUD minus 1

Note 1 The baud rate is defined to be the transfer rate in bits per second (bps)

BAUD Baud rate (in bits per second bps)

fOSC System oscillator clock frequency

UBRRn Contents of the UBRRnH and UBRRnL Registers (0-4095)Some examples of UBRRn values for some system clock frequencies are found in Examplesof Baud Rate Settings

2542 Double Speed Operation (U2Xn)The transfer rate can be doubled by setting the U2Xn bit in UCSRnA Setting this bit only has effect onthe asynchronous operation Set this bit to zero when using synchronous operation

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transferrate for asynchronous communication However in this case the Receiver will only use half the numberof samples (reduced from 16 to 8) for data sampling and clock recovery and therefore a more accuratebaud rate setting and system clock are required when this mode is used

For the Transmitter there are no downsides

2543 External ClockExternal clocking is used by the synchronous slave modes of operation The description in this sectionrefers to the Clock Generation Logic block diagram in the previous section

External clock input from the XCKn pin is sampled by a synchronization register to minimize the chanceof meta-stability The output from the synchronization register must then pass through an edge detectorbefore it can be used by the Transmitter and Receiver This process introduces a two CPU clock perioddelay and therefore the maximum external XCKn clock frequency is limited by the following equationXCKn lt OSC4The value of fosc depends on the stability of the system clock source It is therefore recommended to addsome margin to avoid possible loss of data due to frequency variations

2544 Synchronous Clock OperationWhen synchronous mode is used (UMSEL = 1) the XCKn pin will be used as either clock input (Slave) orclock output (Master) The dependency between the clock edges and data sampling or data change is thesame The basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of theedge the data output (TxDn) is changed

Figure 25-3 Synchronous Mode XCKn Timing

RxDn TxDn

XCKn UCPOL = 0

UCPOL = 1

Sample

The UCPOL bit UCRSC selects which XCKn clock edge is used for data sampling and which is used fordata change As the above timing diagram shows when UCPOL is zero the data will be changed atrising XCKn edge and sampled at falling XCKn edge If UCPOL is set the data will be changed at fallingXCKn edge and sampled at rising XCKn edge

255 Frame FormatsA serial frame is defined to be one character of data bits with synchronization bits (start and stop bits)and optionally a parity bit for error checking The USART accepts all 30 combinations of the following asvalid frame formats

bull 1 start bitbull 5 6 7 8 or 9 data bitsbull no even or odd parity bitbull 1 or 2 stop bits

A frame starts with the start bit followed by the data bits (from five up to nine data bits in total) first theleast significant data bit then the next data bits ending with the most significant bit If enabled the paritybit is inserted after the data bits before the one or two stop bits When a complete frame is transmitted itcan be directly followed by a new frame or the communication line can be set to an idle (high) state thefigure below illustrates the possible combinations of the frame formats Bits inside brackets are optional

Figure 25-4 Frame Formats

10 2 3 4 [5] [6] [7] [8] [P]St Sp (St IDLE)(IDLE)

St Start bit always low

(n) Data bits (0 to 8)

P Parity bit Can be odd or even

Sp Stop bit always high

IDLE No transfers on the communication line (RxDn or TxDn) An IDLE line must be high

The frame format used by the USART is set bybull Character Size bits (UCSRnCUCSZn[20]) select the number of data bits in the framebull Parity Mode bits (UCSRnCUPMn[10]) enable and set the type of parity bitbull Stop Bit Select bit (UCSRnCUSBSn) select the number of stop bits The Receiver ignores the

second stop bit

The Receiver and Transmitter use the same setting Note that changing the setting of any of these bitswill corrupt all ongoing communication for both the Receiver and Transmitter An FE (Frame Error) willonly be detected in cases where the first stop bit is zero

2551 Parity Bit CalculationThe parity bit is calculated by doing an exclusive-or of all the data bits If odd parity is used the result ofthe exclusive or is inverted The relation between the parity bit and data bits is as followseven = minus 1oplushellipoplus3oplus2oplus1oplus0oplus 0

odd = minus 1oplushellipoplus3oplus2oplus1oplus0oplus 1Peven Parity bit using even parity

Podd Parity bit using odd parity

dn Data bit n of the character

If used the parity bit is located between the last data bit and first stop bit of a serial frame

256 USART InitializationThe USART has to be initialized before any communication can take place The initialization processnormally consists of setting the baud rate setting frame format and enabling the Transmitter or theReceiver depending on the usage For interrupt driven USART operation the Global Interrupt Flag shouldbe cleared (and interrupts globally disabled) when doing the initialization

Before doing a re-initialization with changed baud rate or frame format be sure that there are no ongoingtransmissions during the period the registers are changed The TXC Flag (UCSRnATXC) can be used tocheck that the Transmitter has completed all transfers and the RXC Flag can be used to check that thereare no unread data in the receive buffer The UCSRnATXC must be cleared before each transmission(before UDRn is written) if it is used for this purpose

The following simple USART initialization code examples show one assembly and one C function that areequal in functionality The examples assume asynchronous operation using polling (no interrupts enabled)and a fixed frame format The baud rate is given as a function parameter For the assembly code thebaud rate parameter is assumed to be stored in the r17 r16 Registers

USART_Init Set baud rate to UBRR0 out UBRR0H r17 out UBRR0L r16 Enable receiver and transmitter ldi r16 (1ltltRXEN0)|(1ltltTXEN0) out UCSR0Br16 Set frame format 8data 2stop bit ldi r16 (1ltltUSBS0)|(3ltltUCSZ00) out UCSR0Cr16 ret

C Code Example

define FOSC 1843200 Clock Speeddefine BAUD 9600define MYUBRR FOSC16BAUD-1void main( void ) USART_Init(MYUBRR) void USART_Init( unsigned int ubrr) Set baud rate UBRR0H = (unsigned char)(ubrrgtgt8) UBRR0L = (unsigned char)ubrr Enable receiver and transmitter UCSR0B = (1ltltRXEN0)|(1ltltTXEN0) Set frame format 8data 2stop bit

UCSR0C = (1ltltUSBS0)|(3ltltUCSZ00)

More advanced initialization routines can be written to include frame format as parameters disableinterrupts and so on However many applications use a fixed setting of the baud and control registersand for these types of applications the initialization code can be placed directly in the main routine or becombined with initialization code for other IO modules

257 Data Transmission ndash The USART TransmitterThe USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB RegisterWhen the Transmitter is enabled the normal port operation of the TxDn pin is overridden by the USARTand given the function as the Transmitterrsquos serial output The baud rate mode of operation and frameformat must be set up once before doing any transmissions If synchronous operation is used the clockon the XCKn pin will be overridden and used as transmission clock

2571 Sending Frames with 5 to 8 Data BitsA data transmission is initiated by loading the transmit buffer with the data to be transmitted The CPUcan load the transmit buffer by writing to the UDRn IO location The buffered data in the transmit bufferwill be moved to the Shift Register when the Shift Register is ready to send a new frame The ShiftRegister is loaded with new data if it is in an idle state (no ongoing transmission) or immediately after thelast stop bit of the previous frame is transmitted When the Shift Register is loaded with new data it willtransfer one complete frame at the rate given by the Baud Register U2Xn bit or by XCKn depending onthe mode of operation

The following code examples show a simple USART transmit function based on polling of the DataRegister Empty (UDRE) Flag When using frames with less than eight bits the most significant bitswritten to the UDR0 are ignored The USART 0 has to be initialized before the function can be used Forthe assembly code the data to be sent is assumed to be stored in Register R17

USART_Transmit Wait for empty transmit buffer in r17 UCSR0A sbrs r17 UDRE rjmp USART_Transmit Put data (r16) into buffer sends the data out UDR0r16 ret

C Code Example

void USART_Transmit( unsigned char data ) Wait for empty transmit buffer while ( ( UCSR0A amp (1ltltUDRE)) ) Put data into buffer sends the data UDR0 = data

The function simply waits for the transmit buffer to be empty by checking the UDRE Flag before loading itwith new data to be transmitted If the Data Register Empty interrupt is utilized the interrupt routine writesthe data into the buffer

2572 Sending Frames with 9 Data BitsIf 9-bit characters are used (UCSZn = 7) the ninth bit must be written to the TXB8 bit in UCSRnB beforethe low byte of the character is written to UDRn

The ninth bit can be used for indicating an address frame when using multiprocessor communicationmode or for another protocol handling as for example synchronization

The following code examples show a transmit function that handles 9-bit characters For the assemblycode the data to be sent is assumed to be stored in registers R17R16

USART_Transmit Wait for empty transmit buffer in r18 UCSR0A sbrs r18 UDRE rjmp USART_Transmit Copy 9th bit from r17 to TXB8 cbi UCSR0BTXB8 sbrc r170 sbi UCSR0BTXB8 Put LSB data (r16) into buffer sends the data out UDR0r16 ret

C Code Example

void USART_Transmit( unsigned int data ) Wait for empty transmit buffer while ( ( UCSR0A amp (1ltltUDRE))) ) Copy 9th bit to TXB8 UCSR0B amp= ~(1ltltTXB8) if ( data amp 0x0100 ) UCSR0B |= (1ltltTXB8) Put data into buffer sends the data UDR0 = data

Note These transmit functions are written to be general functions They can be optimized if the contentsof the UCSRnB is static For example only the TXB8 bit of the UCSRnB Register is used afterinitialization

2573 Transmitter Flags and InterruptsThe USART Transmitter has two flags that indicate its state USART Data Register Empty (UDRE) andTransmit Complete (TXC) Both flags can be used for generating interrupts

The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to receive new dataThis bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to betransmitted that has not yet been moved into the Shift Register For compatibility with future devicesalways write this bit to zero when writing the UCSRnA Register

When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRnB is written to 1 the USART DataRegister Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts areenabled) UDRE is cleared by writing UDRn When interrupt-driven data transmission is used the DataRegister Empty interrupt routine must either write new data to UDRn in order to clear UDRE or disablethe Data Register Empty interrupt - otherwise a new interrupt will occur once the interrupt routineterminates

The Transmit Complete (TXC) Flag bit is set when the entire frame in the Transmit Shift Register hasbeen shifted out and there are no new data currently present in the transmit buffer The TXC Flag bit iseither automatically cleared when a transmit complete interrupt is executed or it can be cleared by writinga 1 to its bit location The TXC Flag is useful in half-duplex communication interfaces (like the RS-485standard) where a transmitting application must enter receive mode and free the communication busimmediately after completing the transmission

When the Transmit Complete Interrupt Enable (TXCIE) bit in UCSRnB is written to 1 the USARTTransmit Complete Interrupt will be executed when the TXC Flag becomes set (provided that globalinterrupts are enabled) When the transmit complete interrupt is used the interrupt handling routine doesnot have to clear the TXC Flag this is done automatically when the interrupt is executed

2574 Parity GeneratorThe Parity Generator calculates the parity bit for the serial frame data When parity bit is enabled(UCSRnCUPM[1]=1) the transmitter control logic inserts the parity bit between the last data bit and thefirst stop bit of the frame that is sent

2575 Disabling the TransmitterWhen writing the TX Enable bit in the USART Control and Status Register n B (UCSRnBTXEN) to zerothe disabling of the Transmitter will not become effective until ongoing and pending transmissions arecompleted ie when the Transmit Shift Register and Transmit Buffer Register do not contain data to betransmitted When disabled the Transmitter will no longer override the TxDn pin

258 Data Reception ndash The USART ReceiverThe USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRnB Register to 1When the Receiver is enabled the normal pin operation of the RxDn pin is overridden by the USART andgiven the function as the Receiverrsquos serial input The baud rate mode of operation and frame format mustbe set up once before any serial reception can be done If synchronous operation is used the clock onthe XCKn pin will be used as transfer clock

2581 Receiving Frames with 5 to 8 Data BitsThe Receiver starts data reception when it detects a valid start bit Each bit that follows the start bit will besampled at the baud rate or XCKn clock and shifted into the Receive Shift Register until the first stop bitof a frame is received A second stop bit will be ignored by the Receiver When the first stop bit isreceived ie a complete serial frame is present in the Receive Shift Register the contents of the ShiftRegister will be moved into the receive buffer The receive buffer can then be read by reading the UDRnIO location

The following code example shows a simple USART receive function based on polling of the ReceiveComplete (RXC) Flag When using frames with less than eight bits the most significant bits of the dataread from the UDR0 will be masked to zero The USART 0 has to be initialized before the function can beused For the assembly code the received data will be stored in R16 after the code completes

USART_Receive Wait for data to be received in r17 UCSR0A sbrs r17 RXC rjmp USART_Receive Get and return received data from buffer

in r16 UDR0 ret

C Code Example

unsigned char USART_Receive( void ) Wait for data to be received while ( (UCSR0A amp (1ltltRXC)) ) Get and return received data from buffer return UDR0

The function simply waits for data to be present in the receive buffer by checking the RXC Flag beforereading the buffer and returning the value

2582 Receiving Frames with 9 Data BitsIf 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8 bit in UCSRnB beforereading the low bits from the UDRn This rule applies to the FE DOR and UPE Status Flags as wellRead status from UCSRnA then data from UDRn Reading the UDRn IO location will change the state ofthe receive buffer FIFO and consequently the TXB8 FE DOR and UPE bits which all are stored in theFIFO will change

The following code example shows a simple receive function for USART0 that handles both nine-bitcharacters and the status bits For the assembly code the received data will be stored in R17R16 afterthe code completes

USART_Receive Wait for data to be received in r16 UCSR0A sbrs r16 RXC rjmp USART_Receive Get status and 9th bit then data from buffer in r18 UCSR0A in r17 UCSR0B in r16 UDR0 If error return -1 andi r18(1ltltFE)|(1ltltDOR)|(1ltltUPE) breq USART_ReceiveNoError ldi r17 HIGH(-1) ldi r16 LOW(-1)USART_ReceiveNoError Filter the 9th bit then return lsr r17 andi r17 0x01 ret

C Code Example

unsigned int USART_Receive( void ) unsigned char status resh resl Wait for data to be received while ( (UCSR0A amp (1ltltRXC)) )

Get status and 9th bit then data from buffer status = UCSR0A resh = UCSR0B resl = UDR0 If error return -1 if ( status amp (1ltltFE)|(1ltltDOR)|(1ltltUPE) ) return -1 Filter the 9th bit then return resh = (resh gtgt 1) amp 0x01 return ((resh ltlt 8) | resl)

The receive function example reads all the IO Registers into the Register File before any computation isdone This gives an optimal receive buffer utilization since the buffer location read will be free to acceptnew data as early as possible

2583 Receive Compete Flag and InterruptThe USART Receiver has one flag that indicates the Receiver state

The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer Thisflag is one when unreadenspdata exist in the receive buffer and zero when the receive buffer is empty (iedoes not contain any unread data) If the Receiver is disabled (RXEN = 0) the receive buffer will beflushed and consequently the RXCn bit will become zero

When the Receive Complete Interrupt Enable (RXCIE) in UCSRnB is set the USART Receive Completeinterrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled)When interrupt-driven data reception is used the receive complete routine must read the received datafrom UDR in order to clear the RXC Flag otherwise a new interrupt will occur once the interrupt routineterminates

2584 Receiver Error FlagsThe USART Receiver has three Error Flags Frame Error (FE) Data OverRun (DOR) and Parity Error(UPE) All can be accessed by reading UCSRnA Common for the Error Flags is that they are located inthe receive buffer together with the frame for which they indicate the error status Due to the buffering ofthe Error Flags the UCSRnA must be read before the receive buffer (UDRn) since reading the UDRn IOlocation changes the buffer read location Another equality for the Error Flags is that they cannot bealtered by software doing a write to the flag location However all flags must be set to zero when theUCSRnA is written for upward compatibility of future USART implementations None of the Error Flagscan generate interrupts

The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in thereceive buffer The FE Flag is zero when the stop bit was correctly read as 1 and the FE Flag will be onewhen the stop bit was incorrect (zero) This flag can be used for detecting out-of-sync conditionsdetecting break conditions and protocol handling The FE Flag is not affected by the setting of the USBSbit in UCSRnC since the Receiver ignores all except for the first stop bits For compatibility with futuredevices always set this bit to zero when writing to UCSRnA

The Data OverRun (DOR) Flag indicates data loss due to a receiver buffer full condition A Data OverRunoccurs when the receive buffer is full (two characters) a new character is waiting in the Receive ShiftRegister and a new start bit is detected If the DOR Flag is set one or more serial frames were lostbetween the last frame read from UDR and the next frame read from UDR For compatibility with futuredevices always write this bit to zero when writing to UCSRnA The DOR Flag is cleared when the framereceived was successfully moved from the Shift Register to the receive buffer

The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error whenreceived If Parity Check is not enabled the UPE bit will always read 0 For compatibility with futuredevices always set this bit to zero when writing to UCSRnA For more details see Parity Bit Calculationand Parity Checker below

2585 Parity CheckerThe Parity Checker is active when the high USART Parity Mode bit 1 in the USART Control and StatusRegister n C (UCSRnCUPM[1]) is written to 1 The type of Parity Check to be performed (odd or even)is selected by the UCSRnCUPM[0] bit When enabled the Parity Checker calculates the parity of thedata bits in incoming frames and compares the result with the parity bit from the serial frame The resultof the check is stored in the receive buffer together with the received data and stop bits The USARTParity Error Flag in the USART Control and Status Register n A (UCSRnAUPE) can then be read bysoftware to check if the frame had a Parity Error

The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error whenreceived and the Parity Checking was enabled at that point (UPM[1] = 1) This bit is valid until the receivebuffer (UDRn) is read

2586 Disabling the ReceiverIn contrast to the Transmitter disabling of the Receiver will be immediate Data from ongoing receptionswill therefore be lost When disabled (ie UCSRnBRXEN is written to zero) the Receiver will no longeroverride the normal function of the RxDn port pin The Receiver buffer FIFO will be flushed when theReceiver is disabled Remaining data in the buffer will be lost

2587 Flushing the Receive BufferThe receiver buffer FIFO will be flushed when the Receiver is disabled ie the buffer will be emptied ofits contents Unread data will be lost If the buffer has to be flushed during normal operation due to forinstance an error condition read the UDRn IO location until the RXCn Flag is cleared

The following code shows how to flush the receive buffer of USART0

USART_Flush in r16 UCSR0A sbrs r16 RXC ret in r16 UDR0 rjmp USART_Flush

C Code Example

void USART_Flush( void ) unsigned char dummy while ( UCSR0A amp (1ltltRXC) ) dummy = UDR0

259 Asynchronous Data ReceptionThe USART includes a clock recovery and a data recovery unit for handling asynchronous data receptionThe clock recovery logic is used for synchronizing the internally generated baud rate clock to theincoming asynchronous serial frames at the RxDn pin The data recovery logic samples and low passfilters each incoming bit thereby improving the noise immunity of the Receiver The asynchronous

reception operational range depends on the accuracy of the internal baud rate clock the rate of theincoming frames and the frame size in a number of bits

2591 Asynchronous Clock RecoveryThe clock recovery logic synchronizes the internal clock to the incoming serial frames The figure belowillustrates the sampling process of the start bit of an incoming frame The sample rate is 16-times thebaud rate for Normal mode and eight times the baud rate for Double Speed mode The horizontal arrowsillustrate the synchronization variation due to the sampling process Note the larger time variation whenusing the Double Speed mode (UCSRnAU2Xn=1) of operation Samples denoted 0 are samples takenwhile the RxDn line is idle (ie no communication activity)

Figure 25-5 Start Bit Sampling

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2

STARTIDLE

1 2 3 4 5 6 7 8 1 20

Sample(U2X = 0)

Sample(U2X = 1)

When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line the start bitdetection sequence is initiated Let sample 1 denote the first zero-sample as shown in the figure Theclock recovery logic then uses samples 8 9 and 10 for Normal mode and samples 4 5 and 6 forDouble Speed mode (indicated with sample numbers inside boxes on the figure) to decide if a valid startbit is received If two or more of these three samples have logical high levels (the majority wins) the startbit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition on RxDnIf however a valid start bit is detected the clock recovery logic is synchronized and the data recovery canbegin The synchronization process is repeated for each start bit

2592 Asynchronous Data RecoveryWhen the receiver clock is synchronized to the start bit the data recovery can begin The data recoveryunit uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit inDouble Speed mode The figure below shows the sampling of the data bits and the parity bit Each of thesamples is given a number that is equal to the state of the recovery unit

Figure 25-6 Sampling of Data and Parity Bit

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1

1 2 3 4 5 6 7 8 1

Sample(U2X = 0)

Sample(U2X = 1)

The decision of the logic level of the received bit is taken by doing a majority voting of the logic value tothe three samples in the center of the received bit If two or all three center samples (those marked bytheir sample number inside boxes) have high levels the received bit is registered to be a logic 1 If twoor all three samples have low levels the received bit is registered to be a logic 0 This majority votingprocess acts as a low pass filter for the incoming signal on the RxDn pin The recovery process is thenrepeated until a complete frame is received including the first stop bit The Receiver only uses the firststop bit of a frame

The following figure shows the sampling of the stop bit and the earliest possible beginning of the start bitof the next frame

Figure 25-7 Stop Bit Sampling and Next Start Bit Sampling

1 2 3 4 5 6 7 8 9 10 01 01 01

STOP 1

1 2 3 4 5 6 01

Sample(U2X = 0)

Sample(U2X = 1)

(A) (B) (C)

The same majority voting is done to the stop bit as done for the other bits in the frame If the stop bit isregistered to have a logic 0 value the Frame Error (UCSRnAFE) Flag will be set

A new high to low transition indicating the start bit of a new frame can come right after the last of the bitsused for majority voting For Normal Speed mode the first low level sample can be taken at the pointmarked (A) in the figure above For Double Speed mode the first low level must be delayed to (B) (C)marks a stop bit of full length The early start bit detection influences the operational range of theReceiver

2593 Asynchronous Operational RangeThe operational range of the Receiver is dependent on the mismatch between the received bit rate andthe internally generated baud rate If the Transmitter is sending frames at too fast or too slow bit rates orthe internally generated baud rate of the Receiver does not have a similar base frequency (seerecommendations below) the Receiver will not be able to synchronize the frames to the start bit

The following equations can be used to calculate the ratio of the incoming data rate and internal receiverbaud rate

slow = + 1 minus 1 + sdot + fast = + 2 + 1 + bull D Sum of character size and parity size (D = 5 to 10 bit)bull S Samples per bit S = 16 for Normal Speed mode and S = 8 for Double Speed modebull SF First sample number used for majority voting SF = 8 for normal speed and SF = 4

for Double Speed modebull SM Middle sample number used for majority voting SM = 9 for normal speed and

SM = 5 for Double Speed modebull Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to the

receiver baud rate Rfast is the ratio of the fastest incoming data rate that can beaccepted in relation to the receiver baud rate

The following tables list the maximum receiver baud rate error that can be tolerated Note that NormalSpeed mode has higher toleration of baud rate variations

Table 25-2 Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0)

D (Data+Parity Bit)

Rslow [] Rfast [] Max Total Error [] Recommended Max Receiver Error []

5 9320 10667 +667-68 plusmn30

6 9412 10579 +579-588 plusmn25

7 9481 10511 +511-519 plusmn20

8 9536 10458 +458-454 plusmn20

9 9581 10414 +414-419 plusmn15

10 9617 10378 +378-383 plusmn15

Table 25-3 Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1)

D (Data+Parity Bit)

5 9412 10566 +566-588 plusmn25

6 9492 10492 +492-508 plusmn20

7 9552 10435 +435-448 plusmn15

8 9600 10390 +390-400 plusmn15

9 9639 10353 +353-361 plusmn15

10 9670 10323 +323-330 plusmn10

The recommendations of the maximum receiver baud rate error was made under the assumption that theReceiver and Transmitter equally divide the maximum total error

There are two possible sources for the receivers baud rate error The Receiverrsquos system clock (EXTCLK)will always have some minor instability over the supply voltage range and the temperature range Whenusing a crystal to generate the system clock this is rarely a problem but for a resonator the system clockmay differ more than 2 depending on the resonators tolerance The second source for the error is morecontrollable The baud rate generator cannot always do an exact division of the system frequency to getthe baud rate wanted In this case an UBRRn value that gives an acceptable low error can be used ifpossible

2594 Start Frame DetectionThe USART start frame detector can wake up the MCU from Power-down and Standby sleep mode whenit detects a start bit

When a high-to-low transition is detected on RxDn the internal 8 MHz oscillator is powered up and theUSART clock is enabled After start-up the rest of the data frame can be received provided that the baudrate is slow enough in relation to the internal 8 MHz oscillator start-up time Start-up time of the internal 8MHz oscillator varies with supply voltage and temperature

The USART start frame detection works in both asynchronous and synchronous modes It is enabled bywriting the Start Frame Detection Enable bit (SFDE) If the USART Start Interrupt Enable (RXSIE) bit isset the USART Receive Start Interrupt is generated immediately when start is detected

When using the feature without start interrupt the start detection logic activates the internal 8 MHzoscillator and the USART clock while the frame is being received only Other clocks remain stopped untilthe Receive Complete Interrupt wakes up the MCU

The maximum baud rate in synchronous mode depends on the sleep mode the device is woken up from

bull Idle sleep mode system clock frequency divided by fourbull Standby or Power-down 500 kbps

The maximum baud rate in asynchronous mode depends on the sleep mode the device is woken upfrom

bull Idle sleep mode the same as in active modeTable 25-4 Maximum Total Baud Rate Error in Normal Speed Mode

Baud Rate Frame Size

5 6 7 8 9 10

0 - 288 kbps +667-588

+579-508

+511-448

+458-400

+414-361

+378-330

384 kbps +663-588

+575-508

+508-448

+455-400

+412-361

+376-330

576 kbps +610-588

+530-508

+469-448

+420-400

+380-361

+347-330

768 kbps +559-588

+485-508

+429-448

+385-400

+348-361

+318-330

1152 kbps +457-588

+397-508

+351-448

+315-400

+286-361

+261-330

Table 25-5 Maximum Total Baud Rate Error in Double Speed Mode

5 6 7 8 9 10

0 - 576 kbps +566-400

+492-345

+435-303

+390-270

+353-244

+323-222

768 kbps +559-400

+485-345

+429-303

+385-270

+348-244

+318-222

1152 kbps +457-400

+397-345

+351-303

+315-270

+286-244

+261-222

2510 Multi-Processor Communication ModeSetting the Multi-Processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function ofincoming frames received by the USART Receiver Frames that do not contain address information willbe ignored and not put into the receive buffer This effectively reduces the number of incoming framesthat have to be handled by the CPU in a system with multiple MCUs that communicate via the sameserial bus The Transmitter is unaffected by the MPCMn setting but has to be used differently when it is apart of a system utilizing the Multi-processor Communication mode

If the Receiver is set up to receive frames that contain five to eight data bits then the first stop bitindicates if the frame contains data or address information If the Receiver is set up for frames with 9 databits then the ninth bit (RXB8) is used for identifying address and data frames When the frame type bit(the first stop or the ninth bit) is 1 the frame contains an address When the frame type bit is 0 theframe is a data frame

The Multi-Processor Communication mode enables several slave MCUs to receive data from a masterMCU This is done by first decoding an address frame to find out which MCU has been addressed If aparticular slave MCU has been addressed it will receive the following data frames as normal while theother slave MCUs will ignore the received frames until another address frame is received

25101 Using MPCMnFor an MCU to act as a master MCU it can use a 9-bit character frame format (UCSZ1=7) The ninth bit(TXB8) must be set when an address frame (TXB8=1) is being transmitted or cleared when a data frame(TXB=0) is being transmitted The slave MCUs must in this case be set to use a 9-bit character frameformat

The following procedure should be used to exchange data in Multi-Processor Communication Mode

1 All Slave MCUs are in Multi-Processor Communication mode (MPCM in UCSRnA is set)2 The Master MCU sends an address frame and all slaves receive and read this frame In the Slave

MCUs the RXC Flag in UCSRnA will be set as normal3 Each Slave MCU reads the UDRn Register and determines if it has been selected If so it clears

the MPCM bit in UCSRnA otherwise it waits for the next address byte and keeps the MPCMsetting

4 The addressed MCU will receive all data frames until a new address frame is received The otherSlave MCUs which still have the MPCM bit set will ignore the data frames

5 When the last data frame is received by the addressed MCU the addressed MCU sets the MPCMbit and waits for a new address frame from the master The process then repeats from step 2

Using any of the 5- to 8-bit character frame formats is possible but impractical since the Receiver mustchange between using n and n+1 character frame formats This makes full-duplex operation difficult sincethe Transmitter and Receiver use the same character size setting If 5- to 8-bit character frames are usedthe Transmitter must be set to use two stop bit (USBS = 1) since the first stop bit is used for indicating theframe type

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit The MPCM bitshares the same IO location as the TXC Flag and this might accidentally be cleared when using SBI orCBI instructions

2511 Examples of Baud Rate SettingFor standard crystal and resonator frequencies the most commonly used baud rates for asynchronousoperation can be generated by using the UBRRn settings as listed in the table below

UBRRn values which yield an actual baud rate differing less than 05 from the target baud rate are boldin the table Higher error ratings are acceptable but the Receiver will have less noise resistance whenthe error ratings are high especially for large serial frames (see also section Asynchronous OperationalRange) The error values are calculated using the following equation

= BaudRateClosest MatchBaudRate minus 1 2 100

Table 25-6 Examples of UBRRn Settings for Commonly Used Oscillator Frequencies

BaudRate[bps]

fosc = 10000 MHz fosc = 18432 MHz fosc = 20000 MHz

U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1

UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error

2400 25 02 51 02 47 00 95 00 51 02 103 02

4800 12 02 25 02 23 00 47 00 25 02 51 02

9600 6 -70 12 02 11 00 23 00 12 02 25 02

144k 3 85 8 -35 7 00 15 00 8 -35 16 21

192k 2 85 6 -70 5 00 11 00 6 -70 12 02

288k 1 85 3 85 3 00 7 00 3 85 8 -35

384k 1 -186 2 85 2 00 5 00 2 85 6 -70

576k 0 85 1 85 1 00 3 00 1 85 3 85

768k ndash ndash 1 -186 1 -250 2 00 1 -186 2 85

1152k ndash ndash 0 85 0 00 1 00 0 85 1 85

2304k ndash ndash ndash ndash ndash ndash 0 00 ndash ndash ndash ndash

250k ndash ndash ndash ndash ndash ndash ndash ndash ndash ndash 0 00

Max(1) 625 kbps 125 kbps 1152 kbps 2304 kbps 125 kbps 250 kbps

Note 1 UBRRn = 0 Error = 00

Baud Rate[bps]

2400 95 00 191 00 103 02 207 02 191 00 383 00

4800 47 00 95 00 51 02 103 02 95 00 191 00

9600 23 00 47 00 25 02 51 02 47 00 95 00

144k 15 00 31 00 16 21 34 -08 31 00 63 00

192k 11 00 23 00 12 02 25 02 23 00 47 00

288k 7 00 15 00 8 -35 16 21 15 00 31 00

384k 5 00 11 00 6 -70 12 02 11 00 23 00

576k 3 00 7 00 3 85 8 -35 7 00 15 00

768k 2 00 5 00 2 85 6 -70 5 00 11 00

1152k 1 00 3 00 1 85 3 85 3 00 7 00

2304k 0 00 1 00 0 85 1 85 1 00 3 00

Baud Rate[bps]

250k 0 -78 1 -78 0 00 1 00 1 -78 3 -78

05M ndash ndash 0 -78 ndash ndash 0 00 0 -78 1 -78

1M ndash ndash ndash ndash ndash ndash ndash ndash ndash ndash 0 -78

Max(1) 2304 kbps 4608 kbps 250 kbps 05 Mbps 4608 kbps 9216 kbps

(1) UBRRn = 0 Error = 00

Baud Rate[bps]

2400 207 02 416 -01 287 00 575 00 383 00 767 00

4800 103 02 207 02 143 00 287 00 191 00 383 00

9600 51 02 103 02 71 00 143 00 95 00 191 00

144k 34 -08 68 06 47 00 95 00 63 00 127 00

192k 25 02 51 02 35 00 71 00 47 00 95 00

288k 16 21 34 -08 23 00 47 00 31 00 63 00

384k 12 02 25 02 17 00 35 00 23 00 47 00

576k 8 -35 16 21 11 00 23 00 15 00 31 00

768k 6 -70 12 02 8 00 17 00 11 00 23 00

1152k 3 85 8 -35 5 00 11 00 7 00 15 00

2304k 1 85 3 85 2 00 5 00 3 00 7 00

250k 1 00 3 00 2 -78 5 -78 3 -78 6 53

05M 0 00 1 00 ndash ndash 2 -78 1 -78 3 -78

1M ndash ndash 0 00 ndash ndash ndash ndash 0 -78 1 -78

Max(1) 05 Mbps 1 Mbps 6912 kbps 13824 Mbps 9216 kbps 18432 Mbps

Baud Rate [bps] fosc = 160000 MHz

U2Xn = 0 U2Xn = 1

UBRRn Error UBRRn Error

2400 416 -01 832 00

4800 207 02 416 -01

9600 103 02 207 02

144k 68 06 138 -01

192k 51 02 103 02

288k 34 -08 68 06

384k 25 02 51 02

576k 16 21 34 -08

768k 12 02 25 02

1152k 8 -35 16 21

2304k 3 85 8 -35

250k 3 00 7 00

05M 1 00 3 00

1M 0 00 1 00

Max(1) 1 Mbps 2 Mbps

Related Links2593 Asynchronous Operational Range

25121 USART IO Data Register n

Name UDROffset 0xC6 + n0x01 [n=01]Reset 0x00Property -

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the sameIO address referred to as USART Data Register or UDRn The Transmit Data Buffer Register (TXB) willbe the destination for data written to the UDR1 Register location Reading the UDRn Register location willreturn the contents of the Receive Data Buffer Register (RXB)

For 5- 6- or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero bythe Receiver

The transmit buffer can only be written when the UDRE Flag in the UCSRnA Register is set Data iswritten to UDRn when the UCSRnAUDRE Flag is not set will be ignored by the USART Transmitter nWhen data is written to the transmit buffer and the Transmitter is enabled the Transmitter will load thedata into the Transmit Shift Register when the Shift Register is empty Then the data will be seriallytransmitted on the TxDn pin

The receive buffer consists of a two-level FIFO The FIFO will change its state whenever the receivebuffer is accessed Due to this behavior of the receive buffer do not use Read-Modify-Write instructions(SBI and CBI) on this location Be careful when using bit test instructions (SBIC and SBIS) since thesealso will change the state of the FIFO

Bit 7 6 5 4 3 2 1 0 TXB RXB[70]

Bits 70 ndash TXB RXB[70] USART Transmit Receive Data Buffer

25122 USART Control and Status Register n A

Name UCSRAOffset 0xC0 + n0x08 [n=01]Reset 0x20Property -

Bit 7 6 5 4 3 2 1 0 RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn

Access R RW R R R R RW RW Reset 0 0 1 0 0 0 0 0

Bit 7 ndash RXCn USART Receive CompleteThis flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer isempty (ie does not contain any unread data) If the Receiver is disabled the receive buffer will beflushed and consequently the RXC bit will become zero The RXC Flag can be used to generate aReceive Complete interrupt (see the description of the RXCIE bit)

Bit 6 ndash TXCn USART Transmit CompleteThis flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there areno new data currently present in the transmit buffer (UDRn) The TXC Flag bit is automatically clearedwhen a transmit complete interrupt is executed or it can be cleared by writing a one to its bit locationThe TXC Flag can generate a Transmit Complete interrupt (see the description of the TXCIE bit)

Bit 5 ndash UDREn USART Data Register EmptyThe UDRE Flag indicates if the transmit buffer (UDRn) is ready to receive new data If UDRE is one thebuffer is empty and therefore ready to be written The UDRE Flag can generate a Data Register Emptyinterrupt (see the description of the UDRIE bit) UDRE is set after a reset to indicate that the Transmitteris ready

Bit 4 ndash FEn Frame ErrorThis bit is set if the next character in the receive buffer had a Frame Error when received Ie when thefirst stop bit of the next character in the receive buffer is zero This bit is valid until the receive buffer(UDRn) is read The FEn bit is zero when the stop bit of received data is one Always set this bit to zerowhen writing to UCSRnA

This bit is reserved in Master SPI Mode (MSPIM)

Bit 3 ndash DORn Data OverRunThis bit is set if a Data OverRun condition is detected A Data OverRun occurs when the receive buffer isfull (two characters) it is a new character waiting in the Receive Shift Register and a new start bit isdetected This bit is valid until the receive buffer (UDRn) is read Always set this bit to zero when writingto UCSRnA

Bit 2 ndash UPEn USART Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when received and the ParityChecking was enabled at that point (UCSRnCUPM1 = 1) This bit is valid until the receive buffer (UDRn)is read Always set this bit to zero when writing to UCSRnA

Bit 1 ndash U2Xn Double the USART Transmission SpeedThis bit only has effect for the asynchronous operation Write this bit to zero when using synchronousoperation

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling thetransfer rate for asynchronous communication

Bit 0 ndash MPCMn Multi-processor Communication ModeThis bit enables the Multi-processor Communication mode When the MPCM bit is written to one all theincoming frames received by the USART Receiver n that do not contain address information will beignored The Transmitter is unaffected by the MPCM setting Refer to 2510 Multi-ProcessorCommunication Mode for details

25123 USART Control and Status Register n B

Name UCSRBOffset 0xC1 + n0x08 [n=01]Reset 0x00Property -

Bit 7 6 5 4 3 2 1 0 RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n

Access RW RW RW RW RW RW R RW Reset 0 0 0 0 0 0 0 0

Bit 7 ndash RXCIEn RX Complete Interrupt EnableWriting this bit to one enables interrupt on the UCSRnARXC Flag A USART Receive Complete interruptwill be generated only if the RXCIE bit is written to one the Global Interrupt Flag in SREG is written toone and the RXC bit in UCSRnA is set

Bit 6 ndash TXCIEn TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC Flag A USART Transmit Complete interrupt will begenerated only if the TXCIE bit is written to one the Global Interrupt Flag in SREG is written to one andthe TXC bit in UCSRnA is set

Bit 5 ndash UDRIEn USART Data Register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDRE Flag A Data Register Empty interrupt will begenerated only if the UDRIE bit is written to one the Global Interrupt Flag in SREG is written to one andthe UDRE bit in UCSRnA is set

Bit 4 ndash RXENn Receiver EnableWriting this bit to one enables the USART Receiver The Receiver will override normal port operation forthe RxDn pin when enabled Disabling the Receiver will flush the receive buffer invalidating the FE DORand UPE Flags

Bit 3 ndash TXENn Transmitter EnableWriting this bit to one enables the USART Transmitter The Transmitter will override normal port operationfor the TxDn pin when enabled The disabling of the Transmitter (writing TXEN to zero) will not becomeeffective until ongoing and pending transmissions are completed ie when the Transmit Shift Registerand Transmit Buffer Register does not contain data to be transmitted When disabled the Transmitter willno longer override the TxDn port

Bit 2 ndash UCSZn2 Character SizeThe UCSZ2 bits combined with the UCSZ[10] bit in UCSRnC sets the number of data bits (CharacterSize) in a frame the Receiver and Transmitter use

Bit 1 ndash RXB8n Receive Data Bit 8RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bitsMust be read before reading the low bits from UDRn

Bit 0 ndash TXB8n Transmit Data Bit 8TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with ninedata bits Must be written before writing the low bits to UDRn

25124 USART Control and Status Register n C

Name UCSRCOffset 0xC2 + n0x08 [n=01]Reset 0x06Property -

Bit 7 6 5 4 3 2 1 0 UMSELn[10] UPMn[10] USBSn UCSZn1

UDORDnUCSZn0 UCPHAn

UCPOLn

Bits 76 ndash UMSELn[10] USART Mode SelectThese bits select the mode of operation of the USARTn

Table 25-10 USART Mode Selection

UMSEL[10] Mode

00 Asynchronous USART

01 Synchronous USART

10 Reserved

11 Master SPI (MSPIM)(1)

Note 1 The UDORD UCPHA and UCPOL can be set in the same write operation where the MSPIM is

enabled

Bits 54 ndash UPMn[10] USART Parity ModeThese bits enable and set the type of parity generation and check If enabled the Transmitter willautomatically generate and send the parity of the transmitted data bits within each frame The Receiverwill generate a parity value for the incoming data and compare it to the UPM setting If a mismatch isdetected the UPE Flag in UCSRnA will be set

UPM[10] ParityMode

00 Disabled

01 Reserved

10 Enabled Even Parity

11 Enabled Odd Parity

These bits are reserved in Master SPI Mode (MSPIM)

Bit 3 ndash USBSn USART Stop Bit SelectThis bit selects the number of stop bits to be inserted by the Transmitter n The Receiver ignores thissetting

Table 25-12 Stop Bit Settings

USBS Stop Bit(s)

0 1-bit

1 2-bit

Bit 2 ndash UCSZn1 UDORDn USART Character Size Data OrderUCSZ1[10] USART Modes The UCSZ1[10] bits combined with the UCSZ12 bit in UCSR1B sets thenumber of data bits (Character Size) in a frame the Receiver and Transmitter use

Table 25-13 Character Size Settings

UCSZ1[20] Character Size

000 5-bit

001 6-bit

010 7-bit

011 8-bit

100 Reserved

101 Reserved

110 Reserved

111 9-bit

UDORD0 Master SPI Mode When set to one the LSB of the data word is transmitted first When set tozero the MSB of the data word is transmitted first Refer to the USART in SPI Mode - Frame Formats fordetails

Bit 1 ndash UCSZn0 UCPHAn USART Character Size Clock PhaseUCSZ0 USART Modes Refer to UCSZ1

UCPHA Master SPI Mode The UCPHA bit setting determine if data is sampled on the leading edge(first) or tailing (last) edge of XCK Refer to the SPI Data Modes and Timing for details

Bit 0 ndash UCPOLn Clock PolarityUSART n Modes This bit is used for synchronous mode only Write this bit to zero when asynchronousmode is used The UCPOL bit sets the relationship between data output change and data input sampleand the synchronous clock (XCKn)

Table 25-14 USART Clock Polarity Settings

UCPOL Transmitted Data Changed (Output of TxDnPin)

Received Data Sampled (Input on RxDnPin)

0 Rising XCKn Edge Falling XCKn Edge

1 Falling XCKn Edge Rising XCKn Edge

Master SPI Mode The UCPOL bit sets the polarity of the XCKn clock The combination of the UCPOLand UCPHA bit settings determine the timing of the data transfer Refer to the SPI Data Modes andTiming for details

25125 USART Baud Rate n Register Low and High byte

Name UBRROffset 0xC4 + n0x08 [n=01]Reset 0x00Property -

The UBRRnL and UBRRnH register pair represents the 16-bit value UBRRn (n=01) The low byte [70](suffix L) is accessible at the original offset The high byte [158] (suffix H) can be accessed at offset+ 0x01 For more details on reading and writing 16-bit registers refer to Accessing 16-bit TimerCounterRegisters

Bit 15 14 13 12 11 10 9 8 UBRRn[118]

Bit 7 6 5 4 3 2 1 0 UBRRn[70]

Bits 110 ndash UBRRn[110] USART Baud RateThis is a 12-bit register which contains the USART baud rate The UBRRnH contains the four mostsignificant bits and the UBRRnL contains the eight least significant bits of the USART n baud rateOngoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changedWriting UBRRnL will trigger an immediate update of the baud rate prescaler

26 USARTSPI - USART in SPI Mode

261 Featuresbull Full Duplex Three-wire Synchronous Data Transferbull Master Operationbull Supports all four SPI Modes of Operation (Mode 0 1 2 and 3)bull LSB First or MSB First Data Transfer (Configurable Data Order)bull Queued Operation (Double Buffered)bull High-Resolution Baud Rate Generatorbull High Speed Operation (fXCKmax = fCK2)bull Flexible Interrupt Generation

262 OverviewThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to amaster SPI compliant mode of operation

Setting both UMSELn[10] bits to one enables the USART in MSPIM logic In this mode of operation theSPI master control logic takes direct control over the USART resources These resources include thetransmitter and receiver shift register and buffers and the baud rate generator The parity generator andchecker the data and clock recovery logic and the RX and TX control logic is disabled The USART RXand TX control logic is replaced by a common SPI transfer control logic However the pin control logicand interrupt generation logic is identical in both modes of operation

The IO register locations are the same in both modes However some of the functionality of the controlregisters changes when using MSPIM

263 Clock GenerationThe Clock Generation logic generates the base clock for the Transmitter and Receiver For USARTMSPIM mode of operation only internal clock generation (ie master operation) is supported The DataDirection Register for the XCKn pin (DDR_XCKn) must therefore be set to one (ie as output) for theUSART in MSPIM to operate correctly Preferably the DDR_XCKn should be set up before the USART inMSPIM is enabled (ie TXENn and RXENn bit set to one)

The internal clock generation used in MSPIM mode is identical to the USART synchronous master modeThe table below contains the equations for calculating the baud rate or UBRRn setting for SynchronousMaster Mode

Synchronous Mastermode BAUD = OSC2 + 1 = OSC2BAUD minus 1

Note 1 The baud rate is defined to be the transfer rate in bit per second (bps)

ATmega328PB AutomotiveUSARTSPI - USART in SPI Mode

fOSC System Oscillator clock frequency

UBRRn Contents of the UBRRnH and UBRRnL Registers (0-4095)

264 SPI Data Modes and TimingThere are four combinations of XCKn (SCK) phase and polarity with respect to serial data which aredetermined by control bits UCPHAn and UCPOLn The data transfer timing diagrams are shown in thefollowing figure Data bits are shifted out and latched in on opposite edges of the XCKn signal ensuringsufficient time for data signals to stabilize The UCPOLn and UCPHAn functionality is summarized in thefollowing table Note that changing the setting of any of these bits will corrupt all ongoing communicationfor both the Receiver and Transmitter

Table 26-2 UCPOLn and UCPHAn Functionality

UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge

0 0 0 Sample (Rising) Setup (Falling)

0 1 1 Setup (Rising) Sample (Falling)

1 0 2 Sample (Falling) Setup (Rising)

1 1 3 Setup (Falling) Sample (Rising)

Figure 26-1 UCPHAn and UCPOLn Data Transfer Timing Diagrams

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

UCPOL=0 UCPOL=1

265 Frame FormatsA serial frame for the MSPIM is defined to be one character of eight data bits The USART in MSPIMmode has two valid frame formats

bull 8-bit data with MSB firstbull 8-bit data with LSB first

A frame starts with the least or most significant data bit Then the next data bits up to a total of eight aresucceeding ending with the most or least significant bit accordingly When a complete frame istransmitted a new frame can directly follow it or the communication line can be set to an idle (high) state

The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode The Receiverand Transmitter use the same setting Note that changing the setting of any of these bits will corrupt allongoing communication for both the Receiver and Transmitter

16-bit data transfer can be achieved by writing two data bytes to UDRn A UART transmit completeinterrupt will then signal that the 16-bit value has been shifted out

2651 USART MSPIM InitializationThe USART in MSPIM mode has to be initialized before any communication can take place Theinitialization process normally consists of setting the baud rate setting master mode of operation (bysetting DDR_XCKn to one) setting frame format and enabling the Transmitter and the Receiver Only thetransmitter can operate independently For interrupt driven USART operation the Global Interrupt Flagshould be cleared (and thus interrupts globally disabled) when doing the initialization

Note To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must bezero at the time the transmitter is enabled Contrary to the normal mode USART operation the UBRRnmust then be written to the desired value after the transmitter is enabled but before the first transmissionis started Setting UBRRn to zero before enabling the transmitter is not necessary if the initialization isdone immediately after a reset since UBRRn is reset to zero

Before doing a re-initialization with changed baud rate data mode or frame format be sure that there areno ongoing transmissions during the period the registers are changed The TXCn Flag can be used tocheck that the Transmitter has completed all transfers and the RXCn Flag can be used to check thatthere are no unread data in the receive buffer Note that the TXCn Flag must be cleared before eachtransmission (before UDRn is written) if it is used for this purpose

The following simple USART initialization code examples show one assembly and one C function that areequal in functionality The examples assume polling (no interrupts enabled) The baud rate is given as afunction parameter For the assembly code the baud rate parameter is assumed to be stored in ther17r16 registers

Example 26-1 Assembly Code Example

clr r18 out UBRRnHr18 out UBRRnLr18 Setting the XCKn port pin as output enables master mode sbi XCKn_DDR XCKn Set MSPI mode of operation and SPI data mode 0 ldi r18 (1ltltUMSELn1)|(1ltltUMSELn0)|(0ltltUCPHAn)|(0ltltUCPOLn) out UCSRnCr18 Enable receiver and transmitter ldi r18 (1ltltRXENn)|(1ltltTXENn) out UCSRnBr18 Set baud rate IMPORTANT The Baud Rate must be set after the transmitter is enabled out UBRRnH r17 out UBRRnL r18 ret

UBRRn = 0

Setting the XCKn port pin as output enables master mode XCKn_DDR |= (1ltltXCKn) Set MSPI mode of operation and SPI data mode 0 UCSRnC = (1ltltUMSELn1)|(1ltltUMSELn0)|(0ltltUCPHAn)|(0ltltUCPOLn) Enable receiver and transmitter UCSRnB = (1ltltRXENn)|(1ltltTXENn) Set baud rate IMPORTANT The Baud Rate must be set after the transmitter is enabled UBRRn = baud

266 Data TransferUsing the USART in MSPI mode requires the Transmitter to be enabled ie the TXENn bit in theUCSRnB register is set to one When the Transmitter is enabled the normal port operation of the TxDnpin is overridden and given the function as the Transmitters serial output Enabling the receiver isoptional and is done by setting the RXENn bit in the UCSRnB register to one When the receiver isenabled the normal pin operation of the RxDn pin is overridden and given the function as the Receiversserial input The XCKn will in both cases be used as the transfer clock

After initialization the USART is ready for doing data transfers A data transfer is initiated by writing to theUDRn IO location This is the case for both sending and receiving data since the transmitter controls thetransfer clock The data written to UDRn is moved from the transmit buffer to the shift register when theshift register is ready to send a new frame

Note To keep the input buffer in sync with the number of data bytes transmitted the UDRn registermust be read once for each byte transmitted The input buffer operation is identical to normal USARTmode ie if an overflow occurs the character last received will be lost not the first data in the buffer Thismeans that if four bytes are transferred byte 1 first then byte 2 3 and 4 and the UDRn is not readbefore all transfers are completed then byte 3 to be received will be lost and not byte 1

The following code examples show a simple USART in MSPIM mode transfer function based on polling ofthe Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag The USART has to beinitialized before the function can be used For the assembly code the data to be sent is assumed to bestored in Register R16 and the data received will be available in the same register (R16) after the functionreturns

The function simply waits for the transmit buffer to be empty by checking the UDREn Flag before loadingit with new data to be transmitted The function then waits for data to be present in the receive buffer bychecking the RXCn Flag before reading the buffer and returning the value

USART_MSPIM_Transfer Wait for empty transmit buffer in r16 UCSRnA sbrs r16 UDREn rjmp USART_MSPIM_Transfer Put data (r16) into buffer sends the data out UDRnr16 Wait for data to be receivedUSART_MSPIM_Wait_RXCn in r16 UCSRnA sbrs r16 RXCn rjmp USART_MSPIM_Wait_RXCn Get and return received data from buffer in r16 UDRn ret

Wait for empty transmit buffer while ( ( UCSRnA amp (1ltltUDREn)) ) Put data into buffer sends the data UDRn = data Wait for data to be received while ( (UCSRnA amp (1ltltRXCn)) ) Get and return received data from buffer return UDRn

2661 Transmitter and Receiver Flags and InterruptsThe RXCn TXCn and UDREn flags and corresponding interrupts in USART in MSPIM mode areidentical in function to the normal USART operation However the receiver error status flags (FE DORand PE) are not in use and is always read as zero

2662 Disabling the Transmitter or ReceiverThe disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normalUSART operation

267 AVR USART MSPIM vs AVR SPIThe USART in MSPIM mode is fully compatible with the AVR SPI regarding

bull Master mode timing diagrambull The UCPOLn bit functionality is identical to the SPI CPOL bitbull The UCPHAn bit functionality is identical to the SPI CPHA bitbull The UDORDn bit functionality is identical to the SPI DORD bit

However since the USART in MSPIM mode reuses the USART resources the use of the USART inMSPIM mode is somewhat different compared to the SPI In addition to differences in the control registerbits and that only master operation is supported by the USART in MSPIM mode the following featuresdiffer between the two modules

bull The USART in MSPIM mode includes (double) buffering of the transmitter The SPI has no bufferbull The USART in MSPIM mode receiver includes an additional buffer levelbull The SPI WCOL (Write Collision) bit is not included in USART in MSPIM modebull The SPI double speed mode (SPI2X) bit is not included However the same effect is achieved by

setting UBRRn accordinglybull Interrupt timing is not compatiblebull Pin control differs due to the master only operation of the USART in MSPIM mode

A comparison of the USART in MSPIM mode and the SPI pins is shown in the table below

Table 26-3 Comparison of USART in MSPIM Mode and SPI Pins

USART_MSPIM SPI Comments

TxDn MOSI Master Out only

RxDn MISO Master In only

XCKn SCK (Functionally identical)

(NA) SS Not supported by USART in MSPIM

268 Register DescriptionRefer to the USART Register Description

27 TWI - Two-Wire Serial Interface

271 Featuresbull Two TWI instances TWI0 and TWI1bull Simple yet Powerful and Flexible Communication Interface only two Bus Lines Neededbull Both Master and Slave Operation Supportedbull Device can Operate as Transmitter or Receiverbull 7-bit Address Space Allows up to 128 Different Slave Addressesbull Multi-master Arbitration Supportbull Up to 400 kHz Data Transfer Speedbull Slew-rate Limited Output Driversbull Noise Suppression Circuitry Rejects Spikes on Bus Linesbull Fully Programmable Slave Address with General Call Supportbull Address Recognition Causes Wake-up When AVR is in Sleep Modebull Compatible with Philipsrsquo I2C protocol

272 Two-Wire Serial Interface Bus DefinitionThe Two-Wire Serial Interface (TWI) is ideally suited for typical microcontroller applications The TWIprotocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines one for clock (SCL) and one for data (SDA) The only external hardware needed toimplement the bus is a single pull-up resistor for each of the TWI bus lines All devices connected to thebus have individual addresses and mechanisms for resolving bus contention are inherent in the TWIprotocol

Figure 27-1 TWI Bus Interconnection

Device 1 Device 2 Device 3 Device n

2721 TWI TerminologyThe following definitions are frequently encountered in this section

ATmega328PB AutomotiveTWI - Two-Wire Serial Interface

Table 27-1 TWI Terminology

Term Description

Master The device that initiates and terminates a transmission The Master also generates theSCL clock

Slave The device addressed by a Master

Transmitter The device placing data on the bus

Receiver The device reading data from the bus

The Power Reduction TWI bit in the Power Reduction Register (PRRnPRTWI) must be written to 0 toenable the two-wire Serial Interface

TWI0 is in PRR0 and TWI1 is in PRR2

2722 Electrical InterconnectionAs depicted in the TWI Bus Definition both bus lines are connected to the positive supply voltage throughpull-up resistors The bus drivers of all TWI-compliant devices are open-drain or open-collector Thisimplements a wired-AND function which is essential to the operation of the interface A low level on a TWIbus line is generated when one or more TWI devices output a zero A high level is output when all TWIdevices tri-state their outputs allowing the pull-up resistors to pull the line high Note that all AVR devicesconnected to the TWI bus must be powered in order to allow any bus operation

The number of devices that can be connected to the bus is only limited by the bus capacitance limit of400 pF and the 7-bit slave address space Two different sets of specifications are presented there onerelevant for bus speeds below 100 kHz and one valid for bus speeds up to 400 kHz

273 Data Transfer and Frame Format

2731 Transferring BitsEach data bit transferred on the TWI bus is accompanied by a pulse on the clock line The level of thedata line must be stable when the clock line is high The only exception to this rule is for generating startand stop conditions

Figure 27-2 Data Validity

Data Stable Data Stable

Data Change

2732 START and STOP ConditionsThe Master initiates and terminates a data transmission The transmission is initiated when the Masterissues a START condition on the bus and it is terminated when the Master issues a STOP conditionBetween a START and a STOP condition the bus is considered busy and no other master should try toseize control of the bus A special case occurs when a new START condition is issued between a STARTand STOP condition This is referred to as a REPEATED START condition and is used when the Masterwishes to initiate a new transfer without relinquishing control of the bus After a REPEATED START thebus is considered busy until the next STOP This is identical to the START behavior and therefore STARTis used to describe both START and REPEATED START for the remainder of this data sheet unlessotherwise noted As depicted below START and STOP conditions are signaled by changing the level ofthe SDA line when the SCL line is high

Figure 27-3 START REPEATED START and STOP Conditions

START STOPREPEATED STARTSTOP START

2733 Address Packet FormatAll address packets transmitted on the TWI bus are nine bits long consisting of seven address bits oneREADWRITE control bit and an acknowledge bit If the READWRITE bit is set a read operation is to beperformed otherwise a write operation should be performed When a Slave recognizes that it is beingaddressed it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle If the addressedSlave is busy or for some other reason cannot service the Masterrsquos request the SDA line should be lefthigh in the ACK clock cycle The Master can then transmit a STOP condition or a REPEATED STARTcondition to initiate a new transmission An address packet consisting of a slave address and a READ ora WRITE bit is called SLA+R or SLA+W respectively

The MSB of the address byte is transmitted first Slave addresses can freely be allocated by the designerbut the address 0000 000 is reserved for a general call

When a general call is issued all slaves should respond by pulling the SDA line low in the ACK cycle Ageneral call is used when a Master wishes to transmit the same message to several slaves in the systemWhen the general call address followed by a Write bit is transmitted on the bus all slaves set up toacknowledge the general call will pull the SDA line low in the ACK cycle The following data packets willthen be received by all the slaves that acknowledged the general call Note that transmitting the generalcall address followed by a Read bit is meaningless as this would cause contention if several slavesstarted transmitting different data

All addresses of the format 1111 xxx should be reserved for future purposes

Figure 27-4 Address Packet Format

ST AR T

1 2 7 8 9

Addr MSB Addr LSB RW ACK

2734 Data Packet FormatAll data packets transmitted on the TWI bus are nine bits long consisting of one data byte and anacknowledge bit During a data transfer the Master generates the clock and the START and STOPconditions while the Receiver is responsible for acknowledging the reception An Acknowledge (ACK) issignaled by the Receiver pulling the SDA line low during the ninth SCL cycle If the Receiver leaves theSDA line high a NACK is signaled When the Receiver has received the last byte or for some reasoncannot receive any more bytes it should inform the Transmitter by sending a NACK after the final byteThe MSB of the data byte is transmitted first

Figure 27-5 Data Packet Format

1 2 7 8 9

Data MSB Data LSB ACK

AggregateSDA

SDA fromTransmitter

SDA fromReceiver

SCL fromMaster

SLA+RW Data ByteSTOP REPEATEDSTART or NextData Byte

2735 Combining Address and Data Packets Into a TransmissionA transmission basically consists of a START condition a SLA+RW one or more data packets and aSTOP condition An empty message consisting of a START followed by a STOP condition is illegal Notethat the Wired-ANDing of the SCL line can be used to implement handshaking between the Master andthe Slave The Slave can extend the SCL low period by pulling the SCL line low This is useful if the clockspeed set up by the Master is too fast for the Slave or the Slave needs extra time for processing betweenthe data transmissions The Slave extending the SCL low period will not affect the SCL high period whichis determined by the Master As a consequence the Slave can reduce the TWI data transfer speed byprolonging the SCL duty cycle

The following figure depicts a typical data transmission Note that several data bytes can be transmittedbetween the SLA+RW and the STOP condition depending on the software protocol implemented by theapplication software

Figure 27-6 Typical Data Transmission

1 2 7 8 9

Data Byte

SCL1 2 7 8 9

SLA+RW STOPSTART

274 Multi-Master Bus Systems Arbitration and SynchronizationThe TWI protocol allows bus systems with several masters Special concerns have been taken in order toensure that transmissions will proceed as normal even if two or more masters initiate a transmission atthe same time Two problems arise in multi-master systems

bull An algorithm must be implemented allowing only one of the masters to complete the transmissionAll other masters should cease transmission when they discover that they have lost the selectionprocess This selection process is called arbitration When a contending master discovers that ithas lost the arbitration process it should immediately switch to Slave mode to check whether it isbeing addressed by the winning master The fact that multiple masters have started transmission atthe same time should not be detectable to the slaves ie the data being transferred on the busmust not be corrupted

bull Different masters may use different SCL frequencies A scheme must be devised to synchronizethe serial clocks from all masters in order to let the transmission proceed in a lockstep fashionThis will facilitate the arbitration process

The wired-ANDing of the bus lines is used to solve both these problems The serial clocks from allmasters will be wired-ANDed yielding a combined clock with a high period equal to the one from theMaster with the shortest high period The low period of the combined clock is equal to the low period ofthe Master with the longest low period Note that all masters listen to the SCL line effectively starting tocount their SCL high and low time-out periods when the combined SCL line goes high or lowrespectively

Figure 27-7 SCL Synchronization Between Multiple MastersTA low TA high

SCL fromMaster A

SCL fromMaster B

SCL BusLine

TBlow TBhigh

Masters Start Counting Low Period

Masters StartCounting High Period

Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data If thevalue read from the SDA line does not match the value the Master had output it has lost the arbitrationNote that a Master can only lose arbitration when it outputs a high SDA value while another Masteroutputs a low value The losing Master should immediately go to Slave mode checking if it is beingaddressed by the winning Master The SDA line should be left high but losing masters are allowed togenerate a clock signal until the end of the current data or address packet Arbitration will continue untilonly one Master remains and this may take many bits If several masters are trying to address the sameSlave arbitration will continue into the data packet

Figure 27-8 Arbitration Between Two Masters

SDA from Master A

SDA from Master B

SDA Line

SynchronizedSCL Line

START Master A LosesArbitration SDAA SDA

Note that arbitration is not allowed between

bull A REPEATED START condition and a data bitbull A STOP condition and a data bitbull A REPEATED START and a STOP condition

It is the user softwarersquos responsibility to ensure that these illegal arbitration conditions never occur Thisimplies that in multi-master systems all data transfers must use the same composition of SLA+RW anddata packets In other words All transmissions must contain the same number of data packetsotherwise the result of the arbitration is undefined

275 Overview of the TWI ModuleThe TWI module is comprised of several submodules as shown in the following figure The registersdrawn in a thick line are accessible through the AVR data bus

Figure 27-9 Overview of the TWI Module

Address Register(TWAR)

Address Match Unit

Address Comparator

Control Unit

Control Register(TWCR)

Status Register(TWSR)

State Machine andStatus control

Slew-rateControl

SpikeFilter

ControlSpikeFilter

Bit Rate Generator

Bit Rate Register(TWBR)

Prescaler

Bus Interface Unit

START STOPControl

Arbitration detection Ack

Spike Suppression

AddressData ShiftRegister (TWDR)

Slew-rate

2751 SCL and SDA PinsThese pins interface the AVR TWI with the rest of the MCU system The output drivers contain a slew-rate limiter in order to conform to the TWI specification The input stages contain a spike suppression unitremoving spikes shorter than 50 ns Note that the internal pull-ups in the AVR pads can be enabled bysetting the PORT bits corresponding to the SCL and SDA pins as explained in the IO Port section Theinternal pull-ups can in some systems eliminate the need for external ones

2752 Bit Rate Generator UnitThis unit controls the period of SCL when operating in a Master mode The SCL period is controlled bysettings in the TWI Bit Rate Register (TWBRn) and the Prescaler bits in the TWI Status Register(TWSRn) Slave operation does not depend on Bit Rate or Prescaler settings but the CPU clockfrequency in the Slave must be at least 16 times higher than the SCL frequency Note that slaves mayprolong the SCL low period thereby reducing the average TWI bus clock period

The SCL frequency is generated according to the following equationSCL frequency = CPU Clock frequency16 + 2(TWBR) sdot PrescalerValuebull TWBR = Value of the TWI Bit Rate Register TWBRnbull PrescalerValue = Value of the prescaler see description of the TWI Prescaler bits in the TWSR

Status Register description (TWSRnTWPS[10])

Note Pull-up resistor values should be selected according to the SCL frequency and the capacitive busline load See the Two-Wire Serial Interface Characteristics for a suitable value of the pull-up resistor

Related Links348 Two-Wire Serial Interface Characteristics

2753 Bus Interface UnitThis unit contains the Data and Address Shift Register (TWDRn) a STARTSTOP Controller andArbitration detection hardware The TWDRn contains the address or data bytes to be transmitted or theaddress or data bytes received In addition to the 8-bit TWDRn the Bus Interface Unit also contains aregister containing the (N)ACK bit to be transmitted or received This (N)ACK Register is not directlyaccessible by the application software However when receiving it can be set or cleared by manipulatingthe TWI Control Register (TWCRn) When in Transmitter mode the value of the received (N)ACK bit canbe determined by the value in the TWSRn

The STARTSTOP Controller is responsible for generation and detection of START REPEATED STARTand STOP conditions The STARTSTOP controller is able to detect the START and STOP conditionseven when the AVR MCU is in one of the sleep modes enabling the MCU to wake up if addressed by aMaster

If the TWI has initiated a transmission as Master the Arbitration Detection hardware continuouslymonitors the transmission trying to determine if arbitration is in process If the TWI has lost an arbitrationthe Control Unit is informed Correct action can then be taken and appropriate status codes generated

2754 Address Match UnitThe Address Match unit checks if received address bytes match the seven-bit address in the TWIAddress Register (TWARn) If the TWI General Call Recognition Enable bit (TWARnTWGCE) is writtento 1 all incoming address bits will also be compared against the General Call address Upon an addressmatch the Control Unit is informed allowing the correct action to be taken The TWI may or may notacknowledge its address depending on settings in the TWI Control Register (TWCRn) The AddressMatch unit is able to compare addresses even when the AVR MCU is in sleep mode enabling the MCU towake up if addressed by a Master

2755 Control UnitThe Control unit monitors the TWI bus and generates responses corresponding to settings in the TWIControl Register (TWCRn) When an event requiring the attention of the application occurs on the TWIbus the TWI Interrupt Flag (TWINT) is asserted In the next clock cycle the TWI Status Register

(TWSRn) is updated with a status code identifying the event The TWSRn only contains relevant statusinformation when the TWI Interrupt Flag is asserted At all other times the TWSRn contains a specialstatus code indicating that no relevant status information is available As long as the TWINT Flag is setthe SCL line is held low This allows the application software to complete its tasks before allowing theTWI transmission to continue

The TWINT Flag is set in the following situations

bull After the TWI has transmitted a STARTREPEATED START conditionbull After the TWI has transmitted SLA+RWbull After the TWI has transmitted an address bytebull After the TWI has lost arbitrationbull After the TWI has been addressed by own slave address or general callbull After the TWI has received a data bytebull After a STOP or REPEATED START has been received while still addressed as a Slavebull When a bus error has occurred due to an illegal START or STOP condition

276 Using the TWIThe AVR TWI is byte-oriented and interrupt based Interrupts are issued after all bus events likereception of a byte or transmission of a START condition Because the TWI is interrupt-based theapplication software is free to carry on other operations during a TWI byte transfer Note that the TWIInterrupt Enable (TWIE) bit in TWCRn together with the Global Interrupt Enable bit in SREG allows theapplication to decide whether or not an assertion of the TWINT Flag should generate an interrupt requestIf the TWIE bit is cleared the application must poll the TWINT Flag in order to detect actions on the TWIbus

When the TWINT Flag is asserted the TWI has finished an operation and awaits application response Inthis case the TWI Status Register (TWSRn) contains a value indicating the current state of the TWI busThe application software can then decide how the TWI should behave in the next TWI bus cycle bymanipulating the TWCRn and TWDRn Registers

The following figure illustrates a simple example of how the application can interface to the TWIhardware In this example a Master wishes to transmit a single data byte to a Slave A more detailedexplanation follows later in this section Simple code examples are presented in the table below

Figure 27-10 Interfacing the Application to the TWI in a Typical Transmission

START SLA+W A Data A STOP

1 Applicationwrites to TWCR toinitiatetransmission ofSTART

2TWINT setStatus code indicatesSTART condition sent

4TWINT setStatus code indicatesSLA+W sent ACKreceived

6TWINT setStatus code indicatesdata sent ACK received

3 Check TWSR to see if START was sent Application loads SLA+W into TWDR and loads appropriate control signals into TWCR making sure that TWINT is written to one and TWSTA is written to zero

5 CheckTWSR to see if SLA+W wassent and ACK receivedApplication loads data into TWDR andloads appropriate control signals intoTWCR making sure that TWINT iswritten to one

7 CheckTWSR to see if data was sentand ACK receivedApplication loads appropriate controlsignals to send STOP into TWCRmaking sure that TWINT is written to one

TWI bus

IndicatesTWINT set

1 The first step in a TWI transmission is to transmit a START condition This is done by writing aspecific value into TWCRn instructing the TWI n hardware to transmit a START condition Whichvalue to write is described later on However it is important that the TWINT bit is set to the valuewritten Writing a one to TWINT clears the flag The TWI n will not start any operation as long asthe TWINT bit in TWCRn is set Immediately after the application has cleared TWINT the TWI n willinitiate transmission of the START condition

2 When the START condition has been transmitted the TWINT Flag in TWCRn is set and TWSRn isupdated with a status code indicating that the START condition has successfully been sent

3 The application software should now examine the value of TWSRn to make sure that the STARTcondition was successfully transmitted If TWSRn indicates otherwise the application softwaremight take some special action like calling an error routine Assuming that the status code is asexpected the application must load SLA+W into TWDR Remember that TWDRn is used both foraddress and data After TWDRn has been loaded with the desired SLA+W a specific value mustbe written to TWCRn instructing the TWIn hardware to transmit the SLA+W present in TWDRnWhich value to write is described later on However it is important that the TWINT bit is set to thevalue written Writing a one to TWINT clears the flag The TWI will not start any operation as longas the TWINT bit in TWCRn is set Immediately after the application has cleared TWINT the TWIwill initiate transmission of the address packet

4 When the address packet has been transmitted the TWINT Flag in TWCRn is set and TWSRn isupdated with a status code indicating that the address packet has successfully been sent Thestatus code will also reflect whether a Slave acknowledged the packet or not

5 The application software should now examine the value of TWSRn to make sure that the addresspacket was successfully transmitted and that the value of the ACK bit was as expected If TWSRnindicates otherwise the application software might take some special action like calling an errorroutine Assuming that the status code is as expected the application must load a data packet intoTWDRn Subsequently a specific value must be written to TWCRn instructing the TWI n hardwareto transmit the data packet present in TWDRn Which value to write is described later on Howeverit is important that the TWINT bit is set to the value written Writing a one to TWINT clears the flagThe TWI n will not start any operation as long as the TWINT bit in TWCRn is set Immediately afterthe application has cleared TWINT the TWI will initiate transmission of the data packet

6 When the data packet has been transmitted the TWINT Flag in TWCRn is set and TWSRn isupdated with a status code indicating that the data packet has successfully been sent The statuscode will also reflect whether a Slave acknowledged the packet or not

7 The application software should now examine the value of TWSRn to make sure that the datapacket was successfully transmitted and that the value of the ACK bit was as expected If TWSRindicates otherwise the application software might take some special action like calling an errorroutine Assuming that the status code is as expected the application must write a specific value toTWCRn instructing the TWI n hardware to transmit a STOP condition Which value to write isdescribed later on However it is important that the TWINT bit is set to the value written Writing aone to TWINT clears the flag The TWI n will not start any operation as long as the TWINT bit inTWCRn is set Immediately after the application has cleared TWINT the TWI will initiatetransmission of the STOP condition Note that TWINT is not set after a STOP condition has beensent

Even though this example is simple it shows the principles involved in all TWI transmissions These canbe summarized as follows

bull When the TWI has finished an operation and expects application response the TWINT Flag is setThe SCL line is pulled low until TWINT is cleared

bull When the TWINT Flag is set the user must update all TWI n Registers with the value relevant forthe next TWI n bus cycle As an example TWDRn must be loaded with the value to be transmittedin the next bus cycle

bull After all TWI n Register updates and other pending application software tasks have beencompleted TWCRn is written When writing TWCRn the TWINT bit should be set Writing a one toTWINT clears the flag The TWI n will then commence executing whatever operation was specifiedby the TWCRn setting

The following table lists assembly and C implementation examples for TWI0 Note that the code belowassumes that several definitions have been made eg by using include-files

Table 27-2 Assembly and C Code Example

Assembly Code Example C Example Comments

1 ldi r16 (1ltltTWINT)|(1ltltTWSTA)|(1ltltTWEN) out TWCR0 r16

TWCR0 = (1ltltTWINT)|(1ltltTWSTA)|(1ltltTWEN)

Send START condition

2 wait1 in r16TWCR0 sbrs r16TWINT rjmp wait1

while ((TWCR0 amp (1ltltTWINT)))

Wait for TWINT Flag set This indicatesthat the START condition has beentransmitted

3 in r16TWSR0 andi r16 0xF8 cpi r16 START brne ERROR

if ((TWSR0 amp 0xF8) = START) ERROR()

Check value of TWI Status Register Maskprescaler bits If status different fromSTART go to ERROR

ldi r16 SLA_W out TWDR0 r16 ldi r16 (1ltltTWINT) | (1ltltTWEN) out TWCR0 r16

TWDR0 = SLA_W TWCR0 = (1ltltTWINT) | (1ltltTWEN)

Load SLA_W into TWDR Register ClearTWINT bit in TWCR to start transmission ofaddress

Wait for TWINT Flag set This indicatesthat the SLA+W has been transmitted andACKNACK has been received

5 in r16TWSR0 andi r16 0xF8 cpi r16 MT_SLA_ACK brne ERROR

if ((TWSR0 amp 0xF8) = MT_SLA_ACK) ERROR()

Check value of TWI Status Register Maskprescaler bits If status different fromMT_SLA_ACK go to ERROR

ldi r16 DATA out TWDR0 r16 ldi r16 (1ltltTWINT) | (1ltltTWEN) out TWCR r16

TWDR0 = DATA TWCR0 = (1ltltTWINT) | (1ltltTWEN)

Load DATA into TWDR Register ClearTWINT bit in TWCR to start transmission ofdata

Wait for TWINT Flag set This indicatesthat the DATA has been transmitted andACKNACK has been received

7 in r16TWSR0 andi r16 0xF8 cpi r16 MT_DATA_ACK brne ERROR

if ((TWSR0 amp 0xF8) = MT_DATA_ACK) ERROR()

Check value of TWI Status Register Maskprescaler bits If status different fromMT_DATA_ACK go to ERROR

ldi r16 (1ltltTWINT)|(1ltltTWEN)| (1ltltTWSTO) out TWCR0 r16

TWCR0 = (1ltltTWINT)|(1ltltTWEN)|(1ltltTWSTO)

Transmit STOP condition

277 Transmission ModesThe TWI can operate in one of four major modes

bull Master Transmitter (MT)bull Master Receiver (MR)bull Slave Transmitter (ST)bull Slave Receiver (SR)

Several of these modes can be used in the same application As an example the TWI can use MT modeto write data into a TWI EEPROM MR mode to read the data back from the EEPROM If other mastersare present in the system some of these might transmit data to the TWI and then SR mode would beused It is the application software that decides which modes are legal

The following sections describe each of these modes Possible status codes are described along withfigures detailing data transmission in each of the modes These figures use the following abbreviations

S START condition

Rs REPEATED START condition

R Read bit (high level at SDA)

W Write bit (low level at SDA)

A Acknowledge bit (low level at SDA)

A Not acknowledge bit (high level at SDA)

Data 8-bit data byte

P STOP condition

SLA Slave Address

Circles are used to indicate that the TWINT Flag is set The numbers in the circles show the status codeheld in TWSRn with the prescaler bits masked to zero At these points actions must be taken by theapplication to continue or complete the TWI transfer The TWI transfer is suspended until the TWINT Flagis cleared by software

When the TWINT Flag is set the status code in TWSRn is used to determine the appropriate softwareaction For each status code the required software action and details of the following serial transfer aregiven below in the Status Code table for each mode Note that the prescaler bits are masked to zero inthese tables

2771 Master Transmitter ModeIn the Master Transmitter (MT) mode a number of data bytes are transmitted to a Slave Receiver seethe figure below In order to enter a Master mode a START condition must be transmitted The format ofthe following address packet determines whether MT or Master Receiver (MR) mode is to be entered IfSLA+W is transmitted the MT mode is entered if SLA+R is transmitted the MR mode is entered All thestatus codes mentioned in this section assume that the prescaler bits are zero or masked to zero

Figure 27-11 Data Transfer in Master Transmitter Mode

Device 1MASTER

TRANSMITTER

Device 2SLAVE

RECEIVERDevice 3 Device n

A START condition is sent by writing a value to the TWI Control Register n (TWCRn) of the typeTWCRn=1x10x10x

bull The TWI Enable bit (TWCRnTWEN) must be written to 1 to enable the two-wire Serial Interfacebull The TWI Start Condition bit (TWCRnTWSTA) must be written to 1 to transmit a START conditionbull The TWI Interrupt Flag (TWCRnTWINT) must be written to 1 to clear the flag

The TWI n will then test the two-wire Serial Bus and generate a START condition as soon as the busbecomes free After a START condition has been transmitted the TWINT Flag is set by hardware andthe status code in TWSRn will be 0x08 (see Status Code table below) In order to enter MT mode SLA

+W must be transmitted This is done by writing SLA+W to the TWI Data Register (TWDRn) Thereafterthe TWCRnTWINT Flag should be cleared (by writing a 1 to it) to continue the transfer This isaccomplished by writing a value to TWRC of the type TWCR=1x00x10x

When SLA+W has been transmitted and an acknowledgment bit has been received TWINT is set againand a number of status codes in TWSR are possible Possible status codes in Master mode are 0x180x20 or 0x38 The appropriate action to be taken for each of these status codes is detailed in the StatusCode table below

When SLA+W has been successfully transmitted a data packet should be transmitted This is done bywriting the data byte to TWDR TWDR must only be written when TWINT is high If not the access will bediscarded and the Write Collision bit (TWWC) will be set in the TWCRn Register After updating TWDRnthe TWINT bit should be cleared (by writing 1 to it) to continue the transfer This is accomplished bywriting again a value to TWCRn of the type TWCRn=1x00x10x

This scheme is repeated until the last byte has been sent and the transfer is ended either by generatinga STOP condition or a by a repeated START condition A repeated START condition is accomplished bywriting a regular START value TWCRn=1x10x10x A STOP condition is generated by writing a value ofthe type TWCRn=1x01x10x

After a repeated START condition (status code 0x10) the two-wire Serial Interface can access the sameSlave again or a new Slave without transmitting a STOP condition Repeated START enables the Masterto switch between Slaves Master Transmitter mode and Master Receiver mode without losing control ofthe bus

Table 27-3 Status Codes for Master Transmitter Mode

Status Code(TWSR)

PrescalerBits are 0

Status of the Two-WireSerial Bus and Two-WireSerial Interface Hardware

Application Software Response Next Action Taken by TWIHardware

ToFromTWDR

To TWCRn

STA STO TWINT TWEA

0x08 A START condition has beentransmitted

Load SLA+W 0 0 1 X SLA+W will be transmittedACK or NOT ACK will bereceived

0x10 A repeated START conditionhas been transmitted

Load SLA+Wor

0 0 1 X SLA+W will be transmittedACK or NOT ACK will bereceived

Load SLA+R 0 0 1 X SLA+R will be transmittedLogic will switch to MasterReceiver mode

0x18 SLA+W has been transmittedACK has been received

Load databyte or

0 0 1 X Data byte will be transmittedand ACK or NOT ACK will bereceived

No TWDRaction or

1 0 1 X Repeated START will betransmitted

No TWDRaction or

0 1 1 X STOP condition will betransmitted and TWSTO Flagwill be reset

No TWDRaction

1 1 1 X STOP condition followed by aSTART condition will be

Status Code(TWSR)

PrescalerBits are 0

ToFromTWDR

To TWCRn

STA STO TWINT TWEA

transmitted and TWSTO Flagwill be reset

0x20 SLA+W has been transmittedNOT ACK has been received

Load databyte or

No TWDRaction or

No TWDRaction

1 1 1 X STOP condition followed by aSTART condition will betransmitted and TWSTO Flagwill be reset

0x28 Data byte has beentransmittedACK has been received

Load databyte or

No TWDRaction or

No TWDRaction

0x30 Data byte has beentransmittedNOT ACK has been received

Load databyte or

No TWDRaction or

No TWDRaction

Status Code(TWSR)

PrescalerBits are 0

ToFromTWDR

To TWCRn

STA STO TWINT TWEA

0x38 Arbitration lost in SLA+W ordata bytes

No TWDRaction or

0 0 1 X two-wire Serial Bus will bereleased and not addressedSlave mode entered

No TWDRaction

1 0 1 X A START condition will betransmitted when the busbecomes free

Figure 27-12 Formats and States in the Master Transmitter Mode

S SLA W A DATA A P

0x08 0x18 0x28

R SLA W

A or A

Other mastercontinues A or A

Other mastercontinues

0x78 0xB0 To correspondingstates in slave mode

Successfulltransmissionto a slavereceiver

Next transferstarted with arepeated startcondition

Not acknowledgereceived after theslave address

Not acknowledgereceived after a databyte

Arbitration lost in slaveaddress or data byte

Arbitration lost andaddressed as slave

DATA A

From master to slave

From slave to master

Any number of data bytesand their associated acknowledge bits

This number (contained in TWSR) correspondsto a defined state of the Two-Wire Serial Bus Theprescaler bits are zero or masked to zero

2772 Master Receiver ModeIn the Master Receiver (MR) mode a number of data bytes are received from a Slave Transmitter (seenext figure) In order to enter a Master mode a START condition must be transmitted The format of thefollowing address packet determines whether Master Transmitter (MT) or MR mode is to be entered IfSLA+W is transmitted the MT mode is entered if SLA+R is transmitted the MR mode is entered All thestatus codes mentioned in this section assume that the prescaler bits are zero or are masked to zero

Figure 27-13 Data Transfer in Master Receiver Mode

Device 1MASTER

RECEIVER

Device 2SLAVE

TRANSMITTERDevice 3 Device n

A START condition is sent by writing to the TWI Control register (TWCRn) a value of the typeTWCRn=1x10x10x

bull TWCRnTWEN must be written to 1 to enable the two-wire Serial Interfacebull TWCRnTWSTA must be written to 1 to transmit a START conditionbull TWCRnTWINT must be cleared by writing a 1 to it

The TWI will then test the two-wire Serial Bus and generate a START condition as soon as the busbecomes free After a START condition has been transmitted the TWINT Flag is set by hardware and thestatus code in TWSRn will be 0x08 (see the Status Code table below) In order to enter MR mode SLA+R must be transmitted This is done by writing SLA+R to TWDR Thereafter the TWINT flag should becleared (by writing 1 to it) to continue the transfer This is accomplished by writing a value to TWCRn ofthe type TWCRn=1x00x10x

When SLA+R has been transmitted and an acknowledgment bit has been received TWINT is set againand a number of status codes in TWSRn are possible Possible status codes in Master mode are 0x380x40 or 0x48 The appropriate action to be taken for each of these status codes is detailed in the tablebelow Received data can be read from the TWDR Register when the TWINT Flag is set high byhardware This scheme is repeated until the last byte has been received After the last byte has beenreceived the MR should inform the ST by sending a NACK after the last received data byte The transferis ended by generating a STOP condition or a repeated START condition A repeated START condition issent by writing to the TWI Control register (TWCRn) a value of the type TWCRn=1x10x10x again ASTOP condition is generated by writing TWCRn=1x01x10x

After a repeated START condition (status code 0x10) the two-wire Serial Interface can access the sameSlave again or a new Slave without transmitting a STOP condition Repeated START enables the Masterto switch between Slaves Master Transmitter mode and Master Receiver mode without losing controlover the bus

Table 27-4 Status codes for Master Receiver Mode

Status Code(TWSRn)

Prescaler Bitsare 0

Status of the Two-Wire SerialBus and Two-Wire SerialInterface Hardware

ToFromTWD

To TWCRn

STA STO TWINT TWEA

Load SLA+R 0 0 1 X SLA+R will be transmitted

Status Code(TWSRn)

Prescaler Bitsare 0

ToFromTWD

To TWCRn

STA STO TWINT TWEA

ACK or NOT ACK will bereceived

Load SLA+R 0 0 1 X SLA+R will be transmittedACK or NOT ACK will bereceived

Load SLA+W 0 0 1 X SLA+W will be transmitted

Logic will switch to MasterTransmitter mode

0x38 Arbitration lost in SLA+R orNOT ACK bit

No TWDRaction

0 0 1 X two-wire Serial Bus will bereleased and not addressedSlave mode will be entered

0x40 SLA+R has been transmittedACK has been received

No TWDRaction

0 0 1 0 Data byte will be received andNOT ACK will be returned

0 0 1 1 Data byte will be received andACK will be returned

0x48 SLA+R has been transmittedNOT ACK has been received

0x50 Data byte has been receivedACK has been returned

Read databyte

0x58 Data byte has been receivedNOT ACK has been returned

Read databyte

Figure 27-14 Formats and States in the Master Receiver Mode

S SLA R A A

0x08 0x40 0x50

A or A

0x38 0x38

0x68 0x78 0xB0

Successfullreceptionfrom a slavereceiver

To correspondingstates in slave mode

DATA A

DATA DATA

2773 Slave Transmitter ModeIn the Slave Transmitter (ST) mode a number of data bytes are transmitted to a Master Receiver as inthe figure below All the status codes mentioned in this section assume that the prescaler bits are zero orare masked to zero

Figure 27-15 Data Transfer in Slave Transmitter Mode

Device 3 Device n

Device 2MASTER

RECEIVER

Device 1SLA VE

TRANSMITTER

To initiate the SR mode the TWI (Slave) Address Register (TWARn) and the TWI Control Register(TWCRn) must be initialized as follows

The upper seven bits of TWARn are the address to which the two-wire Serial Interface will respond whenaddressed by a Master (TWARnTWA[60]) If the LSB of TWARn is written to TWARnTWGCI=1 the TWIwill respond to the general call address (0x00) otherwise it will ignore the general call address

TWCRn must hold a value of the type TWCRn=0100010x - TWEN must be written to one to enable theTWI The TWEA bit must be written to one to enable the acknowledgment of the devicersquos own slaveaddress or the general call address TWSTA and TWSTO must be written to zero

When TWARn and TWCRn have been initialized the TWI waits until it is addressed by its own slaveaddress (or the general call address if enabled) followed by the data direction bit If the direction bit is ldquo1rdquo(read) the TWI will operate in ST mode otherwise SR mode is entered After its own slave address andthe write bit have been received the TWINT Flag is set and a valid status code can be read fromTWSRb The status code is used to determine the appropriate sofTWARne action The appropriate actionto be taken for each status code is detailed in the table below The ST mode may also be entered ifarbitration is lost while the TWI is in the Master mode (see state 0xB0)

If the TWCRnTWEA bit is written to zero during a transfer the TWI will transmit the last byte of thetransfer State 0xC0 or state 0xC8 will be entered depending on whether the Master Receiver transmits aNACK or ACK after the final byte The TWI is switched to the not addressed Slave mode and will ignorethe Master if it continues the transfer Thus the Master Receiver receives all 1 as serial data State 0xC8is entered if the Master demands additional data bytes (by transmitting ACK) even though the Slave hastransmitted the last byte (TWEA zero and expecting NACK from the Master)

While TWCRnTWEA is zero the TWI does not respond to its own slave address However the two-wireSerial Bus is still monitored and address recognition may resume at any time by setting TWEA Thisimplies that the TWEA bit may be used to temporarily isolate the TWI from the two-wire Serial Bus

In all sleep modes other than the Idle mode the clock system to the TWI is turned off If the TWEA bit isset the interface can still acknowledge its own slave address or the general call address by using thetwo-wire Serial Bus clock as a clock source The part will then wake up from sleep and the TWI will holdthe SCL clock will low during the wake-up and until the TWINT Flag is cleared (by writing 1 to it) Furtherdata transmission will be carried out as normal with the AVR clocks running as normal Observe that ifthe AVR is set up with a long start-up time the SCL line may be held low for a long time blocking otherdata transmissions

Note The two-wire Serial Interface Data Register (TWDRn) does not reflect the last byte present on thebus when waking up from these Sleep modes

Table 27-5 Status Codes for Slave Transmitter Mode

Status Code(TWSRb)

PrescalerBits are 0

Application SofTWARne Response Next Action Taken by TWIHardware

ToFromTWDRn

To TWCRn

STA STO TWINT TWEA

0xA8 Own SLA+R has beenreceivedACK has been returned

Load databyte

X 0 1 0 Last data byte will be transmittedand NOT ACK should be received

X 0 1 1 Data byte will be transmitted andACK should be received

0xB0 Arbitration lost in SLA+RW asMaster

own SLA+R has beenreceived

ACK has been returned

Load databyte

0xB8 Data byte in TWDRn has beentransmitted

ACK has been received

Load databyte

0xC0 Data byte in TWDRn has beentransmitted

NOT ACK has been received

No TWDRnaction

0 0 1 0 Switched to the not addressedSlave modeno recognition of own SLA orGCA

0 0 1 1 Switched to the not addressedSlave mode

own SLA will be recognized

GCA will be recognized ifTWGCE = ldquo1rdquo

no recognition of own SLA orGCA

a START condition will betransmitted when the busbecomes free

GCA will be recognized ifTWGCE = ldquo1rdquo a START conditionwill be transmitted when the busbecomes free

Status Code(TWSRb)

PrescalerBits are 0

ToFromTWDRn

To TWCRn

STA STO TWINT TWEA

0xC8 Last data byte in TWDRn hasbeen transmitted (TWEA =ldquo0rdquo)

No TWDRnaction

a START condition will betransmitted when the bus

becomes free

Figure 27-16 Formats and States in the Slave Transmitter Mode

S SLA R A A

0xA8 0xB8

P or S

DATA A

P or SAll 1s

AReception of the ownslave address and one ormore data bytes

Arbitration lost as masterand addressed as slave

Last data byte transmittedSwitched to not addressedslave (TWEA = 0)

This number (contained in TWSR) correspondsto a defined state of the Two-Wire Ser ial Bus Theprescaler bits are zero or masked to zero

DATA DATA

2774 Slave Receiver ModeIn the Slave Receiver (SR) mode a number of data bytes are received from a Master Transmitter (seefigure below) All the status codes mentioned in this section assume that the prescaler bits are zero or aremasked to zero

Figure 27-17 Data transfer in Slave Receiver mode

Device 3 Device n

Device 2MASTER

TRANSMITTER

Device 1SLAVE

RECEIVER

To initiate the SR mode the TWI (Slave) Address Register n (TWARn) and the TWI Control Register n(TWCRn) must be initialized as follows

The upper seven bits of TWARn are the address to which the two-wire Serial Interface will respond whenaddressed by a Master (TWARnTWA[60]) If the LSB of TWARn is written to TWARnTWGCI=1 the TWIn will respond to the general call address (0x00) otherwise it will ignore the general call address

TWCRn must hold a value of the type TWCRn=0100010x - TWCRnTWEN must be written to 1 toenable the TWI TWCRnTWEA bit must be written to 1 to enable the acknowledgment of the devicersquosown slave address or the general call address TWCRnTWSTA and TWSTO must be written to zero

When TWARn and TWCRn have been initialized the TWI waits until it is addressed by its own slaveaddress (or the general call address if enabled) followed by the data direction bit If the direction bit is 0(write) the TWI will operate in SR mode otherwise ST mode is entered After its own slave address andthe write bit have been received the TWINT Flag is set and a valid status code can be read from TWSRThe status code is used to determine the appropriate software action as detailed in the table below TheSR mode may also be entered if arbitration is lost while the TWI is in the Master mode (see states 0x68and 0x78)

If the TWCRnTWEA bit is reset during a transfer the TWI will return a Not Acknowledge (1) to SDAafter the next received data byte This can be used to indicate that the Slave is not able to receive anymore bytes While TWEA is zero the TWI does not acknowledge its own slave address However thetwo-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEAThis implies that the TWEA bit may be used to temporarily isolate the TWI from the two-wire Serial Bus

In all sleep modes other than the Idle mode the clock system to the TWI is turned off If the TWEA bit isset the interface can still acknowledge its own slave address or the general call address by using thetwo-wire Serial Bus clock as a clock source The part will then wake up from sleep and the TWI will holdthe SCL clock low during the wake-up and until the TWINT Flag is cleared (by writing 1 to it) Furtherdata reception will be carried out as normal with the AVR clocks running as normal Observe that if theAVR is set up with a long start-up time the SCL line may be held low for a long time blocking other datatransmissions

Table 27-6 Status Codes for Slave Receiver Mode

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

0x60 Own SLA+W has beenreceivedACK has been returned

No TWDRnaction

X 0 1 0 Data byte will be received andNOT ACK will be returned

X 0 1 1 Data byte will be received andACK will be returned

0x68 Arbitration lost in SLA+RW asMaster

own SLA+W has beenreceived

No TWDRnaction

0x70 General call address has beenreceived

No TWDRnaction

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

General call address has beenreceived

0x80 Previously addressed with ownSLA+W

data has been received

Read databyte

NOT ACK has been returned

Read databyte

becomes free

0x90 Previously addressed withgeneral call

Read databyte

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

NOT ACK has been returned 0 0 1 1 Switched to the not addressedSlave mode

0xA0 A STOP condition or repeatedSTART condition has beenreceived while still addressedas Slave

No action 0 0 1 0 Switched to the not addressedSlave modeno recognition of own SLA orGCA

becomes free

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

Figure 27-18 Formats and States in the Slave Receiver Mode

S SLA W A DATA A

0x60 0x80

P or SDATA A

0x80 0xA0

P or SA

A DATA A

0x70 0x90

P or SDATA A

0x90 0xA0

P or SA

General Call

DATA A

Reception of the ownslave address and one ormore data bytes All areacknowledged

Last data byte receivedis not acknowledged

Reception of the general calladdress and one or more databytes

Last data byte received isnot acknowledged

Arbitration lost as master andaddressed as sla v e b y gene r al call

This n umber (contained in TWSR) correspondsto a defined state of the Two-Wire Serial Bus Theprescaler bits are zero or masked to zero

2775 Miscellaneous StatesThere are two status codes that do not correspond to a defined TWI state see the table in this section

Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set Thisoccurs between other states and when the TWI is not involved in a serial transfer

Status 0x00 indicates that a bus error has occurred during a two-wire Serial Bus transfer A bus erroroccurs when a START or STOP condition occurs at an illegal position in the format frame Examples ofsuch illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bitWhen a bus error occurs TWINT is set To recover from a bus error the TWSTO Flag must set andTWINT must be cleared by writing a logic one to it This causes the TWI to enter the not addressed Slavemode and to clear the TWSTO Flag (no other bits in TWCRn are affected) The SDA and SCL lines arereleased and no STOP condition is transmitted

Table 27-7 Miscellaneous States

Status Code(TWSR)

Prescaler Bits are0

Application Software Response Next Action Taken byTWI Hardware

ToFromTWDRn

To TWCRn

STA STO TWINT TWEA

0xF8 No relevant state informationavailable TWINT = ldquo0rdquo

No TWDRnaction

No TWCRn action Wait or proceed currenttransfer

0x00 Bus error due to an illegalSTART or STOP condition

No TWDRnaction

0 1 1 X Only the internal hardwareis affected no STOPcondition is sent on thebus In all cases the bus isreleased and TWSTO iscleared

2776 Combining Several TWI ModesIn some cases several TWI modes must be combined in order to complete the desired action Considerfor example reading data from a serial EEPROM Typically such a transfer involves the following steps

1 The transfer must be initiated2 The EEPROM must be instructed what location should be read3 The reading must be performed4 The transfer must be finished

Note that data is transmitted both from Master to Slave and vice versa The Master must instruct theSlave what location it wants to read requiring the use of the MT mode Subsequently data must be readfrom the Slave implying the use of the MR mode Thus the transfer direction must be changed TheMaster must keep control of the bus during all these steps and the steps should be carried out as anatomical operation If this principle is violated in a multi-master system another Master can alter the datapointer in the EEPROM between steps 2 and 3 and the Master will read the wrong data location Such achange in transfer direction is accomplished by transmitting a REPEATED START between thetransmission of the address byte and reception of the data After a REPEATED START the Master keepsownership of the bus The flow in this transfer is depicted in the following figure

Figure 27-19 Combining Several TWI Modes to Access a Serial EEPROMMaster Transmitter Master Receiver

S = START Rs = REPEATED START P = STOP

Transmitted from master to slave Transmitted from slave to master

S SLA+W A ADDRESS A Rs SLA+R A DATA A P

278 Multi-Master Systems and ArbitrationIf multiple masters are connected to the same bus transmissions may be initiated simultaneously by oneor more of them The TWI standard ensures that such situations are handled in such a way that one ofthe masters will be allowed to proceed with the transfer and that no data will be lost in the process Anexample of an arbitration situation is depicted below where two masters are trying to transmit data to aSlave Receiver

Figure 27-20 An Arbitration Example

Device 1MASTER

TRANSMITTER

Device 2MASTER

TRANSMITTER

Device 3SLAVE

RECEIVERDevice n

Several different scenarios may arise during arbitration as described below

bull Two or more masters are performing identical communication with the same Slave In this caseneither the Slave nor any of the masters will know about the bus contention

bull Two or more masters are accessing the same Slave with different data or direction bit In this casearbitration will occur either in the READWRITE bit or in the data bits The masters trying to outputa 1 on SDA while another Master outputs a zero will lose the arbitration Losing masters will switchto not addressed Slave mode or wait until the bus is free and transmit a new START conditiondepending on application software action

bull Two or more masters are accessing different slaves In this case arbitration will occur in the SLAbits Masters trying to output a 1 on SDA while another Master outputs a zero will lose thearbitration Masters losing arbitration in SLA will switch to Slave mode to check if they are beingaddressed by the winning Master If addressed they will switch to SR or ST mode depending onthe value of the READWRITE bit If they are not being addressed they will switch to not addressedSlave mode or wait until the bus is free and transmit a new START condition depending onapplication software action

This is summarized in the next figure Possible status values are given in circles

Figure 27-21 Possible Status Codes Caused by Arbitration

OwnAddress General Call

received

Arbitration lost in SLA

TWI bus will be released and not addressed slave mode will be enteredA START condition will be transmitted when the bus becomes free

Arbitration lost in Data

Direction

Data byte will be received and NOT ACK will be returnedData byte will be received and ACK will be returned

Last data byte will be transmitted and NOT ACK should be receivedData byte will be transmitted and ACK should be received

SLASTART Data STOP

ReadB0

2791 TWI n Bit Rate Register

Name TWBROffset 0xB8 + n0x20 [n=01]Reset 0x00Property -

Bit 7 6 5 4 3 2 1 0 TWBR [70]

Bits 70 ndash TWBR [70] TWI Bit Rate RegisterTWBR selects the division factor for the bit rate generator The bit rate generator is a frequency dividerwhich generates the SCL clock frequency in the Master modes

2792 TWI Status Register n

Name TWSROffset 0xB9 + n0x20 [n=01]Reset 0xF8Property -

Bit 7 6 5 4 3 2 1 0 TWS7 TWS6 TWS5 TWS4 TWS3 TWPS[10]

Access R R R R R RW RW Reset 1 1 1 1 1 0 0

Bits 3 4 5 6 7 ndash TWS TWI Status BitThe TWS[73] reflect the status of the TWI logic and the two-wire Serial Bus The different status codesare described in 277 Transmission Modes Note that the value read from TWSR contains both the 5-bitstatus value and the 2-bit prescaler value The application designer should mask the prescaler bits tozero when checking the Status bits This makes status checking independent of prescaler setting Thisapproach is used in this data sheet unless otherwise noted

Bits 10 ndash TWPS[10] TWI PrescalerThese bits can be read and written and control the bit rate prescaler

Table 27-8 TWI Bit Rate Prescaler

TWPS[10] Prescaler Value

To calculate bit rates refer to 2752 Bit Rate Generator Unit The value of TWPS[10] is used in theequation

2793 TWI (Slave) Address Register n

Name TWAROffset 0xBA + n0x20 [n=01]Reset 0x02Property -

The TWARn should be loaded with the 7-bit Slave address (in the seven most significant bits of TWARn)to which the TWI n will respond when programmed as a Slave Transmitter or Receiver and not needed inthe Master modes In multi-master systems TWARn must be set in masters which can be addressed asSlaves by other Masters

The LSB of TWARn is used to enable recognition of the general call address (0x00) There is anassociated address comparator that looks for the slave address (or general call address if enabled) in thereceived serial address If a match is found an interrupt request is generated

Bit 7 6 5 4 3 2 1 0 TWA[60] TWGCE

Bits 71 ndash TWA[60] TWI (Slave) AddressThese seven bits constitute the slave address of the TWI n unit

Bit 0 ndash TWGCE TWI General Call Recognition Enable BitIf set this bit enables the recognition of a General Call given over the two-wire Serial Bus n

2794 TWI Data Register n

Name TWDROffset 0xBB + n0x20 [n=01]Reset 0x01Property -

In Transmit mode TWDRn contains the next byte to be transmitted In Receive mode the TWDRncontains the last byte received It is writable while the TWI n is not in the process of shifting a byte Thisoccurs when the TWI Interrupt Flag in the TWI Control Register n (TWCRnTWINT) is set by hardwareNote that the Data Register cannot be initialized by the user before the first interrupt occurs The data inTWDRn remains stable as long as TWCRnTWINT is set While data is shifted out data on the bus issimultaneously shifted in TWDRn always contains the last byte present on the bus except after a wakeup from a sleep mode by the TWI n interrupt In this case the contents of TWDRn is undefined In thecase of a lost bus arbitration no data is lost in the transition from Master to Slave Handling of the ACKbit is controlled automatically by the TWI logic the CPU cannot access the ACK bit directly

Bit 7 6 5 4 3 2 1 0 TWD[70]

Bits 70 ndash TWD[70] TWI DataThese eight bits constitute the next data byte to be transmitted or the latest data byte received on thetwo-wire Serial Bus

2795 TWI Control Register n

Name TWCROffset 0xBC + n0x20 [n=01]Reset 0x00Property -

The TWCRn is used to control the operation of the TWI n It is used to enable the TWI n to initiate aMaster access by applying a START condition to the bus to generate a Receiver acknowledge togenerate a stop condition and to control halting of the bus while the data to be written to the bus arewritten to the TWDRn It also indicates a write collision if data is attempted written to TWDRn while theregister is inaccessible

Bit 7 6 5 4 3 2 1 0 TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE

Access RW RW RW RW R RW RW Reset 0 0 0 0 0 0 0

Bit 7 ndash TWINT TWI Interrupt FlagThis bit is set by hardware when the TWI n has finished its current job and expects application softwareresponse If the I-bit in the Status Register (SREGI) and the TWI Interrupt Enable bit in the TWI ControlRegister n (TWCRnTWIE) are set the MCU will jump to the TWI Interrupt Vector While the TWINT Flagis set the SCL low period is stretched The TWINT Flag must be cleared by software by writing a logicone to it

Note that this flag is not automatically cleared by hardware when executing the interrupt routine Alsonote that clearing this flag starts the operation of the TWI n so all accesses to the TWI Address Register(TWARn) TWI Status Register (TWSRn) and TWI Data Register (TWDRn) must be complete beforeclearing this flag

Bit 6 ndash TWEA TWI Enable AcknowledgeThis bit controls the generation of the acknowledge pulse If the TWEA bit is written to one the ACKpulse is generated on the TWI n bus if the following conditions are met

1 The devicersquos own slave address has been received2 A general call has been received while the TWGCE bit in the TWARn is set3 A data byte has been received in Master Receiver or Slave Receiver mode

By writing the TWEA bit to zero the device can be virtually disconnected from the two-wire Serial Bustemporarily Address recognition can then be resumed by writing the TWEA bit to one again

Bit 5 ndash TWSTA TWI START ConditionThe application writes the TWSTA bit to one when it desires TWI n to become a Master on the two-wireSerial Bus The TWI n hardware checks if the bus is available and generates a START condition on thebus if it is free However if the bus is not free the TWI n waits until a STOP condition is detected andthen generates a new START condition to claim the bus Master status TWSTA must be cleared bysoftware when the START condition has been transmitted

Bit 4 ndash TWSTO TWI STOP ConditionWriting the TWSTO bit to one in Master mode will generate a STOP condition on the two-wire Serial BusTWI n When the STOP condition is executed on the bus the TWSTO bit is automatically cleared In

Slave mode setting the TWSTO bit can be used to recover from an error condition This will not generatea STOP condition but the TWI n returns to a well-defined unaddressed Slave mode and releases theSCL and SDA lines to a high impedance state

Bit 3 ndash TWWC TWI Write Collision FlagThe TWWC bit is set when attempting to write to the TWI n Data Register (TWDRn) whenTWCRnTWINT is low This flag is cleared by writing the TWDRn register when TWINT is high

Bit 2 ndash TWEN TWI EnableThe TWEN bit enables TWI n operation and activates the TWI n interface When TWEN is written to onethe TWI n takes control over the IO pins connected to the SCL and SDA pins enabling the slew-ratelimiters and spike filters If this bit is written to zero the TWI n is switched OFF and all transmissions ofTWI n are terminated regardless of any ongoing operation

Bit 0 ndash TWIE TWI Interrupt EnableWhen this bit is written to one and the I-bit in the Status Register (SREGI) is set the TWI n interruptrequest will be activated for as long as the TWCRnTWINT Flag is high

2796 TWI (Slave) Address Mask Register n

Name TWAMROffset 0xBD + n0x20 [n=01]Reset 0x00Property -

Bit 7 6 5 4 3 2 1 0 TWAM[60]

Bits 71 ndash TWAM[60] TWI (Slave) AddressThe TWAMRn can be loaded with a 7-bit Slave Address mask Each of the bits in TWAMRn can mask(disable) the corresponding address bits in the TWI Address Register n (TWARn) If the mask bit is set toone then the address match logic ignores the compare between the incoming address bit and thecorresponding bit in TWARn

Figure 27-22 Address Match Logic Example For TWI0

TWAMR0

AddressBit 0

AddressMatch

Address Bit Comparator 61

28 AC - Analog Comparator

281 OverviewThe Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1 the AnalogComparator output ACO is set The comparatorrsquos output can be set to trigger the TimerCounter1 InputCapture function In addition the comparator can trigger a separate interrupt exclusive to the AnalogComparator The user can select Interrupt triggering on comparator output rise fall or toggle A blockdiagram of the comparator and its surrounding logic is shown below

The Power Reduction ADC bit in the Power Reduction Register (PRR0PRADC) must be written to 0 inorder to be able to use the ADC input MUX

Figure 28-1 Analog Comparator Block Diagram

BANDGAPREFERENCE

ADC MULTIPLEXEROUTPUT

ACMEADEN

INTERRUPT SELECT

ACIS1 ACIS0 ACIC

TO TC1 CAPTURETRIGGER MUX

ANALOGCOMPARATORIRQ

Note Refer to the Pin Configuration and the IO Ports description for Analog Comparator pin placement

Related Links18 IO-Ports14123 PRR05 Pin Configurations14 PM - Power Management and Sleep Modes1411 Minimizing Power Consumption

282 Analog Comparator Multiplexed InputIt is possible to select any of the ADC[70] pins to replace the negative input to the Analog ComparatorThe ADC multiplexer is used to select this input and consequently the ADC must be switched off toutilize this feature If the Analog Comparator Multiplexer Enable bit in the ADC Control and StatusRegister B (ADCSRBACME) is 1 and the ADC is switched off (ADCSRAADEN=0) the three leastsignificant Analog Channel Selection bits in the ADC Multiplexer Selection register (ADMUXMUX[20])select the input pin to replace the negative input to the Analog Comparator as shown in the table belowWhen ADCSRBACME=0 or ADCSRAADEN=1 AIN1 is applied to the negative input of the AnalogComparator

ATmega328PB AutomotiveAC - Analog Comparator

Table 28-1 Analog Comparator Multiplexed Input

ACME ADEN MUX[20] Analog Comparator Negative Input

0 x xxx AIN1

1 1 xxx AIN1

1 0 000 ADC0

1 0 001 ADC1

1 0 010 ADC2

1 0 011 ADC3

1 0 100 ADC4

1 0 101 ADC5

1 0 110 ADC6

1 0 111 ADC7

2831 Analog Comparator Control and Status Register

Name ACSROffset 0x50Reset NAProperty When addressing as IO Register address offset is 0x30

Bit 7 6 5 4 3 2 1 0 ACD ACBG ACO ACI ACIE ACIC ACIS [10]

Access RW RW R RW RW RW RW RW Reset 0 0 0 0 0 0 0 0

Bit 7 ndash ACD Analog Comparator DisableWhen this bit is written logic one the power to the Analog Comparator is switched off This bit can be setat any time to turn off the Analog Comparator This will reduce power consumption in Active and Idlemode When changing the ACD bit the Analog Comparator Interrupt must be disabled by clearing theACIE bit in ACSR Otherwise an interrupt can occur when the bit is changed

Bit 6 ndash ACBG Analog Comparator Bandgap SelectWhen this bit is set a fixed bandgap reference voltage replaces the positive input to the AnalogComparator When this bit is cleared AIN0 is applied to the positive input of the Analog ComparatorWhen the bandgap reference is used as input to the Analog Comparator it will take a certain time for thevoltage to stabilize If not stabilized the first conversion may give a wrong value

Bit 5 ndash ACO Analog Comparator OutputThe output of the Analog Comparator is synchronized and then directly connected to ACO Thesynchronization introduces a delay of 1 - 2 clock cycles

Bit 4 ndash ACI Analog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1and ACIS0 The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit inSREG is set ACI is cleared by hardware when executing the corresponding interrupt handling vectorAlternatively ACI is cleared by writing a logic one to the flag

Bit 3 ndash ACIE Analog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set the Analog Comparatorinterrupt is activated When written logic zero the interrupt is disabled

Bit 2 ndash ACIC Analog Comparator Input Capture EnableWhen written logic one this bit enables the input capture function in TimerCounter1 to be triggered bythe Analog Comparator The comparator output is in this case directly connected to the input capturefront-end logic making the comparator utilize the noise canceler and edge select features of the Timer

Counter1 Input Capture interrupt When written logic zero no connection between the AnalogComparator and the input capture function exists To make the comparator trigger the TimerCounter1Input Capture interrupt the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set

Bits 10 ndash ACIS [10] Analog Comparator Interrupt Mode SelectThese bits determine which comparator events that trigger the Analog Comparator interrupt

Table 28-2 ACIS[10] Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle

0 1 Reserved

1 0 Comparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge

When changing the ACIS1ACIS0 bits the Analog Comparator Interrupt must be disabled by clearing itsInterrupt Enable bit in the ACSR Register Otherwise an interrupt can occur when the bits are changed

2832 Digital Input Disable Register 1

Name DIDR1Offset 0x7FReset 0x00Property -

Bit 7 6 5 4 3 2 1 0 AIN1D AIN0D

Access R R R R R R RW RW Reset 0 0 0 0 0 0 0 0

Bits 0 1 ndash AIND AIN Digital Input DisableWhen this bit is written logic one the digital input buffer on the AIN10 pin is disabled The correspondingPIN Register bit will always read as zero when this bit is set When an analog signal is applied to theAIN10 pin and the digital input from this pin is not needed this bit should be written logic one to reducepower consumption in the digital input buffer

29 ADC - Analog to Digital Converter

291 Featuresbull 10-bit Resolutionbull 05 LSB Integral Nonlinearitybull plusmn35 LSB Absolute Accuracybull 13 - 260 μs Conversion Timebull Up to 20 kSPS Maximum Conversion Speed (faster ADC rates may be allowed for industrial

devices)bull Six Multiplexed Single-Ended Input Channelsbull Two Additional Multiplexed Single Ended Input Channels (TQFP and QFN Package only)bull Optional Left Adjustment for ADC Result Readoutbull 0 - VCC ADC Input Voltage Rangebull Selectable 11V ADC Reference Voltagebull Free Running or Single Conversion Modebull Interrupt on ADC Conversion Completebull Sleep Mode Noise Canceler

292 OverviewThe device features a 10-bit successive approximation ADC The ADC is connected to an 8-channelAnalog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port AThe single-ended voltage inputs refer to 0V (GND)

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at aconstant level during conversion A block diagram of the ADC is shown below

The ADC has a separate analog supply voltage pin AVCC AVCC must not differ more than plusmn03V fromVCC See section 296 ADC Noise Canceler on how to connect this pin

The Power Reduction ADC bit in the Power Reduction Register (PRR0PRADC) must be written to 0 inorder to enable the ADC

The ADC converts an analog input voltage to a 10-bit digital value through successive approximationThe minimum value represents GND and the maximum value represents the voltage on the AREF pinminus 1 LSB Optionally AVCC or an internal 11V reference voltage may be connected to the AREF pinby writing to the REFSn bits in the ADMUX Register The internal voltage reference must be decoupledby an external capacitor at the AREF pin to improve noise immunity

ATmega328PB AutomotiveADC - Analog to Digital Converter

Figure 29-1 Analog to Digital Converter Block Schematic OperationADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

15 0ADC MULTIPLEXER

SELECT (ADMUX)ADC CTRL amp STATUSREGISTER (ADCSRA)

ADC DATA REGISTER (ADCHADCL)

CONVERSION LOGIC

10-BIT DAC+-

SAMPLE amp HOLDCOMPARATOR

INTERNAL 11V REFERENCE

MUX DECODER

]ADC MULTIPLEXER OUTPUT

BANDGAP REFERENCE

PRESCALER

INPUT MUX

The analog input channel is selected by writing to the MUX bits in the ADC Multiplexer Selection registerADMUXMUX[30] Any of the ADC input pins as well as GND and a fixed bandgap voltage referencecan be selected as single ended inputs to the ADC The ADC is enabled by writing a 1 to the ADCEnable bit in the ADC Control and Status Register A (ADCSRAADEN) Voltage reference and inputchannel selections will not take effect until ADEN is set The ADC does not consume power when ADENis cleared so it is recommended to switch the ADC OFF before entering the power-saving sleep modes

The ADC generates a 10-bit result which is presented in the ADC Data Registers ADCH and ADCL Bydefault the result is presented right adjusted but can optionally be presented left adjusted by setting theADC Left Adjust Result bit ADMUXADLAR

If the result is left adjusted and no more than 8-bit precision is required it is sufficient to read ADCHOtherwise ADCL must be read first then ADCH to ensure that the content of the Data Registers belongs

to the same conversion Once ADCL is read the ADC access to the Data Registers is blocked Thismeans that if ADCL has been read and a second conversion completes before ADCH is read neitherregister is updated and the result from the second conversion is lost When ADCH is read ADC access tothe ADCH and ADCL Registers is re-enabled

The ADC has its own interrupt which can be triggered when a conversion completes When ADC accessto the Data Registers is prohibited between the reading of ADCH and ADCL the interrupt will trigger evenif the result is lost

Related Links14 PM - Power Management and Sleep Modes1410 Power Reduction Registers

293 Starting a ConversionA single conversion is started by writing a 0 to the Power Reduction ADC bit in the Power ReductionRegister (PRR0PRADC) and writing a 1 to the ADC Start Conversion bit in the ADC Control and StatusRegister A (ADCSRAADSC) ADCS will stay high as long as the conversion is in progress and will becleared by hardware when the conversion is completed If a different data channel is selected while aconversion is in progress the ADC will finish the current conversion before performing the channelchange

Alternatively a conversion can be triggered automatically by various sources Auto Triggering is enabledby setting the ADC Auto Trigger Enable bit (ADCSRAADATE) The trigger source is selected by settingthe ADC Trigger Select bits in the ADC Control and Status Register B (ADCSRBADTS) See thedescription of the ADCSRBADTS for a list of available trigger sources

When a positive edge occurs on the selected trigger signal the ADC prescaler is reset and a conversionis started This provides a method of starting conversions at fixed intervals If the trigger signal still is setwhen the conversion completes a new conversion will not be started If another positive edge occurs onthe trigger signal during conversion the edge will be ignored Note that an interrupt flag will be set even ifthe specific interrupt is disabled or the Global Interrupt Enable bit in the AVR Status Register (SREGI) iscleared A conversion can thus be triggered without causing an interrupt However the Interrupt Flagmust be cleared in order to trigger a new conversion at the next interrupt event

Figure 29-2 ADC Auto Trigger Logic

SOURCE 1

SOURCE n

ADTS[20]

CONVERSIONLOGIC

PRESCALER

START CLKADC

EDGEDETECTOR

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as theongoing conversion has finished The ADC then operates in Free Running mode constantly sampling

and updating the ADC Data Register The first conversion must be started by writing a 1 toADCSRAADSC In this mode the ADC will perform successive conversions independently of whetherthe ADC Interrupt Flag (ADIF) is cleared or not

If Auto Triggering is enabled single conversions can be started by writing ADCSRAADSC to 1 ADSCcan also be used to determine if a conversion is in progress The ADSC bit will be read as 1 during aconversion independently of how the conversion was started

294 Prescaling and Conversion TimingFigure 29-3 ADC Prescaler

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0ADPS1ADPS2

ResetADENSTART

By default the successive approximation circuitry requires an input clock frequency between 50 kHz and200 kHz to get maximum resolution If a lower resolution than 10 bits is needed the input clock frequencyto the ADC can be higher than 200 kHz to get a higher sample rate

The ADC module contains a prescaler which generates an acceptable ADC clock frequency from anyCPU frequency above 100 kHz The prescaling is selected by the ADC Prescaler Select bits in the ADCControl and Status Register A (ADCSRAADPS) The prescaler starts counting from the moment the ADCis switched on by writing the ADC Enable bit ADCSRAADEN to 1 The prescaler keeps running for aslong as ADEN=1 and is continuously reset when ADEN=0

When initiating a single ended conversion by writing a 1 to the ADC Start Conversion bit(ADCSRAADSC) the conversion starts at the following rising edge of the ADC clock cycle

A normal conversion takes 13 ADC clock cycles The first conversion after the ADC is switched on (ieADCSRAADEN is written to 1) takes 25 ADC clock cycles in order to initialize the analog circuitry

When the bandgap reference voltage is used as input to the ADC it will take a certain time for the voltageto stabilize If not stabilized the first value read after the first conversion may be wrong

The actual sample-and-hold takes place 15 ADC clock cycles after the start of a normal conversion and135 ADC clock cycles after the start of a first conversion When a conversion is complete the result iswritten to the ADC Data Registers (ADCL and ADCH) and the ADC Interrupt Flag (ADCSRAADIF) is setIn Single Conversion mode ADCSRAADSC is cleared simultaneously The software may then setADCSRAADSC again and a new conversion will be initiated on the first rising ADC clock edge

When Auto Triggering is used the prescaler is reset when the trigger event occurs This assures a fixeddelay from the trigger event to the start of conversion In this mode the sample-and-hold takes place twoADC clock cycles after the rising edge on the trigger source signal Three additional CPU clock cycles areused for synchronization logic

In Free Running mode a new conversion will be started immediately after the conversion completeswhile ADCRSAADSC remains high See also the ADC Conversion Time table below

Figure 29-4 ADC Timing Diagram First Conversion (Single Conversion Mode)

Sign and MSB of Result

LSB of Result

ADC Clock

Sample and Hold

Cycle Number

1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2

First ConversionNextConversion

MUX and REFSUpdate

ConversionComplete

Figure 29-5 ADC Timing Diagram Single Conversion

1 2 3 4 5 6 7 8 9 10 11 12 13

LSB of Result

ADC Clock

Cycle Number 1 2

One Conversion Next Conversion

Sample and HoldMUX and REFSUpdate

ConversionComplete

MUX and REFSUpdate

Figure 29-6 ADC Timing Diagram Auto Triggered Conversion

1 2 3 4 5 6 7 8 9 10 11 12 13

LSB of Result

ADC Clock

TriggerSource

Cycle Number 1 2

ConversionCompletePrescaler

PrescalerReset

Sample ampHold

MUX and REFSUpdate

Figure 29-7 ADC Timing Diagram Free Running Conversion

11 12 13

LSB of Result

ADC Clock

Cycle Number 1 2

ConversionComplete

Table 29-1 ADC Conversion Time

Condition Sample amp Hold [Cycles from Start of Conversion]

Conversion Time [Cycles]

First conversion 135 25

Normal conversions single ended 15 13

Auto Triggered conversions 2 135

295 Changing Channel or Reference SelectionThe Analog Channel Selection bits (MUX) and the Reference Selection bits (REFS) bits in the ADCMultiplexer Selection Register (ADMUXMUX and ADMUXREFS) are single buffered through atemporary register to which the CPU has random access This ensures that the channels and reference

selection only takes place at a safe point during the conversion The channel and reference selection iscontinuously updated until a conversion is started Once the conversion starts the channel and referenceselection is locked to ensure a sufficient sampling time for the ADC Continuous updating resumes in thelast ADC clock cycle before the conversion completes (indicated by ADCSRAADIF set) Note that theconversion starts on the following rising ADC clock edge after ADSC is written The user is thus advisednot to write new channel or reference selection values to ADMUX until one ADC clock cycle after theADC Start Conversion bit (ADCRSAADSC) was written

If Auto Triggering is used the exact time of the triggering event can be indeterministic Special care mustbe taken when updating the ADMUX Register in order to control which conversion will be affected by thenew settings

If both the ADC Auto Trigger Enable and ADC Enable bits (ADCRSAADATE ADCRSAADEN) arewritten to 1 an interrupt event can occur at any time If the ADMUX Register is changed in this periodthe user cannot tell if the next conversion is based on the old or the new settings ADMUX can be safelyupdated in the following ways

1 When ADATE or ADEN is cleared11 During conversion minimum one ADC clock cycle after the trigger event12 After a conversion before the Interrupt Flag used as trigger source is cleared

When updating ADMUX in one of these conditions the new settings will affect the next ADC conversion

2951 ADC Input ChannelsWhen changing channel selections the user should observe the following guidelines to ensure that thecorrect channel is selected

bull In Single Conversion mode always select the channel before starting the conversion The channelselection may be changed one ADC clock cycle after writing one to ADSC However the simplestmethod is to wait for the conversion to complete before changing the channel selection

bull In Free Running mode always select the channel before starting the first conversion The channelselection may be changed one ADC clock cycle after writing one to ADSC However the simplestmethod is to wait for the first conversion to complete and then change the channel selection Sincethe next conversion has already started automatically the next result will reflect the previouschannel selection Subsequent conversions will reflect the new channel selection

The user is advised not to write new channel or reference selection values during the Free Runningmode

2952 ADC Voltage ReferenceThe reference voltage for the ADC (VREF) indicates the conversion range for the ADC Single-endedchannels that exceed VREF will result in codes close to 0x3FF VREF can be selected as either AVCCinternal 11V reference or external AREF pin

AVCC is connected to the ADC through a passive switch The internal 11V reference is generated fromthe internal bandgap reference (VBG) through an internal amplifier In either case the external AREF pinis directly connected to the ADC and the reference voltage can be made more immune to noise byconnecting a capacitor between the AREF pin and ground VREF can also be measured at the AREF pinwith a high impedance voltmeter Note that VREF is a high impedance source and only a capacitive loadshould be connected to a system

If the user has a fixed voltage source connected to the AREF pin the user may not use the otherreference voltage options in the application as they will be shorted to the external voltage If no externalvoltage is applied to the AREF pin the user may switch between AVCC and 11V as reference selection

The first ADC conversion result after switching reference voltage source may be inaccurate and the useris advised to discard this result

296 ADC Noise CancelerThe ADC features a noise canceler that enables conversion during sleep mode to reduce noise inducedfrom the CPU core and other IO peripherals The noise canceler can be used with ADC Noise Reductionand Idle mode To make use of this feature the following procedure should be used

1 Make sure that the ADC is enabled and is not busy converting Single Conversion mode must beselected and the ADC conversion complete interrupt must be enabled

2 Enter ADC Noise Reduction mode (or Idle mode) The ADC will start a conversion once the CPUhas been halted

3 If no other interrupts occur before the ADC conversion completes the ADC interrupt will wake upthe CPU and execute the ADC Conversion Complete interrupt routine If another interrupt wakes upthe CPU before the ADC conversion is complete that interrupt will be executed and an ADCConversion Complete interrupt request will be generated when the ADC conversion completes TheCPU will remain in active mode until a new sleep command is executed

Note The ADC will not be automatically turned off when entering other sleep modes than Idle mode andADC Noise Reduction mode The user is advised to write zero to ADCRSAADEN before entering suchsleep modes to avoid excessive power consumption

2961 Analog Input CircuitryThe analog input circuitry for single ended channels is illustrated below An analog source applied toADCn is subjected to the pin capacitance and input leakage of that pin regardless of whether thatchannel is selected as input for the ADC When the channel is selected the source must drive the SHcapacitor through the series resistance (combined resistance in the input path)

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less If sucha source is used the sampling time will be negligible If a source with higher impedance is used thesampling time will depend on how long time the source needs to charge the SH capacitor with can varywidely The user is recommended to use only low impedance sources with slowly varying signals sincethis minimizes the required charge transfer to the SH capacitor

Signal components higher than the Nyquist frequency (fADC2) should not be present for either kind ofchannels to avoid distortion from unpredictable signal convolution The user is advised to remove highfrequency components with a low-pass filter before applying the signals as inputs to the ADC

Figure 29-8 Analog Input Circuitry

1100k ΩCSH = 14pF

IILVCC2

2962 Analog Noise Canceling TechniquesDigital circuitry inside and outside the device generates EMI which might affect the accuracy of analogmeasurements If conversion accuracy is critical the noise level can be reduced by applying the followingtechniques

1 Keep analog signal paths as short as possible Make sure analog tracks run over the analogground plane and keep them well away from high-speed switching digital tracks11 The AVCC pin on the device should be connected to the digital VCC supply voltage via an LCnetwork as shown in the figure below

12 Use the ADC noise canceler function to reduce induced noise from the CPU

13 If any ADC [30] port pins are used as digital outputs it is essential that these do not switchwhile a conversion is in progress However using the two-wire Interface (ADC4 and ADC5) will onlyaffect the conversion on ADC4 and ADC5 and not the other ADC channels

Figure 29-9 ADC Power Connections

PC1 (ADC1)

PC0 (ADC0)

10 micro

Note If the resistivity in the inductor is too high the AVCC may exceed its range VCC - 03V lt AVCC ltVCC + 03V

2963 ADC Accuracy DefinitionsAn n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs) Thelowest code is read as 0 and the highest code is read as 2n-1

Several parameters describe the deviation from the ideal behavior

bull Offset The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 05LSB) Ideal value 0 LSB

Figure 29-10 Offset ErrorOutput Code

VREF Input Voltage

Ideal ADC

Actual ADC

OffsetError

bull Gain error After adjusting for offset the gain error is found as the deviation of the last transition(0x3FE to 0x3FF) compared to the ideal transition (at 15 LSB below maximum) Ideal value 0LSB

Figure 29-11 Gain ErrorOutput Code

VREF Input Voltage

Ideal ADC

Actual ADC

GainError

bull Integral Non-linearity (INL) After adjusting for offset and gain error the INL is the maximumdeviation of an actual transition compared to an ideal transition for any code Ideal value 0 LSB

Figure 29-12 Integral Non-linearity (INL)Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

bull Differential Non-linearity (DNL) The maximum deviation of the actual code width (the intervalbetween two adjacent transitions) from the ideal code width (1 LSB) Ideal value 0 LSB

Figure 29-13 Differential Non-Linearity (DNL)Output Code

0 VREF Input Voltage

bull Quantization Error Due to the quantization of the input voltage into a finite number of codes arange of input voltages (1 LSB wide) will code to the same value Always plusmn05 LSB

bull Absolute accuracy The maximum deviation of an actual (unadjusted) transition compared to anideal transition for any code This is the compound effect of offset gain error differential error non-linearity and quantization error Ideal value plusmn05 LSB

297 ADC Conversion ResultAfter the conversion is complete (ADCSRAADIF is set) the conversion result can be found in the ADCResult Registers (ADCL ADCH)

For single-ended conversion the result isADC = IN sdot 1024REF

where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see alsodescriptions of ADMUXREFSn and ADMUXMUX) 0x000 represents analog ground and 0x3FFrepresents the selected reference voltage minus one LSB

2981 ADC Multiplexer Selection Register

Name ADMUXOffset 0x7CReset 0x00Property -

Bit 7 6 5 4 3 2 1 0 REFS [10] ADLAR MUX [30]

Bits 76 ndash REFS [10] Reference SelectionThese bits select the voltage reference for the ADC If these bits are changed during a conversion thechange will not go into effect until this conversion is complete (ADIF in ADCSRA is set) The internalvoltage reference options may not be used if an external reference voltage is being applied to the AREFpin

Table 29-2 ADC Voltage Reference Selection

REFS[10] Voltage Reference Selection

00 AREF Internal Vref turned OFF

01 AVCC with external capacitor at AREF pin

10 Reserved

11 Internal 11V Voltage Reference with external capacitor at AREF pin

Bit 5 ndash ADLAR ADC Left Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register Write oneto ADLAR to left adjust the result Otherwise the result is right adjusted Changing the ADLAR bit willaffect the ADC Data Register immediately regardless of any ongoing conversions For a completedescription of this bit refer to ADCL and ADCH

Bits 30 ndash MUX [30] Analog Channel SelectionThe value of these bits selects which analog inputs are connected to the ADC If these bits are changedduring a conversion the change will not go in effect until this conversion is complete (ADIF in 2982 ADCSRA is set)

Table 29-3 Input Channel Selection

MUX[30] Single Ended Input

0000 ADC0

0001 ADC1

0010 ADC2

0011 ADC3

0100 ADC4

0101 ADC5

0110 ADC6

0111 ADC7

1000 Reserved

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 11V (VBG)

1111 0V (GND)

Related Links156 Watchdog System Reset

3287 Setting the Boot Loader Lock Bits by SPMTo set the Boot Loader Lock bits and general Lock Bits write the desired data to R0 write ldquo0x0001001rdquo toSPMCSR and execute SPM within four clock cycles after writing SPMCSR

Bit 7 6 5 4 3 2 1 0

R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1

The tables in 326 Boot Loader Lock Bits show how the different settings of the Boot Loader bits affectthe Flash access

If bits 50 in R0 are cleared (zero) the corresponding Lock bit will be programmed if an SPM instructionis executed within four cycles after BLBSET and SPMEN are set in SPMCSR (SPMCSRBLBSET andSPMCSRSPMEN) The Z-pointer donrsquot care during this operation but for future compatibility it isrecommended to load the Z-pointer with 0x0001 (same as used for reading the lOck bits) For futurecompatibility it is also recommended to set bits 7 and 6 in R0 to ldquo1rdquo when writing the Lock bits Whenprogramming the Lock bits the entire Flash can be read during the operation

3288 EEPROM Write Prevents Writing to SPMCSRAn EEPROM write operation will block all software programming to Flash Reading the Fuses and Lockbits from software will also be prevented during the EEPROM write operation It is recommended that theuser checks the status bit (EEPE) in the EECR Register (EECREEPE) and verifies that the bit is clearedbefore writing to the SPMCSR Register

3289 Reading the Fuse and Lock Bits from SoftwareIt is possible to read both the Fuse and Lock bits (LB) from software To read the Lock bits load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR (SPMCSRBLBSET andSPMCSRSPMEN) When an LPM instruction is executed within three CPU cycles after the BLBSET andSPMEN bits are set in SPMCSR (SPMCSRBLBSET and SPMCSRSPMEN) the value of the Lock bitswill be loaded in the destination register The SPMCSRBLBSET and SPMCSRSPMEN will auto-clearupon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles orno SPM instruction is executed within four CPU cycles When SPMCSRBLBSET and SPMCSRSPMENare cleared LPM will work as described in the Instruction set Manual

Bit 7 6 5 4 3 2 1 0

Rd - - BLB12 BLB11 BLB02 BLB01 LB2 LB1

The algorithm for reading the Fuse Low byte (FLB) is similar to the one described above for reading theLock bits To read the Fuse Low byte load the Z-pointer with 0x0000 and set the BLBSET and SPMENbits in SPMCSR (SPMCSRBLBSET and SPMCSRSPMEN) When an LPM instruction is executed within

three cycles after the SPMCSRBLBSET and SPMCSRSPMEN are set the value of the Fuse Low byte(FLB) will be loaded into the destination register as shown below

Bit 7 6 5 4 3 2 1 0

Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Similarly when reading the Fuse High byte (FHB) load 0x0003 in the Z-pointer When an LPM instructionis executed within three cycles after the SPMCSRBLBSET and SPMCSRSPMEN are set the value ofthe Fuse High byte (FHB) will be loaded into the destination register as shown below

Bit 7 6 5 4 3 2 1 0

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

When reading the Extended Fuse byte (EFB) load 0x0002 in the Z-pointer When an LPM instruction isexecuted within three cycles after the SPMCSRBLBSET and SPMCSRSPMEN are set the value of theExtended Fuse byte (EFB) will be loaded into the destination register as shown below

Bit 7 6 5 4 3 2 1 0

Rd - - - - EFB3 EFB2 EFB1 EFB0

Fuse and Lock bits that are programmed read as 0 Fuse and Lock bits that are unprogrammed will readas 1

32810 Reading the Signature Row from SoftwareTo read the Signature Row from software load the Z-pointer with the signature byte address given in thefollowing table and set the SIGRD and SPMEN bits in SPMCSR (SPMCSRSIGRD andSPMCSRSPMEN) When an LPM instruction is executed within three CPU cycles after theSPMCSRSIGRD and SPMCSRSPMEN are set the signature byte value will be loaded in thedestination register The SPMCSRSIGRD and SPMCSRSPMEN will auto-clear upon completion ofreading the Signature Row Lock bits or if no LPM instruction is executed within three CPU cycles WhenSPMCSRSIGRD and SPMCSRSPMEN are cleared LPM will work as described in the Instruction setManual

32811 Preventing Flash CorruptionDuring periods of low VCC the Flash program can be corrupted because the supply voltage is too low forthe CPU and the Flash to operate properly These issues are the same as for board level systems usingthe Flash and the same design solutions should be applied

A Flash program corruption can be caused by two situations when the voltage is too low First a regularwrite sequence to the Flash requires a minimum voltage to operate correctly Secondly the CPU itself canexecute instructions incorrectly if the supply voltage for executing instructions is too low

Flash corruption can easily be avoided by following these design recommendations (one is sufficient)

1 If it is no need for a Boot Loader update in the system program the Boot Loader Lock bits toprevent any Boot Loader software updates

2 Keep the AVR RESET active (low) during periods of insufficient power supply voltage This can bedone by enabling the internal Brown-out Detector (BOD) if the operating voltage matches thedetection level If not an external low VCC reset protection circuit can be used If a reset occurs

while a write operation is in progress the write operation will be completed provided that the powersupply voltage is sufficient

3 Keep the AVR core in Power-Down Sleep mode during periods of low VCC This will prevent theCPU from attempting to decode and execute instructions effectively protecting the SPMCSRRegister and thus the Flash from unintentional writes

32812 Programming Time for Flash when Using SPMThe calibrated RC Oscillator is used to time Flash accesses The following table shows the typicalprogramming time for Flash accesses from the CPU

Table 32-5 SPM Programming Time

Symbol Min ProgrammingTime

Max ProgrammingTime

Flash write (Page Erase Page Write and write Lockbits by SPM)

32 ms 34 ms

Note Minimum and maximum programming time is per individual operation

32813 Simple Assembly Code Example for a Boot Loader

-the routine writes one page of data from RAM to Flash the first data location in RAM is pointed to by the Y pointer the first data location in Flash is pointed to by the Z-pointer -error handling is not included -the routine must be placed inside the Boot space (at least the Do_spm sub routine) Only code inside NRWW section can be read during Self-Programming (Page Erase and Page Write) -registers used r0 r1 temp1 (r16) temp2 (r17) looplo (r24) loophi (r25) spmcrval (r20) storing and restoring of registers is not included in the routine register usage can be optimized at the expense of code size -It is assumed that either the interrupt table is moved to the Boot loader section or that the interrupts are disabled

equ PAGESIZEB = PAGESIZE2 PAGESIZEB is page size in BYTES not words

org SMALLBOOTSTART

Write_page Page Erase ldi spmcrval (1ltltPGERS) | (1ltltSPMEN) call Do_spm

re-enable the RWW section must be avoided if the page buffer is pre-filled Will flush the page buffer

ldi spmcrval (1ltltRWWSRE) | (1ltltSPMEN) call Do_spm

transfer data from RAM to Flash page buffer ldi looplo low(PAGESIZEB) init loop variable ldi loophi high(PAGESIZEB) not required for PAGESIZEBlt=256

Wrloop ld r0 Y+ ld r1 Y+ ldi spmcrval (1ltltSPMEN) call Do_spm adiw ZHZL 2 sbiw loophilooplo 2 use subi for PAGESIZEBlt=256 brne Wrloop

execute Page Write subi ZL low(PAGESIZEB) restore pointer sbci ZH high(PAGESIZEB) not required for PAGESIZEBlt=256 ldi spmcrval (1ltltPGWRT) | (1ltltSPMEN) call Do_spm

re-enable the RWW section ldi spmcrval (1ltltRWWSRE) | (1ltltSPMEN) call Do_spm

read back and check optional ldi looplo low(PAGESIZEB) init loop variable ldi loophi high(PAGESIZEB) not required for PAGESIZEBlt=256 subi YL low(PAGESIZEB) restore pointer sbci YH high(PAGESIZEB)

Rdloop lpm r0 Z+ ld r1 Y+ cpse r0 r1 jmp Error sbiw loophilooplo 1 use subi for PAGESIZEBlt=256 brne Rdloop

return to RWW section verify that RWW section is safe to read

Return in temp1 SPMCSR sbrs temp1 RWWSB If RWWSB is set the RWW section is not ready yet ret re-enable the RWW section ldi spmcrval (1ltltRWWSRE) | (1ltltSPMEN) call Do_spm rjmp Return

Do_spm check for previous SPM complete

Wait_spm in temp1 SPMCSR sbrc temp1 SPMEN rjmp Wait_spm

input spmcrval determines SPM action disable interrupts if enabled store status in temp2 SREG cli check that no EEPROM write access is present

Wait_ee sbic EECR EEPE rjmp Wait_ee SPM timed sequence out SPMCSR spmcrval spm restore SREG (to enable interrupts if originally enabled) out SREG temp2 ret

32814 Boot Loader ParametersIn the following tables the parameters used in the description of the self programming are given

Table 32-6 Boot Size Configuration

BOOTSZ1 BOOTSZ0 BootSize

Pages ApplicationFlash Section

BootLoaderFlashSection

EndApplicationSection

Boot ResetAddress(Start BootLoaderSection)

1 1 256words

4 0x0000 -0x3EFF

0x3F00 -0x3FFF

0x3EFF 0x3F00

1 0 512words

8 0x0000 -0x3DFF

0x3E00 -0x3FFF

0x3DFF 0x3E00

0 1 1024words

16 0x0000 -0x3BFF

0x3C00 -0x3FFF

0x3BFF 0x3C00

0 0 2048words

32 0x0000 -0x37FF

0x3800 -0x3FFF

0x37FF 0x3800

Note The different BOOTSZ Fuse configurations are shown in Figure 32-2

Table 32-7 Read-While-Write Limit

Section Pages Address

Read-While-Write section (RWW) 224 0x0000 - 0x37FF

No Read-While-Write section (NRWW) 32 0x3800 - 0x3FFF

Note For details about these two sections see 3242 NRWW ndash No Read-While-Write Section and 3241 RWW ndash Read-While-Write Section

Table 32-8 Explanation of Different Variables used in Figure and the Mapping to the Z-pointer

Variable CorrespondingVariable (1)

Description

PCMSB 13 Most significant bit in the Program Counter (The ProgramCounter is 14 bits PC[130])

PAGEMSB 5 Most significant bit which is used to address the wordswithin one page (64 words in a page requires 6 bits PC[50])

ZPCMSB Z14 Bit in Z-register that is mapped to PCMSB Because Z0 isnot used the ZPCMSB equals PCMSB + 1

ZPAGEMSB Z6 Bit in Z-register that is mapped to PAGEMSB BecauseZ0 is not used the ZPAGEMSB equals PAGEMSB + 1

PCPAGE PC[136] Z[147] Program counter page address Page select for pageerase and page write

PCWORD PC[50] Z[61] Program counter word address Word select for fillingtemporary buffer (must be zero during page writeoperation)

Note 1 Z[15] always ignored Z0 should be zero for all SPM commands byte select for the LPM

instructionSee Addressing the Flash During Self-Programming for details about the use of Z-pointer duringSelf- Programming

3291 SPMCSR ndash Store Program Memory Control and Status Register

Name SPMCSROffset 0x57 [ID-000004d0]Reset 0x00Property When addressing as IO Register address offset is 0x37

The Store Program Memory Control and Status Register contains the control bits needed to control theBoot Loader operations

Bit 7 6 5 4 3 2 1 0 SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN

Bit 7 ndash SPMIE SPM Interrupt EnableWhen the SPMIE bit is written to one and the I-bit in the Status Register is set (one) the SPM readyinterrupt will be enabled The SPM ready Interrupt will be executed as long as the SPMEN bit in theSPMCSR Register is cleared

Bit 6 ndash RWWSB Read-While-Write Section BusyWhen a Self-Programming (Page Erase or Page Write) operation to the RWW section is initiated theRWWSB will be set (one) by hardware When the RWWSB bit is set the RWW section cannot beaccessed The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programmingoperation is completed Alternatively the RWWSB bit will automatically be cleared if a page loadoperation is initiated

Bit 5 ndash SIGRD Signature Row ReadIf this bit is written to one at the same time as SPMEN the next LPM instruction within three clock cycleswill read a byte from the signature row into the destination register Refer to Reading the Fuse and LockBits from Software in this chapter An SPM instruction within four cycles after SIGRD and SPMEN are setwill have no effect This operation is reserved for future use and should not be used

Bit 4 ndash RWWSRE Read-While-Write Section Read EnableWhen programming (Page Erase or Page Write) to the RWW section the RWW section is blocked forreading (the RWWSB will be set by hardware) To re-enable the RWW section the user software mustwait until the programming is completed (SPMEN will be cleared) Then if the RWWSRE bit is written toone at the same time as SPMEN the next SPM instruction within four clock cycles re-enables the RWWsection The RWW section cannot be re-enabled while the Flash is busy with a Page Erase or a PageWrite (SPMEN is set) If the RWWSRE bit is written while the Flash is being loaded the Flash loadoperation will abort and the data loaded will be lost

Bit 3 ndash BLBSET Boot Lock Bit SetIf this bit is written to one at the same time as SPMEN the next SPM instruction within four clock cyclessets Boot Lock bits and Memory Lock bits according to the data in R0 The data in R1 and the address inthe Z-pointer are ignored The BLBSET bit will automatically be cleared upon completion of the Lock bitset or if no SPM instruction is executed within four clock cycles

An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Register(SPMCSRBLBSET and SPMCSRSPMEN) will read either the Lock bits or the Fuse bits (depending onZ0 in the Z-pointer) into the destination register Refer to Reading the Fuse and Lock Bits from Softwarein this chapter

Bit 2 ndash PGWRT Page WriteIf this bit is written to one at the same time as SPMEN the next SPM instruction within four clock cyclesexecutes Page Write with the data stored in the temporary buffer The page address is taken from thehigh part of the Z-pointer The data in R1 and R0 are ignored The PGWRT bit will auto-clear uponcompletion of a Page Write or if no SPM instruction is executed within four clock cycles The CPU ishalted during the entire Page Write operation if the NRWW section is addressed

Bit 1 ndash PGERS Page EraseIf this bit is written to one at the same time as SPMEN the next SPM instruction within four clock cyclesexecutes Page Erase The page address is taken from the high part of the Z-pointer The data in R1 andR0 are ignored The PGERS bit will auto-clear upon completion of a Page Erase or if no SPM instructionis executed within four clock cycles The CPU is halted during the entire Page Write operation if theNRWW section is addressed

Bit 0 ndash SPMEN Store Program MemoryThis bit enables the SPM instruction for the next four clock cycles If written to one together with eitherRWWSRE BLBSET PGWRT or PGERS the following SPM instruction will have a special meaning (seethe description above) If only SPMEN is written the following SPM instruction will store the value inR1R0 in the temporary page buffer addressed by the Z-pointer The LSB of the Z-pointer is ignored TheSPMEN bit will auto-clear upon completion of an SPM instruction or if no SPM instruction is executedwithin four clock cycles During Page Erase and Page Write the SPMEN bit remains high until theoperation is completedWriting any other combination than ldquo0x10001rdquo ldquo0x01001rdquo ldquo0x00101rdquo ldquo0x00011rdquo or ldquo0x00001rdquo in the lowerfive bits will have no effect

33 MEMPROG - Memory Programming

331 Program And Data Memory Lock BitsThe device provides six Lock bits These can be left unprogrammed (1) or can be programmed (0) toobtain the additional features listed in the table Lock Bit Protection Modes below The Lock bits can onlybe erased to 1 with the Chip Erase command

Table 33-1 Lock Bit Byte(1)

Lock Bit Byte Bit No Description Default Value

7 ndash 1 (unprogrammed)

BLB12 5 Boot Lock bit 1 (unprogrammed)

LB2 1 Lock bit 1 (unprogrammed)

Note 1 1 means unprogrammed 0 means programmed

Table 33-2 Lock Bit Protection Modes(1)(2)

Memory Lock Bits Protection Type

LB Mode LB2 LB1

1 1 1 No memory lock features enabled

2 1 0 Further programming of the Flash and EEPROM is disabled in Parallel and SerialProgramming modes The Fuse bits are locked in both Serial and ParallelProgramming modes(1)

3 0 0 Further programming and verification of the Flash and EEPROM is disabled inParallel and Serial Programming modes The Boot Lock bits and Fuse bits arelocked in both Serial and Parallel Programming modes(1)

Note 1 Program the Fuse bits and Boot Lock bits before programming the LB1 and LB22 1 means unprogrammed 0 means programmed

ATmega328PB AutomotiveMEMPROG - Memory Programming

Table 33-3 Lock Bit Protection - BLB0 Mode(1)(2)

BLB0Mode

BLB02 BLB01

1 1 1 No restrictions for SPM or Load Program Memory (LPM) instructionaccessing the Application section

BLB1Mode

BLB12 BLB11

3 0 0 SPM is not allowed to write to the Boot Loader section and LPMexecuting from the Application section is not allowed to read from the BootLoader section If Interrupt Vectors are placed in the Application sectioninterrupts are disabled while executing from the Boot Loader section

332 Fuse BitsThe device has three Fuse bytes The following tables describe briefly the functionality of all the fusesand how they are mapped into the Fuse bytes Note that the fuses are read as logical zero ldquo0rdquo if they areprogrammed

Table 33-5 Extended Fuse Byte for ATmega328PB

Extended Fuse Byte Bit No Description Default Value

ndash 7 ndash 1

ndash 6 ndash 1

ndash 5 ndash 1

ndash 4 ndash 1

CFD 3 Disable Clock Failure Detection 0 (programmed CFD disable)

BODLEVEL2(1) 2 Brown-out Detector trigger level 1 (unprogrammed)

Note 1 Refer to Table BODLEVEL Fuse Coding in System and Reset Characteristics for BODLEVEL Fuse

decoding

Table 33-6 Fuse High Byte

High Fuse Byte Bit No Description Default Value

RSTDISBL(1) 7 External Reset Disable 1 (unprogrammed)

DWEN 6 debugWIRE Enable 1 (unprogrammed)

SPIEN(2) 5 Enable Serial Program and DataDownloading

0 (programmed SPI programmingenabled)

WDTON(3) 4 Watchdog Timer Always On 1 (unprogrammed)

EESAVE 3 EEPROM memory is preserved throughthe Chip Erase

1 (unprogrammed) EEPROM notpreserved

BOOTSZ1 2 Select Boot Size (see Boot Loader Parameters)

0 (programmed)(4)

BOOTRST 0 Select Reset Vector 1 (unprogrammed)

Note 1 Refer to Alternate Functions of Port C in IO-Ports chapter for description of RSTDISBL Fuse2 The SPIEN Fuse is not accessible in serial programming mode3 Refer to WDTCSR ndash Watchdog Timer Control Register for details4 The default value of BOOTSZ[10] results in maximum Boot Size See table Boot Size

Configuration in subsection Boot Loader Parameters in the previous chapter for details

Table 33-7 Fuse Low Byte

Low Fuse Byte Bit No Description Default Value

CKDIV8(4) 7 Divide clock by 8 0 (programmed)

CKOUT(3) 6 Clock output 1 (unprogrammed)

SUT1 5 Select start-up time 1 (unprogrammed)(1)

SUT0 4 Select start-up time 0 (programmed)(1)

CKSEL3 3 Select Clock source 0 (programmed)(2)

CKSEL1 1 Select Clock source 1 (unprogrammed)(2)

Note 1 The default value of SUT[10] results in maximum start-up time for the default clock source See

table Start-Up Times for the Internal Calibrated RC Oscillator Clock Selection - SUT in CalibratedInternal RC Oscillator of System Clock and Clock Options chapter for details

2 The default setting of CKSEL[30] results in internal RC Oscillator 8 MHz See table InternalCalibrated RC Oscillator Operating Modes in Calibrated Internal RC Oscillator of the System Clockand Clock Options chapter for details

3 The CKOUT Fuse allows the system clock to be output on PORTB0 Refer to Clock Output Buffersection in the System Clock and Clock Options chapter for details

4 Refer to System Clock Prescaler section in the System Clock and Clock Options chapter for details

The status of the Fuse bits is not affected by Chip Erase Note that the Fuse bits are locked if Lock bit1(LB1) is programmed Program the Fuse bits before programming the Lock bits

Related Links346 System and Reset Characteristics183 Alternate Port Functions1592 WDTCSR125 Calibrated Internal RC Oscillator128 Clock Output Buffer1210 System Clock Prescaler

3321 Latching of FusesThe fuse values are latched when the device enters programming mode and changes of the fuse valueswill have no effect until the part leaves Programming mode This does not apply to the EESAVE Fusewhich will take effect once it is programmed The fuses are also latched on Power-up in Normal mode

333 Signature BytesThe device have a three-byte signature code This code can be read in both serial and parallel modealso when the device is locked The three bytes reside in a separate address space For the device thesignature bytes are given in the following table

Table 33-8 Device ID

Part Signature Bytes Address

0x000 0x001 0x002

ATmega328PB 0x1E 0x95 0x16

334 Calibration ByteThe device has a byte calibration value for the Internal RC Oscillator This byte resides in the high byte ofaddress 0x000 in the signature address space During reset this byte is automatically written into theOSCCAL Register to ensure correct frequency of the calibrated RC Oscillator

335 Serial NumberThe product has a serial number which offers a unique ID to identify a specified part while it is in the fieldIt consists of several bytes which can be accessed from the signature address space

The Signature row includes factory-programmed databull ID for each device typebull Serial number for each devicebull Calibration bytes for factory calibrated peripherals

3351 Signature Row Summary - SIGROW

Offset Name Bit Pos

0x00 SIGROW_DEVICEID0 70 DEVICEID[70]

0x01 SIGROW_RCOC 70 RCOC[70]

0x03 Reserved

0x050x0D

Reserved

0x0E SIGROW_SERNUM0 70 SERNUM[70]

0x0F SIGROW_SERNUM1 70 SERNUM[70]

0x10 SIGROW_SERNUM2 70 SERNUM[70]

0x12 SIGROW_SERNUM 4 70 SERNUM[70]

Offset Name Bit Pos

33511 Device ID nName SIGROW_DEVICEIDn

Offset 0x00 + n0x02 [n=02]

Reset [Device ID]

Property -

Bit 7 6 5 4 3 2 1 0

Register DEVICEID[70]

Access R R R R R R R R

Reset 0 0 0 0 0 0 0 0

Bits 70 ndash DEVICEID[70] Byte n of the Device ID

33512 RC Oscillator Calibration ByteThis signature row location is loaded to OSCCAL-register during start-up

Name SIGROW_RCOC

Offset 0x01

Reset [RC oscillator calibration]

Property -

Bit 7 6 5 4 3 2 1 0

Register RCOC[70]

Reset x x x x x x x x

Bits 70 ndash RCOC[70] RC Oscillator Calibration Byte

33513 Serial Number Byte nEach device has an individual serial number representing a unique ID This can be used to identify aspecific device in the field The serial number consists of ten bytes SIGROWSERNUM[90]

Name SIGROW_SERNUMn

Offset 0x0E + n0x01 [n=09]

Reset [device serial number]

Property -

Bit 7 6 5 4 3 2 1 0

Register SERNUM[70]

Bits 70 ndash SERNUM[70] Serial Number

Each device has an individual serial number representing a unique ID This can be used to identify aspecific device in the field The serial number consists of ten bytes

336 Page SizeTable 33-9 No of Words in a Page and No of Pages in the Flash

Device Flash Size Page Size PCWORD No of Pages

PCPAGE PCMSB

ATmega328PB 16K words (32 KB)

64 words PC[50] 256 PC[136] 13

Table 33-10 No of Words in a Page and No of Pages in the EEPROM

Device EEPROMSize

Page Size

PCWORD No of Pages

PCPAGE EEAMSB

ATmega328PB 1 KB 4 bytes EEA[10] 256 EEA[92] 9

337 Parallel Programming Parameters Pin Mapping and CommandsThis section describes how to parallel program and verify Flash Program memory EEPROM Datamemory Memory Lock bits and Fuse bits in the device Pulses are assumed to be at least 250 ns unlessotherwise noted

3371 Signal NamesIn this section some pins of this device are referenced by signal names describing their functionalityduring parallel programming Refer to figure Parallel Programming and table Pin Name Mapping belowPins not described in the following table are referenced by pin names

The XA1XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse The bitcoding is shown in table XA1 and XA0 Coding below

When pulsing WR or OE the command loaded determines the action executed The different commandsare shown in table Command Byte Bit Coding below

Figure 33-1 Parallel Programming

PC[10]PB[50] DATA

RDYBSY

+45 - 55V

Note VCC - 03V lt AVCC lt VCC + 03V however AVCC should always be within 45 - 55V

Table 33-11 Pin Name Mapping

Signal Name inProgramming Mode

Pin Name IO Function

RDYBSY PD1 O 0 Device is busy programming 1 Device is ready fornew command

OE PD2 I Output Enable (Active low)

WR PD3 I Write Pulse (Active low)

BS1 PD4 I Byte Select 1 (ldquo0rdquo selects Low byte ldquo1rdquo selects Highbyte)

XA0 PD5 I XTAL Action Bit 0

PAGEL PD7 I Program memory and EEPROM Data Page Load

BS2 PC2 I Byte Select 2 (ldquo0rdquo selects Low byte ldquo1rdquo selects 2rsquondHigh byte)

DATA PC[10] PB[50] IO Bi-directional Data bus (Output when OE is low)

Table 33-12 Pin Values Used to Enter Programming Mode

Pin Symbol Value

PAGEL Prog_enable[3] 0

XA1 Prog_enable[2] 0

Pin Symbol Value

BS1 Prog_enable[0] 0

Table 33-13 XA1 and XA0 Coding

XA1 XA0 Action When XTAL1 is Pulsed

0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1)

0 1 Load Data (High or Low data byte for Flash determined by BS1)

1 0 Load Command

1 1 No Action Idle

Table 33-14 Command Byte Bit Coding

Command Byte Command Executed

1000 0000 Chip Erase

0100 0000 Write Fuse bits

0010 0000 Write Lock bits

0001 0000 Write Flash

0001 0001 Write EEPROM

0000 1000 Read Signature Bytes and Calibration byte

0000 0100 Read Fuse and Lock bits

0000 0010 Read Flash

0000 0011 Read EEPROM

338 Parallel Programming

3381 Entering Programming ModeFollow the steps below to put the device in Parallel (High-voltage) Programming mode

1 Set the Prog_enable pins listed in the table Pin Values Used to Enter Programming Mode above toldquo0x0000rdquo RESET pin to 0V and VCC to 0V

2 Apply 45ndash55V between VCC and GNDEnsure that VCC reaches at least 27V within the next 20 μs

3 Wait for 20ndash60 μs and apply 115ndash125V to RESET4 Keep the Prog_enable pins unchanged for at least 10 μs after the high voltage has been applied to

ensure the Prog_enable signature has been latched5 Wait at least 300 μs before giving any parallel programming commands6 Exit Programming mode by powering down the device or by bringing RESET pin to 0V

If the rise time of VCC is unable to fulfill the requirements listed above the following alternative methodcan be used to put the device in Parallel (High-voltage) Programming mode

1 Set the Prog_enable pins listed in the table Pin Values Used to Enter Programming Mode above toldquo0000rdquo RESET pin to 0V and VCC to 0V

2 Apply 45ndash55V between VCC and GND3 Monitor VCC and as soon as VCC reaches 09ndash11V apply 115ndash125V to RESET4 Keep the Prog_enable pins unchanged for at least 10 μs after the high voltage has been applied to

ensure the Prog_enable signature has been latched5 Wait until VCC reaches 45ndash55V before giving any parallel programming commands6 Exit Programming mode by powering down the device or by bringing RESET pin to 0V

3382 Considerations for Efficient ProgrammingThe loaded command and address are retained in the device during programming For efficientprogramming the following should be considered

bull The command needs only be loaded once when writing or reading multiple memory locationsbull Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the EESAVE

Fuse is programmed) and Flash after a Chip Erasebull Address high byte needs only be loaded before programming or reading a new 256-word window in

Flash or 256 byte EEPROM This consideration also applies to Signature bytes reading

3383 Chip EraseThe Chip Erase will erase the Flash the SRAM and the EEPROM memories plus Lock bits The Lock bitsare not reset until the program memory has been completely erased The Fuse bits are not changed AChip Erase must be performed before the Flash andor EEPROM are reprogrammed

Note The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed

Load Command ldquoChip Eraserdquo

1 Set XA1 XA0 to ldquo10rdquo This enables command loading2 Set BS1 to ldquo0rdquo3 Set DATA to ldquo1000 0000rdquo This is the command for Chip Erase4 Give XTAL1 a positive pulse This loads the command5 Give WR a negative pulse This starts the Chip Erase RDYBSY goes low6 Wait until RDYBSY goes high before loading a new command

3384 Programming the FlashThe Flash is organized in pages as a number of Words in a Page and number of Pages in the FlashWhen programming the Flash the program data is latched into a page buffer This allows one page ofprogram data to be programmed simultaneously The following procedure describes how to program theentire Flash memory

Step A Load Command ldquoWrite Flashrdquo1 Set XA1 XA0 to ldquo10rdquo This enables command loading2 Set BS1 to ldquo0rdquo3 Set DATA to ldquo0001 0000rdquo This is the command for Write Flash4 Give XTAL1 a positive pulse This loads the command

Step B Load Address Low Byte1 Set XA1 XA0 to ldquo00rdquo This enables address loading

2 Set BS1 to ldquo0rdquo This selects low address3 Set DATA = Address low byte (0x00 - 0xFF)4 Give XTAL1 a positive pulse This loads the address low byte

Step C Load Data Low Byte1 Set XA1 XA0 to ldquo01rdquo This enables data loading2 Set DATA = Data low byte (0x00 - 0xFF)3 Give XTAL1 a positive pulse This loads the data byte

Step D Load Data High Byte1 Set BS1 to ldquo1rdquo This selects high data byte2 Set XA1 XA0 to ldquo01rdquo This enables data loading3 Set DATA = Data high byte (0x00 - 0xFF)4 Give XTAL1 a positive pulse This loads the data byte

Step E Latch Data1 Set BS1 to ldquo1rdquo This selects high data byte2 Give PAGEL a positive pulse This latches the data bytes (Refer to figure Programming the Flash

Waveforms in this section for signal waveforms)

Step F Repeat B Through E Until the Entire Buffer is Filled or Until All Data Within the Page isLoadedWhile the lower bits in the address are mapped to words within the page the higher bits address thepages within the FLASH This is illustrated in the following figure Addressing the Flash Which isOrganized in Pages in this section Note that if less than eight bits are required to address words in thepage (page size lt 256) the most significant bit(s) in the address low byte are used to address the pagewhen performing a Page Write

Step G Load Address High Byte1 Set XA1 XA0 to ldquo00rdquo This enables address loading2 Set BS1 to ldquo1rdquo This selects high address3 Set DATA = Address high byte (0x00 - 0xFF)4 Give XTAL1 a positive pulse This loads the address high byte

Step H Program Page1 Give WR a negative pulse This starts programming of the entire page of data RDYBSY goes low2 Wait until RDYBSY goes high (Refer to the figure Programming the Flash Waveforms in this

section for signal waveforms)

Step I Repeat B Through H Until the Entire Flash is Programmed or Until All Data Has BeenProgrammed

Step J End Page Programming1 1 Set XA1 XA0 to ldquo10rdquo This enables command loading2 Set DATA to ldquo0000 0000rdquo This is the command for No Operation

3 Give XTAL1 a positive pulse This loads the command and the internal write signals are reset

Figure 33-2 Addressing the Flash Which is Organized in Pages

PROGRAM MEMORY

INSTRUCTION WORD

PAGEEND

PROGRAMCOUNTER

Note PCPAGE and PCWORD are listed in table No of Words in a Page and No of Pages in the Flashin Page Size section

Programming the Flash Waveforms

RDYBSY

RESET+12V

0x10 ADDR LOW ADDR HIGHDATA DATA LOW DATA HIGH ADDR LOW DATA LOW DATA HIGH

XX XX XX

A B C D E B C D E G H

Note ldquoXXrdquo is donrsquot care The letters refer to the programming description above

3385 Programming the EEPROMThe EEPROM is organized in pages refer to table No of Words in a Page and No of Pages in theEEPROM in the Page Size section When programming the EEPROM the program data is latched into apage buffer This allows one page of data to be programmed simultaneously The programming algorithm

for the EEPROM data memory is as follows (for details on Command Address and Data loading refer to 3384 Programming the Flash)

1 Step A Load Command ldquo0001 0001rdquo2 Step G Load Address High Byte (0x00 - 0xFF)3 Step B Load Address Low Byte (0x00 - 0xFF)4 Step C Load Data (0x00 - 0xFF)5 Step E Latch data (give PAGEL a positive pulse)6 Step K Repeat 3 through 5 until the entire buffer is filled7 Step L Program EEPROM page

71 Set BS1 to ldquo0rdquo72 Give WR a negative pulse This starts programming of the EEPROM page RDYBSY goes

low73 Wait until to RDYBSY goes high before programming the next page (refer to the following

figure for signal waveforms)

Figure 33-3 Programming the EEPROM Waveforms

RDYBSY

RESET+12V

0x11 ADDR HIGHDATA ADDR LOW DATA ADDR LOW DATA XX

A G B C E B C E L

3386 Reading the FlashThe algorithm for reading the Flash memory is as follows (refer to 3384 Programming the Flash in thischapter for details on Command and Address loading)

1 Step A Load Command ldquo0000 0010rdquo2 Step G Load Address High Byte (0x00 - 0xFF)3 Step B Load Address Low Byte (0x00 - 0xFF)4 Set OE to ldquo0rdquo and BS1 to ldquo0rdquo The Flash word low byte can now be read at DATA5 Set BS1 to ldquo1rdquo The Flash word high byte can now be read at DATA6 Set OE to ldquo1rdquo

3387 Reading the EEPROMThe algorithm for reading the EEPROM memory is as follows (refer to 3384 Programming the Flash fordetails on Command and Address loading)

1 Step A Load Command ldquo0000 0011rdquo2 Step G Load Address High Byte (0x00 - 0xFF)3 Step B Load Address Low Byte (0x00 - 0xFF)4 Set OE to ldquo0rdquo and BS1 to ldquo0rdquo The EEPROM Data byte can now be read at DATA5 Set OE to ldquo1rdquo

3388 Programming the Fuse Low BitsThe algorithm for programming the Fuse Low bits is as follows (refer to 3384 Programming the Flash fordetails on Command and Data loading)

1 Step A Load Command ldquo0100 0000rdquo2 Step C Load Data Low Byte Bit n = ldquo0rdquo programs and bit n = ldquo1rdquo erases the Fuse bit3 Give WR a negative pulse and wait for RDYBSY to go high

3389 Programming the Fuse High BitsThe algorithm for programming the Fuse High bits is as follows (refer to 3384 Programming the Flashfor details on Command and Data loading)

1 Step A Load Command ldquo0100 0000rdquo2 Step C Load Data Low Byte Bit n = ldquo0rdquo programs and bit n = ldquo1rdquo erases the Fuse bit3 Set BS1 to ldquo1rdquo and BS2 to ldquo0rdquo This selects high data byte4 Give WR a negative pulse and wait for RDYBSY to go high5 Set BS1 to ldquo0rdquo This selects low data byte

33810 Programming the Extended Fuse BitsThe algorithm for programming the Extended Fuse bits is as follows (refer to 3384 Programming theFlash for details on Command and Data loading)

1 Step A Load Command ldquo0100 0000rdquo2 Step C Load Data Low Byte Bit n = ldquo0rdquo programs and bit n = ldquo1rdquo erases the Fuse bit3 Set BS1 to ldquo0rdquo and BS2 to ldquo1rdquo This selects extended data byte4 Give WR a negative pulse and wait for RDYBSY to go high5 Set BS2 to ldquo0rdquo This selects low data byte

Figure 33-4 Programming the FUSES Waveforms

RDYBSY

RESET +12V

0x40DATA DATA XX

A C0x40 DATA XX

Write Fuse Low byte Write Fuse high byte

0x40 DATA XX

Write Extended Fuse byte

33811 Programming the Lock BitsThe algorithm for programming the Lock bits is as follows (refer to 3384 Programming the Flash fordetails on Command and Data loading)

1 Step A Load Command ldquo0010 0000rdquo2 Step C Load Data Low Byte Bit n = ldquo0rdquo programs the Lock bit If LB mode 3 is programmed (LB1

and LB2 is programmed) it is not possible to program the Boot Lock bits by any ExternalProgramming mode

3 Give WR a negative pulse and wait for RDYBSY to go high

The Lock bits can only be cleared by executing Chip Erase

33812 Reading the Fuse and Lock BitsThe algorithm for reading the Fuse and Lock bits is as follows (refer to 3384 Programming the Flash fordetails on Command loading)

1 Step A Load Command ldquo0000 0100rdquo2 Set OE to ldquo0rdquo BS2 to ldquo0rdquo and BS1 to ldquo0rdquo The status of the Fuse Low bits can now be read at DATA

(ldquo0rdquo means programmed)3 Set OE to ldquo0rdquo BS2 to ldquo1rdquo and BS1 to ldquo1rdquo The status of the Fuse High bits can now be read at DATA

(ldquo0rdquo means programmed)4 Set OE to ldquo0rdquo BS2 to ldquo1rdquo and BS1 to ldquo0rdquo The status of the Extended Fuse bits can now be read at

DATA (ldquo0rdquo means programmed)5 Set OE to ldquo0rdquo BS2 to ldquo0rdquo and BS1 to ldquo1rdquo The status of the Lock bits can now be read at DATA (ldquo0rdquo

means programmed)6 Set OE to ldquo1rdquo

Figure 33-5 Mapping Between BS1 BS2 and the Fuse and Lock Bits During Read

Lock Bits 0

Fuse High Byte

Fuse Low Byte 0

Extended Fuse Byte

33813 Reading the Signature BytesThe algorithm for reading the Signature bytes is as follows (refer to 3384 Programming the Flash fordetails on Command and Address loading)

1 Step A Load Command ldquo0000 1000rdquo2 Step B Load Address Low Byte (0x00 - 0x02)3 Set OE to ldquo0rdquo and BS1 to ldquo0rdquo The selected Signature byte can now be read at DATA4 Set OE to ldquo1rdquo

33814 Reading the Calibration ByteThe algorithm for reading the Calibration byte is as follows (refer to 3384 Programming the Flash fordetails on Command and Address loading)

1 Step A Load Command ldquo0000 1000rdquo2 Step B Load Address Low Byte 0x003 Set OE to ldquo0rdquo and BS1 to ldquo1rdquo The Calibration byte can now be read at DATA4 Set OE to ldquo1rdquo

33815 Parallel Programming CharacteristicsFor characteristics of the Parallel Programming refer to Parallel Programming Characteristics

339 Serial DownloadingBoth the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESETis pulled to GND The serial interface consists of pins SCK MOSI (input) and MISO (output) AfterRESET is set low the Programming Enable instruction needs to be executed first before the programerase operations can be executed

Figure 33-6 Serial Programming and Verify VCC = 27 - 55V

+27 - 55V

+27 - 55V (2)

Note 1 If the device is clocked by the internal Oscillator it is no need to connect a clock source to the

XTAL1 pin2 VCC - 03V lt AVCC lt VCC + 03V however AVCC should always be within the specified voltage

range (VCC) for the device

When programming the EEPROM an auto-erase cycle is built into the self-timed programming operation(in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction The ChipErase operation turns the content of every memory location in both the Program and EEPROM arraysinto 0xFF

Depending on CKSEL Fuses a valid clock must be present The minimum low and high periods for theserial clock (SCK) input are defined as follows

bull Low gt 2 CPU clock cycles for fck lt 12 MHz 3 CPU clock cycles for fck ge 12 MHzbull High gt 2 CPU clock cycles for fck lt 12 MHz 3 CPU clock cycles for fck ge 12 MHz

3391 Serial Programming Pin MappingTable 33-15 Pin Mapping Serial Programming

Symbol Pins IO Description

MOSI PB3 I Serial Data in

MISO PB4 O Serial Data out

SCK PB5 I Serial Clock

Note The pin mapping for SPI programming is listed Not all parts use the SPI pins dedicated for theinternal SPI interface

3392 Serial Programming AlgorithmWhen writing serial data to the device data is clocked on the rising edge of SCK

When reading data from the device data is clocked on the falling edge of SCK Refer to the figure SerialProgramming Waveforms in SPI Serial Programming Characteristics section for timing details

To program and verify the device in the serial programming mode the following sequence isrecommended (see Serial Programming Instruction set in Table 33-17)

1 Power-up sequenceApply power between VCC and GND while RESET and SCK are set to ldquo0rdquo In some systems theprogrammer cannot guarantee that SCK is held low during power-up In this case RESET must begiven a positive pulse of at least two CPU clock cycles duration after SCK has been set to ldquo0rdquo

2 Wait for at least 20 ms and enable serial programming by sending the Programming Enable serialinstruction to pin MOSI

3 The serial programming instructions will not work if the communication is out of synchronizationWhen in sync the second byte (0x53) will echo back when issuing the third byte of theProgramming Enable instruction Whether the echo is correct or not all four bytes of the instructionmust be transmitted If the 0x53 did not echo back give RESET a positive pulse and issue a newProgramming Enable command

4 The Flash is programmed one page at a time The memory page is loaded one byte at a time bysupplying the 6 LSB of the address and data together with the Load Program Memory Pageinstruction To ensure correct loading of the page the data low byte must be loaded before datahigh byte is applied for a given address The Program Memory Page is stored by loading the WriteProgram Memory Page instruction with the 7 MSB of the address If polling (RDYBSY) is not usedthe user must wait at least tWD_FLASH before issuing the next page Accessing the serialprogramming interface before the Flash write operation completes can result in incorrectprogramming

5 A The EEPROM array is programmed one byte at a time by supplying the address and datatogether with the appropriate Write instruction An EEPROM memory location is first automaticallyerased before new data is written If polling (RDYBSY) is not used the user must wait at leasttWD_EEPROM before issuing the next byte In a chip erased device no 0xFFs in the data file(s) needto be programmedB The EEPROM array is programmed one page at a time The Memory page is loaded one byte ata time by supplying the 6 LSB of the address and data together with the Load EEPROM MemoryPage instruction The EEPROM Memory Page is stored by loading the Write EEPROM MemoryPage Instruction with the 7 MSB of the address When using EEPROM page access only bytelocations loaded with the Load EEPROM Memory Page instruction is altered The remaininglocations remain unchanged If polling (RDYBSY) is not used the user must wait at leasttWD_EEPROM before issuing the next byte In a chip erased device no 0xFF in the data file(s) needto be programmed

6 Any memory location can be verified by using the Read instruction which returns the content at theselected address at serial output MISO

7 At the end of the programming session RESET can be set high to commence normal operation8 Power-off sequence (if needed)

Set RESET to ldquo1rdquo

Turn VCC power off

Table 33-16 Typical Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol Typical Wait Delay

tWD_FLASH 26 ms

tWD_EEPROM 36 ms

tWD_ERASE 105 ms

tWD_FUSE 26 ms

3393 Serial Programming Instruction Set

This section describes the Instruction Set

Table 33-17 Serial Programming Instruction Set (Hexadecimal Values)

InstructionOperation Instruction FormatByte 1 Byte 2 Byte 3 Byte 4

Programming Enable 0xAC 0x53 0x00 0x00Chip Erase (Program MemoryEEPROM) 0xAC 0x80 0x00 0x00Poll RDYBSY 0xF0 0x00 0x00 data byte outLoad InstructionsLoad Extended Address byte(1) 0x4D 0x00 Extended adr 0x00Load Program Memory Page High byte 0x48 0x00 adr LSB high data byte inLoad Program Memory Page Low byte 0x40 0x00 adr LSB low data byte inLoad EEPROM Memory Page (page access) 0xC1 0x00 0000 000aa(2) data byte inRead Instructions(5)

Read Program Memory High byte 0x28 adr MSB adr LSB high data byte outRead Program Memory Low byte 0x20 adr MSB adr LSB low data byte outRead EEPROM Memory 0xA0 0000 00aa(2) aaaa aaaa(2) data byte outRead Lock bits(3) 0x58 0x00 0x00 data byte outRead Signature Byte 0x30 0x00 0000 000aa(2) data byte outRead Fuse bits(3) 0x50 0x00 0x00 data byte outRead Fuse High bits(3) 0x58 0x08 0x00 data byte outRead Extended Fuse Bits(3) 0x50 0x08 0x00 data byte outRead Calibration Byte 0x38 0x00 0x00 data byte outWrite Instructions(5)

Write Program Memory Page(6) 0x4C adr MSB(8) adr LSB(8) 0x00Write EEPROM Memory 0xC0 0000 00aa(2) aaaa aaaa(2) data byte inWrite EEPROM Memory Page (page access) 0xC2 0000 00aa(2) aaaa aa00(2) 0x00Write Lock bits(3)(4) 0xAC 0xE0 0x00 data byte inWrite Fuse bits(3)(4) 0xAC 0xA0 0x00 data byte inWrite Fuse High bits(3)(4) 0xAC 0xA8 0x00 data byte inWrite Extended Fuse Bits(3)(4) 0xAC 0xA4 0x00 data byte in

1 Not all instructions are applicable for all parts2 a = address3 Bits are programmed lsquo0rsquo unprogrammed lsquo1rsquo4 To ensure future compatibility unused Fuses and Lock bits should be unprogrammed (lsquo1rsquo)5 Refer to the corresponding section for Fuse and Lock bits Calibration and Signature bytes and

Page size6 Instructions accessing program memory use a word address This address may be random within

the page range

Note See httpwwwmicrochipcomdesign-centers8-bitmicrochip-avr-mcus for Application Notesregarding programming and programmers

If the LSB in RDYBSY data byte out is lsquo1rsquo a programming operation is still pending Wait until this bitreturns lsquo0rsquo before the next instruction is carried out

Within the same page the low data byte must be loaded prior to the high data byte

After data is loaded into the page buffer program the EEPROM page Refer to the following figure

Within the same moisture group the user should not configure all the sensors to the single multi-touchgroup

Figure 33-7 Serial Programming Instruction Example

Byte 1 Byte 2 Byte 3 Byte 4

Adr MSB Adr LSBBit 15 B 0

Serial Programming Instruction

Program MemoryEEPROM Memory

Page N-1

Page Buffer

Write Program Memory PageWrite EEPROM Memory Page

Load Program Memory Page (HighLow Byte)Load EEPROM Memory Page (page access)

Bit 15 B 0

Adr MSB Adr LSB

Page Offset

Page Number

3394 SPI Serial Programming CharacteristicsFigure 33-8 Serial Programming Waveforms

SERIAL CLOCK INPUT(SCK)

SERIAL DATA INPUT(MOSI)

(MISO)

SAMPLE

SERIAL DATA OUTPUT

34 Electrical CharacteristicsApplicable over recommended operating range from TA = -40 - 105degC VCC = +27V to +55V Typicalnumbers are given at 25degC VCC=3V unless otherwise noted

341 Absolute Maximum RatingsTable 34-1 Absolute Maximum Ratings

Operating Temperature -40degC to +105degC

Storage Temperature -65degC to +150degC

Voltage on any Pin except RESETwith respect to Ground

-05V to VCC+05V

Voltage on RESET with respect to Ground -05V to +130V

Maximum Operating Voltage 60V

DC Current per IO Pin 400 mA

DC Current VCC and GND Pins 1000 mA

Note Stresses beyond those listed under ldquoAbsolute Maximum Ratingsrdquo may cause permanent damageto the device This is a stress rating only and functional operation of the device at these or otherconditions beyond those indicated in the operational sections of this specification is not implied Exposureto absolute maximum rating conditions for extended periods may affect device reliability

Note During parallel programming a 12V signal is connected to the Reset pin There is therefore nointernal protection diode from the Reset pin to VCC To achieve the same protection on the Reset pin ason other IO pins external protection should be added

342 DC CharacteristicsTable 34-2 Common DC Characteristics

Symbol Parameter Condition Min Typ Max Units

VIL Input Low Voltage except XTAL1and RESET pin

VCC = 27V - 55V -05 03VCC(1) V

VIH Input High Voltage exceptXTAL1 and RESET pins

VCC = 27V - 55V 06VCC(2) VCC + 05 V

VIL1 Input Low VoltageXTAL1 pin

VCC = 27V - 55V -05 01VCC(1) V

VIH1 Input High Voltage XTAL1 pin

VCC = 27V - 55V 07VCC(2) VCC + 05 V

VIL2 Input Low Voltage RESET pin

VCC = 27V - 55V -05 01VCC(1) V

ATmega328PB AutomotiveElectrical Characteristics

VIH2 Input High Voltage RESET pin

VCC = 27V - 55V 09VCC(2) VCC + 05 V

VIL3 Input Low Voltage RESET pin as IO

VCC = 27V - 55V -05 03VCC(1) V

VIH3 Input High Voltage RESET pin as IO

VCC = 27V - 55V 06VCC(2) VCC + 05 V

VOL Output Low Voltage(4)

except RESET pinIOL = 20 mA

VCC = 5V

TA=85degC 09

TA=105degC 10

IOL = 10 mA

VCC = 3V

TA=85degC 06

TA=105degC 07 V

VOH Output High Voltage(3)

except Reset pinIOH = 20 mA

VCC = 5V

TA=85degC 40

TA=105degC 39

IOH = 10 mA

VCC = 3V

TA=85degC 21

TA=105degC 20 V

IIL Input LeakageCurrent IO Pin

VCC = 55V pin low(absolute value)

IIH Input LeakageCurrent IO Pin

VCC = 55V pin high(absolute value)

RRST Reset Pull-up Resistor 30 60 kΩ

RPU IO Pin Pull-up Resistor 20 50 kΩ

VACIO Analog Comparator Input Offset Voltage

GND lt VIN lt VCC-01V lt10 45 mV

IACLK Analog Comparator Input Leakage Current

VCC=5V

Vin = VCC2

-100 100 nA

tACPD Analog Comparator Propagation Delay

400 ns

Note 1 ldquoMaxrdquo means the highest value where the pin is guaranteed to be read as low2 ldquoMinrdquo means the lowest value where the pin is guaranteed to be read as high3 Although each IO port can source more than the test conditions (20 mA at VCC = 5V 10 mA at VCC

= 3V) under steady state conditions (non-transient) the following must be observed31 The sum of all IOH for ports C0 - C5 D0- D4 ADC7 RESET should not exceed 100 mA

32 The sum of all IOH for ports B0 - B5 D5 - D7 ADC6 XTAL1 XTAL2 should not exceed100 mAIf IIOH exceeds the test condition VOH may exceed the related specification Pins are notguaranteed to source current greater than the listed test condition

4 Although each IO port can sink more than the test conditions (20 mA at VCC = 5V 10 mA at VCC =3V) under steady state conditions (non-transient) the following must be observed41 The sum of all IOL for ports C0 - C5 ADC7 ADC6 should not exceed 100 mA42 The sum of all IOL for ports B0 - B5 D5 - D7 XTAL1 XTAL2 should not exceed 100 mA43 The sum of all IOL for ports D0 - D4 RESET should not exceed 100 mA

If IOL exceeds the test condition VOL may exceed the related specification Pins are notguaranteed to sink current greater than the listed test condition

Related Links1411 Minimizing Power Consumption

343 Power ConsumptionTable 34-3 ATmega328PB Automotive DC Characteristics

Symbol Parameter Condition Min Typ(2) Max Units

ICC Power Supply Current(1) Active 4 MHz VCC = 3V T=105degC 14 25 mA

Active 8 MHz VCC = 5V T=105degC 52 80

Idle 4 MHz VCC = 3V T=105degC 04 07

Power-save mode(3) 32 kHz TOSC enabledVCC = 3V

T = 25degC 15 μA

T = 85degC 21

T = 105degC 28

Power-down mode(3) WDT enabled VCC = 3V T = 25degC 32 8

T = 85degC 38 8

T = 105degC 46 10

WDT disabled VCC = 3V T = 25degC 02 2

T = 85degC 07 2

T = 105degC 14 5

Note 1 Values when minimizing the power consumption (PRR0 and PRR1 all bits set)2 Typical values are at 25degC unless otherwise noted3 The current consumption values include input leakage current

344 Speed GradesMaximum frequency is dependent on VCC As shown in figure Maximum Frequency vs VCC theMaximum Frequency vs VCC curve is linear between 27V lt VCC lt 45V

Figure 34-1 Maximum Frequency vs VCC

27V 45V 55V

Safe Operating Area

345 Clock Characteristics

3451 Calibrated Internal RC Oscillator AccuracyTable 34-4 Calibration Accuracy of Internal RC Oscillator

Frequency VCC Temperature CalibrationAccuracy

FactoryCalibration

80 MHz 27V - 55V 0degC to +85degC plusmn4

80 MHz 27V - 55V -40degC to +105degC plusmn5

UserCalibration (1) Fixed voltage within

73 - 81 MHzFixed voltage within27V - 55V

Fixed temperature within-40degC to + 105degC

plusmn1

Note 1 Accuracy of oscillator frequency at calibration point fixed temperature and fixed voltage

3452 External Clock Drive WaveformsFigure 34-2 External Clock Drive Waveforms

3453 External Clock DriveTable 34-5 External Clock Drive

Symbol Parameter VCC= 27 - 55V VCC= 45 - 55V Units

Min Max Min Max

1tCLCL Oscillator Frequency 0 8 0 16 MHz

tCLCL Clock Period 125 - 625 - ns

tCHCX High Time 50 - 25 - ns

tCLCX Low Time 50 - 25 - ns

tCLCH Rise Time - 16 - 05 μs

tCHCL Fall Time - 16 - 05 μs

ΔtCLCL Change in period from one clock cycle to the next - 2 - 2

346 System and Reset CharacteristicsTable 34-6 Reset Brown-out and Internal Voltage Characteristics(1)

VPOT Power-on Reset Threshold Voltage (rising) 07 15 17 V

Power-on Reset Threshold Voltage (falling)(2) 06 10 17 V

SRON Power-on Slope Rate 001 - 9 Vms

VRST RESET Pin Threshold Voltage 02 VCC - 09 VCC V

tRST Minimum pulse width on RESET Pin - - 25 μs

VHYST Brown-out Detector Hysteresis - 50 - mV

tBOD Min Pulse Width on Brown-out Reset - 2 - μs

VBG Bandgap reference voltage VCC=27TA=25degC

10 11 12 V

tBG Bandgap reference start-up time VCC=27TA=25degC

- 40 70 μs

IBG Bandgap reference current consumption VCC=27TA=25degC

- 10 - μA

Note 1 Values are guidelines only2 The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)

Table 34-7 BODLEVEL Fuse Coding(1)(2)

BODLEVEL [20] Fuses Min VBOT Typ VBOT Max VBOT Units

111 BOD Disabled

101 25 27 29 V

100 41 43 45

Other Reserved

Note 1 VBOT may be below nominal minimum operating voltage for some devices For devices where this

is the case the device is tested down to VCC = VBOT during the production test This guaranteesthat a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of themicrocontroller is no longer guaranteed The test is performed using BODLEVEL = 101 and 100

2 VBOT tested at 25degC and 105degC in production

347 SPI Timing CharacteristicsTable 34-8 SPI Timing Parameters

Description Mode Min Typ Max Units

1 SCK period Master - See Table24-5

2 SCK highlow Master - 50 dutycycle

3 RiseFalltime

Master - 36 -

4 Setup Master - 10 -

5 Hold Master - 10 -

6 Out to SCK Master - 05 bull tsck -

7 SCK to out Master - 10 -

8 SCK to outhigh

Master - 10 -

9 SS low to out Slave - 15 -

10 SCK period Slave 4 bull tck - -

11 SCK highlow(1)

Slave 2 bull tck - -

12 RiseFalltime

Slave - - 1600

13 Setup Slave 10 - -

14 Hold Slave tck - -

15 SCK to out Slave - 15 -

16 SCK to SShigh

Slave 20 - -

17 SS high totri-state

Slave - 10 -

18 SS low toSCK

Note 1 In SPI Programming mode the minimum SCK highlow period is

bull 2 tCLCL for fCK lt 12 MHzbull 3 tCLCL for fCK gt 12 MHz

Figure 34-3 SPI Interface Timing Requirements (Master Mode)

MOSI(Data Output)

SCK(CPOL = 1)

MISO(Data Input)

SCK(CPOL = 0)

MSB LSB

LSBMSB

Figure 34-4 SPI Interface Timing Requirements (Slave Mode)

MISO(Data Output)

SCK(CPOL = 1)

MOSI(Data Input)

SCK(CPOL = 0)

MSB LSB

LSBMSB

1213 14

348 Two-Wire Serial Interface CharacteristicsTable in this section describes the requirements for devices connected to the two-wire Serial Bus Thetwo-wire Serial Interface meets or exceeds these requirements under the noted conditions

Timing symbols refer to Figure 34-5

Table 34-9 Two-Wire Serial Bus Requirements

Symbol Parameter Condition Min Max Units

VIL Input Low-voltage -05 03 VCC V

VIH Input High-voltage 07 VCC VCC + 05 V

Vhys(1) Hysteresis of Schmitt Trigger

Inputs005 VCC

(2) ndash V

VOL(1) Output Low-voltage 3mA sink current 0 04 V

tr(1) Rise Time for both SDA andSCL

20 + 01Cb(3)(2) 300 ns

tof(1) Output Fall Time from VIHmin to

VILmax

10 pF lt Cb lt 400 pF(3) 20 + 01Cb(3)(2) 250 ns

tSP(1) Spikes Suppressed by Input

Filter0 50(2) ns

Ii Input Current each IO Pin 01VCC lt Vi lt 09VCC -10 10 μA

Ci(1) Capacitance for each IO Pin ndash 10 pF

fSCL SCL Clock Frequency fCK(4) gt max(16fSCL 250

kHz)(5)0 400 kHz

Rp Value of Pull-up resistor fSCL le 100 kHz CCminus 04V3mA 1000ns

fSCL gt 100 kHz CCminus 04V3mA 300ns tHDSTA Hold Time (repeated) START

ConditionfSCL le 100 kHz 40 ndash μs

fSCL gt 100 kHz 06 ndash μs

tLOW Low Period of the SCL Clock fSCL le 100 kHz 47 ndash μs

tHIGH High period of the SCL clock fSCL le 100 kHz 40 ndash μs

tSUSTA Set-up time for a repeatedSTART condition

fSCL le 100 kHz 47 ndash μs

tHDDAT Data hold time fSCL le 100 kHz 0 345 μs

fSCL gt 100 kHz 0 09 μs

tSUDAT Data setup time fSCL le 100 kHz 250 ndash ns

fSCL gt 100 kHz 100 ndash ns

tSUSTO Setup time for STOP condition fSCL le 100 kHz 40 ndash μs

tBUF Bus free time between a STOPand START condition

Note 1 This parameter is characterized and not 100 tested2 Required only for fSCL gt 100 kHz3 Cb = capacitance of one bus line in pF4 fCK = CPU clock frequency5 This requirement applies to all two-wire Serial Interface operation Other devices connected to the

two-wire Serial Bus need only obey the general fSCL requirement

Figure 34-5 Two-Wire Serial Bus Timing

tSUSTA

tHDSTA tHDDAT tSUDATtSUSTO

349 ADC CharacteristicsTable 34-10 ADC Characteristics

Resolution - 10 - Bits

TUE Absolute accuracy (IncludingINL DNL quantization errorgain and offset error)

VREF = 4V VCC = 5V clkADC = 250 kHz

- 35 7 LSB

INL Integral Non-Linearity VREF = 4V VCC = 5VclkADC = 250 kHz

- 05 35 LSB

DNL(2) Differential Non-Linearity VREF = 4V VCC = 5VclkADC = 250 kHz

- 025 1 LSB

Gain Error VREF = 4V VCC = 5VclkADC = 250 kHz

-5 2 5 LSB

Offset Error VREF = 4V VCC = 5VclkADC = 250 kHz

-5 -25 0 LSB

Conversion Time Free Running Conversion 52 - 260 μs

Clock Frequency 50 - 250 kHz

AVCC(1) Analog Supply Voltage VCC - 03 - VCC + 03 V

VREF Reference Voltage 10 - AVCC V

VIN Input Voltage GND - VREF V

Input Bandwidth - 385 kHz

VINT Internal Voltage Reference 10 11 12 V

RREF Reference Input Resistance - 50 - kΩ

RAIN Analog Input Resistance - 100 - MΩ

Note 1 AVCC absolute minmax 27V55V2 These values are based on characterization and not covered by production test limits

3410 Parallel Programming CharacteristicsTable 34-11 Parallel Programming Characteristics VCC = 5V plusmn 10

Symbol Parameter Min Max Units

VPP Programming Enable Voltage 115 125 V

IPP Programming Enable Current - 250 μA

tDVXH Data and Control Valid before XTAL1 High 67 - ns

tXLXH XTAL1 Low to XTAL1 High 300 - ns

tXHXL XTAL1 Pulse Width High 150 - ns

tXLDX Data and Control Hold after XTAL1 Low 67 - ns

tXLWL XTAL1 Low to WR Low 0 - ns

tXLPH XTAL1 Low to PAGEL high 0 - ns

tPLXH PAGEL low to XTAL1 high 150 - ns

tBVPH BS1 Valid before PAGEL High 67 - ns

tPHPL PAGEL Pulse Width High 200 - ns

tPLBX BS1 Hold after PAGEL Low 67 - ns

tWLBX BS21 Hold after RDYBSY high 67 - ns

tPLWL PAGEL Low to WR Low 67 - ns

tBVWL BS1 Valid to WR Low 67 - ns

tWLWH WR Pulse Width Low 150 - ns

tWLRL WR Low to RDYBSY Low 0 1 μs

tWLRH WR Low to RDYBSY High(1) 2 45 ms

tWLRH_CE WR Low to RDYBSY High for Chip Erase(2) 75 12 ms

tXLOL XTAL1 Low to OE Low 0 - ns

tBVDV BS1 Valid to DATA valid 0 500 ns

tOLDV OE Low to DATA Valid - 500 ns

tOHDZ OE High to DATA Tri-stated - 500 ns

Note 1 tWLRH is valid for the Write Flash Write EEPROM Write Fuse bits and Write Lock bits commands2 tWLRH_CE is valid for the Chip Erase command

Figure 34-6 Parallel Programming Timing Including Some General Timing Requirements

Data amp Contol(DATA XA01 BS1 BS2)

XTAL1 tXHXL

tDVXH tXLDX

RDYBSY

PAGEL tPHPL

tPLBXtBVPH

tWLBXtBVWL

Figure 34-7 Parallel Programming Timing Loading Sequence With Timing Requirements

tPLXHXLXHt tXLPH

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)DATA

LOAD ADDRESS(LOW BYTE)

LOAD DATA (LOW BYTE)

LOAD DATA(HIGH BYTE)

LOAD DATA LOAD ADDRESS(LOW BYTE)

Note The timing requirements shown in 3410 Parallel Programming Characteristics (ie tDVXH tXHXLand tXLDX) also apply to loading operation

Figure 34-8 Parallel Programming Timing Reading Sequence (Within the Same Page) WithTiming Requirements

READ DATA (LOW BYTE)

READ DATA(HIGH BYTE)

Note The timing requirements shown in 3410 Parallel Programming Characteristics (ie tDVXH tXHXLand tXLDX) also apply to reading operation

35 Typical CharacteristicsApplicable over recommended operating range from TA = -40degC to +105degC VCC = +27V to +55V

The following charts show typical behavior These figures are not tested during manufacturing All currentconsumption measurements are performed with all IO pins configured as inputs and with internal pull-ups enabled A sine wave generator with rail-to-rail output is used as clock source

All Active- and Idle current consumption measurements are done with all bits in the PRR registers set andthus the corresponding IO modules are turned off Also the Analog Comparator is disabled during thesemeasurements The power consumption in Power-down mode is independent of clock selection

The current consumption is a function of several factors such as operating voltage operating frequencyloading of IO pins switching rate of IO pins code executed and ambient temperature The dominatingfactors are operating voltage and frequency

The current drawn from capacitive loaded pins may be estimated (for one pin) as CL times VCC times f where CL =load capacitance VCC = operating voltage and f = average switching frequency of IO pin

The parts are characterized at frequencies higher than test limits Parts are not guaranteed to functionproperly at frequencies higher than the ordering code indicates

The difference between current consumption in Power-down mode with Watchdog Timer enabled andPower-down mode with Watchdog Timer disabled represents the differential current drawn by theWatchdog Timer

351 Active Supply CurrentFigure 35-1 Active Supply Current vs Low Frequency (01-10MHz)

00 01 02 03 04 05 06 07 08 09 10Frequency [MHz]

Vcc [V]2733445555

ATmega328PB AutomotiveTypical Characteristics

Figure 35-2 Active Supply Current vs Frequency (1-16MHz)

0 2 4 6 8 10 12 14 16Frequency [MHz]

Vcc [V]2736445555

Figure 35-3 Active Supply Current vs VCC (Internal RC Oscillator 128kHz)

25 30 35 40 45 50 55Vcc [V]

Temperature[degC]-402585105

Figure 35-4 Active Supply Current vs VCC (Internal RC Oscillator 1MHz)

25 30 35 40 45 50 55Vcc [V]

352 Idle Supply CurrentFigure 35-6 Idle Supply Current vs Low Frequency (01-10MHz)

00 01 02 03 04 05 06 07 08 09 10Frequency [MHz]

Vcc [V]27445555

Figure 35-7 Idle Supply Current vs Frequency (1-16MHz)

0 2 4 6 8 10 12 14 16Frequency [MHz]

Vcc [V]2736445555

Figure 35-8 Idle Supply Current vs VCC (Internal RC Oscillator 128kHz)

25 30 35 40 45 50 55Vcc [V]

Figure 35-9 Idle Supply Current vs VCC (Internal RC Oscillator 1MHz)

25 30 35 40 45 50 55Vcc [V]

353 ATmega328PB Automotive Supply Current of IO ModulesThe tables and formulas below can be used to calculate the additional current consumption for thedifferent IO modules in Active and Idle mode The enabling or disabling of the IO modules are controlledby the Power Reduction Register

Table 35-1 ATmega328PB Automotive Additional Current Consumption for the different IOmodules (absolute values)

PRR bit Typical numbers Unit

VCC = 3V F = 4 MHz VCC = 5V F = 8 MHz

PRUSART1 287 1078 μA

PRUSART0 281 1109

PRTWI 442 1692

PRTIM2 386 140

PRTIM1 229 888

PRTIM0 116 452

PRSPI 383 1598

PRADC 443 16511

PRTIM4 282 955

PRTIM3 471 1641

PRSPI1 40 1579

PRPTC 278 1082

It is possible to calculate the typical current consumption based on the numbers from the above table forother VCC and frequency settings than listed there

Related Links1410 Power Reduction Registers

354 Power-down Supply CurrentFigure 35-11 Power-Down Supply Current vs VCC (Watchdog Timer Disabled)

25 30 35 40 45 50 55Vcc [V]

Figure 35-12 Power-Down Supply Current vs VCC (Watchdog Timer Enabled)

25 30 35 40 45 50 55Vcc [V]

Figure 35-13 Power-Down Supply Current vs VCC (AREF VCCDIV2)

25 30 35 40 45 50 55Vcc [V]

Temperature[degC]2585105

355 Pin Pull-UpFigure 35-14 IO Pin Pull-up Resistor Current vs Input Voltage (VCC = 27V)

00 03 06 09 12 15 18 21 24 27Vop [V]

Figure 35-15 IO Pin Pull-up Resistor Current vs Input Voltage (VCC = 5V)

00 05 10 15 20 25 30 35 40 45 50Vop [V]

Figure 35-16 Reset Pull-up Resistor Current vs Reset Pin Voltage(VCC = 27V)

00 03 06 09 12 15 18 21 24 27Vreset [V]

Figure 35-17 Reset Pull-up Resistor Current vs Reset Pin Voltage (VCC = 5V)

00 05 10 15 20 25 30 35 40 45 50Vreset [V]

356 Pin Driver StrengthFigure 35-18 IO Pin Output Voltage vs Source Current (VCC = 3V)

0 4 8 12 16 20IOH [mA]

Figure 35-19 IO Pin Output Voltage vs Source Current (VCC = 5V)

0 4 8 12 16 20IOH [mA]

Figure 35-20 IO Pin Output Voltage vs Sink Current (VCC = 3V)

0 4 8 12 16 20IOL [mA]

357 Pin Threshold and HysteresisFigure 35-22 IO Pin Input Threshold Voltage vs VCC (VIH IO Pin read as lsquo1rsquo)

25 30 35 40 45 50 55Vcc [V]

Figure 35-23 IO Pin Input Threshold Voltage vs VCC (VIL IO Pin read as lsquo0rsquo)

25 30 35 40 45 50 55Vcc [V]

Figure 35-24 IO Pin Input Hysteresis vs VCC

25 30 35 40 45 50 55Vcc [V]

Figure 35-25 Reset Input Threshold Voltage vs VCC (VIH IO Pin read as lsquo1rsquo)

25 30 35 40 45 50 55Vcc [V]

Figure 35-26 Reset Input Threshold Voltage vs VCC (VIL IO Pin read as lsquo0rsquo)

25 30 35 40 45 50 55Vcc [V]

Figure 35-27 Reset Pin Input Hysteresis vs VCC

25 30 35 40 45 50 55Vcc [V]

358 BOD ThresholdFigure 35-28 BOD Thresholds vs Temperature (BODLEVEL is 27V)

-40 -20 0 20 40 60 80 100 120Temperature [degC]

RiseFall01

Figure 35-29 BOD Thresholds vs Temperature (BODLEVEL is 43V)

RiseFall01

Figure 35-30 Calibrated Bandgap Voltage vs Vcc

25 30 35 40 45 50 55Vcc [V]

Figure 35-31 Bandgap Voltage vs Temperature

Vcc [V]273355

359 Analog Comparator OffsetFigure 35-32 AC Offset vs Common Voltage (VCC = 30V)

-05 00 05 10 15 20 25 30

CMV [V]

Temperature [degC]-402585105

Figure 35-33 AC Offset vs Common Voltage (VCC = 50V)

-05 00 05 10 15 20 25 30 35 40 45 50

CMV [V]

3510 Internal Oscillator SpeedFigure 35-34 Watchdog Oscillator Frequency vs Temperature

Vcc [V]2733555

Figure 35-35 Watchdog Oscillator Frequency vs VCC

25 30 35 40 45 50 55Vcc [V]

Figure 35-36 Calibrated 8MHz RC Oscillator Frequency vs VCC

25 30 35 40 45 50 55Vcc [V]

Figure 35-37 Calibrated 8MHz RC Oscillator Frequency vs Temperature

Vcc [V]273345555

Figure 35-38 8MHz RC Oscillator Frequency vs OSCCAL Value

0 32 64 96 128 160 192 224 256OSCCAL [x1]

Figure 35-39 OSCCAL Value StepSize in Base Frequency = 80MHz

0 32 64 96 128 160 192 224 256OSCCAL [x1]

3511 Current Consumption of Peripheral UnitsFigure 35-40 Active Supply Current vs VCC (With ADC conversion 50kHz)

25 30 35 40 45 50 55Vcc [V]

Figure 35-41 Active Supply Current vs VCC (With ADC No conversion)

25 30 35 40 45 50 55Vcc [V]

Figure 35-42 ADC Current vs Vcc (AREF = AVcc)

25 30 35 40 45 50 55Vcc [V]

Figure 35-43 Analog Comparator Current vs Vcc

25 30 35 40 45 50 55

Vcc [V]

Figure 35-44 Brownout Detector Current vs Vcc

25 30 35 40 45 50 55Vcc [V]

Figure 35-45 Programming Current vs Vcc

0005101520253035404550556065707580

25 30 35 40 45 50 55Vcc [V]

3512 Current Consumption in Reset and Reset Pulse WidthFigure 35-46 Reset Supply Current vs Low Frequency (01MHz - 10MHz)

00 01 02 03 04 05 06 07 08 09 10Frequency [MHz]

Vcc [V]33445555

Figure 35-47 Reset Supply Current vs Frequency (1MHz - 16MHz)

0 2 4 6 8 10 12 14 16Frequency [MHz]

Vcc [V]2736445555

Figure 35-48 Reset Supply Current vs VCC (Excluding current through Reset Pullup)

25 30 35 40 45 50 55Vcc [V]

Figure 35-49 Minimum Reset Pulse Width vs VCC

25 30 35 40 45 50 55Vcc [V]

36 Register Summary

Offset Name Bit Pos

0x23 PINB 70 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0

0x24 DDRB 70 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

0x25 PORTB 70 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0

0x26 PINC 70 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0

0x27 DDRC 70 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

0x28 PORTC 70 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0

0x29 PIND 70 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0

0x2A DDRD 70 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

0x2B PORTD 70 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0

0x2C PINE 70 PINE3 PINE2 PINE1 PINE0

0x2D DDRE 70 DDRE3 DDRE2 DDRE1 DDRE0

0x2E PORTE 70 PORTE3 PORTE2 PORTE1 PORTE0

Reserved

0x35 TIFR0 70 OCF0B OCF0A TOV0

0x36 TIFR1 70 ICF1 OCF1B OCF1A TOV1

0x3A Reserved

0x3B PCIFR 70 PCIF3 PCIF2 PCIF1 PCIF0

0x3C EIFR 70 INTF1 INTF0

0x3D EIMSK 70 INT1 INT0

0x3E GPIOR0 70 GPIOR0[70]

0x3F EECR 70 EEPM[10] EERIE EEMPE EEPE EERE

0x40 EEDR 70 EEDR[70]

0x41 EEARL and EEARH70 EEAR[70]

158 EEAR[98]

0x43 GTCCR 70 TSM PSRASY PSRSYNC

0x44 TCCR0A 70 COM0A[10] COM0B [10] WGM0[10]

0x45 TCCR0B 70 FOC0A FOC0B WGM0 [2] CS0[20]

0x46 TCNT0 70 TCNT0[70]

0x47 OCR0A 70 OCR0A[70]

0x48 OCR0B 70 OCR0B[70]

0x49 Reserved

0x4A GPIOR1 70 GPIOR1[70]

0x4B GPIOR2 70 GPIOR2[70]

0x4C SPCR0 70 SPIE0 SPE0 DORD0 MSTR0 CPOL0 CPHA0 SPR0 [10]

0x4D SPSR0 70 SPIF0 WCOL0 SPI2X0

0x4E SPDR0 70 SPID[70]

0x4F Reserved

0x50 ACSR 70 ACD ACBG ACO ACI ACIE ACIC ACIS [10]

ATmega328PB AutomotiveRegister Summary

Offset Name Bit Pos

0x51 DWDR 70 DWDR[70]

0x52 Reserved

0x53 SMCR 70 SM[20] SE

0x54 MCUSR 70 WDRF BORF EXTRF PORF

0x55 MCUCR 70 BODS BODSE PUD IVSEL IVCE

0x56 Reserved

0x57 SPMCSR 70 SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN

Reserved

0x5D SPL and SPH70 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

158 SP11 SP10 SP9 SP8

0x5F SREG 70 I T H S V N Z C

0x60 WDTCSR 70 WDIF WDIE WDP[3] WDCE WDE WDP[20]

0x61 CLKPR 70 CLKPCE CLKPS [30]

0x62 XFDCSR 70 XFDIF XFDIE

0x63 Reserved

0x64 PRR0 70 PRTWI0 PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI0 PRUSART0 PRADC

0x65 Reserved

0x66 OSCCAL 70 CAL [70]

0x67 Reserved

0x68 PCICR 70 PCIE3 PCIE2 PCIE1 PCIE0

0x69 EICRA 70 ISC1 [10] ISC0 [10]

0x6A Reserved

0x6B PCMSK0 70 PCINT[70]

0x6C PCMSK1 70 PCINT[148]

0x6D PCMSK2 70 PCINT[2316]

0x6E TIMSK0 70 OCIE0B OCIE0A TOIE0

0x6F TIMSK1 70 ICIE1 OCIE1B OCIE1A TOIE1

0x70 TIMSK2 70 OCIE2B OCIE2A TOIE2

0x71 TIMSK3 70 ICIE3 OCIE3B OCIE3A TOIE3

0x73 PCMSK3 70 PCINT[2724]

Reserved

0x78 ADCL and ADCH70 ADC[70]

158 ADC[98]

158 ADC[92]

0x7A ADCSRA 70 ADEN ADSC ADATE ADIF ADIE ADPS [20]

0x7B ADCSRB 70 ACME ADTS [20]

0x7C ADMUX 70 REFS [10] ADLAR MUX [30]

0x7D Reserved

0x7E DIDR0 70 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D

0x7F DIDR1 70 AIN1D AIN0D

Offset Name Bit Pos

0x80 TCCR1A 70 COM1A[10] COM1B[10] WGM1[10]

0x81 TCCR1B 70 ICNC1 ICES1 WGM1[3] WGM1[2] CS1[20]

0x82 TCCR1C 70 FOC1A FOC1B

0x83 Reserved

0x84TCNT1L and

TCNT1H

70 TCNT1[70]

158 TCNT1[158]

0x86 ICR1L and ICR1H70 ICR1[70]

158 ICR1[158]

0x88OCR1AL and

OCR1AH

70 OCR1A[70]

158 OCR1A[158]

0x8AOCR1BL and

OCR1BH

70 OCR1B[70]

158 OCR1B[158]

Reserved

0x93 Reserved

0x94TCNT3L and

TCNT3H

70 TCNT3[70]

158 TCNT3[158]

158 ICR3[158]

0x98OCR3AL and

OCR3AH

70 OCR3A[70]

158 OCR3A[158]

0x9AOCR3BL and

OCR3BH

70 OCR3B[70]

158 OCR3B[158]

Reserved

0xA0 TCCR4A 70 COM4A[10] COM4B[10] WGM4[10]

0xA1 TCCR4B 70 ICNC4 ICES4 WGM4[3] WGM4[2] CS4[20]

0xA2 TCCR4C 70 FOC4A FOC4B

0xA3 Reserved

0xA4TCNT4L and

TCNT4H

70 TCNT4[70]

158 TCNT4[158]

0xA6 ICR4L and ICR4H70 ICR4[70]

158 ICR4[158]

0xA8OCR4AL and

OCR4AH

70 OCR4A[70]

158 OCR4A[158]

0xAAOCR4BL and

OCR4BH

70 OCR4B[70]

158 OCR4B[158]

0xAC SPCR1 70 SPIE1 SPE1 DORD1 MSTR1 CPOL1 CPHA1 SPR1 [10]

0xAD SPSR1 70 SPIF1 WCOL1 SPI2X1

0xAE SPDR1 70 SPID1[70]

0xAF Reserved

Offset Name Bit Pos

0xB0 TCCR2A 70 COM2A [10] COM2B [10] WGM2 [10]

0xB1 TCCR2B 70 FOC2A FOC2B WGM2 [2] CS2[20]

0xB2 TCNT2 70 TCNT2[70]

0xB3 OCR2A 70 OCR2A[70]

0xB4 OCR2B 70 OCR2B[70]

0xB5 Reserved

0xB6 ASSR 70 EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB

0xB7 Reserved

0xB8 TWBR0 70 TWBR [70]

0xB9 TWSR0 70 TWS7 TWS6 TWS5 TWS4 TWS3 TWPS[10]

0xBA TWAR0 70 TWA[60] TWGCE

0xBB TWDR0 70 TWD[70]

0xBC TWCR0 70 TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE

0xBD TWAMR0 70 TWAM[60]

Reserved

0xC0 UCSR0A 70 RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn

0xC1 UCSR0B 70 RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n

0xC2 UCSR0C 70 UMSELn[10] UPMn[10] USBSnUCSZn1

UDORDn

UCSZn0

UCPHAnUCPOLn

0xC3 Reserved

0xC4UBRR0L and

UBRR0H

70 UBRRL[70]

158 UBRRL[118]

0xC6 UDR0 70 TXB RXB[70]

0xCA UCSR1C 70 UMSELn[10] UPMn[10] USBSnUCSZn1

UDORDn

UCSZn0

UCPHAnUCPOLn

0xCB Reserved

0xCCUBRR1L and

UBRR1H

70 UBRRL[70]

158 UBRRL[118]

Reserved

0xD8 TWBR1 70 TWBR [70]

0xD9 TWSR1 70 TWS7 TWS6 TWS5 TWS4 TWS3 TWPS[10]

0xDA TWAR1 70 TWA[60] TWGCE

0xDB TWDR1 70 TWD[70]

0xDC TWCR1 70 TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE

0xDD TWAMR1 70 TWAM[60]

37 Instruction Set SummaryARITHMETIC AND LOGIC INSTRUCTIONS

Mnemonics Operands Description Operation Flags Clocks

ADD Rd Rr Add two Registers without Carry Rd larr Rd + Rr ZCNVH 1

ADC Rd Rr Add two Registers with Carry Rd larr Rd + Rr + C ZCNVH 1

ADIW RdlK Add Immediate to Word RdhRdl larr RdhRdl + K ZCNVS 2

SUB Rd Rr Subtract two Registers Rd larr Rd - Rr ZCNVH 1

SUBI Rd K Subtract Constant from Register Rd larr Rd - K ZCNVH 1

SBC Rd Rr Subtract two Registers with Carry Rd larr Rd - Rr - C ZCNVH 1

SBCI Rd K Subtract Constant from Reg with Carry Rd larr Rd - K - C ZCNVH 1

SBIW RdlK Subtract Immediate from Word RdhRdl larr RdhRdl - K ZCNVS 2

AND Rd Rr Logical AND Registers Rd larr Rd middot Rr ZNV 1

ANDI Rd K Logical AND Register and Constant Rd larr Rd middot K ZNV 1

OR Rd Rr Logical OR Registers Rd larr Rd v Rr ZNV 1

ORI Rd K Logical OR Register and Constant Rd larr Rd v K ZNV 1

EOR Rd Rr Exclusive OR Registers Rd larr Rd oplus Rr ZNV 1

COM Rd Onersquos Complement Rd larr 0xFF - Rd ZCNV 1

NEG Rd Tworsquos Complement Rd larr 0x00 - Rd ZCNVH 1

SBR RdK Set Bit(s) in Register Rd larr Rd v K ZNV 1

CBR RdK Clear Bit(s) in Register Rd larr Rd middot (0xFF - K) ZNV 1

INC Rd Increment Rd larr Rd + 1 ZNV 1

DEC Rd Decrement Rd larr Rd - 1 ZNV 1

TST Rd Test for Zero or Minus Rd larr Rd middot Rd ZNV 1

CLR Rd Clear Register Rd larr Rd oplus Rd ZNV 1

SER Rd Set Register Rd larr 0xFF None 1

MUL Rd Rr Multiply Unsigned R1R0 larr Rd x Rr ZC 2

MULS Rd Rr Multiply Signed R1R0 larr Rd x Rr ZC 2

MULSU Rd Rr Multiply Signed with Unsigned R1R0 larr Rd x Rr ZC 2

FMUL Rd Rr Fractional Multiply Unsigned R1R0 larr (Rd x Rr) ltlt 1 ZC 2

FMULS Rd Rr Fractional Multiply Signed R1R0 larr (Rd x Rr) ltlt 1 ZC 2

FMULSU Rd Rr Fractional Multiply Signed with Unsigned R1R0 larr (Rd x Rr) ltlt 1 ZC 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC larr PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC larr Z None 2

JMP(1) k Direct Jump PC larr k None 3

ATmega328PB AutomotiveInstruction Set Summary

BRANCH INSTRUCTIONS

RCALL k Relative Subroutine Call PC larr PC + k + 1 None 3

ICALL Indirect Call to (Z) PC larr Z None 3

CALL(1) k Direct Subroutine Call PC larr k None 4

RET Subroutine Return PC larr STACK None 4

RETI Interrupt Return PC larr STACK I 4

CPSE RdRr Compare Skip if Equal if (Rd = Rr) PC larr PC + 2 or 3 None 123

CP RdRr Compare Rd - Rr Z NVCH 1

CPC RdRr Compare with Carry Rd - Rr - C Z NVCH 1

CPI RdK Compare Register with Immediate Rd - K Z NVCH 1

SBRC Rr b Skip if Bit in Register Cleared if (Rr(b)=0) PC larr PC + 2 or 3 None 123

SBRS Rr b Skip if Bit in Register is Set if (Rr(b)=1) PC larr PC + 2 or 3 None 123

SBIC A b Skip if Bit in IO Register Cleared if (IO(Ab)=1) PC larr PC + 2 or 3 None 123

SBIS A b Skip if Bit in IO Register is Set if (IO(Ab)=1) PC larr PC + 2 or 3 None 123

BRBS s k Branch if Status Flag Set if (SREG(s) = 1) then PClarrPC+k + 1 None 12

BRBC s k Branch if Status Flag Cleared if (SREG(s) = 0) then PClarrPC+k + 1 None 12

BREQ k Branch if Equal if (Z = 1) then PC larr PC + k + 1 None 12

BRNE k Branch if Not Equal if (Z = 0) then PC larr PC + k + 1 None 12

BRCS k Branch if Carry Set if (C = 1) then PC larr PC + k + 1 None 12

BRCC k Branch if Carry Cleared if (C = 0) then PC larr PC + k + 1 None 12

BRSH k Branch if Same or Higher if (C = 0) then PC larr PC + k + 1 None 12

BRLO k Branch if Lower if (C = 1) then PC larr PC + k + 1 None 12

BRMI k Branch if Minus if (N = 1) then PC larr PC + k + 1 None 12

BRPL k Branch if Plus if (N = 0) then PC larr PC + k + 1 None 12

BRGE k Branch if Greater or Equal Signed if (N oplus V= 0) then PC larr PC + k + 1 None 12

BRLT k Branch if Less Than Zero Signed if (N oplus V= 1) then PC larr PC + k + 1 None 12

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC larr PC + k + 1 None 12

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC larr PC + k + 1 None 12

BRTS k Branch if T Flag Set if (T = 1) then PC larr PC + k + 1 None 12

BRTC k Branch if T Flag Cleared if (T = 0) then PC larr PC + k + 1 None 12

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC larr PC + k + 1 None 12

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC larr PC + k + 1 None 12

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC larr PC + k + 1 None 12

BRID k Branch if Interrupt Disabled if ( I = 0) then PC larr PC + k + 1 None 12

BIT AND BIT-TEST INSTRUCTIONS

SBI Pb Set Bit in IO Register IO(Pb) larr 1 None 2

CBI Pb Clear Bit in IO Register IO(Pb) larr 0 None 2

LSL Rd Logical Shift Left Rd(n+1) larr Rd(n) Rd(0) larr 0 ZCNV 1

LSR Rd Logical Shift Right Rd(n) larr Rd(n+1) Rd(7) larr 0 ZCNV 1

ROL Rd Rotate Left Through Carry Rd(0)larrCRd(n+1)larr Rd(n)CnotRd(7) ZCNV 1

ROR Rd Rotate Right Through Carry Rd(7)larrCRd(n)larr Rd(n+1)ClarrRd(0) ZCNV 1

ASR Rd Arithmetic Shift Right Rd(n) larr Rd(n+1) n=06 ZCNV 1

SWAP Rd Swap Nibbles Rd(30)larrRd(74)Rd(74)notRd(30) None 1

BSET s Flag Set SREG(s) larr 1 SREG(s) 1

BCLR s Flag Clear SREG(s) larr 0 SREG(s) 1

BST Rr b Bit Store from Register to T T larr Rr(b) T 1

BLD Rd b Bit load from T to Register Rd(b) larr T None 1

SEC Set Carry C larr 1 C 1

CLC Clear Carry C larr 0 C 1

SEN Set Negative Flag N larr 1 N 1

CLN Clear Negative Flag N larr 0 N 1

SEZ Set Zero Flag Z larr 1 Z 1

CLZ Clear Zero Flag Z larr 0 Z 1

SEI Global Interrupt Enable I larr 1 I 1

CLI Global Interrupt Disable I larr 0 I 1

SES Set Signed Test Flag S larr 1 S 1

CLS Clear Signed Test Flag S larr 0 S 1

SEV Set Tworsquos Complement Overflow V larr 1 V 1

CLV Clear Tworsquos Complement Overflow V larr 0 V 1

SET Set T in SREG T larr 1 T 1

CLT Clear T in SREG T larr 0 T 1

SEH Set Half Carry Flag in SREG H larr 1 H 1

CLH Clear Half Carry Flag in SREG H larr 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd Rr Move Between Registers Rd larr Rr None 1

MOVW Rd Rr Copy Register Word Rd+1Rd larr Rr+1Rr None 1

LDI Rd K Load Immediate Rd larr K None 1

LD Rd X Load Indirect Rd larr (X) None 2

LD Rd X+ Load Indirect and Post-Increment Rd larr (X) X larr X + 1 None 2

LD Rd - X Load Indirect and Pre-Decrement X larr X - 1 Rd larr (X) None 2

LD Rd Y Load Indirect Rd larr (Y) None 2

LD Rd Y+ Load Indirect and Post-Increment Rd larr (Y) Y larr Y + 1 None 2

LD Rd - Y Load Indirect and Pre-Decrement Y larr Y - 1 Rd larr (Y) None 2

LDD RdY+q Load Indirect with Displacement Rd larr (Y + q) None 2

LD Rd Z Load Indirect Rd larr (Z) None 2

LD Rd Z+ Load Indirect and Post-Increment Rd larr (Z) Z larr Z+1 None 2

LD Rd -Z Load Indirect and Pre-Decrement Z larr Z - 1 Rd larr (Z) None 2

LDD Rd Z+q Load Indirect with Displacement Rd larr (Z + q) None 2

LDS Rd k Load Direct from SRAM Rd larr (k) None 2

ST X Rr Store Indirect (X) larr Rr None 2

ST X+ Rr Store Indirect and Post-Increment (X) larr Rr X larr X + 1 None 2

ST - X Rr Store Indirect and Pre-Decrement X larr X - 1 (X) larr Rr None 2

ST Y Rr Store Indirect (Y) larr Rr None 2

ST Y+ Rr Store Indirect and Post-Increment (Y) larr Rr Y larr Y + 1 None 2

ST - Y Rr Store Indirect and Pre-Decrement Y larr Y - 1 (Y) larr Rr None 2

STD Y+qRr Store Indirect with Displacement (Y + q) larr Rr None 2

ST Z Rr Store Indirect (Z) larr Rr None 2

ST Z+ Rr Store Indirect and Post-Increment (Z) larr Rr Z larr Z + 1 None 2

ST -Z Rr Store Indirect and Pre-Decrement Z larr Z - 1 (Z) larr Rr None 2

STD Z+qRr Store Indirect with Displacement (Z + q) larr Rr None 2

STS k Rr Store Direct to SRAM (k) larr Rr None 2

LPM Load Program Memory R0 larr (Z) None 3

LPM Rd Z Load Program Memory Rd larr (Z) None 3

LPM Rd Z+ Load Program Memory and Post-Inc Rd larr (Z) Z larr Z+1 None 3

SPM Store Program Memory (Z) larr R1R0 None -

IN Rd A In from IO Location Rd larr IO (A) None 1

OUT A Rr Out to IO Location IO (A) larr Rr None 1

PUSH Rr Push Register on Stack STACK larr Rr None 2

POP Rd Pop Register from Stack Rd larr STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation No Operation None 1

SLEEP Sleep (see specific descr for Sleep function) None 1

WDR Watchdog Reset (see specific descr for WDRtimer) None 1

BREAK Break For On-chip Debug Only None NA

38 Packaging Information

381 32-Pin TQFP

ATmega328PB AutomotivePackaging Information

382 32-Pin VQFN

Package Drawing Contactpackagedrawingsatmelcom

GPC DRAWING NO REV TITLE

21ZBS A

062416

32 Leads - 050mm Pitch 5x5x09mm Body sizeVery Thin Quad Flat Lead Package (VQFN) Sawn -Wettable Flanks

1Notes

This drawing is for general information only Refer to JEDEC Drawing MO-220 Variation VHHD-5 for proper dimensions tolerances datums etc(excepted D2E2 Nom and Max)Dimensions b applies to metallized terminal and is measured between 015mm and 030mm from the terminal tipIf the terminal has the optical radius on the other end of the terminal the dimensions should not be measured in that radius area

Seating PlaneC

Exposed DieAttach Pad

Top View

Bottom View

Side View

PIN 1 Corner

COMMON DIMENSIONS(Unit of Measure = mm)MIN NOM NOTEMAXSymbol

A 080 085 090A1 000 0035A2 065A3 0203 REFDE 500 BSC

D2E2 35 36L 035 040

R 010 0125 015

b 020 025e 05 BSC

0100aaa0100bbb008ccc

0100ddd0100eee

Tolerances of Form and Position

030 2S 004

ccc Cbbb C

eee C A B

PIN 1 ID

ddd M C A B

nX bnX L

Drawings not scaled

aaa C B

39 Errata

391 Rev A1 Reduced ADC accuracy for Vdd from 27V to 41V

Description bull DNL less than -1 (missing codes) can be observed for ADC codes 256512 and 768

bull Increased gain error

FixWorkaround Use Vdd below 27V or above 41V if accurate ADC is needed

392 Rev C - D1 If the Peripheral Touch Controller (PTC) is enabled in sleep mode the PTC might stop working

Description If the Peripheral Touch Controller (PTC) is enabled in sleep mode the PTCmight stop working

FixWorkaround Disable the PTC before entering sleep mode

2 Reduced ADC accuracy for Vdd from 27V to 41V

393 Rev A - D1 Reduced ADC accuracy for Vdd from 27V to 41V

FixWorkaround Use Vdd outside the range 27V to 41V if accurate ADC is needed

ATmega328PB AutomotiveErrata

40 Revision HistoryDoc Rev Date Comments

A 122017 Initial document release

B 72018 Updated Absolute Max Ratings table remove Preliminary for the data sheet otherminor corrections

ATmega328PB AutomotiveRevision History

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Customers should contact their distributor representative or Field Application Engineer (FAE) for supportLocal sales offices are also available to help customers A listing of sales offices and locations is includedin the back of this document

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Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheetbull Microchip believes that its family of products is one of the most secure families of its kind on the

market today when used in the intended manner and under normal conditionsbull There are dishonest and possibly illegal methods used to breach the code protection feature All of

these methods to our knowledge require using the Microchip products in a manner outside theoperating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so isengaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of theircode Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving thecode protection features of our products Attempts to break Microchiprsquos code protection feature may be aviolation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your softwareor other copyrighted work you may have a right to sue for relief under that Act

Legal Notice

Information contained in this publication regarding device applications and the like is provided only foryour convenience and may be superseded by updates It is your responsibility to ensure that yourapplication meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORYOR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITSCONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSEMicrochip disclaims all liability arising from this information and its use Use of Microchip devices in lifesupport andor safety applications is entirely at the buyerrsquos risk and the buyer agrees to defendindemnify and hold harmless Microchip from any and all damages claims suits or expenses resultingfrom such use No licenses are conveyed implicitly or otherwise under any Microchip intellectualproperty rights unless otherwise stated

Trademarks

The Microchip name and logo the Microchip logo AnyRate AVR AVR logo AVR Freaks BeaconThingsBitCloud CryptoMemory CryptoRF dsPIC FlashFlex flexPWR Heldo JukeBlox KeeLoq KeeLoq logoKleer LANCheck LINK MD maXStylus maXTouch MediaLB megaAVR MOST MOST logo MPLABOptoLyzer PIC picoPower PICSTART PIC32 logo Prochip Designer QTouch RightTouch SAM-BASpyNIC SST SST Logo SuperFlash tinyAVR UNIO and XMEGA are registered trademarks ofMicrochip Technology Incorporated in the USA and other countries

ClockWorks The Embedded Control Solutions Company EtherSynch Hyper Speed Control HyperLightLoad IntelliMOS mTouch Precision Edge and Quiet-Wire are registered trademarks of MicrochipTechnology Incorporated in the USA

Adjacent Key Suppression AKS Analog-for-the-Digital Age Any Capacitor AnyIn AnyOut BodyComchipKIT chipKIT logo CodeGuard CryptoAuthentication CryptoCompanion CryptoControllerdsPICDEM dsPICDEMnet Dynamic Average Matching DAM ECAN EtherGREEN In-Circuit SerialProgramming ICSP Inter-Chip Connectivity JitterBlocker KleerNet KleerNet logo Mindi MiWimotorBench MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach OmniscientCode Generation PICDEM PICDEMnet PICkit PICtail PureSilicon QMatrix RightTouch logo REALICE Ripple Blocker SAM-ICE Serial Quad IO SMART-IS SQI SuperSwitcher SuperSwitcher II TotalEndurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA aretrademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademark of Microchip Technology Germany II GmbH amp Co KG a subsidiary ofMicrochip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

ISBN 978-1-5224-3311-8

Quality Management System Certified by DNV

ISOTS 16949Microchip received ISOTS-169492009 certification for its worldwide headquarters design and waferfabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in Californiaand India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg

DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory andanalog products In addition Microchiprsquos quality system for the design and manufacture of developmentsystems is ISO 90012000 certified

AMERICAS ASIAPACIFIC ASIAPACIFIC EUROPECorporate Office2355 West Chandler BlvdChandler AZ 85224-6199Tel 480-792-7200Fax 480-792-7277Technical SupporthttpwwwmicrochipcomsupportWeb AddresswwwmicrochipcomAtlantaDuluth GATel 678-957-9614Fax 678-957-1455Austin TXTel 512-257-3370BostonWestborough MATel 774-760-0087Fax 774-760-0088ChicagoItasca ILTel 630-285-0071Fax 630-285-0075DallasAddison TXTel 972-818-7423Fax 972-818-2924DetroitNovi MITel 248-848-4000Houston TXTel 281-894-5983IndianapolisNoblesville INTel 317-773-8323Fax 317-773-5453Tel 317-536-2380Los AngelesMission Viejo CATel 949-462-9523Fax 949-462-9608Tel 951-273-7800Raleigh NCTel 919-844-7510New York NYTel 631-435-6000San Jose CATel 408-735-9110Tel 408-436-4270Canada - TorontoTel 905-695-1980Fax 905-695-2078

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Austria - WelsTel 43-7242-2244-39Fax 43-7242-2244-393Denmark - CopenhagenTel 45-4450-2828Fax 45-4485-2829Finland - EspooTel 358-9-4520-820France - ParisTel 33-1-69-53-63-20Fax 33-1-69-30-90-79Germany - GarchingTel 49-8931-9700Germany - HaanTel 49-2129-3766400Germany - HeilbronnTel 49-7131-67-3636Germany - KarlsruheTel 49-721-625370Germany - MunichTel 49-89-627-144-0Fax 49-89-627-144-44Germany - RosenheimTel 49-8031-354-560Israel - RarsquoananaTel 972-9-744-7705Italy - MilanTel 39-0331-742611Fax 39-0331-466781Italy - PadovaTel 39-049-7625286Netherlands - DrunenTel 31-416-690399Fax 31-416-690340Norway - TrondheimTel 47-7289-7561Poland - WarsawTel 48-22-3325737Romania - BucharestTel 40-21-407-87-50Spain - MadridTel 34-91-708-08-90Fax 34-91-708-08-91Sweden - GothenbergTel 46-31-704-60-40Sweden - StockholmTel 46-8-5090-4654UK - WokinghamTel 44-118-921-5800Fax 44-118-921-5820

Worldwide Sales and Service

Introduction

Features

Table of Contents

1 Description

2 Configuration Summary

3 Ordering Information

4 Block Diagram

5 Pin Configurations

51 Pin Descriptions

511 VCC

512 GND

513 Port B (PB[70]) XTAL1XTAL2TOSC1TOSC2

514 Port C (PC[50])

515 PC6RESET

516 Port D (PD[70])

517 Port E (PE[30])

518 AVCC

519 AREF

5110 ADC[76] (TQFP and VFQFN Package Only)

6 IO Multiplexing

7 Automotive Quality Grade

8 Resources


10 AVR CPU Core

101 Overview

102 ALU ndash Arithmetic Logic Unit

103 Status Register


104 General Purpose Register File

1041 The X-register Y-register and Z-register

105 Stack Pointer


106 Instruction Execution Timing

107 Reset and Interrupt Handling

1071 Interrupt Response Time

11 AVR Memories

111 Overview

112 In-System Reprogrammable Flash Program Memory

113 SRAM Data Memory

1131 Data Memory Access Times

114 EEPROM Data Memory

1141 EEPROM ReadWrite Access

1142 Preventing EEPROM Corruption

115 IO Memory

1151 General Purpose IO Registers


1161 Accessing 16-Bit Registers








121 Clock Systems and Their Distribution







122 Clock Sources

1221 Default Clock Source

1222 Clock Start-Up Sequence

1223 Clock Source Connections

123 Low-Power Crystal Oscillator

124 Low Frequency Crystal Oscillator

125 Calibrated Internal RC Oscillator

126 128 kHz Internal Oscillator

127 External Clock

128 Clock Output Buffer

129 TimerCounter Oscillator

1210 System Clock Prescaler





131 Overview

132 Features

133 Operations

134 Timing Diagram




141 Overview

142 Sleep Modes

143 BOD Disable

144 Idle Mode

145 ADC Noise Reduction Mode

146 Power-Down Mode

147 Power-Save Mode

148 Standby Mode

149 Extended Standby Mode

1410 Power Reduction Registers

1411 Minimizing Power Consumption

14111 Analog to Digital Converter


14113 Brown-Out Detector

14114 Internal Voltage Reference

14115 Watchdog Timer

14116 Port Pins

14117 On-chip Debug System






151 Resetting the AVR

152 Reset Sources

153 Power-on Reset

154 External Reset

155 Brown-out Detection

156 Watchdog System Reset


1571 Voltage Reference Enable Signals and Start-up Time

158 Watchdog Timer

1581 Features

1582 Overview




16 INT- Interrupts

161 Interrupt Vectors in ATmega328PB


1621 Moving Interrupts Between Application and Boot Space


17 EXTINT - External Interrupts

171 Pin Change Interrupt Timing











18 IO-Ports

181 Overview

182 Ports as General Digital IO

1821 Configuring the Pin

1822 Toggling the Pin

1823 Switching Between Input and Output

1824 Reading the Pin Value

1825 Digital Input Enable and Sleep Modes

1826 Unconnected Pins

183 Alternate Port Functions

1831 Alternate Functions of Port B

1832 Alternate Functions of Port C

1833 Alternate Functions of Port D

1834 Alternate Functions of Port E
















191 Features

192 Overview

1921 Definitions

1922 Registers

193 TimerCounter Clock Sources

194 Counter Unit

195 Output Compare Unit

1951 Force Output Compare

1952 Compare Match Blocking by TCNTn Write

1953 Using the Output Compare Unit

196 Compare Match Output Unit

1961 Compare Output Mode and Waveform Generation

197 Modes of Operation

1971 Normal Mode

1972 Clear Timer on Compare Match (CTC) Mode

1973 Fast PWM Mode

1974 Phase Correct PWM Mode

198 TimerCounter Timing Diagrams











201 Features

202 Overview

2021 Definitions

2022 Registers

203 Accessing 16-bit TimerCounter Registers


205 Counter Unit

206 Input Capture Unit

2061 Input Capture Trigger Source

2062 Noise Canceler

2063 Using the Input Capture Unit



208 Output Compare Units


2091 Normal Mode


2093 Fast PWM Mode


2095 Phase and Frequency Correct PWM Mode






























21 TimerCounter 0 1 3 4 Prescalers

211 Internal Clock Source

212 Prescaler Reset

213 External Clock Source




221 Features

222 Overview

2221 Definitions

2222 Registers


224 Counter Unit



2252 Compare Match Blocking by TCNT2 Write





2271 Normal Mode


2273 Fast PWM Mode



229 Asynchronous Operation of TimerCounter2

2210 TimerCounter Prescaler












231 Overview

232 Description

2321 Timing Example


241 Features

242 Overview


2431 Slave Mode

2432 Master Mode

244 Data Modes









251 Features

252 Overview

253 Block Diagram

254 Clock Generation

2541 Internal Clock Generation ndash The Baud Rate Generator

2542 Double Speed Operation (U2Xn)

2543 External Clock

2544 Synchronous Clock Operation

255 Frame Formats

2551 Parity Bit Calculation

256 USART Initialization

257 Data Transmission ndash The USART Transmitter

2571 Sending Frames with 5 to 8 Data Bits

2572 Sending Frames with 9 Data Bits

2573 Transmitter Flags and Interrupts

2574 Parity Generator

2575 Disabling the Transmitter

258 Data Reception ndash The USART Receiver

2581 Receiving Frames with 5 to 8 Data Bits

2582 Receiving Frames with 9 Data Bits

2583 Receive Compete Flag and Interrupt

2584 Receiver Error Flags

2585 Parity Checker

2586 Disabling the Receiver

2587 Flushing the Receive Buffer

259 Asynchronous Data Reception

2591 Asynchronous Clock Recovery

2592 Asynchronous Data Recovery

2593 Asynchronous Operational Range

2594 Start Frame Detection

2510 Multi-Processor Communication Mode

25101 Using MPCMn

2511 Examples of Baud Rate Setting








261 Features

262 Overview


264 SPI Data Modes and Timing

265 Frame Formats

2651 USART MSPIM Initialization

266 Data Transfer

2661 Transmitter and Receiver Flags and Interrupts

2662 Disabling the Transmitter or Receiver

267 AVR USART MSPIM vs AVR SPI



271 Features

272 Two-Wire Serial Interface Bus Definition

2721 TWI Terminology

2722 Electrical Interconnection


2731 Transferring Bits

2732 START and STOP Conditions

2733 Address Packet Format

2734 Data Packet Format

2735 Combining Address and Data Packets Into a Transmission

274 Multi-Master Bus Systems Arbitration and Synchronization

275 Overview of the TWI Module

2751 SCL and SDA Pins

2752 Bit Rate Generator Unit

2753 Bus Interface Unit

2754 Address Match Unit

2755 Control Unit

276 Using the TWI

277 Transmission Modes

2771 Master Transmitter Mode

2772 Master Receiver Mode

2773 Slave Transmitter Mode

2774 Slave Receiver Mode

2775 Miscellaneous States

2776 Combining Several TWI Modes

278 Multi-Master Systems and Arbitration









281 Overview

282 Analog Comparator Multiplexed Input





291 Features

292 Overview

293 Starting a Conversion

294 Prescaling and Conversion Timing

295 Changing Channel or Reference Selection

2951 ADC Input Channels

2952 ADC Voltage Reference

296 ADC Noise Canceler

2961 Analog Input Circuitry

2962 Analog Noise Canceling Techniques

2963 ADC Accuracy Definitions

297 ADC Conversion Result









301 Features

302 Overview

303 Block Diagram

304 Signal Description

305 System Dependencies

3051 IO Lines

30511 Mutual-Capacitance Sensor Arrangement

30512 Self-Capacitance Sensor Arrangement

306 Functional Description


311 Features

312 Overview

313 Physical Interface

314 Software Break Points

315 Limitations of debugWIRE




321 Features

322 Overview

323 Application and Boot Loader Flash Sections

3231 Application Section

3232 BLS ndash Boot Loader Section

324 Read-While-Write and No Read-While-Write Flash Sections

3241 RWW ndash Read-While-Write Section

3242 NRWW ndash No Read-While-Write Section

325 Entering the Boot Loader Program

326 Boot Loader Lock Bits

327 Addressing the Flash During Self-Programming

328 Self-Programming the Flash

3281 Performing Page Erase by SPM

3282 Filling the Temporary Buffer (Page Loading)

3283 Performing a Page Write

3284 Using the SPM Interrupt

3285 Consideration While Updating Boot Loader Section (BLS)

3286 Prevent Reading the RWW Section During Self-Programming

3287 Setting the Boot Loader Lock Bits by SPM

3288 EEPROM Write Prevents Writing to SPMCSR

3289 Reading the Fuse and Lock Bits from Software

32810 Reading the Signature Row from Software

32811 Preventing Flash Corruption

32812 Programming Time for Flash when Using SPM


32814 Boot Loader Parameters




331 Program And Data Memory Lock Bits

332 Fuse Bits

3321 Latching of Fuses

333 Signature Bytes

334 Calibration Byte

335 Serial Number


33511 Device ID n

33512 RC Oscillator Calibration Byte

33513 Serial Number Byte n

336 Page Size

337 Parallel Programming Parameters Pin Mapping and Commands

3371 Signal Names


3381 Entering Programming Mode

3382 Considerations for Efficient Programming

3383 Chip Erase

3384 Programming the Flash

3385 Programming the EEPROM

3386 Reading the Flash

3387 Reading the EEPROM

3388 Programming the Fuse Low Bits

3389 Programming the Fuse High Bits

33810 Programming the Extended Fuse Bits

33811 Programming the Lock Bits

33812 Reading the Fuse and Lock Bits

33813 Reading the Signature Bytes

33814 Reading the Calibration Byte

33815 Parallel Programming Characteristics

339 Serial Downloading

3391 Serial Programming Pin Mapping

3392 Serial Programming Algorithm


3394 SPI Serial Programming Characteristics

34 Electrical Characteristics

341 Absolute Maximum Ratings

342 DC Characteristics

343 Power Consumption

344 Speed Grades


3451 Calibrated Internal RC Oscillator Accuracy

3452 External Clock Drive Waveforms

3453 External Clock Drive

346 System and Reset Characteristics

347 SPI Timing Characteristics

348 Two-Wire Serial Interface Characteristics

349 ADC Characteristics


35 Typical Characteristics

351 Active Supply Current

352 Idle Supply Current

353 ATmega328PB Automotive Supply Current of IO Modules

354 Power-down Supply Current

355 Pin Pull-Up

356 Pin Driver Strength

357 Pin Threshold and Hysteresis

358 BOD Threshold

359 Analog Comparator Offset

3510 Internal Oscillator Speed

3511 Current Consumption of Peripheral Units

3512 Current Consumption in Reset and Reset Pulse Width

36 Register Summary

37 Instruction Set Summary


381 32-Pin TQFP

382 32-Pin VQFN

39 Errata

391 Rev A

392 Rev C - D

393 Rev A - D

40 Revision History



Customer Support


Legal Notice

Trademarks



ndash Two Programmable Serial USARTsndash Two MasterSlave SPI Serial Interfacesndash Two Byte-Oriented Two-Wire Serial Interfaces (Philips I2C Compatible)ndash Programmable Watchdog Timer with Separate On-chip Oscillatorndash On-Chip Analog Comparatorndash Interrupt and Wake-Up on Pin Change

bull Special Microcontroller Featuresndash Power-On Reset and Programmable Brown-Out Detectionndash Internal 8 MHz Calibrated Oscillatorndash External and Internal Interrupt Sourcesndash Six Sleep Modes Idle ADC Noise Reduction Power-save Power-down Standby and Extended

Standbyndash Clock Failure Detection Mechanism and Switch to Internal 8 MHz RC Oscillator in case of Failurendash Individual Serial Number to Represent a Unique ID

bull IO and Packagesndash 27 Programmable IO Linesndash 32-pin TQFP and 32-pin Wettable Flank QFN

bull Operating Voltagendash 27 - 55V

bull Temperature Rangendash -40degC to 105degC

bull Speed Gradendash 0 - 16 MHz 45 ndash 55Vndash 0 - 8 MHz 27 ndash 55V

bull Power Consumption at 1 MHz 27V 25degCndash Active Mode 032 mAndash Power-Down Mode 02 μAndash Power-Save Mode 13 μA (Including 32 kHz RTC)

Table of Contents

Introduction1

Features 1

1 Description10

4 Block Diagram 13

6 IO Multiplexing18

8 Resources 21

18 IO-Ports 100

Legal Notice458

Trademarks 458

Pin count 32

Flash (KB) 32

SRAM (KB) 2

EEPROM (KB) 1

TWI (I2C) 2

USART 2

ADC 10-bit 15 ksps

ADC channels 8

PWM channels 10

PTC Available

Package Type

USART 0

ADCADC[70]AREF

RxD0TxD0XCK0

MISO1MOSI1SCK1SS1

IOPORTS

DATABUS

GPIOR[20]

EXTINT

FLASHNVM

programming

debugWire

DATABUS

TC 0(8-bit)

ACAIN0AIN1ACO

EEPROM

EEPROMIF

PTCX[150]Y[230]

TC 1(16-bit)

OC1ABT1

TC 3(16-bit)

TC 4(16-bit)

OC3ABT3

OC4ABT4

TC 2(8-bit async)

SDA0SCL0

SDA1SCL1

USART 1RxD1TxD1XCK1

InternalReference

Watchdog Timer

Power management

and clock control

Calib RC

128kHz int osc

32768kHz XOSC

External clock

XTAL2 TOSC2

XTAL1 TOSC1

16MHz LP XOSC

PCINT[270]INT[10]

T0OC0AOC0B

MISO0MOSI0SCK0SS0

OC2AOC2B

PB[70]PC[6 0]PD[70]PE[30]

PE[32] PC[50]AREF

PE[30] PD[70] PC[60] PB[70]PD3 PD2

PB1 PB2PD5PB0

PB3PD3

PD0 PD2PE3PE2

PD1 PD2PE1PE0

PD0PD1PD4

PC0PE3PC1PE2

PC4PC5

PE0PE1

PB4PB3PB5

PD4PD6PD5

PB4PB3PB5PB2

SPIPROG

PARPROG

PD6PD7PE0

32 31 30 29 28 27 265

9 10 11 12 13 14 15 16

PC0 (ADC0PTCYMISO1)

PC1 (ADC1PTCYSCK1)

(XCK0T0PTCXY) PD4

(SCL1T4PTCXY) PE1

(XTAL1TOSC1) PB6

(XTAL2TOSC2) PB7

(OC2BINT1PTCXY) PD3

Ground

Programmingdebug

Digital

Analog

CrystalCLK

PB5 (PTCXYXCK1SCK0)

32 31 30 29 28 27 26

9 10 11 12 13 14 15 16

PC0 (ADC0PTCYMISO1)

PC1 (ADC1PTCYSCK1)

(XCK0T0PTCXY) PD4

(SCL1T4PTCXY) PE1

(XTAL1TOSC1) PB6

(XTAL2TOSC2) PB7

(OC2BINT1PTCXY) PD3

PB5 (PTCXYXCK1SCK0)

51 Pin Descriptions

512 GNDGround

518 AVCC

18 AVCC

20 AREF

21 GND

10 AVR CPU Core

Register file

Program counter

Instruction decode

Data memory

ALUStatus register

Stack pointer

Bit 7 6 5 4 3 2 1 0 I T H S V N Z C

R0 0x00

R1 0x01

R2 0x02

hellip

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

hellip

X-register 7 0 7 0

R27 R26

15 YH YL 0

Y-register 7 0 7 0

R29 R28

15 ZH ZL 0

Z-register 7 0 7 0

R31 R30

Bit 15 14 13 12 11 10 9 8 SP11 SP10 SP9 SP8

T1 T2 T3 T4

Result Write Back

T1 T2 T3 T4

clkCPU

C Code Example(1)

11 AVR Memories

0x0000

0x3FFF

Program Memory

Boot Flash Section

0x0000 ndash 0x001F

0x0100

0x08FF

64 IO registers

32 registers

0x0020 ndash 0x005F

0x0060 ndash 0x00FF

0x0000 ndash 0x001F

T1 T2 T3

Compute Address

Bit 15 14 13 12 11 10 9 8 EEAR[98]

Bit 7 6 5 4 3 2 1 0 EEAR[70]

Bit 7 6 5 4 3 2 1 0 EEDR[70]

01 18ms Erase Only

10 18ms Write Only

C Code Example(1)

Bit 7 6 5 4 3 2 1 0 GPIOR2[70]

Bit 7 6 5 4 3 2 1 0 GPIOR1[70]

Bit 7 6 5 4 3 2 1 0 GPIOR0[70]

EEPROM

WatchdogTimer

ClockMultiplexer

Watchdog Oscillator

Oscillator

clkASY

clkCPU

Reset Logic

clkFLASH

clkADC

Watchdog clock

clkSYS

clkPTC

External Clock 0000

Reserved 0001

0ms 0ms

4 ms 43 ms

65 ms 69 ms

04 - 09 100(3) ndash

09 - 30 101 12 - 22

30 - 80 110 12 - 22

80 - 160 111 12 - 22

CKSEL0 SUT[10]

258 CK 19CK + 4 ms(1) 0 00

258 CK 19CK + 65 ms(1) 0 01

1K CK 19CK(2) 0 10

1K CK 19CK + 4 ms(2) 0 11

1K CK 19CK + 65 ms(2) 1 00

16K CK 19CK + 4 ms 1 10

16K CK 19CK + 65 ms 1 11

125 30

11 Reserved

Recommended Usage

0100(1) 1K CK

76 - 84 0010(2)

Reserved 11

128 kHz 0011

Reserved 11

Frequency CKSEL[30]

0 - 16 MHz 0000

EXTERNALCLOCKSIGNAL

EXTCLK

SUT[10]

Reserved 11

Bit 7 6 5 4 3 2 1 0 CAL [70]

Bit 7 6 5 4 3 2 1 0 CLKPCE CLKPS [30]

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

External Clock

System clock

XOSC CKSEL

XOSC Failed

WDT 128kHz CLK

XOSC(External CLK

128kHz

RC clock

Ext clock

Sys clock

Xosc failed

Delayed xosc failed

ch Tim

Bit 7 6 5 4 3 2 1 0 SM[20] SE

SM[20] Sleep Mode

000 Idle

010 Power-down

011 Power-save

100 Reserved

101 Reserved

110 Standby(1)

C Code Example

Delay Counters

CKSEL[30]

CKTIMEOUT

DATA BUS

ClockGenerator

SPIKEFILTER

Pull-up Resistor

WatchdogOscillator

SUT[10]

RSTDISBL

TIME-OUT

INTERNALRESET

TIME-OUT

INTERNALRESET

TIME-OUT

INTERNALRESET

VBOT-VBOT+

MCU RESET

INTERRUPT

128 kHzOSCILLATOR

C Code Example

1 0 0 Stopped None

0 0 0 0 2K (2048) 16 ms

0 0 0 1 4K (4096) 32 ms

0 0 1 0 8K (8192) 64 ms

0 0 1 1 16K (16384) 0125s

0 1 0 0 32K (32768) 025s

0 1 0 1 64K (65536) 05s

0 1 1 0 128K (131072) 10s

0 1 1 1 256K (262144) 20s

1 0 0 0 512K (524288) 40s

1 0 0 1 1024K (1048576) 80s

1 0 1 0 Reserved

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

In general

C Code Example

D Q D Q

PCINT[i]pin

D Q D Q D Q

7PCIFn

(interruptflag)

PCINT[i] pin

pin_lat

pin_sync

pcint_in[i]

pcint_syn

pcint_setflag

Bit 7 6 5 4 3 2 1 0 ISC1 [10] ISC0 [10]

Bit 7 6 5 4 3 2 1 0 INT1 INT0

Bit 7 6 5 4 3 2 1 0 INTF1 INTF0

Bit 7 6 5 4 3 2 1 0 PCINT[2724]

Bit 7 6 5 4 3 2 1 0 PCINT[2316]

Bit 7 6 5 4 3 2 1 0 PCINT[148]

Bit 7 6 5 4 3 2 1 0 PCINT[70]

18 IO-Ports

Details

SYNCHRONIZER

WDx WRITE DDRx

PUD PULLUP DISABLE

clkIO IO CLOCK

RDx READ DDRx

PORTxn

SLEEP SLEEP CONTROL

IO Pull-up Comment

XXX in r17 PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

SYSTEM CLK

tpd max

tpd min

0x00 0xFF

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

r17tpd

RRxWRx

SYNCHRONIZER

WDx WRITE DDRx

RPx READ PORTx PIN

PUD PULLUP DISABLE

clkIO IO CLOCK

RDx READ DDRx

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

PORTxn

1DIEOVxn

WPx WRITE PINx

SignalName

PB5SCK0XCK0PCINT5

PB4MISO0RXD1PCINT4

DDOV 0 0 0 0

SCK0 INPUT

Signal Name

DDOV 0 0 0 0

OC1B OC1A 0

DIEOV 1 1 1 1

PCINT2 INPUT

SPI0 SS

ICP1 INPUT

source

SignalName

PVOE 0 TWEN0 TWEN0

PVOV 0 0 0

SignalName

PC3ADC3PCINT11

PC2ADC2PCINT10

PC1ADC1SCK1PCINT9

PC0ADC0MISO1PCINT8

DDOV 0 0 0 0

SignalName

PC3ADC3PCINT11

PC2ADC2PCINT10

PC1ADC1SCK1PCINT9

PC0ADC0MISO1PCINT8

SignalName

PD7AIN1PCINT23

PD6AIN0OC0APCINT22

PD5T1OC0BPCINT21

PD4XCK0T0PCINT20

PUOE 0 0 0 0

PUO 0 0 0 0

DDOE 0 0 0 0

DDOV 0 0 0 0

DIEOV 1 1 1 1

SignalName

PD3OC2BINT1PCINT19

PD1TXD0OC4APCINT17

PD0OC3ARXD0PCINT16

DDOV 0 0 1 0

DIEOV 1 1 1 1

PCINT27

PCINT26

PCINT25

PCINT24

source

SignalName

PE1T4SCL1PCINT25

DDOV 0 0 0 0

C Code Example

Clock Select

TimerCounter

WaveformGeneration

FixedTOP

Control Logic

TOP BOTTOM

Direction

TOVn(IntReq)

OCnA(IntReq)

OCnB(IntReq)

TCCRnA TCCRnB

TnEdgeDetector

( From Prescaler )

DATA BUS

TCNTn Control Logic

TOVn(IntReq)

Clock Select

TnEdgeDetector

( From Prescaler )

bottom

direction

OCFnx (IntReq)

DATA BUS

WGMn[10]

Waveform Generator

COMnx[10]

bottom

OCnxPinOCnx

COMnx[1]COMnx[0]

1Period 2 3

(COMnx[10] = 0x2)

(COMnx[10] = 0x3)

4 5 6 7

Period

(COMnx[10] = 2)

(COMnx[10] = 3)

OCRnx Update

clkTn(clkIO1)

clkTn(clkIO8)

OCRnx Value

clkTn(clkIO8)

TCNTn(CTC)

clkTn(clkIO8)

Bit 7 6 5 4 3 2 1 0 COM0A[10] COM0B [10] WGM0[10]

0 1 Reserved

Bit 7 6 5 4 3 2 1 0 TCNT0[70]

Bit 7 6 5 4 3 2 1 0 OCR0A[70]

Bit 7 6 5 4 3 2 1 0 OCR0B[70]

Bit 7 6 5 4 3 2 1 0 OCF0B OCF0A TOV0

TEMP (8-bit)

DATA BUS (8-bit)

Direction

TOVn(IntReq)

Clock Select

TOP BOTTOM

TnEdgeDetector

( From Prescaler )

ICFn (IntReq)

AnalogComparator

ICRnH (8-bit)

NoiseCanceler

EdgeDetector

TEMP (8-bit)

DATA BUS (8-bit)

ICRnL (8-bit)

ACIC ICNC ICESACO

OCnxPinOCnx

COMnx[1]COMnx[0]

OCFnx (IntReq)

OCRnxH Buf (8-bit)

TEMP (8-bit)

DATA BUS (8-bit)

OCRnxL Buf (8-bit)

COMnx[10]WGMn[30]

BOTTOM

OCnA(Toggle)

1 4Period 2 3

(COMnA[10] = 0x1)

1 7Period 2 3 4 5 6 8

(COMnx[10] = 0x2)

(COMnx[10] = 0x3)

1 2 3 4

Period

(COMnx[10]] = 0x2)

(COMnx[10] = 0x3)

1 2 3 4

Period

(COMnx[10] = 0x2)

(COMnx[10] = 0x3)

clkTn(clkIO1)

OCRnx Value

clkTn(clkIO8)

as TOP)

TCNTn(CTC and FPWM)

clkTn(clkIO1)

as TOP)

TCNTn(CTC and FPWM)

clkTn(clkIO8)

Bit 7 6 5 4 3 2 1 0 COM1A[10] COM1B[10] WGM1[10]

COM1A[1]COM1B[1]

COM1A[0]COM1B[0]

Description

COM1A[1]COM1B[1]

COM1A[0]COM1B[0]

Description

COM1A[1]COM1B[1]

COM1A[0]COM1B[0]

Description

COM1A[1]COM1B[1]

COM1A[0]COM1B[0]

Description

(CTC1)(1)WGM1[1]

(PWM1[1])(1)WGM1[0]

(PWM1[0])(1)Timer

Counter

Mode ofOperation

TOP Update of

OCR1x at

TOV1 Flag

Set on

(CTC1)(1)WGM1[1]

(PWM1[1])(1)WGM1[0]

(PWM1[0])(1)Timer

Counter

Mode ofOperation

TOP Update of

OCR1x at

TOV1 Flag

Set on

0x01FF TOP BOTTOM

0x03FF TOP BOTTOM

0x01FF BOTTOM TOP

0x03FF BOTTOM TOP

Correct

ICR1 BOTTOM BOTTOM

Correct

OCR1A BOTTOM BOTTOM

ICR1 TOP BOTTOM

OCR1A TOP BOTTOM

Bit 7 6 5 4 3 2 1 0 FOC1A FOC1B

Bit 15 14 13 12 11 10 9 8 TCNT1[158]

Bit 7 6 5 4 3 2 1 0 TCNT1[70]

Bit 15 14 13 12 11 10 9 8 ICR1[158]

Bit 7 6 5 4 3 2 1 0 ICR1[70]

Bit 15 14 13 12 11 10 9 8 OCR1A[158]

Bit 7 6 5 4 3 2 1 0 OCR1A[70]

Bit 15 14 13 12 11 10 9 8 OCR1B[158]

Bit 7 6 5 4 3 2 1 0 OCR1B[70]

Bit 7 6 5 4 3 2 1 0 COM3A[10] COM3B[10] WGM3[10]

COM3A[1]COM3B[1]

COM3A[0]COM3B[0]

Description

COM3A[1]COM3B[1]

COM3A0COM3B[0]

Description

COM3A[1]COM3B[1]

COM3A[0]COM3B[0]

Description

(CTC1)(1)WGM3[1]

(PWM1[1])(1)WGM3[0]

(PWM1[0])(1)Timer

Counter

Mode ofOperation

TOP Update of

OCR1x at

TOV1 Flag

Set on

0x01FF TOP BOTTOM

0x03FF TOP BOTTOM

0x01FF BOTTOM TOP

0x03FF BOTTOM TOP

Correct

ICR1 BOTTOM BOTTOM

Correct

OCR3A BOTTOM BOTTOM

ICR3 TOP BOTTOM

OCR3A TOP BOTTOM

Bit 7 6 5 4 3 2 1 0 FOC3A FOC3B

Bit 15 14 13 12 11 10 9 8 TCNT3[158]

Bit 7 6 5 4 3 2 1 0 TCNT3[70]

Bit 15 14 13 12 11 10 9 8 ICR3[158]

Bit 7 6 5 4 3 2 1 0 ICR3[70]

Bit 15 14 13 12 11 10 9 8 OCR3A[158]

Bit 7 6 5 4 3 2 1 0 OCR3A[70]

Bit 15 14 13 12 11 10 9 8 OCR3B[158]

Bit 7 6 5 4 3 2 1 0 OCR3B[70]

Bit 7 6 5 4 3 2 1 0 COM4A[10] COM4B[10] WGM4[10]

COM4A[1]COM4B[1]

COM4A[0]COM4B[0]

Description

COM4A[1]COM4B[1]

COM4A[0]COM4B[0]

Description

COM4A[1]COM4B[1]

COM4A[0]COM4B[0]

Description

(CTC1)(1)WGM4[1]

(PWM1[1])(1)WGM4[0]

(PWM1[0])(1)Timer

Counter

Mode ofOperation

TOP Update of

OCR4x at

TOV1 Flag

Set on

0x01FF TOP BOTTOM

0x03FF TOP BOTTOM

0x01FF BOTTOM TOP

0x03FF BOTTOM TOP

Correct

ICR4 BOTTOM BOTTOM

Correct

OCR4A BOTTOM BOTTOM

ICR4 TOP BOTTOM

OCR4A TOP BOTTOM

Bit 7 6 5 4 3 2 1 0 FOC4A FOC4B

Bit 15 14 13 12 11 10 9 8 TCNT4[158]

Bit 7 6 5 4 3 2 1 0 TCNT4[70]

Bit 15 14 13 12 11 10 9 8 ICR4[158]

Bit 7 6 5 4 3 2 1 0 ICR4[70]

Bit 15 14 13 12 11 10 9 8 OCR4A[158]

Bit 7 6 5 4 3 2 1 0 OCR4A[70]

Bit 15 14 13 12 11 10 9 8 OCR4B[158]

Bit 7 6 5 4 3 2 1 0 OCR4B[70]

D QD Q

clk IO

CSn0CSn1CSn2

Synchronization

10-BIT TC PRESCALER

clk IO

Clock Select

TimerCounter

WaveformGeneration

FixedTOP

Control Logic

TOP BOTTOM

Direction

TOVn(IntReq)

OCnA(IntReq)

OCnB(IntReq)

TCCRnA TCCRnB

TnEdgeDetector

( From Prescaler )

DATA BUS

TCNTn Control Logic

TOVn(IntReq)

topbottom

direction

TCOscillator

Prescaler

clk Tnclear

OCFnx (IntReq)

DATA BUS

WGMn[10]

Waveform Generator

COMnx[10]

bottom

OCnxPinOCnx

COMnx[1]COMnx[0]

1Period 2 3

(COMnx[10] = 0x2)

(COMnx[10] = 0x3)

4 5 6 7

Period

(COMnx[10] = 2)

(COMnx[10] = 3)

OCRnx Update

clkTn(clkIO1)

clkTn(clkIO8)

OCRnx Value

clkTn(clkIO8)

TCNTn(CTC)

clkTn(clkIO8)

10-BIT TC PRESCALER

IO clkT2S

TOSC1cl

clk T2

0PSRASY

CS20CS21CS22

Bit 7 6 5 4 3 2 1 0 COM2A [10] COM2B [10] WGM2 [10]

0 1 Reserved

Mode ofOperation

TOV Flag Seton(1)

Bit 7 6 5 4 3 2 1 0 TCNT2[70]

Bit 7 6 5 4 3 2 1 0 OCR2A[70]

Bit 7 6 5 4 3 2 1 0 OCR2B[70]

Bit 7 6 5 4 3 2 1 0 OCF2B OCF2A TOV2

OC3B OC4B PD2

TimerCounter 3

TimerCounter 4 OC4B

COM3B0COM3B1

COM4B0COM4B1

RPORTD2 DDRD2

OC4B(CTC Mode)

OC3B(FPWM Mode)

PD2(PORTD2 = 0)

PD2(PORTD2 = 1)

(Period) 3

clk IO

DIVIDER248163264128

SHIFTENABLE

C Code Example

return SPDR

Bit 1Bit 6

LSBMSB

SAMPLE IMOSIMISO

MSBLSB

Bit 6Bit 1

Bit 5Bit 2

Bit 4Bit 3

Bit 3Bit 4

Bit 2Bit 5

SAMPLE IMOSIMISO

MSBLSB

Bit 6Bit 1

Bit 5Bit 2

Bit 4Bit 3

Bit 3Bit 4

Bit 2Bit 5

Bit 1Bit 6

LSBMSB

0 Rising Falling

1 Falling Rising

0 Sample Setup

1 Setup Sample

0 0 0 fosc4

0 0 1 fosc16

0 1 0 fosc64

0 1 1 fosc128

1 0 0 fosc2

1 0 1 fosc8

1 1 0 fosc32

1 1 1 fosc64

0 Rising Falling

1 Falling Rising

0 Sample Setup

1 Setup Sample

0 0 0 fosc4

0 0 1 fosc16

0 1 0 fosc64

0 1 1 fosc128

1 0 0 fosc2

1 0 1 fosc8

1 1 0 fosc32

1 1 1 fosc64

Bit 7 6 5 4 3 2 1 0 SPID[70]

Bit 7 6 5 4 3 2 1 0 SPID1[70]

PARITYGENERATOR

UBRRn [HL]

UDRn(Transmit)

BAUD RATE GENERATOR

TxDnPINCONTROL

UDRn (Receive)

PINCONTROL

DATARECOVERY

CLOCKRECOVERY

PINCONTROL

TXCONTROL

RXCONTROL

PARITYCHECKER

SYNC LOGIC

Clock Generator

Transmitter

Receiver

UBRRn+1

SyncRegister

XCKnPin

UMSELn

DDR_XCKn

DDR_XCKnrxclk

Detector

UCPOLn

Signal description

RxDn TxDn

XCKn UCPOL = 0

UCPOL = 1

Sample

second stop bit

C Code Example

in r16 UDR0 ret

C Code Example

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2

STARTIDLE

1 2 3 4 5 6 7 8 1 20

Sample(U2X = 0)

Sample(U2X = 1)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1

1 2 3 4 5 6 7 8 1

Sample(U2X = 0)

Sample(U2X = 1)

1 2 3 4 5 6 7 8 9 10 01 01 01

STOP 1

1 2 3 4 5 6 01

Sample(U2X = 0)

Sample(U2X = 1)

(A) (B) (C)

D (Data+Parity Bit)

5 9320 10667 +667-68 plusmn30

6 9412 10579 +579-588 plusmn25

7 9481 10511 +511-519 plusmn20

8 9536 10458 +458-454 plusmn20

9 9581 10414 +414-419 plusmn15

10 9617 10378 +378-383 plusmn15

D (Data+Parity Bit)

5 9412 10566 +566-588 plusmn25

6 9492 10492 +492-508 plusmn20

7 9552 10435 +435-448 plusmn15

8 9600 10390 +390-400 plusmn15

9 9639 10353 +353-361 plusmn15

10 9670 10323 +323-330 plusmn10

5 6 7 8 9 10

0 - 288 kbps +667-588

+579-508

+511-448

+458-400

+414-361

+378-330

384 kbps +663-588

+575-508

+508-448

+455-400

+412-361

+376-330

576 kbps +610-588

+530-508

+469-448

+420-400

+380-361

+347-330

768 kbps +559-588

+485-508

+429-448

+385-400

+348-361

+318-330

1152 kbps +457-588

+397-508

+351-448

+315-400

+286-361

+261-330

5 6 7 8 9 10

0 - 576 kbps +566-400

+492-345

+435-303

+390-270

+353-244

+323-222

768 kbps +559-400

+485-345

+429-303

+385-270

+348-244

+318-222

1152 kbps +457-400

+397-345

+351-303

+315-270

+286-244

+261-222

BaudRate[bps]

2400 25 02 51 02 47 00 95 00 51 02 103 02

4800 12 02 25 02 23 00 47 00 25 02 51 02

9600 6 -70 12 02 11 00 23 00 12 02 25 02

144k 3 85 8 -35 7 00 15 00 8 -35 16 21

192k 2 85 6 -70 5 00 11 00 6 -70 12 02

288k 1 85 3 85 3 00 7 00 3 85 8 -35

384k 1 -186 2 85 2 00 5 00 2 85 6 -70

576k 0 85 1 85 1 00 3 00 1 85 3 85

768k ndash ndash 1 -186 1 -250 2 00 1 -186 2 85

1152k ndash ndash 0 85 0 00 1 00 0 85 1 85

Baud Rate[bps]

2400 95 00 191 00 103 02 207 02 191 00 383 00

4800 47 00 95 00 51 02 103 02 95 00 191 00

9600 23 00 47 00 25 02 51 02 47 00 95 00

144k 15 00 31 00 16 21 34 -08 31 00 63 00

192k 11 00 23 00 12 02 25 02 23 00 47 00

288k 7 00 15 00 8 -35 16 21 15 00 31 00

384k 5 00 11 00 6 -70 12 02 11 00 23 00

576k 3 00 7 00 3 85 8 -35 7 00 15 00

768k 2 00 5 00 2 85 6 -70 5 00 11 00

1152k 1 00 3 00 1 85 3 85 3 00 7 00

2304k 0 00 1 00 0 85 1 85 1 00 3 00

Baud Rate[bps]

250k 0 -78 1 -78 0 00 1 00 1 -78 3 -78

Baud Rate[bps]

2400 207 02 416 -01 287 00 575 00 383 00 767 00

4800 103 02 207 02 143 00 287 00 191 00 383 00

9600 51 02 103 02 71 00 143 00 95 00 191 00

144k 34 -08 68 06 47 00 95 00 63 00 127 00

192k 25 02 51 02 35 00 71 00 47 00 95 00

288k 16 21 34 -08 23 00 47 00 31 00 63 00

384k 12 02 25 02 17 00 35 00 23 00 47 00

576k 8 -35 16 21 11 00 23 00 15 00 31 00

768k 6 -70 12 02 8 00 17 00 11 00 23 00

1152k 3 85 8 -35 5 00 11 00 7 00 15 00

2304k 1 85 3 85 2 00 5 00 3 00 7 00

250k 1 00 3 00 2 -78 5 -78 3 -78 6 53

05M 0 00 1 00 ndash ndash 2 -78 1 -78 3 -78

U2Xn = 0 U2Xn = 1

2400 416 -01 832 00

4800 207 02 416 -01

9600 103 02 207 02

144k 68 06 138 -01

192k 51 02 103 02

288k 34 -08 68 06

384k 25 02 51 02

576k 16 21 34 -08

768k 12 02 25 02

1152k 8 -35 16 21

2304k 3 85 8 -35

250k 3 00 7 00

05M 1 00 3 00

1M 0 00 1 00

Bit 7 6 5 4 3 2 1 0 TXB RXB[70]

UDORDnUCSZn0 UCPHAn

UCPOLn

UMSEL[10] Mode

10 Reserved

enabled

UPM[10] ParityMode

00 Disabled

01 Reserved

USBS Stop Bit(s)

0 1-bit

1 2-bit

000 5-bit

001 6-bit

010 7-bit

011 8-bit

100 Reserved

101 Reserved

110 Reserved

111 9-bit

Bit 15 14 13 12 11 10 9 8 UBRRn[118]

Bit 7 6 5 4 3 2 1 0 UBRRn[70]

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

UCPOL=0 UCPOL=1

UBRRn = 0

Term Description

Data Change

ST AR T

1 2 7 8 9

AggregateSDA

SDA fromTransmitter

SDA fromReceiver

SCL fromMaster

1 2 7 8 9

Data Byte

SCL1 2 7 8 9

SLA+RW STOPSTART

SCL fromMaster A

SCL fromMaster B

SCL BusLine

TBlow TBhigh

SDA from Master A

SDA from Master B

SDA Line

Address Match Unit

Address Comparator

Control Unit

Slew-rateControl

SpikeFilter

ControlSpikeFilter

Bit Rate Generator

Prescaler

Bus Interface Unit

START STOPControl

Spike Suppression

Slew-rate

TWI bus

IndicatesTWINT set

S START condition

P STOP condition

SLA Slave Address

Device 1MASTER

TRANSMITTER

Device 2SLAVE

Status Code(TWSR)

PrescalerBits are 0

ToFromTWDR

To TWCRn

STA STO TWINT TWEA

Load SLA+Wor

Load databyte or

No TWDRaction or

No TWDRaction

Status Code(TWSR)

PrescalerBits are 0

ToFromTWDR

To TWCRn

STA STO TWINT TWEA

Load databyte or

No TWDRaction or

No TWDRaction

Load databyte or

No TWDRaction or

No TWDRaction

Load databyte or

No TWDRaction or

No TWDRaction

Status Code(TWSR)

PrescalerBits are 0

ToFromTWDR

To TWCRn

STA STO TWINT TWEA

No TWDRaction or

No TWDRaction

S SLA W A DATA A P

0x08 0x18 0x28

R SLA W

A or A

DATA A

Device 1MASTER

RECEIVER

Device 2SLAVE

Status Code(TWSRn)

Prescaler Bitsare 0

ToFromTWD

To TWCRn

STA STO TWINT TWEA

Status Code(TWSRn)

Prescaler Bitsare 0

ToFromTWD

To TWCRn

STA STO TWINT TWEA

No TWDRaction

Read databyte

S SLA R A A

0x08 0x40 0x50

A or A

0x38 0x38

0x68 0x78 0xB0

DATA A

DATA DATA

Device 3 Device n

Device 2MASTER

RECEIVER

Device 1SLA VE

TRANSMITTER

Status Code(TWSRb)

PrescalerBits are 0

ToFromTWDRn

To TWCRn

STA STO TWINT TWEA

Load databyte

No TWDRnaction

Status Code(TWSRb)

PrescalerBits are 0

ToFromTWDRn

To TWCRn

STA STO TWINT TWEA

No TWDRnaction

becomes free

S SLA R A A

0xA8 0xB8

P or S

DATA A

P or SAll 1s

DATA DATA

Device 3 Device n

Device 2MASTER

TRANSMITTER

Device 1SLAVE

RECEIVER

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

No TWDRnaction

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

Read databyte

becomes free

Read databyte

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

becomes free

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

S SLA W A DATA A

0x60 0x80

P or SDATA A

0x80 0xA0

P or SA

A DATA A

0x70 0x90

P or SDATA A

0x90 0xA0

P or SA

General Call

DATA A

Status Code(TWSR)

Prescaler Bits are0

ToFromTWDRn

To TWCRn

STA STO TWINT TWEA

No TWDRnaction

Device 1MASTER

TRANSMITTER

Device 2MASTER

TRANSMITTER

Device 3SLAVE

RECEIVERDevice n

received

Direction

SLASTART Data STOP

ReadB0

Bit 7 6 5 4 3 2 1 0 TWBR [70]

Bit 7 6 5 4 3 2 1 0 TWA[60] TWGCE

Bit 7 6 5 4 3 2 1 0 TWD[70]

Bit 7 6 5 4 3 2 1 0 TWAM[60]

TWAMR0

AddressBit 0

AddressMatch

BANDGAPREFERENCE

ACMEADEN

INTERRUPT SELECT

ACIS1 ACIS0 ACIC

ANALOGCOMPARATORIRQ

0 x xxx AIN1

1 1 xxx AIN1

1 0 000 ADC0

1 0 001 ADC1

1 0 010 ADC2

1 0 011 ADC3

1 0 100 ADC4

1 0 101 ADC5

1 0 110 ADC6

1 0 111 ADC7

0 1 Reserved

Bit 7 6 5 4 3 2 1 0 AIN1D AIN0D

COMPLETE IRQ

8-BIT DATA BUS

15 0ADC MULTIPLEXER

CONVERSION LOGIC

10-BIT DAC+-

MUX DECODER

BANDGAP REFERENCE

PRESCALER

INPUT MUX

SOURCE 1

SOURCE n

ADTS[20]

CONVERSIONLOGIC

PRESCALER

START CLKADC

EDGEDETECTOR

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0ADPS1ADPS2

ResetADENSTART

LSB of Result

ADC Clock

Sample and Hold

Cycle Number

1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2

MUX and REFSUpdate

ConversionComplete

1 2 3 4 5 6 7 8 9 10 11 12 13

LSB of Result

ADC Clock

Cycle Number 1 2

ConversionComplete

MUX and REFSUpdate

1 2 3 4 5 6 7 8 9 10 11 12 13

LSB of Result

ADC Clock

TriggerSource

Cycle Number 1 2

PrescalerReset

Sample ampHold

MUX and REFSUpdate

11 12 13

LSB of Result

ADC Clock

Cycle Number 1 2

ConversionComplete

1100k ΩCSH = 14pF

IILVCC2

PC1 (ADC1)

PC0 (ADC0)

10 micro

VREF Input Voltage

Ideal ADC

Actual ADC

OffsetError

VREF Input Voltage

Ideal ADC

Actual ADC

GainError

VREF Input Voltage

Ideal ADC

Actual ADC

10 Reserved

0000 ADC0

0001 ADC1

0010 ADC2

0011 ADC3

0100 ADC4

0101 ADC5

0110 ADC6

0111 ADC7

1000 Reserved

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 11V (VBG)

1111 0V (GND)

100 16

101 32

110 64

111 128

Bit 15 14 13 12 11 10 9 8 ADC[98]

Bit 7 6 5 4 3 2 1 0 ADC[70]

Bit 15 14 13 12 11 10 9 8 ADC[92]

Bit 7 6 5 4 3 2 1 0 ADC[10]

Bit 7 6 5 4 3 2 1 0 ACME ADTS [20]

CompensationCircuit

RS IRQ

Result

X Line Driver

InputControl

CompensationCircuit

RS IRQ

Result

X Line Driver

InputControl

PTCModule

Cx0y0 Cx0y1 Cx0ym

Cx1y0 Cx1y1 Cx1ym

Cxny0 Cxny1 Cxnym

PTCModule

Link Application

QTouchLibrary

dW(RESET)

27 - 55V

Bit 7 6 5 4 3 2 1 0 DWDR[70]

The user can select

BLB0Mode

BLB1Mode

Bit 15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

PROGRAM MEMORY

Z - REGISTER

ZPAGEMSB

ZPCMSB

INSTRUCTION WORD

PAGEEND

PROGRAMCOUNTER

Bit 7 6 5 4 3 2 1 0

Max ProgrammingTime

32 ms 34 ms

org SMALLBOOTSTART

1 1 256words

4 0x0000 -0x3EFF

0x3F00 -0x3FFF

0x3EFF 0x3F00

1 0 512words

8 0x0000 -0x3DFF

0x3E00 -0x3FFF

0x3DFF 0x3E00

0 1 1024words

16 0x0000 -0x3BFF

0x3C00 -0x3FFF

0x3BFF 0x3C00

0 0 2048words

32 0x0000 -0x37FF

0x3800 -0x3FFF

0x37FF 0x3800

Description

LB Mode LB2 LB1

BLB0Mode

BLB02 BLB01

BLB1Mode

BLB12 BLB11

ndash 7 ndash 1

ndash 6 ndash 1

ndash 5 ndash 1

ndash 4 ndash 1

decoding

0 (programmed)(4)

0x000 0x001 0x002

Offset Name Bit Pos

0x03 Reserved

0x050x0D

Reserved

Offset Name Bit Pos

Offset 0x00 + n0x02 [n=02]

Reset [Device ID]

Property -

Bit 7 6 5 4 3 2 1 0

Reset 0 0 0 0 0 0 0 0

Name SIGROW_RCOC

Offset 0x01

Property -

Bit 7 6 5 4 3 2 1 0

Register RCOC[70]

Name SIGROW_SERNUMn

Property -

Bit 7 6 5 4 3 2 1 0

Register SERNUM[70]

PCPAGE PCMSB

64 words PC[50] 256 PC[136] 13

Device EEPROMSize

Page Size

PCWORD No of Pages

PCPAGE EEAMSB

PC[10]PB[50] DATA

RDYBSY

+45 - 55V

Pin Symbol Value

1 0 Load Command

1 1 No Action Idle

PROGRAM MEMORY

INSTRUCTION WORD

PAGEEND

PROGRAMCOUNTER

RDYBSY

RESET+12V

XX XX XX

RDYBSY

RESET+12V

A G B C E B C E L

RDYBSY

RESET +12V

0x40DATA DATA XX

A C0x40 DATA XX

0x40 DATA XX

Lock Bits 0

Fuse High Byte

Fuse Low Byte 0

Extended Fuse Byte

+27 - 55V

+27 - 55V (2)

Turn VCC power off

tWD_FLASH 26 ms

tWD_EEPROM 36 ms

tWD_ERASE 105 ms

tWD_FUSE 26 ms

the page range

Page N-1

Page Buffer

Bit 15 B 0

Adr MSB Adr LSB

Page Offset

Page Number

(MISO)

SAMPLE

SERIAL DATA OUTPUT

-05V to VCC+05V

VCC = 27V - 55V -05 03VCC(1) V

VCC = 27V - 55V 06VCC(2) VCC + 05 V

VCC = 27V - 55V -05 01VCC(1) V

VCC = 27V - 55V 07VCC(2) VCC + 05 V

VCC = 27V - 55V -05 01VCC(1) V

VCC = 27V - 55V 09VCC(2) VCC + 05 V

VCC = 27V - 55V -05 03VCC(1) V

VCC = 27V - 55V 06VCC(2) VCC + 05 V

VCC = 5V

TA=85degC 09

TA=105degC 10

IOL = 10 mA

VCC = 3V

TA=85degC 06

TA=105degC 07 V

VCC = 5V

TA=85degC 40

TA=105degC 39

IOH = 10 mA

VCC = 3V

TA=85degC 21

TA=105degC 20 V

VCC=5V

Vin = VCC2

-100 100 nA

400 ns

T = 25degC 15 μA

T = 85degC 21

T = 105degC 28

T = 85degC 38 8

T = 105degC 46 10

T = 85degC 07 2

T = 105degC 14 5

27V 45V 55V

Safe Operating Area

FactoryCalibration

plusmn1

Min Max Min Max

10 11 12 V

- 40 70 μs

- 10 - μA

111 BOD Disabled

101 25 27 29 V

100 41 43 45

Other Reserved

3 RiseFalltime

Master - 36 -

8 SCK to outhigh

Master - 10 -

11 SCK highlow(1)

12 RiseFalltime

Slave - - 1600

16 SCK to SShigh

Slave 20 - -

Slave - 10 -

18 SS low toSCK

MOSI(Data Output)

SCK(CPOL = 1)

MISO(Data Input)

SCK(CPOL = 0)

MSB LSB

LSBMSB

MISO(Data Output)

SCK(CPOL = 1)

MOSI(Data Input)

SCK(CPOL = 0)

MSB LSB

LSBMSB

1213 14

Inputs005 VCC

(2) ndash V

20 + 01Cb(3)(2) 300 ns

VILmax

10 pF lt Cb lt 400 pF(3) 20 + 01Cb(3)(2) 250 ns

Filter0 50(2) ns

kHz)(5)0 400 kHz

tSUSTA

- 35 7 LSB

- 05 35 LSB

- 025 1 LSB

-5 2 5 LSB

-5 -25 0 LSB

XTAL1 tXHXL

tDVXH tXLDX

RDYBSY

PAGEL tPHPL

tPLBXtBVPH

tWLBXtBVWL

tPLXHXLXHt tXLPH

00 01 02 03 04 05 06 07 08 09 10Frequency [MHz]

Vcc [V]2733445555

0 2 4 6 8 10 12 14 16Frequency [MHz]

Vcc [V]2736445555

25 30 35 40 45 50 55Vcc [V]

00 01 02 03 04 05 06 07 08 09 10Frequency [MHz]

Vcc [V]27445555

0 2 4 6 8 10 12 14 16Frequency [MHz]

Vcc [V]2736445555

25 30 35 40 45 50 55Vcc [V]

PRUSART0 281 1109

PRTWI 442 1692

PRTIM2 386 140

PRTIM1 229 888

PRTIM0 116 452

PRSPI 383 1598

PRADC 443 16511

PRTIM4 282 955

PRTIM3 471 1641

PRSPI1 40 1579

PRPTC 278 1082

25 30 35 40 45 50 55Vcc [V]

00 03 06 09 12 15 18 21 24 27Vop [V]

00 05 10 15 20 25 30 35 40 45 50Vop [V]

00 03 06 09 12 15 18 21 24 27Vreset [V]

00 05 10 15 20 25 30 35 40 45 50Vreset [V]

0 4 8 12 16 20IOH [mA]

0 4 8 12 16 20IOL [mA]

25 30 35 40 45 50 55Vcc [V]

RiseFall01

25 30 35 40 45 50 55Vcc [V]

Vcc [V]273355

-05 00 05 10 15 20 25 30

CMV [V]

-05 00 05 10 15 20 25 30 35 40 45 50

CMV [V]

Vcc [V]2733555

25 30 35 40 45 50 55Vcc [V]

Vcc [V]273345555

0 32 64 96 128 160 192 224 256OSCCAL [x1]

25 30 35 40 45 50 55Vcc [V]

25 30 35 40 45 50 55

Vcc [V]

25 30 35 40 45 50 55Vcc [V]

0005101520253035404550556065707580

25 30 35 40 45 50 55Vcc [V]

00 01 02 03 04 05 06 07 08 09 10Frequency [MHz]

Vcc [V]33445555

0 2 4 6 8 10 12 14 16Frequency [MHz]

Vcc [V]2736445555

25 30 35 40 45 50 55Vcc [V]

36 Register Summary

Offset Name Bit Pos

Reserved

0x3A Reserved

158 EEAR[98]

0x46 TCNT0 70 TCNT0[70]

0x47 OCR0A 70 OCR0A[70]

0x48 OCR0B 70 OCR0B[70]

0x49 Reserved

0x4F Reserved

Offset Name Bit Pos

0x52 Reserved

0x56 Reserved

Reserved

158 SP11 SP10 SP9 SP8

0x63 Reserved

0x65 Reserved

0x67 Reserved

0x69 EICRA 70 ISC1 [10] ISC0 [10]

0x6A Reserved

Reserved

158 ADC[98]

158 ADC[92]

0x7D Reserved

Offset Name Bit Pos

0x83 Reserved

0x84TCNT1L and

TCNT1H

70 TCNT1[70]

158 TCNT1[158]

158 ICR1[158]

0x88OCR1AL and

OCR1AH

70 OCR1A[70]

158 OCR1A[158]

0x8AOCR1BL and

OCR1BH

70 OCR1B[70]

158 OCR1B[158]

Reserved

0x93 Reserved

0x94TCNT3L and

TCNT3H

70 TCNT3[70]

158 TCNT3[158]

158 ICR3[158]

0x98OCR3AL and

OCR3AH

70 OCR3A[70]

158 OCR3A[158]

0x9AOCR3BL and

OCR3BH

70 OCR3B[70]

158 OCR3B[158]

Reserved

0xA3 Reserved

0xA4TCNT4L and

TCNT4H

70 TCNT4[70]

158 TCNT4[158]

158 ICR4[158]

0xA8OCR4AL and

OCR4AH

70 OCR4A[70]

158 OCR4A[158]

0xAAOCR4BL and

OCR4BH

70 OCR4B[70]

158 OCR4B[158]

0xAF Reserved

Offset Name Bit Pos

0xB5 Reserved

0xB7 Reserved

Reserved

UDORDn

UCSZn0

UCPHAnUCPOLn

0xC3 Reserved

0xC4UBRR0L and

UBRR0H

70 UBRRL[70]

158 UBRRL[118]

UDORDn

UCSZn0

UCPHAnUCPOLn

0xCB Reserved

0xCCUBRR1L and

UBRR1H

70 UBRRL[70]

158 UBRRL[118]

Reserved

BRANCH INSTRUCTIONS

381 32-Pin TQFP

382 32-Pin VQFN

21ZBS A

062416

1Notes

Seating PlaneC

Top View

Bottom View

Side View

PIN 1 Corner

A 080 085 090A1 000 0035A2 065A3 0203 REFDE 500 BSC

D2E2 35 36L 035 040

R 010 0125 015

b 020 025e 05 BSC

0100ddd0100eee

030 2S 004

ccc Cbbb C

eee C A B

PIN 1 ID

ddd M C A B

nX bnX L

Drawings not scaled

aaa C B

39 Errata

Customer Support

Legal Notice

Trademarks

ISBN 978-1-5224-3311-8

Introduction

Features

Table of Contents

1 Description

4 Block Diagram

51 Pin Descriptions

511 VCC

512 GND


514 Port C (PC[50])

515 PC6RESET

516 Port D (PD[70])

517 Port E (PE[30])

518 AVCC

519 AREF


6 IO Multiplexing


8 Resources


10 AVR CPU Core

101 Overview


103 Status Register




105 Stack Pointer





11 AVR Memories

111 Overview







115 IO Memory


















122 Clock Sources








127 External Clock








131 Overview

132 Features

133 Operations

134 Timing Diagram




141 Overview

142 Sleep Modes

143 BOD Disable

144 Idle Mode


146 Power-Down Mode

147 Power-Save Mode

148 Standby Mode









14116 Port Pins








152 Reset Sources

153 Power-on Reset

154 External Reset





158 Watchdog Timer

1581 Features

1582 Overview




16 INT- Interrupts

















18 IO-Ports

181 Overview




























191 Features

192 Overview

1921 Definitions

1922 Registers


194 Counter Unit








1971 Normal Mode


1973 Fast PWM Mode













201 Features

202 Overview

2021 Definitions

2022 Registers



205 Counter Unit



2062 Noise Canceler






2091 Normal Mode


2093 Fast PWM Mode


































212 Prescaler Reset





221 Features

222 Overview

2221 Definitions

2222 Registers


224 Counter Unit








2271 Normal Mode


2273 Fast PWM Mode
















231 Overview

232 Description

2321 Timing Example


241 Features

242 Overview


2431 Slave Mode

2432 Master Mode

244 Data Modes









251 Features

252 Overview

253 Block Diagram




2543 External Clock


255 Frame Formats














2585 Parity Checker









25101 Using MPCMn









261 Features

262 Overview



265 Frame Formats


266 Data Transfer






271 Features
















2755 Control Unit

276 Using the TWI

















281 Overview






291 Features

292 Overview



















301 Features

302 Overview

303 Block Diagram



3051 IO Lines





311 Features

312 Overview







321 Features

322 Overview





























332 Fuse Bits


333 Signature Bytes


335 Serial Number


33511 Device ID n



336 Page Size


3371 Signal Names




3383 Chip Erase






















344 Speed Grades















355 Pin Pull-Up



358 BOD Threshold





36 Register Summary



381 32-Pin TQFP

382 32-Pin VQFN

39 Errata

391 Rev A

392 Rev C - D

393 Rev A - D

40 Revision History



Customer Support


Legal Notice

Trademarks



Table of Contents

Introduction1

Features 1

1 Description10

4 Block Diagram 13

6 IO Multiplexing18

8 Resources 21

18 IO-Ports 100

Legal Notice458

Trademarks 458

Pin count 32

Flash (KB) 32

SRAM (KB) 2

EEPROM (KB) 1

TWI (I2C) 2

USART 2

ADC 10-bit 15 ksps

ADC channels 8

PWM channels 10

PTC Available

Package Type

USART 0

ADCADC[70]AREF

RxD0TxD0XCK0

MISO1MOSI1SCK1SS1

IOPORTS

DATABUS

GPIOR[20]

EXTINT

FLASHNVM

programming

debugWire

DATABUS

TC 0(8-bit)

ACAIN0AIN1ACO

EEPROM

EEPROMIF

PTCX[150]Y[230]

TC 1(16-bit)

OC1ABT1

TC 3(16-bit)

TC 4(16-bit)

OC3ABT3

OC4ABT4

TC 2(8-bit async)

SDA0SCL0

SDA1SCL1

USART 1RxD1TxD1XCK1

InternalReference

Watchdog Timer

Power management

and clock control

Calib RC

128kHz int osc

32768kHz XOSC

External clock

XTAL2 TOSC2

XTAL1 TOSC1

16MHz LP XOSC

PCINT[270]INT[10]

T0OC0AOC0B

MISO0MOSI0SCK0SS0

OC2AOC2B

PB[70]PC[6 0]PD[70]PE[30]

PE[32] PC[50]AREF

PE[30] PD[70] PC[60] PB[70]PD3 PD2

PB1 PB2PD5PB0

PB3PD3

PD0 PD2PE3PE2

PD1 PD2PE1PE0

PD0PD1PD4

PC0PE3PC1PE2

PC4PC5

PE0PE1

PB4PB3PB5

PD4PD6PD5

PB4PB3PB5PB2

SPIPROG

PARPROG

PD6PD7PE0

32 31 30 29 28 27 265

9 10 11 12 13 14 15 16

PC0 (ADC0PTCYMISO1)

PC1 (ADC1PTCYSCK1)

(XCK0T0PTCXY) PD4

(SCL1T4PTCXY) PE1

(XTAL1TOSC1) PB6

(XTAL2TOSC2) PB7

(OC2BINT1PTCXY) PD3

Ground

Programmingdebug

Digital

Analog

CrystalCLK

PB5 (PTCXYXCK1SCK0)

32 31 30 29 28 27 26

9 10 11 12 13 14 15 16

PC0 (ADC0PTCYMISO1)

PC1 (ADC1PTCYSCK1)

(XCK0T0PTCXY) PD4

(SCL1T4PTCXY) PE1

(XTAL1TOSC1) PB6

(XTAL2TOSC2) PB7

(OC2BINT1PTCXY) PD3

PB5 (PTCXYXCK1SCK0)

51 Pin Descriptions

512 GNDGround

518 AVCC

18 AVCC

20 AREF

21 GND

10 AVR CPU Core

Register file

Program counter

Instruction decode

Data memory

ALUStatus register

Stack pointer

Bit 7 6 5 4 3 2 1 0 I T H S V N Z C

R0 0x00

R1 0x01

R2 0x02

hellip

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

hellip

X-register 7 0 7 0

R27 R26

15 YH YL 0

Y-register 7 0 7 0

R29 R28

15 ZH ZL 0

Z-register 7 0 7 0

R31 R30

Bit 15 14 13 12 11 10 9 8 SP11 SP10 SP9 SP8

T1 T2 T3 T4

Result Write Back

T1 T2 T3 T4

clkCPU

C Code Example(1)

11 AVR Memories

0x0000

0x3FFF

Program Memory

Boot Flash Section

0x0000 ndash 0x001F

0x0100

0x08FF

64 IO registers

32 registers

0x0020 ndash 0x005F

0x0060 ndash 0x00FF

0x0000 ndash 0x001F

T1 T2 T3

Compute Address

Bit 15 14 13 12 11 10 9 8 EEAR[98]

Bit 7 6 5 4 3 2 1 0 EEAR[70]

Bit 7 6 5 4 3 2 1 0 EEDR[70]

01 18ms Erase Only

10 18ms Write Only

C Code Example(1)

Bit 7 6 5 4 3 2 1 0 GPIOR2[70]

Bit 7 6 5 4 3 2 1 0 GPIOR1[70]

Bit 7 6 5 4 3 2 1 0 GPIOR0[70]

EEPROM

WatchdogTimer

ClockMultiplexer

Watchdog Oscillator

Oscillator

clkASY

clkCPU

Reset Logic

clkFLASH

clkADC

Watchdog clock

clkSYS

clkPTC

External Clock 0000

Reserved 0001

0ms 0ms

4 ms 43 ms

65 ms 69 ms

04 - 09 100(3) ndash

09 - 30 101 12 - 22

30 - 80 110 12 - 22

80 - 160 111 12 - 22

CKSEL0 SUT[10]

258 CK 19CK + 4 ms(1) 0 00

258 CK 19CK + 65 ms(1) 0 01

1K CK 19CK(2) 0 10

1K CK 19CK + 4 ms(2) 0 11

1K CK 19CK + 65 ms(2) 1 00

16K CK 19CK + 4 ms 1 10

16K CK 19CK + 65 ms 1 11

125 30

11 Reserved

Recommended Usage

0100(1) 1K CK

76 - 84 0010(2)

Reserved 11

128 kHz 0011

Reserved 11

Frequency CKSEL[30]

0 - 16 MHz 0000

EXTERNALCLOCKSIGNAL

EXTCLK

SUT[10]

Reserved 11

Bit 7 6 5 4 3 2 1 0 CAL [70]

Bit 7 6 5 4 3 2 1 0 CLKPCE CLKPS [30]

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

External Clock

System clock

XOSC CKSEL

XOSC Failed

WDT 128kHz CLK

XOSC(External CLK

128kHz

RC clock

Ext clock

Sys clock

Xosc failed

Delayed xosc failed

ch Tim

Bit 7 6 5 4 3 2 1 0 SM[20] SE

SM[20] Sleep Mode

000 Idle

010 Power-down

011 Power-save

100 Reserved

101 Reserved

110 Standby(1)

C Code Example

Delay Counters

CKSEL[30]

CKTIMEOUT

DATA BUS

ClockGenerator

SPIKEFILTER

Pull-up Resistor

WatchdogOscillator

SUT[10]

RSTDISBL

TIME-OUT

INTERNALRESET

TIME-OUT

INTERNALRESET

TIME-OUT

INTERNALRESET

VBOT-VBOT+

MCU RESET

INTERRUPT

128 kHzOSCILLATOR

C Code Example

1 0 0 Stopped None

0 0 0 0 2K (2048) 16 ms

0 0 0 1 4K (4096) 32 ms

0 0 1 0 8K (8192) 64 ms

0 0 1 1 16K (16384) 0125s

0 1 0 0 32K (32768) 025s

0 1 0 1 64K (65536) 05s

0 1 1 0 128K (131072) 10s

0 1 1 1 256K (262144) 20s

1 0 0 0 512K (524288) 40s

1 0 0 1 1024K (1048576) 80s

1 0 1 0 Reserved

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

In general

C Code Example

D Q D Q

PCINT[i]pin

D Q D Q D Q

7PCIFn

(interruptflag)

PCINT[i] pin

pin_lat

pin_sync

pcint_in[i]

pcint_syn

pcint_setflag

Bit 7 6 5 4 3 2 1 0 ISC1 [10] ISC0 [10]

Bit 7 6 5 4 3 2 1 0 INT1 INT0

Bit 7 6 5 4 3 2 1 0 INTF1 INTF0

Bit 7 6 5 4 3 2 1 0 PCINT[2724]

Bit 7 6 5 4 3 2 1 0 PCINT[2316]

Bit 7 6 5 4 3 2 1 0 PCINT[148]

Bit 7 6 5 4 3 2 1 0 PCINT[70]

18 IO-Ports

Details

SYNCHRONIZER

WDx WRITE DDRx

PUD PULLUP DISABLE

clkIO IO CLOCK

RDx READ DDRx

PORTxn

SLEEP SLEEP CONTROL

IO Pull-up Comment

XXX in r17 PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

SYSTEM CLK

tpd max

tpd min

0x00 0xFF

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

r17tpd

RRxWRx

SYNCHRONIZER

WDx WRITE DDRx

RPx READ PORTx PIN

PUD PULLUP DISABLE

clkIO IO CLOCK

RDx READ DDRx

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

PORTxn

1DIEOVxn

WPx WRITE PINx

SignalName

PB5SCK0XCK0PCINT5

PB4MISO0RXD1PCINT4

DDOV 0 0 0 0

SCK0 INPUT

Signal Name

DDOV 0 0 0 0

OC1B OC1A 0

DIEOV 1 1 1 1

PCINT2 INPUT

SPI0 SS

ICP1 INPUT

source

SignalName

PVOE 0 TWEN0 TWEN0

PVOV 0 0 0

SignalName

PC3ADC3PCINT11

PC2ADC2PCINT10

PC1ADC1SCK1PCINT9

PC0ADC0MISO1PCINT8

DDOV 0 0 0 0

SignalName

PC3ADC3PCINT11

PC2ADC2PCINT10

PC1ADC1SCK1PCINT9

PC0ADC0MISO1PCINT8

SignalName

PD7AIN1PCINT23

PD6AIN0OC0APCINT22

PD5T1OC0BPCINT21

PD4XCK0T0PCINT20

PUOE 0 0 0 0

PUO 0 0 0 0

DDOE 0 0 0 0

DDOV 0 0 0 0

DIEOV 1 1 1 1

SignalName

PD3OC2BINT1PCINT19

PD1TXD0OC4APCINT17

PD0OC3ARXD0PCINT16

DDOV 0 0 1 0

DIEOV 1 1 1 1

PCINT27

PCINT26

PCINT25

PCINT24

source

SignalName

PE1T4SCL1PCINT25

DDOV 0 0 0 0

C Code Example

Clock Select

TimerCounter

WaveformGeneration

FixedTOP

Control Logic

TOP BOTTOM

Direction

TOVn(IntReq)

OCnA(IntReq)

OCnB(IntReq)

TCCRnA TCCRnB

TnEdgeDetector

( From Prescaler )

DATA BUS

TCNTn Control Logic

TOVn(IntReq)

Clock Select

TnEdgeDetector

( From Prescaler )

bottom

direction

OCFnx (IntReq)

DATA BUS

WGMn[10]

Waveform Generator

COMnx[10]

bottom

OCnxPinOCnx

COMnx[1]COMnx[0]

1Period 2 3

(COMnx[10] = 0x2)

(COMnx[10] = 0x3)

4 5 6 7

Period

(COMnx[10] = 2)

(COMnx[10] = 3)

OCRnx Update

clkTn(clkIO1)

clkTn(clkIO8)

OCRnx Value

clkTn(clkIO8)

TCNTn(CTC)

clkTn(clkIO8)

Bit 7 6 5 4 3 2 1 0 COM0A[10] COM0B [10] WGM0[10]

0 1 Reserved

Bit 7 6 5 4 3 2 1 0 TCNT0[70]

Bit 7 6 5 4 3 2 1 0 OCR0A[70]

Bit 7 6 5 4 3 2 1 0 OCR0B[70]

Bit 7 6 5 4 3 2 1 0 OCF0B OCF0A TOV0

TEMP (8-bit)

DATA BUS (8-bit)

Direction

TOVn(IntReq)

Clock Select

TOP BOTTOM

TnEdgeDetector

( From Prescaler )

ICFn (IntReq)

AnalogComparator

ICRnH (8-bit)

NoiseCanceler

EdgeDetector

TEMP (8-bit)

DATA BUS (8-bit)

ICRnL (8-bit)

ACIC ICNC ICESACO

OCnxPinOCnx

COMnx[1]COMnx[0]

OCFnx (IntReq)

OCRnxH Buf (8-bit)

TEMP (8-bit)

DATA BUS (8-bit)

OCRnxL Buf (8-bit)

COMnx[10]WGMn[30]

BOTTOM

OCnA(Toggle)

1 4Period 2 3

(COMnA[10] = 0x1)

1 7Period 2 3 4 5 6 8

(COMnx[10] = 0x2)

(COMnx[10] = 0x3)

1 2 3 4

Period

(COMnx[10]] = 0x2)

(COMnx[10] = 0x3)

1 2 3 4

Period

(COMnx[10] = 0x2)

(COMnx[10] = 0x3)

clkTn(clkIO1)

OCRnx Value

clkTn(clkIO8)

as TOP)

TCNTn(CTC and FPWM)

clkTn(clkIO1)

as TOP)

TCNTn(CTC and FPWM)

clkTn(clkIO8)

Bit 7 6 5 4 3 2 1 0 COM1A[10] COM1B[10] WGM1[10]

COM1A[1]COM1B[1]

COM1A[0]COM1B[0]

Description

COM1A[1]COM1B[1]

COM1A[0]COM1B[0]

Description

COM1A[1]COM1B[1]

COM1A[0]COM1B[0]

Description

COM1A[1]COM1B[1]

COM1A[0]COM1B[0]

Description

(CTC1)(1)WGM1[1]

(PWM1[1])(1)WGM1[0]

(PWM1[0])(1)Timer

Counter

Mode ofOperation

TOP Update of

OCR1x at

TOV1 Flag

Set on

(CTC1)(1)WGM1[1]

(PWM1[1])(1)WGM1[0]

(PWM1[0])(1)Timer

Counter

Mode ofOperation

TOP Update of

OCR1x at

TOV1 Flag

Set on

0x01FF TOP BOTTOM

0x03FF TOP BOTTOM

0x01FF BOTTOM TOP

0x03FF BOTTOM TOP

Correct

ICR1 BOTTOM BOTTOM

Correct

OCR1A BOTTOM BOTTOM

ICR1 TOP BOTTOM

OCR1A TOP BOTTOM

Bit 7 6 5 4 3 2 1 0 FOC1A FOC1B

Bit 15 14 13 12 11 10 9 8 TCNT1[158]

Bit 7 6 5 4 3 2 1 0 TCNT1[70]

Bit 15 14 13 12 11 10 9 8 ICR1[158]

Bit 7 6 5 4 3 2 1 0 ICR1[70]

Bit 15 14 13 12 11 10 9 8 OCR1A[158]

Bit 7 6 5 4 3 2 1 0 OCR1A[70]

Bit 15 14 13 12 11 10 9 8 OCR1B[158]

Bit 7 6 5 4 3 2 1 0 OCR1B[70]

Bit 7 6 5 4 3 2 1 0 COM3A[10] COM3B[10] WGM3[10]

COM3A[1]COM3B[1]

COM3A[0]COM3B[0]

Description

COM3A[1]COM3B[1]

COM3A0COM3B[0]

Description

COM3A[1]COM3B[1]

COM3A[0]COM3B[0]

Description

(CTC1)(1)WGM3[1]

(PWM1[1])(1)WGM3[0]

(PWM1[0])(1)Timer

Counter

Mode ofOperation

TOP Update of

OCR1x at

TOV1 Flag

Set on

0x01FF TOP BOTTOM

0x03FF TOP BOTTOM

0x01FF BOTTOM TOP

0x03FF BOTTOM TOP

Correct

ICR1 BOTTOM BOTTOM

Correct

OCR3A BOTTOM BOTTOM

ICR3 TOP BOTTOM

OCR3A TOP BOTTOM

Bit 7 6 5 4 3 2 1 0 FOC3A FOC3B

Bit 15 14 13 12 11 10 9 8 TCNT3[158]

Bit 7 6 5 4 3 2 1 0 TCNT3[70]

Bit 15 14 13 12 11 10 9 8 ICR3[158]

Bit 7 6 5 4 3 2 1 0 ICR3[70]

Bit 15 14 13 12 11 10 9 8 OCR3A[158]

Bit 7 6 5 4 3 2 1 0 OCR3A[70]

Bit 15 14 13 12 11 10 9 8 OCR3B[158]

Bit 7 6 5 4 3 2 1 0 OCR3B[70]

Bit 7 6 5 4 3 2 1 0 COM4A[10] COM4B[10] WGM4[10]

COM4A[1]COM4B[1]

COM4A[0]COM4B[0]

Description

COM4A[1]COM4B[1]

COM4A[0]COM4B[0]

Description

COM4A[1]COM4B[1]

COM4A[0]COM4B[0]

Description

(CTC1)(1)WGM4[1]

(PWM1[1])(1)WGM4[0]

(PWM1[0])(1)Timer

Counter

Mode ofOperation

TOP Update of

OCR4x at

TOV1 Flag

Set on

0x01FF TOP BOTTOM

0x03FF TOP BOTTOM

0x01FF BOTTOM TOP

0x03FF BOTTOM TOP

Correct

ICR4 BOTTOM BOTTOM

Correct

OCR4A BOTTOM BOTTOM

ICR4 TOP BOTTOM

OCR4A TOP BOTTOM

Bit 7 6 5 4 3 2 1 0 FOC4A FOC4B

Bit 15 14 13 12 11 10 9 8 TCNT4[158]

Bit 7 6 5 4 3 2 1 0 TCNT4[70]

Bit 15 14 13 12 11 10 9 8 ICR4[158]

Bit 7 6 5 4 3 2 1 0 ICR4[70]

Bit 15 14 13 12 11 10 9 8 OCR4A[158]

Bit 7 6 5 4 3 2 1 0 OCR4A[70]

Bit 15 14 13 12 11 10 9 8 OCR4B[158]

Bit 7 6 5 4 3 2 1 0 OCR4B[70]

D QD Q

clk IO

CSn0CSn1CSn2

Synchronization

10-BIT TC PRESCALER

clk IO

Clock Select

TimerCounter

WaveformGeneration

FixedTOP

Control Logic

TOP BOTTOM

Direction

TOVn(IntReq)

OCnA(IntReq)

OCnB(IntReq)

TCCRnA TCCRnB

TnEdgeDetector

( From Prescaler )

DATA BUS

TCNTn Control Logic

TOVn(IntReq)

topbottom

direction

TCOscillator

Prescaler

clk Tnclear

OCFnx (IntReq)

DATA BUS

WGMn[10]

Waveform Generator

COMnx[10]

bottom

OCnxPinOCnx

COMnx[1]COMnx[0]

1Period 2 3

(COMnx[10] = 0x2)

(COMnx[10] = 0x3)

4 5 6 7

Period

(COMnx[10] = 2)

(COMnx[10] = 3)

OCRnx Update

clkTn(clkIO1)

clkTn(clkIO8)

OCRnx Value

clkTn(clkIO8)

TCNTn(CTC)

clkTn(clkIO8)

10-BIT TC PRESCALER

IO clkT2S

TOSC1cl

clk T2

0PSRASY

CS20CS21CS22

Bit 7 6 5 4 3 2 1 0 COM2A [10] COM2B [10] WGM2 [10]

0 1 Reserved

Mode ofOperation

TOV Flag Seton(1)

Bit 7 6 5 4 3 2 1 0 TCNT2[70]

Bit 7 6 5 4 3 2 1 0 OCR2A[70]

Bit 7 6 5 4 3 2 1 0 OCR2B[70]

Bit 7 6 5 4 3 2 1 0 OCF2B OCF2A TOV2

OC3B OC4B PD2

TimerCounter 3

TimerCounter 4 OC4B

COM3B0COM3B1

COM4B0COM4B1

RPORTD2 DDRD2

OC4B(CTC Mode)

OC3B(FPWM Mode)

PD2(PORTD2 = 0)

PD2(PORTD2 = 1)

(Period) 3

clk IO

DIVIDER248163264128

SHIFTENABLE

C Code Example

return SPDR

Bit 1Bit 6

LSBMSB

SAMPLE IMOSIMISO

MSBLSB

Bit 6Bit 1

Bit 5Bit 2

Bit 4Bit 3

Bit 3Bit 4

Bit 2Bit 5

SAMPLE IMOSIMISO

MSBLSB

Bit 6Bit 1

Bit 5Bit 2

Bit 4Bit 3

Bit 3Bit 4

Bit 2Bit 5

Bit 1Bit 6

LSBMSB

0 Rising Falling

1 Falling Rising

0 Sample Setup

1 Setup Sample

0 0 0 fosc4

0 0 1 fosc16

0 1 0 fosc64

0 1 1 fosc128

1 0 0 fosc2

1 0 1 fosc8

1 1 0 fosc32

1 1 1 fosc64

0 Rising Falling

1 Falling Rising

0 Sample Setup

1 Setup Sample

0 0 0 fosc4

0 0 1 fosc16

0 1 0 fosc64

0 1 1 fosc128

1 0 0 fosc2

1 0 1 fosc8

1 1 0 fosc32

1 1 1 fosc64

Bit 7 6 5 4 3 2 1 0 SPID[70]

Bit 7 6 5 4 3 2 1 0 SPID1[70]

PARITYGENERATOR

UBRRn [HL]

UDRn(Transmit)

BAUD RATE GENERATOR

TxDnPINCONTROL

UDRn (Receive)

PINCONTROL

DATARECOVERY

CLOCKRECOVERY

PINCONTROL

TXCONTROL

RXCONTROL

PARITYCHECKER

SYNC LOGIC

Clock Generator

Transmitter

Receiver

UBRRn+1

SyncRegister

XCKnPin

UMSELn

DDR_XCKn

DDR_XCKnrxclk

Detector

UCPOLn

Signal description

RxDn TxDn

XCKn UCPOL = 0

UCPOL = 1

Sample

second stop bit

C Code Example

in r16 UDR0 ret

C Code Example

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2

STARTIDLE

1 2 3 4 5 6 7 8 1 20

Sample(U2X = 0)

Sample(U2X = 1)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1

1 2 3 4 5 6 7 8 1

Sample(U2X = 0)

Sample(U2X = 1)

1 2 3 4 5 6 7 8 9 10 01 01 01

STOP 1

1 2 3 4 5 6 01

Sample(U2X = 0)

Sample(U2X = 1)

(A) (B) (C)

D (Data+Parity Bit)

5 9320 10667 +667-68 plusmn30

6 9412 10579 +579-588 plusmn25

7 9481 10511 +511-519 plusmn20

8 9536 10458 +458-454 plusmn20

9 9581 10414 +414-419 plusmn15

10 9617 10378 +378-383 plusmn15

D (Data+Parity Bit)

5 9412 10566 +566-588 plusmn25

6 9492 10492 +492-508 plusmn20

7 9552 10435 +435-448 plusmn15

8 9600 10390 +390-400 plusmn15

9 9639 10353 +353-361 plusmn15

10 9670 10323 +323-330 plusmn10

5 6 7 8 9 10

0 - 288 kbps +667-588

+579-508

+511-448

+458-400

+414-361

+378-330

384 kbps +663-588

+575-508

+508-448

+455-400

+412-361

+376-330

576 kbps +610-588

+530-508

+469-448

+420-400

+380-361

+347-330

768 kbps +559-588

+485-508

+429-448

+385-400

+348-361

+318-330

1152 kbps +457-588

+397-508

+351-448

+315-400

+286-361

+261-330

5 6 7 8 9 10

0 - 576 kbps +566-400

+492-345

+435-303

+390-270

+353-244

+323-222

768 kbps +559-400

+485-345

+429-303

+385-270

+348-244

+318-222

1152 kbps +457-400

+397-345

+351-303

+315-270

+286-244

+261-222

BaudRate[bps]

2400 25 02 51 02 47 00 95 00 51 02 103 02

4800 12 02 25 02 23 00 47 00 25 02 51 02

9600 6 -70 12 02 11 00 23 00 12 02 25 02

144k 3 85 8 -35 7 00 15 00 8 -35 16 21

192k 2 85 6 -70 5 00 11 00 6 -70 12 02

288k 1 85 3 85 3 00 7 00 3 85 8 -35

384k 1 -186 2 85 2 00 5 00 2 85 6 -70

576k 0 85 1 85 1 00 3 00 1 85 3 85

768k ndash ndash 1 -186 1 -250 2 00 1 -186 2 85

1152k ndash ndash 0 85 0 00 1 00 0 85 1 85

Baud Rate[bps]

2400 95 00 191 00 103 02 207 02 191 00 383 00

4800 47 00 95 00 51 02 103 02 95 00 191 00

9600 23 00 47 00 25 02 51 02 47 00 95 00

144k 15 00 31 00 16 21 34 -08 31 00 63 00

192k 11 00 23 00 12 02 25 02 23 00 47 00

288k 7 00 15 00 8 -35 16 21 15 00 31 00

384k 5 00 11 00 6 -70 12 02 11 00 23 00

576k 3 00 7 00 3 85 8 -35 7 00 15 00

768k 2 00 5 00 2 85 6 -70 5 00 11 00

1152k 1 00 3 00 1 85 3 85 3 00 7 00

2304k 0 00 1 00 0 85 1 85 1 00 3 00

Baud Rate[bps]

250k 0 -78 1 -78 0 00 1 00 1 -78 3 -78

Baud Rate[bps]

2400 207 02 416 -01 287 00 575 00 383 00 767 00

4800 103 02 207 02 143 00 287 00 191 00 383 00

9600 51 02 103 02 71 00 143 00 95 00 191 00

144k 34 -08 68 06 47 00 95 00 63 00 127 00

192k 25 02 51 02 35 00 71 00 47 00 95 00

288k 16 21 34 -08 23 00 47 00 31 00 63 00

384k 12 02 25 02 17 00 35 00 23 00 47 00

576k 8 -35 16 21 11 00 23 00 15 00 31 00

768k 6 -70 12 02 8 00 17 00 11 00 23 00

1152k 3 85 8 -35 5 00 11 00 7 00 15 00

2304k 1 85 3 85 2 00 5 00 3 00 7 00

250k 1 00 3 00 2 -78 5 -78 3 -78 6 53

05M 0 00 1 00 ndash ndash 2 -78 1 -78 3 -78

U2Xn = 0 U2Xn = 1

2400 416 -01 832 00

4800 207 02 416 -01

9600 103 02 207 02

144k 68 06 138 -01

192k 51 02 103 02

288k 34 -08 68 06

384k 25 02 51 02

576k 16 21 34 -08

768k 12 02 25 02

1152k 8 -35 16 21

2304k 3 85 8 -35

250k 3 00 7 00

05M 1 00 3 00

1M 0 00 1 00

Bit 7 6 5 4 3 2 1 0 TXB RXB[70]

UDORDnUCSZn0 UCPHAn

UCPOLn

UMSEL[10] Mode

10 Reserved

enabled

UPM[10] ParityMode

00 Disabled

01 Reserved

USBS Stop Bit(s)

0 1-bit

1 2-bit

000 5-bit

001 6-bit

010 7-bit

011 8-bit

100 Reserved

101 Reserved

110 Reserved

111 9-bit

Bit 15 14 13 12 11 10 9 8 UBRRn[118]

Bit 7 6 5 4 3 2 1 0 UBRRn[70]

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

UCPOL=0 UCPOL=1

UBRRn = 0

Term Description

Data Change

ST AR T

1 2 7 8 9

AggregateSDA

SDA fromTransmitter

SDA fromReceiver

SCL fromMaster

1 2 7 8 9

Data Byte

SCL1 2 7 8 9

SLA+RW STOPSTART

SCL fromMaster A

SCL fromMaster B

SCL BusLine

TBlow TBhigh

SDA from Master A

SDA from Master B

SDA Line

Address Match Unit

Address Comparator

Control Unit

Slew-rateControl

SpikeFilter

ControlSpikeFilter

Bit Rate Generator

Prescaler

Bus Interface Unit

START STOPControl

Spike Suppression

Slew-rate

TWI bus

IndicatesTWINT set

S START condition

P STOP condition

SLA Slave Address

Device 1MASTER

TRANSMITTER

Device 2SLAVE

Status Code(TWSR)

PrescalerBits are 0

ToFromTWDR

To TWCRn

STA STO TWINT TWEA

Load SLA+Wor

Load databyte or

No TWDRaction or

No TWDRaction

Status Code(TWSR)

PrescalerBits are 0

ToFromTWDR

To TWCRn

STA STO TWINT TWEA

Load databyte or

No TWDRaction or

No TWDRaction

Load databyte or

No TWDRaction or

No TWDRaction

Load databyte or

No TWDRaction or

No TWDRaction

Status Code(TWSR)

PrescalerBits are 0

ToFromTWDR

To TWCRn

STA STO TWINT TWEA

No TWDRaction or

No TWDRaction

S SLA W A DATA A P

0x08 0x18 0x28

R SLA W

A or A

DATA A

Device 1MASTER

RECEIVER

Device 2SLAVE

Status Code(TWSRn)

Prescaler Bitsare 0

ToFromTWD

To TWCRn

STA STO TWINT TWEA

Status Code(TWSRn)

Prescaler Bitsare 0

ToFromTWD

To TWCRn

STA STO TWINT TWEA

No TWDRaction

Read databyte

S SLA R A A

0x08 0x40 0x50

A or A

0x38 0x38

0x68 0x78 0xB0

DATA A

DATA DATA

Device 3 Device n

Device 2MASTER

RECEIVER

Device 1SLA VE

TRANSMITTER

Status Code(TWSRb)

PrescalerBits are 0

ToFromTWDRn

To TWCRn

STA STO TWINT TWEA

Load databyte

No TWDRnaction

Status Code(TWSRb)

PrescalerBits are 0

ToFromTWDRn

To TWCRn

STA STO TWINT TWEA

No TWDRnaction

becomes free

S SLA R A A

0xA8 0xB8

P or S

DATA A

P or SAll 1s

DATA DATA

Device 3 Device n

Device 2MASTER

TRANSMITTER

Device 1SLAVE

RECEIVER

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

No TWDRnaction

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

Read databyte

becomes free

Read databyte

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

becomes free

Status Code(TWSR)

PrescalerBits are 0

TofromTWDRn

To TWCRn

STA STO TWINT TWEA

S SLA W A DATA A

0x60 0x80

P or SDATA A

0x80 0xA0

P or SA

A DATA A

0x70 0x90

P or SDATA A

0x90 0xA0

P or SA

General Call

DATA A

Status Code(TWSR)

Prescaler Bits are0

ToFromTWDRn

To TWCRn

STA STO TWINT TWEA

No TWDRnaction

Device 1MASTER

TRANSMITTER

Device 2MASTER

TRANSMITTER

Device 3SLAVE

RECEIVERDevice n

received

Direction

SLASTART Data STOP

ReadB0

Bit 7 6 5 4 3 2 1 0 TWBR [70]

Bit 7 6 5 4 3 2 1 0 TWA[60] TWGCE

Bit 7 6 5 4 3 2 1 0 TWD[70]

Bit 7 6 5 4 3 2 1 0 TWAM[60]

TWAMR0

AddressBit 0

AddressMatch

BANDGAPREFERENCE

ACMEADEN

INTERRUPT SELECT

ACIS1 ACIS0 ACIC

ANALOGCOMPARATORIRQ

0 x xxx AIN1

1 1 xxx AIN1

1 0 000 ADC0

1 0 001 ADC1

1 0 010 ADC2

1 0 011 ADC3

1 0 100 ADC4

1 0 101 ADC5

1 0 110 ADC6

1 0 111 ADC7

0 1 Reserved

Bit 7 6 5 4 3 2 1 0 AIN1D AIN0D

COMPLETE IRQ

8-BIT DATA BUS

15 0ADC MULTIPLEXER

CONVERSION LOGIC

10-BIT DAC+-

MUX DECODER

BANDGAP REFERENCE

PRESCALER

INPUT MUX

SOURCE 1

SOURCE n

ADTS[20]

CONVERSIONLOGIC

PRESCALER

START CLKADC

EDGEDETECTOR

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0ADPS1ADPS2

ResetADENSTART

LSB of Result

ADC Clock

Sample and Hold

Cycle Number

1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2

MUX and REFSUpdate

ConversionComplete

1 2 3 4 5 6 7 8 9 10 11 12 13

LSB of Result

ADC Clock

Cycle Number 1 2

ConversionComplete

MUX and REFSUpdate

1 2 3 4 5 6 7 8 9 10 11 12 13

LSB of Result

ADC Clock

TriggerSource

Cycle Number 1 2

PrescalerReset

Sample ampHold

MUX and REFSUpdate

11 12 13

LSB of Result

ADC Clock

Cycle Number 1 2

ConversionComplete

1100k ΩCSH = 14pF

IILVCC2

PC1 (ADC1)

PC0 (ADC0)

10 micro

VREF Input Voltage

Ideal ADC

Actual ADC

OffsetError

VREF Input Voltage

Ideal ADC

Actual ADC

GainError

VREF Input Voltage

Ideal ADC

Actual ADC

10 Reserved

0000 ADC0

0001 ADC1

0010 ADC2

0011 ADC3

0100 ADC4

0101 ADC5

0110 ADC6

0111 ADC7

1000 Reserved

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 11V (VBG)

1111 0V (GND)

100 16

101 32

110 64

111 128

Bit 15 14 13 12 11 10 9 8 ADC[98]

Bit 7 6 5 4 3 2 1 0 ADC[70]

Bit 15 14 13 12 11 10 9 8 ADC[92]

Bit 7 6 5 4 3 2 1 0 ADC[10]

Bit 7 6 5 4 3 2 1 0 ACME ADTS [20]

CompensationCircuit

RS IRQ

Result

X Line Driver

InputControl

CompensationCircuit

RS IRQ

Result

X Line Driver

InputControl

PTCModule

Cx0y0 Cx0y1 Cx0ym

Cx1y0 Cx1y1 Cx1ym

Cxny0 Cxny1 Cxnym

PTCModule

Link Application

QTouchLibrary

dW(RESET)

27 - 55V

Bit 7 6 5 4 3 2 1 0 DWDR[70]

The user can select

BLB0Mode

BLB1Mode

Bit 15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

PROGRAM MEMORY

Z - REGISTER

ZPAGEMSB

ZPCMSB

INSTRUCTION WORD

PAGEEND

PROGRAMCOUNTER

Bit 7 6 5 4 3 2 1 0

Max ProgrammingTime

32 ms 34 ms

org SMALLBOOTSTART

1 1 256words

4 0x0000 -0x3EFF

0x3F00 -0x3FFF

0x3EFF 0x3F00

1 0 512words

8 0x0000 -0x3DFF

0x3E00 -0x3FFF

0x3DFF 0x3E00

0 1 1024words

16 0x0000 -0x3BFF

0x3C00 -0x3FFF

0x3BFF 0x3C00

0 0 2048words

32 0x0000 -0x37FF

0x3800 -0x3FFF

0x37FF 0x3800

Description

LB Mode LB2 LB1

BLB0Mode

BLB02 BLB01

BLB1Mode

BLB12 BLB11

ndash 7 ndash 1

ndash 6 ndash 1

ndash 5 ndash 1

ndash 4 ndash 1

decoding

0 (programmed)(4)

0x000 0x001 0x002

Offset Name Bit Pos

0x03 Reserved

0x050x0D

Reserved

Offset Name Bit Pos

Offset 0x00 + n0x02 [n=02]

Reset [Device ID]

Property -

Bit 7 6 5 4 3 2 1 0

Reset 0 0 0 0 0 0 0 0

Name SIGROW_RCOC

Offset 0x01

Property -

Bit 7 6 5 4 3 2 1 0

Register RCOC[70]

Name SIGROW_SERNUMn

Property -

Bit 7 6 5 4 3 2 1 0

Register SERNUM[70]

PCPAGE PCMSB

64 words PC[50] 256 PC[136] 13

Device EEPROMSize

Page Size

PCWORD No of Pages

PCPAGE EEAMSB

PC[10]PB[50] DATA

RDYBSY

+45 - 55V

Pin Symbol Value

1 0 Load Command

1 1 No Action Idle

PROGRAM MEMORY

INSTRUCTION WORD

PAGEEND

PROGRAMCOUNTER

RDYBSY

RESET+12V

XX XX XX

RDYBSY

RESET+12V

A G B C E B C E L

RDYBSY

RESET +12V

0x40DATA DATA XX

A C0x40 DATA XX

0x40 DATA XX

Lock Bits 0

Fuse High Byte

Fuse Low Byte 0

Extended Fuse Byte

+27 - 55V

+27 - 55V (2)

Turn VCC power off

tWD_FLASH 26 ms

tWD_EEPROM 36 ms

tWD_ERASE 105 ms

tWD_FUSE 26 ms

the page range

Page N-1

Page Buffer

Bit 15 B 0

Adr MSB Adr LSB

Page Offset

Page Number

(MISO)

SAMPLE

SERIAL DATA OUTPUT

-05V to VCC+05V

VCC = 27V - 55V -05 03VCC(1) V

VCC = 27V - 55V 06VCC(2) VCC + 05 V

VCC = 27V - 55V -05 01VCC(1) V

VCC = 27V - 55V 07VCC(2) VCC + 05 V

VCC = 27V - 55V -05 01VCC(1) V

VCC = 27V - 55V 09VCC(2) VCC + 05 V

VCC = 27V - 55V -05 03VCC(1) V

VCC = 27V - 55V 06VCC(2) VCC + 05 V

VCC = 5V

TA=85degC 09

TA=105degC 10

IOL = 10 mA

VCC = 3V

TA=85degC 06

TA=105degC 07 V

VCC = 5V

TA=85degC 40

TA=105degC 39

IOH = 10 mA

VCC = 3V

TA=85degC 21

TA=105degC 20 V

VCC=5V

Vin = VCC2

-100 100 nA

400 ns

T = 25degC 15 μA

T = 85degC 21

T = 105degC 28

T = 85degC 38 8

T = 105degC 46 10

T = 85degC 07 2

T = 105degC 14 5

27V 45V 55V

Safe Operating Area

FactoryCalibration

plusmn1

Min Max Min Max

10 11 12 V

- 40 70 μs

- 10 - μA

111 BOD Disabled

101 25 27 29 V

100 41 43 45

Other Reserved

3 RiseFalltime

Master - 36 -

8 SCK to outhigh

Master - 10 -

11 SCK highlow(1)

12 RiseFalltime

Slave - - 1600

16 SCK to SShigh

Slave 20 - -

Slave - 10 -

18 SS low toSCK

MOSI(Data Output)

SCK(CPOL = 1)

MISO(Data Input)

SCK(CPOL = 0)

MSB LSB

LSBMSB

MISO(Data Output)

SCK(CPOL = 1)

MOSI(Data Input)

SCK(CPOL = 0)

MSB LSB

LSBMSB

1213 14

Inputs005 VCC

(2) ndash V

20 + 01Cb(3)(2) 300 ns

VILmax

10 pF lt Cb lt 400 pF(3) 20 + 01Cb(3)(2) 250 ns

Filter0 50(2) ns

kHz)(5)0 400 kHz

tSUSTA

- 35 7 LSB

- 05 35 LSB

- 025 1 LSB

-5 2 5 LSB

-5 -25 0 LSB

XTAL1 tXHXL

tDVXH tXLDX

RDYBSY

PAGEL tPHPL

tPLBXtBVPH

tWLBXtBVWL

tPLXHXLXHt tXLPH

00 01 02 03 04 05 06 07 08 09 10Frequency [MHz]

Vcc [V]2733445555

0 2 4 6 8 10 12 14 16Frequency [MHz]

Vcc [V]2736445555

25 30 35 40 45 50 55Vcc [V]

00 01 02 03 04 05 06 07 08 09 10Frequency [MHz]

Vcc [V]27445555

0 2 4 6 8 10 12 14 16Frequency [MHz]

Vcc [V]2736445555

25 30 35 40 45 50 55Vcc [V]

PRUSART0 281 1109

PRTWI 442 1692

PRTIM2 386 140

PRTIM1 229 888

PRTIM0 116 452

PRSPI 383 1598

PRADC 443 16511

PRTIM4 282 955

PRTIM3 471 1641

PRSPI1 40 1579

PRPTC 278 1082

25 30 35 40 45 50 55Vcc [V]

00 03 06 09 12 15 18 21 24 27Vop [V]

00 05 10 15 20 25 30 35 40 45 50Vop [V]

00 03 06 09 12 15 18 21 24 27Vreset [V]

00 05 10 15 20 25 30 35 40 45 50Vreset [V]

0 4 8 12 16 20IOH [mA]

0 4 8 12 16 20IOL [mA]

25 30 35 40 45 50 55Vcc [V]

RiseFall01

25 30 35 40 45 50 55Vcc [V]

Vcc [V]273355

-05 00 05 10 15 20 25 30

CMV [V]

-05 00 05 10 15 20 25 30 35 40 45 50

CMV [V]

Vcc [V]2733555

25 30 35 40 45 50 55Vcc [V]

Vcc [V]273345555

0 32 64 96 128 160 192 224 256OSCCAL [x1]

25 30 35 40 45 50 55Vcc [V]

25 30 35 40 45 50 55

Vcc [V]

25 30 35 40 45 50 55Vcc [V]

0005101520253035404550556065707580

25 30 35 40 45 50 55Vcc [V]

00 01 02 03 04 05 06 07 08 09 10Frequency [MHz]

Vcc [V]33445555

0 2 4 6 8 10 12 14 16Frequency [MHz]

Vcc [V]2736445555

25 30 35 40 45 50 55Vcc [V]

36 Register Summary

Offset Name Bit Pos

Reserved

0x3A Reserved

158 EEAR[98]

0x46 TCNT0 70 TCNT0[70]

0x47 OCR0A 70 OCR0A[70]

0x48 OCR0B 70 OCR0B[70]

0x49 Reserved

0x4F Reserved

Offset Name Bit Pos

0x52 Reserved

0x56 Reserved

Reserved

158 SP11 SP10 SP9 SP8

0x63 Reserved

0x65 Reserved

0x67 Reserved

0x69 EICRA 70 ISC1 [10] ISC0 [10]

0x6A Reserved

Reserved

158 ADC[98]

158 ADC[92]

0x7D Reserved

Offset Name Bit Pos

0x83 Reserved

0x84TCNT1L and

TCNT1H

70 TCNT1[70]

158 TCNT1[158]

158 ICR1[158]

0x88OCR1AL and

OCR1AH

70 OCR1A[70]

158 OCR1A[158]

0x8AOCR1BL and

OCR1BH

70 OCR1B[70]

158 OCR1B[158]

Reserved

0x93 Reserved

0x94TCNT3L and

TCNT3H

70 TCNT3[70]

158 TCNT3[158]

158 ICR3[158]

0x98OCR3AL and

OCR3AH

70 OCR3A[70]

158 OCR3A[158]

0x9AOCR3BL and

OCR3BH

70 OCR3B[70]

158 OCR3B[158]

Reserved

0xA3 Reserved

0xA4TCNT4L and

TCNT4H

70 TCNT4[70]

158 TCNT4[158]

158 ICR4[158]

0xA8OCR4AL and

OCR4AH

70 OCR4A[70]

158 OCR4A[158]

0xAAOCR4BL and

OCR4BH

70 OCR4B[70]

158 OCR4B[158]

0xAF Reserved

Offset Name Bit Pos

0xB5 Reserved

0xB7 Reserved

Reserved

UDORDn

UCSZn0

UCPHAnUCPOLn

0xC3 Reserved

0xC4UBRR0L and

UBRR0H

70 UBRRL[70]

158 UBRRL[118]

UDORDn

UCSZn0

UCPHAnUCPOLn

0xCB Reserved

0xCCUBRR1L and

UBRR1H

70 UBRRL[70]

158 UBRRL[118]

Reserved

BRANCH INSTRUCTIONS

381 32-Pin TQFP

382 32-Pin VQFN

21ZBS A

062416

1Notes

Seating PlaneC

Top View

Bottom View

Side View

PIN 1 Corner

A 080 085 090A1 000 0035A2 065A3 0203 REFDE 500 BSC

D2E2 35 36L 035 040

R 010 0125 015

b 020 025e 05 BSC

0100ddd0100eee

030 2S 004

ccc Cbbb C

eee C A B

PIN 1 ID

ddd M C A B

nX bnX L

Drawings not scaled

aaa C B

39 Errata

Customer Support

Legal Notice

Trademarks

ISBN 978-1-5224-3311-8

Introduction

Features

Table of Contents

1 Description

4 Block Diagram

51 Pin Descriptions

511 VCC

512 GND


514 Port C (PC[50])

515 PC6RESET

516 Port D (PD[70])

517 Port E (PE[30])

518 AVCC

519 AREF


6 IO Multiplexing


8 Resources


10 AVR CPU Core

101 Overview


103 Status Register




105 Stack Pointer





11 AVR Memories

111 Overview







115 IO Memory


















122 Clock Sources








127 External Clock








131 Overview

132 Features

133 Operations

134 Timing Diagram




141 Overview

142 Sleep Modes

143 BOD Disable

144 Idle Mode


146 Power-Down Mode

147 Power-Save Mode

148 Standby Mode









14116 Port Pins








152 Reset Sources

153 Power-on Reset

154 External Reset





158 Watchdog Timer

1581 Features

1582 Overview




16 INT- Interrupts

















18 IO-Ports

181 Overview




























191 Features

192 Overview

1921 Definitions

1922 Registers


194 Counter Unit








1971 Normal Mode


1973 Fast PWM Mode













201 Features

202 Overview

2021 Definitions

2022 Registers



205 Counter Unit



2062 Noise Canceler






2091 Normal Mode


2093 Fast PWM Mode


































212 Prescaler Reset





221 Features

222 Overview

2221 Definitions

2222 Registers


224 Counter Unit








2271 Normal Mode


2273 Fast PWM Mode
















231 Overview

232 Description

2321 Timing Example


241 Features

242 Overview


2431 Slave Mode

2432 Master Mode

244 Data Modes









251 Features

252 Overview

253 Block Diagram




2543 External Clock


255 Frame Formats














2585 Parity Checker









25101 Using MPCMn









261 Features

262 Overview



265 Frame Formats


266 Data Transfer






271 Features
















2755 Control Unit

276 Using the TWI

















281 Overview






291 Features

292 Overview



















301 Features

302 Overview

303 Block Diagram



3051 IO Lines





311 Features

312 Overview







321 Features

322 Overview





























332 Fuse Bits


333 Signature Bytes


335 Serial Number


33511 Device ID n



336 Page Size


3371 Signal Names




3383 Chip Erase






















344 Speed Grades















355 Pin Pull-Up



358 BOD Threshold





36 Register Summary



381 32-Pin TQFP

382 32-Pin VQFN

39 Errata

391 Rev A

392 Rev C - D

393 Rev A - D

40 Revision History



Customer Support


Legal Notice

Trademarks



Documents

ATmega328PB Automotive Complete - Microchip Technology · The ATmega328PB Automotive is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing