Atm Card Security System

7/31/2019 Atm Card Security System

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ATM CARD SYSTEM

Introduction

The microcontroller in the ATM machine asks for the confirmation from the user mobile. This usermobile can be changed whenever the user wishes to. As the details are received by the user in his

mobile, he has to send the confirmation message to the modem. Thus, the microcontroller receives

this message as the confirmation and allows the person to proceed with the further transactions.

Thus, the system does not give any scope for any malpractices that can take place in the ATM

centers. Even if the user ATM card is lost, the card cannot be misused by any other person because

as soon as the card is inserted into the ATM machine, the system sends the details of the card to

the user mobile and also asks for the confirmation from the user for the next step to forward. Thus,

the user can trace his ATM card very easily.

1.1 Objective of the project

The project aims at providing the security to the ATM card of the user. The project uses the

GSM technology and Embedded Systems to design this application. The main objective of this

project is to design a system that can provide the security to the ATM card of the user. This can be

accomplished by organizing the procedure of sending the message with the card details to the user

mobile whenever the card is inserted into the ATM machine by anyone and at any ATM center and

also asking for the confirmation from the user. The system does not respond to any of the keys

pressed by the user standing in front of the ATM machine unless it receives the confirmation

message (or unique code) from the user.

This project is a device that collects data whenever the card is inserted into the ATM machine

and sends the entire details like time of insertion, place of insertion, name of the card holder etc tothe user mobile. The system codes the data into a format that can be understood by the controlling

section. This system also collects information from the master device and implements commands

that are directed by the master.


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The objective of the project is to develop a microcontroller based security system. It consists

of a GSM modem, microcontroller, the interfacing unit to allow the communication between the

microcontroller and mobile, buzzer circuit, LCD, EEPROM based card.

1.2 Background of the Project

The software application and the hardware implementation help the microcontroller read

the data whenever the card is inserted into the ATM machine and send these details to the user

mobile and also ask for the confirmation from the user in order to proceed further. The system does

not allow any kind of operations to take place until it receives the confirmation from the user

mobile.

The Controlling unit has an application program to allow the microcontroller send the

details through the modem to the user mobile and display it on the LCD. The performance of the

design is maintained by controlling unit.

1.3 Organization of the Thesis

In view of the proposed thesis work explanation of theoretical aspects and algorithms used

in this work are presented as per the sequence described below.

Chapter 1 describes a brief review of the objectives and goals of the work.

Chapter 2 discusses the existing technologies and the study of various technologies in

detail.

Chapter 3 describes the Block diagram and its description. The construction and

description of various modules used for the application are described in detail.

Chapter 4 explains the Software tools required for the project, the Code developed for the

design.

Chapter 5 presents the results, overall conclusions of the study and proposes possible

improvements and directions of future research work.


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Chapter 2

Overview of the technologies used

Embedded Systems:

An embedded system can be defined as a computing device that does a specific focused job.

Appliances such as the air-conditioner, VCD player, DVD player, printer, fax machine, mobile

phone etc. are examples of embedded systems. Each of these appliances will have a processor and

special hardware to meet the specific requirement of the application along with the embedded

software that is executed by the processor for meeting that specific requirement.

The embedded software is also called firm ware. The desktop/laptop computer is a general

purpose computer. You can use it for a variety of applications such as playing games, word

processing, accounting, software development and so on.

In contrast, the software in the embedded systems is always fixed listed below:


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Embedded systems do a very specific task, they cannot be programmed to do different things. .

Embedded systems have very limited resources, particularly the memory. Generally, they do not

have secondary storage devices such as the CDROM or the floppy disk. Embedded systems have

to work against some deadlines. A specific job has to be completed within a specific time. In some

embedded systems, called real-time systems, the deadlines are stringent. Missing a deadline may

cause a catastrophe-loss of life or damage to property. Embedded systems are constrained for

power. As many embedded systems operate through a battery, the power consumption has to be

very low.

Some embedded systems have to operate in extreme environmental conditions such as very high

temperatures and humidity.

Following are the advantages of Embedded Systems:

1. They are designed to do a specific task and have real time performance constraints which

must be met.

2. They allow the system hardware to be simplified so costs are reduced.

3. They are usually in the form of small computerized parts in larger devices which serve a

general purpose.

4. The program instructions for embedded systems run with limited computer hardware

resources, little memory and small or even non-existent keyboard or screen.

Introduction: The Evolution of Mobile Telephone Systems

Cellular is one of the fastest growing and most demanding telecommunications applications.

Today, it represents a continuously increasing percentage of all new telephone subscriptions

around the world. Currently there are more than 45 million cellular subscribers worldwide, and

nearly 50 percent of those subscribers are located in the United States.

The concept of cellular service is the use of low power transmitters where frequencies can be

reused within a geographic area. The idea of cell based mobile radio service was formulated in the

United States at Bell Labs in the early 1970s. Cellular systems began in the United States with the

release of the advanced mobile phone service (AMPS) system in 1983. The AMPS standard was


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adopted by Asia, Latin America and Oceanic countries, creating the largest potential market in the

world for cellular.

In the early 1980s, most mobile telephone systems were analog rather than digital, like today's

newer systems. One challenge facing analog systems was the inability to handle the growing

capacity needs in a cost efficient manner. As a result, digital technology was welcomed.

The advantages of digital systems over analog systems include ease of signaling, lower levels of

interference, integration of transmission and switching and increased ability to meet capacity

demands. The table below shows the worldwide development of mobile telephone systems.


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Chapter 3

Hardware Implementation of the Project

This chapter briefly explains about the Hardware Implementation of the project. It discusses the

design and working of the design with the help of block diagram and circuit diagram and

explanation of circuit diagram in detail. It explains the features, timer programming, serial

communication, interrupts of AT89S52 microcontroller. It also explains the various modules used

in this project.

3.1 Project Design

The implementation of the project design can be divided in two parts.

Hardware implementation

Firmware implementation

Hardware implementation deals in drawing the schematic on the plane paper according to the

application, testing the schematic design over the breadboard using the various ICs to find if the

design meets the objective, carrying out the PCB layout of the schematic tested on breadboard,

finally preparing the board and testing the designed hardware.

The firmware part deals in programming the microcontroller so that it can control the operation of

the ICs used in the implementation. In the present work, we have used the Orcad design software

for PCB circuit design, the Keil v3 software development tool to write and compile the source


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code, which has been written in the C language. The Proload programmer has been used to write

this compile code into the microcontroller. The firmware implementation is explained in the next

chapter.

The project design and principle are explained in this chapter using the block diagram and circuit

diagram. The block diagram discusses about the required components of the design and working

condition is explained using circuit diagram and system wiring diagram.

3.1.1 Block Diagram of the Project and its Description

The block diagram of the design is as shown in Fig 3.1. It consists of power supply unit,

microcontroller, GSM modem, Serial communication unit, buzzer, EEPROM based card and LCD.

The brief description of each unit is explained as follows.

3.2 Power Supply:


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The input to the circuit is applied from the regulated power supply. The a.c. input i.e., 230V from

the mains supply is step down by the transformer to 12V and is fed to a rectifier. The output

obtained from the rectifier is a pulsating d.c voltage. So in order to get a pure d.c voltage, the

output voltage from the rectifier is fed to a filter to remove any a.c components present even after

rectification. Now, this voltage is given to a voltage regulator to obtain a pure constant dc voltage.

Transformer:

Usually, DC voltages are required to operate various electronic equipment and these

voltages are 5V, 9V or 12V. But these voltages cannot be obtained directly. Thus the a.c input

available at the mains supply i.e., 230V is to be brought down to the required voltage level. This is

done by a transformer. Thus, a step down transformer is employed to decrease the voltage to a

required level.

Rectifier:

The output from the transformer is fed to the rectifier. It converts A.C. into pulsating D.C.

The rectifier may be a half wave or a full wave rectifier. In this project, a bridge rectifier is usedbecause of its merits like good stability and full wave rectification.

Filter:

Capacitive filter is used in this project. It removes the ripples from the output of rectifier

and smoothens the D.C. Output received from this filter is constant until the mains voltage and


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load is maintained constant. However, if either of the two is varied, D.C. voltage received at this

point changes. Therefore a regulator is applied at the output stage.

Voltage regulator:

As the name itself implies, it regulates the input applied to it. A voltage regulator is an

electrical regulator designed to automatically maintain a constant voltage level. In this project,

power supply of 5V and 12V are required. In order to obtain these voltage levels, 7805 and 7812

voltage regulators are to be used. The first number 78 represents positive supply and the numbers

05, 12 represent the required output voltage levels.

3.3 Microcontrollers:

Microprocessors and microcontrollers are widely used in embedded systems products.

Microcontroller is a programmable device. A microcontroller has a CPU in addition to a fixed

amount of RAM, ROM, I/O ports and a timer embedded all on a single chip. The fixed amount of

on-chip ROM, RAM and number of I/O ports in microcontrollers makes them ideal for many

applications in which cost and space are critical.

The Intel 8051 is Harvard architecture, single chip microcontroller (C) which was developed by

Intel in 1980 for use in embedded systems. It was popular in the 1980s and early 1990s, but today

it has largely been superseded by a vast range of enhanced devices with 8051-compatible processor

cores that are manufactured by more than 20 independent manufacturers including Atmel, Infineon

Technologies and Maxim Integrated Products.

8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data at a time. Data

larger than 8 bits has to be broken into 8-bit pieces to be processed by the CPU. 8051 is available

in different memory types such as UV-EPROM, Flash and NV-RAM.


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Features of AT89S52:

8K Bytes of Re-programmable Flash Memory.

RAM is 256 bytes.

4.0V to 5.5V Operating Range.

Fully Static Operation: 0 Hz to 33 MHzs

Three-level Program Memory Lock.

256 x 8-bit Internal RAM.

32 Programmable I/O Lines.

Three 16-bit Timer/Counters.

Eight Interrupt Sources.

Full Duplex UART Serial Channel.

Low-power Idle and Power-down Modes.

Interrupt recovery from power down mode.

Watchdog timer.

Dual data pointer.

Power-off flag.

Fast programming time.

Flexible ISP programming (byte and page mode).

Description:

The AT89s52 is a low-voltage, high-performance CMOS 8-bit microcomputer with 8K bytes of

Flash programmable memory. The device is manufactured using Atmels high

density nonvolatile memory technology and is compatible with the industry-

standard MCS-51 instruction set. The on chip flash allows the program memory to

be reprogrammed in system or by a conventional non volatile memory programmer.

By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel

AT89s52 is a powerful microcomputer, which provides a highly flexible and cost-

effective solution to many embedded control applications.


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In addition, the AT89s52 is designed with static logic for operation down to zero frequency and

supports two software selectable power saving modes. The Idle Mode stops the

CPU while allowing the RAM, timer/counters, serial port and interrupt system to

continue functioning. The power-down mode saves the RAM contents but freezes

the oscillator disabling all other chip functions until the next hardware reset.


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Pin description:

Vcc Pin 40 provides supply voltage to the chip. The voltage source is +5V.

GND Pin 20 is the ground.


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Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL

inputs. When 1s are written to port 0 pins, the pins can be used as high impedance

inputs. Port 0 can also be configured to be the multiplexed low-order address/data

bus during accesses to external program and data memory. In this mode, P0 has

internal pull-ups. Port 0 also receives the code bytes during Flash programming and

outputs the code bytes during Program verification. External pull-ups are required

during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled

high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that

are externally being pulled low will source current (IIL) because of the internal

pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2

external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX),

respectively, as shown in the following table. Port 1 also receives the low-order

address bytes during Flash programming and verification.

Port 2




are externally being pulled low will source current (IIL) because of the internal

pull-ups.


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Port 2 emits the high-order address byte during fetches from external program memory and during

accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In

this application, Port 2 uses strong internal pull-ups when emitting 1s. During

accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2

emits the contents of the P2 Special Function Register. The port also receives the

high-order address bits and some control signals during Flash programming and

verification.

Port 3




are externally being pulled low will source current (IIL) because of the pull-ups.

Port 3 receives some control signals for Flash programming and verification. Port 3

also serves the functions of various special features of the AT89S52, as shown in

the following table.

RST (Reset input): A high on this pin for two machine cycles while the oscillator is running

resets the device. This pin drives high for 98 oscillator periods after the Watchdog

times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable

this feature. In the default state of bit DISRTO, the RESET HIGH out feature is

enabled.


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ALE/PROG (Address Latch Enable) is an output pulse for latching the low byte of the address

during accesses to external memory. This pin is also the program pulse input

(PROG) during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be

used for external timing or clocking purposes. Note, however, that one ALE pulse

is skipped during each access to external data memory. If desired, ALE operation

can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is

active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly

pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in

external execution mode.

PSEN (Program Store Enable) is the read strobe to external program memory. When the

AT89S52 is executing code from external program memory, PSEN is activated

twice each machine cycle, except that two PSEN activations are skipped during

each access to external data memory.

EA/VPP (External Access Enable) EA must be strapped to GND in order to enable the device to

fetch code from external program memory locations starting at 0000H up to

FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally

latched on reset.EA should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage (VPP) during Flash

programming.

XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2: Output from the inverting oscillator amplifier.


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XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can beconfigured for use as an on-chip oscillator. Either a quartz crystal or ceramic

resonator may be used. To drive the device from an external clock source, XTAL2

should be left unconnected while XTAL1 is driven. There are no requirements on

the duty cycle of the external clock signal, since the input to the internal clocking

circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage

high and low time specifications must be observed.


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Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in

the following table. It should be noted that not all of the addresses are occupied and

unoccupied addresses may not be implemented on the chip. Read accesses to these

addresses will in general return random data, and write accesses will have an

indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future

products to invoke new features. In that case, the reset or inactive values of the new

bits will always be 0.

Timer 2 Registers:

Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register

pair (RCAP2H, RCAP2L) is the Capture/Reload register for Timer 2 in 16-bit

capture mode or 16-bit auto-reload mode.

Interrupt Registers:

The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the

six interrupt sources in the IP register.


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Dual Data Pointer Registers:

To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer

Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H

and 85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The

user should ALWAYS initialize the DPS bit to the appropriate value before

accessing the respective Data Pointer Register.

Power off Flag:

The Power off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1 during

power up. It can be set and rest under software control and is not affected by reset.

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes

each of external Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the

AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through

1FFFH are directed to internal memory and fetches to addresses 2000H through

FFFFH are to external memory.


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Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel

address space to the Special Function Registers. This means that the upper 128

bytes have the same addresses as the SFR space but are physically separate from

SFR space.

When an instruction accesses an internal location above address 7FH, the address mode used in the

instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the

SFR space. Instructions which use direct addressing access the SFR space.

For example, the following direct addressing instruction accesses the SFR at location 0A0H (which

is P2).

MOV 0A0H, #data

The instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the

following indirect addressing instruction, where R0 contains 0A0H, accesses the

data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

It should be noted that stack operations are examples of indirect addressing, so the upper 128 bytes

of data RAM are available as stack space.

Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer

Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To

enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST

register (SFR location 0A6H).


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When the WDT is enabled, it will increment every machine cycle while the oscillator is running.

The WDT timeout period is dependent on the external clock frequency. There is no

way to disable the WDT except through reset (either hardware reset or WDT

overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse

at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR

location 0A6H). When the WDT is enabled, the user needs to service it regularly by

writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter

overflows when it reaches 16383 (3FFFH) and this will reset the device. When the

WDT is enabled, it will increment every machine cycle while the oscillator is

running. This means the user must reset the WDT at least for every 16383 machine

cycles.

To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only

register. The WDT counter cannot be read or written. When WDT overflows, it will

generate an output RESET pulse at the RST pin. The RESET pulse duration is

98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be

serviced in those sections of code that will periodically be executed within the time

required to prevent a WDT reset.

WDT during Power-down and Idle

In Power down mode the oscillator stops, which means the WDT also stops. Thus the user does not

need to service the WDT in Power down mode.

There are two methods of exiting Power down mode:

By a hardware reset or

By a level-activated external interrupt which is enabled prior to entering Power down mode.


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When Power-down is exited with hardware reset, servicing the WDT should occur as it normally

does whenever the AT89S52 is reset. Exiting Power down with an interrupt is

significantly different.

The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought

high, the interrupt is serviced. To prevent the WDT from resetting the device while

the interrupt pin is held low, the WDT is not started until the interrupt is pulled

high. It is suggested that the WDT be reset during the interrupt service for the

interrupt used to exit Power down mode.

To ensure that the WDT does not overflow within a few states of exiting Power down, it is best to

reset the WDT just before entering Power down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether

the WDT continues to count if enabled. The WDT keeps counting during IDLE

(WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the

AT89S52 while in IDLE mode, the user should always set up a timer that will

periodically exit IDLE, service the WDT and reenter IDLE mode. With WDIDLE

bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon

exit from IDLE.

UART

The Atmel 8051 Microcontrollers implement three general purpose, 16-bit timers/ counters. They

are identified as Timer 0, Timer 1 and Timer 2 and can be independently configured to operate in a

variety of modes as a timer or as an event counter. When operating as a timer, the timer/counter

runs for a programmed length of time and then issues an interrupt request. When operating as a

counter, the timer/counter counts negative transitions on an external pin. After a preset number of

counts, the counter issues an interrupt request. The various operating modes of each timer/counter

are described in the following sections.

A basic operation consists of timer registers THx and TLx (x= 0, 1) connected in cascade to form a

16-bit timer. Setting the run control bit (TRx) in TCON register turns the timer on by allowing the


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selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it

sets the timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and

TLx timer registers. Timer registers can be accessed to obtain the current count or to enter preset

values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise

the behavior of the timer/counter is unpredictable.

The C/T control bit (in TCON register) selects timer operation or counter operation, by selecting

the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit

must be cleared when changing the mode of operation, otherwise the behavior of the timer/counter

is unpredictable. For timer operation (C/Tx# = 0), the timer register counts the divided-down

peripheral clock. The timer register is incremented once every peripheral cycle (6 peripheral clock

periods). The timer clock rate is FPER / 6, i.e. FOSC / 12 in standard mode or FOSC / 6 in X2

mode. For counter operation (C/Tx# = 1), the timer register counts the negative transitions on the

Tx external input pin. The external input is sampled every peripheral cycle. When the sample is

high in one cycle and low in the next one, the counter is incremented.

Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the

maximum count rate is FPER / 12, i.e. FOSC / 24 in standard mode or FOSC / 12 in X2 mode.

There are no restrictions on the duty cycle of the external input signal, but to ensure that a given

level is sampled at least once before it changes, it should be held for at least one full peripheral

cycle. In addition to the timer or counter selection, Timer 0 and Timer 1 have four operating

modes from which to select which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1and 2

are the same for both timer/counters. Mode 3 is different.

The four operating modes are described below. Timer 2, has three modes of operation: capture,

auto-reload and baud rate generator.

Timer 0

Timer 0 functions as either a timer or event counter in four modes of operation. Timer 0 is

controlled by the four lower bits of the TMOD register and bits 0, 1, 4 and 5 of the TCON register.


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TMOD register selects the method of timer gating (GATE0), timer or counter operation (T/C0#)

and mode of operation (M10 and M00). The TCON register provides timer 0 control functions:

overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).

For normal timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the

selected input. Setting GATE0 and TR0 allows external pin INT0# to control timer operation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag, generating an interrupt

request. It is important to stop timer/counter before changing mode.

Mode 0 (13-bit Timer)

Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (TH0 register) with a

modulo-32 prescaler implemented with the lower five bits of the TL0 register. The upper three bits

of TL0 register are indeterminate and should be ignored. Prescaler overflow increments the TH0

register.


Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits. Mode 1

configures timer 0 as a 16-bit timer with the TH0 and TL0 registers connected in cascade. The

selected input increments the TL0 register.

Mode 2 (8-bit Timer with Auto-Reload)

Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically reloads from the TH0

register. TL0 overflow sets TF0 flag in the TCON register and reloads TL0 with the contents of

TH0, which is preset by software.

Mode 3 (Two 8-bit Timers)

Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. This

mode is provided for applications requiring an additional 8-bit timer or counter. TL0 uses the timer

0 control bits C/T0# and GATE0 in the TMOD register, and TR0 and TF0 in the TCON register in

the normal manner. TH0 is locked into a timer function (counting FPER /6) and takes over use of


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the timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of timer 1 is restricted when

timer 0 is in mode 3.

Timer 1

Timer 1 is identical to timer 0, except for mode 3, which is a hold-count mode. The following

comments help to understand the differences:

Timer 1 functions as either a timer or event counter in three modes of operation. Timer 1s mode

3 is a hold-count mode.

Timer 1 is controlled by the four high-order bits of the TMOD register and bits 2, 3, 6 and 7 of

the TCON register. The TMOD register selects the method of timer gating (GATE1), timer or

counter operation (C/T1#) and mode of operation (M11 and M01). The TCON register provides

timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and

interrupt type control bit (IT1).

Timer 1 can serve as the baud rate generator for the serial port. Mode 2 is best suited for this

purpose.

For normal timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the

selected input. Setting GATE1 and TR1 allows external pin INT1# to control timer operation.

Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt

request.

When timer 0 is in mode 3, it uses timer 1s overflow flag (TF1) and run control bit (TR1). For

this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate

generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on.

It is important to stop timer/counter before changing modes.


Mode 0 configures Timer 1 as a 13-bit timer, which is set up as an 8-bit timer (TH1 register) with a

modulo-32 prescaler implemented with the lower 5 bits of the TL1 register. The upper 3 bits of the

TL1 register are ignored. Prescaler overflow increments the TH1 register.



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Mode 1 configures Timer 1 as a 16-bit timer with the TH1 and TL1 registers connected in cascade.

The selected input increments the TL1 register.

Mode 2 (8-bit Timer with Auto Reload)

Mode 2 configures Timer 1 as an 8-bit timer (TL1 register) with automatic reload from the TH1

register on overflow. TL1 overflow sets the TF1 flag in the TCON register and reloads TL1 with

the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.

Mode 3 (Halt)

Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1

when TR1 run control bit is not available i.e., when Timer 0 is in mode 3.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type

of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes:

capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by

bits in T2CON. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the

TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator

periods, the count rate is 1/12 of the oscillator frequency.


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In the Counter function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T2. In this function, the external input is sampled

during S5P2 of every machine cycle. When the samples show a high in one cycle

and a low in the next cycle, the count is incremented. The new count value appears

in the register during S3P1 of the cycle following the one in which the transition

was detected. Since two machine cycles (24 oscillator periods) are required torecognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator

frequency. To ensure that a given level is sampled at least once before it changes,

the level should be held for at least one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is

a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can

then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same

operation, but a 1-to-0 transition at external input T2EX also causes the current

value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In

addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2

bit, like TF2, can generate an interrupt.


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Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode.

This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD.

Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set,

Timer 2 can count up or down, depending on the value of the T2EX pin.


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The above figure shows Timer 2 automatically counting up when DCEN = 0. In this mode, two

options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to

0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the

timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The

values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If

EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0

transition at external input T2EX. This transition also sets the EXF2 bit. Both the

TF2 and EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In this mode,

the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2

count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow

also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer

registers, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal

the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and

causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of

resolution. In this operating mode, EXF2 does not flag an interrupt.


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Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note that

the baud rates for transmit and receive can be different if Timer 2 is used for the

receiver or transmitter and Timer 1 is used for the other function. Setting RCLK

and/or TCLK puts Timer 2 into its baud rate generator mode.

The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes

the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and

RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are

determined by Timer 2s overflow rate according to the following equation.

The Timer can be configured for either timer or counter operation. In most applications, it is

configured for timer operation (CP/T2 = 0). The timer operation is different for

Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments

every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator,

however, it increments every state time (at 1/2 the oscillator frequency). The baud

rate formula is given below.


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where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned

integer.

Timer 2 as a baud rate generator is shown in the below figure. This figure is valid only if RCLK or

TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not

generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX

will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,

TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as

an extra external interrupt.

It should be noted that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator

mode, TH2 or TL2 should not be read from or written to. Under these conditions,

the Timer is incremented every state time, and the results of a read or write may not

be accurate. The RCAP2 registers may be read but should not be written to, because

a write might overlap a reload and cause write and/or reload errors. The timer

should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.


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Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in the below figure.

This pin, besides being a regular I/O pin, has two alternate functions. It can be

programmed to input the external clock for Timer/Counter 2 or to output a 50%

duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating

frequency).


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To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and

bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator frequency and the reload value

of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following

equation.

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to

when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a

baud-rate generator and a clock generator simultaneously. Note, however, that the

baud rate and clock-out frequencies cannot be determined independently from one

another since they both use RCAP2H and RCAP2L.

Interrupts

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three

timer interrupts (Timers 0, 1, and 2) and the serial port interrupt. These interrupts

are all shown in the below figure.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit

in Special Function Register IE. IE also contains a global disable bit, EA, which

disables all interrupts at once. The below table shows that bit position IE.6 is

unimplemented. User software should not write a 1 to this bit position, since it may

be used in future AT89 products.


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Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither

of these flags is cleared by hardware when the service routine is vectored to. In fact,

the service routine may have to determine whether it was TF2 or EXF2 that

generated the interrupt, and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers

overflow. The values are then polled by the circuitry in the next cycle. However,

the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the

timer overflows.


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Power saving modes of operation :

8051 has two power saving modes. They are:

1. Idle Mode

2. Power Down mode.The two power saving modes are entered by setting two bits IDL and PD in the special

function register (PCON) respectively.

The structure of PCON register is as follows.

PCON: Address 87H


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The schematic diagram for 'Power down' mode and 'Idle' mode is given as follows:

Idle Mode:

Idle mode is entered by setting IDL bit to 1 (i.e., IDL=1). The clock signal is gated off to

CPU, but not to interrupt, timer and serial port functions. The CPU status is preserved

entirely. SP, PC, PSW, Accumulator and other registers maintain their data during IDLE

mode. The port pins hold their logical states they had at the time Idle was initialized. ALE

and PSEN(bar) are held at logic high levels.

Ways to exit Idle Mode:

1. 1. Activation of any enabled interrupt will clear PCON.0 bit and hence the Idle

Mode is exited. The program goes to the Interrupt Service Routine (ISR). After RETI is

executed at the end of ISR, the next instruction will start from the one following the

instruction that enabled the Idle Mode.

2.

3. 2. A hardware reset exits the idle mode. The CPU starts from the instruction

following the instruction that invoked the Idle mode.


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Power Down Mode:

The Power Down Mode is entered by setting the PD bit to 1. The internal clock to the

entire microcontroller is stopped. However, the program is not dead. The Power down

Mode is exited (PCON.1 is cleared to 0) by Hardware Reset only. The CPU starts from the

next instruction where the Power down Mode was invoked. Port values are not changed/

overwritten in power down mode. Vcc can be reduced to 2V in Power down Mode.

However Vcc has to be restored to normal value before Power down Mode is exited.

Program Memory Lock Bits

The AT89S52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to

obtain the additional features listed in the table.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset.

If the device is powered up without a reset, the latch initializes to a random value and holds that

value until reset is activated. The latched value of EA must agree with the current logic level at that

pin in order for the device to function properly.

Programming the Flash Parallel Mode

The AT89S52 is shipped with the on-chip Flash memory array ready to be programmed. The

programming interface needs a high-voltage (12-volt) program enable signal and is compatible

with conventional third-party Flash or EPROM programmers. The AT89S52 code memory array is

programmed byte-by-byte.


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Programming Algorithm:

Before programming the AT89S52, the address, data and control signals should be set up

according to the Flash Programming Modes. To program the AT89S52, take the following steps:

1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V.

5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte write

cycle is self-timed and typically takes no more than 50 s. Repeat steps 1 through

5, changing the address and data for the entire array or until the end of the object

file is reached.

Data Polling:

The AT89S52 features Data Polling to indicate the end of a byte write cycle. During a write cycle,

an attempted read of the last byte written will result in the complement of the

written data on P0.7. Once the write cycle has been completed, true data is valid on

all outputs, and the next cycle may begin. Data Polling may begin any time after a

write cycle has been initiated.


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Ready/Busy:

The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is

pulled low after ALE goes high during programming to indicate BUSY. P3.0 is

pulled high again when programming is done to indicate READY.

Program Verify:

If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back

via the address and data lines for verification. The status of the individual lock bits

can be verified directly by reading them back.

Reading the Signature Bytes:

The signature bytes are read by the same procedure as a normal verification of locations 000H,

100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The

values returned are as follows.

(000H) = 1EH indicates manufactured by Atmel

(100H) = 52H indicates AT89S52

(200H) = 06H

Chip Erase:

In the parallel programming mode, a chip erase operation is initiated by using the proper

combination of control signals and by pulsing ALE/PROG low for a duration of

200 ns - 500 ns.

In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase

instruction. In this mode, chip erase is self-timed and takes about 500 ms. During

chip erase, a serial read from any address location will return 00H at the data

output.

Programming the Flash Serial Mode


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The Code memory array can be programmed using the serial ISP interface while RST is pulled to

VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output).

After RST is set high, the Programming Enable instruction needs to be executed

first before other operations can be executed. Before a reprogramming sequence

can occur, a Chip Erase operation is required.

The Chip Erase operation turns the content of every memory location in the Code array into FFH.

Either an external system clock can be supplied at pin XTAL1 or a crystal needs to

be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK)

frequency should be less than 1/16 of the crystal frequency. With a 33 MHz

oscillator clock, the maximum SCK frequency is 2 MHz.

Serial Programming Algorithm

To program and verify the AT89S52 in the serial programming mode, the following sequence is

recommended:

1. Power-up sequence:

a. Apply power between VCC and GND pins.

b. Set RST pin to H.

If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to

XTAL1 pin and wait for at least 10 milliseconds.

2. Enable serial programming by sending the Programming Enable serial instruction to pin

MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be

less than the CPU clock at XTAL1 divided by 16.

3. The Code array is programmed one byte at a time in either the Byte or Page mode. The write

cycle is self-timed and typically takes less than 0.5 ms at 5V.

4. Any memory location can be verified by using the Read instruction which returns the content at

the selected address at serial output MISO/P1.6.

5. At the end of a programming session, RST can be set low to commence normal device

operation.

Power-off sequence (if needed):

1. Set XTAL1 to L (if a crystal is not used).


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2. Set RST to L.

3. Turn VCC power off.

Data Polling:

The Data Polling feature is also available in the serial mode. In this mode, during a write cycle an

attempted read of the last byte written will result in the complement of the MSB of

the serial output byte on MISO.

Serial Programming Instruction Set

The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in the table

given below.


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Programming Interface Parallel Mode

Every code byte in the Flash array can be programmed by using the appropriate combination of

control signals. The write operation cycle is self-timed and once initiated, will automatically time

itself to completion.


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After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to

clock in the enable data bytes. No pulsing of Reset signal is necessary. SCK should

be no faster than 1/16 of the system clock at XTAL1.


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For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper

address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out.

Then the next instruction will be ready to be decoded.

3.4 Serial Communication:

The main requirements for serial communication are:

1. Microcontroller

2. PC

3. RS 232 cable

4. MAX 232 IC

5. HyperTerminal

When the pins P3.0 and P3.1 of microcontroller are set, UART which is inbuilt in the

microcontroller will be enabled to start the serial communication.

Timers:

The 8051 has two timers: Timer 0 and Timer 1. They can be used either as timers to generate a

time delay or as counters to count events happening outside the microcontroller.

Both Timer 0 and Timer 1 are 16-bit wide. Since the 8051 has an 8-bit architecture, each 16-bit

timer is accessed as two separate registers of low byte and high byte.Lower byte register of Timer 0 is TL0 and higher byte is TH0. Similarly lower byte register of

Timer1 is TL1 and higher byte register is TH1.

TMOD (timer mode) register:

Both timers 0 and 1 use the same register TMOD to set the various operation modes. TMOD is an

8-bit register in which the lower 4 bits are set aside for Timer 0 and the upper 4 bits for Timer 1. In

each case, the lower 2 bits are used to set the timer mode and the upper 2 bits to specify the

operation.


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GATE

Every timer has a means of starting and stopping. Some timers do this by software, some by

hardware and some have both software and hardware controls. The timers in the 8051 have both.

The start and stop of the timer are controlled by the way of software by the TR (timer start) bits

TR0 and TR1. These instructions start and stop the timers as long as GATE=0 in the TMOD

register. The hardware way of starting and stopping the timer by an external source is achieved by

making GATE=1 in the TMOD register.

C/T

Timer or counter selected. Cleared for timer operation and set for counter operation.

M1

Mode bit 1

M0

Mode bit 0

Mode Selection

M1 M0 Mode Operating Mode

0 0 0 13-bit timer mode8-bit timer/counter THx with TLx as 5-bit prescaler

0 1 1 16-bit timer mode

16-bit timer/counters THx and TLx are cascaded

1 0 2 8-bit auto reload timer/counter

THx holds a value that is to be reloaded into TLx each time


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it overflows

1 1 3 Split timer mode

The mode used here to generate a time delay is MODE 2. This mode 2 is an 8-bit timer and

therefore it allows only values of 00H to FFH to be loaded into the timers register TH. After TH is

loaded with the 8-bit value, the 8051 give a copy of it to TL. When the timer starts, it starts to

count up by incrementing the TL register. It counts up until it reaches its limit of FFH. When it

rolls over from FFH to 00H, it sets high the TF (timer flag). If Timer 0 is used, TF0 goes high and

if Timer 1 is used, TF1 goes high. When the TL register rolls from FFH to 0 and TF is set to 1, TL

is reloaded automatically with the original value kept by the TH register.

Asynchronous and Synchronous Serial Communication

Computers transfer data in two ways: parallel and serial. In parallel data transfers, often 8 or more

lines are used to transfer data to a device that is only a few feet away. Although a lot of data can be

transferred in a short amount of time by using many wires in parallel, the distance cannot be great.

To transfer to a device located many meters away, the serial method is best suitable.

In serial communication, the data is sent one bit at a time. The 8051 has serial communication

capability built into it, thereby making possible fast data transfer using only a few wires.

The fact that serial communication uses a single data line instead of the 8-bit data line instead of

the 8-bit data line of parallel communication not only makes it cheaper but also enables two

computers located in two different cities to communicate over the telephone.

Serial data communication uses two methods, asynchronous and synchronous. The synchronous

method transfers a block of data at a time, while the asynchronous method transfers a single byte at

a time. With synchronous communications, the two devices initially synchronize themselves to

each other, and then continually send characters to stay in sync. Even when data is not really being

sent, a constant flow of bits allows each device to know where the other is at any given time. That

is, each character that is sent is either actual data or an idle character. Synchronous

communications allows faster data transfer rates than asynchronous methods, because additional


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bits to mark the beginning and end of each data byte are not required. The serial ports on IBM-

style PCs are asynchronous devices and therefore only support asynchronous serial

communications.

Asynchronous means "no synchronization", and thus does not require sending and receiving idle

characters. However, the beginning and end of each byte of data must be identified by start and

stop bits. The start bit indicates when the data byte is about to begin and the stop bit signals when

it ends. The requirement to send these additional two bits causes asynchronous communication to

be slightly slower than synchronous however it has the advantage that the processor does not have

to deal with the additional idle characters.

There are special IC chips made by many manufacturers for serial data communications. These

chips are commonly referred to as UART(universal asynchronous receiver-transmitter) and

USART(universal synchronous-asynchronous receiver-transmitter). The 8051 has a built-in

UART.

In the asynchronous method, the data such as ASCII characters are packed between a start and a

stop bit. The start bit is always one bit, but the stop bit can be one or two bits. The start bit is

always a 0 (low) and stop bit (s) is 1 (high). This is called framing.

The rate of data transfer in serial data communication is stated as bps (bits per second). Another

widely used terminology for bps is baud rate. The data transfer rate of a given computer system

depends on communication ports incorporated into that system. And in asynchronous serial data

communication, this baud rate is generally limited to 100,000bps. The baud rate is fixed to

9600bps in order to interface with the microcontroller using a crystal of 11.0592 MHz.

RS232 CABLE:

To allow compatibility among data communication equipment, an interfacing standard called

RS232 is used. Since the standard was set long before the advent of the TTL logic family, its input

and output voltage levels are not TTL compatible. For this reason, to connect any RS232 to a


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microcontroller system, voltage converters such as MAX232 are used to convert the TTL logic

levels to the RS232 voltage levels and vice versa.

MAX 232:

Max232 IC is a specialized circuit which makes standard voltages as required by RS232 standards.

This IC provides best noise rejection and very reliable against discharges and short circuits.

MAX232 IC chips are commonly referred to as line drivers.

To ensure data transfer between PC and microcontroller, the baud rate and voltage levels of

Microcontroller and PC should be the same. The voltage levels of microcontroller are logic1 and

logic 0 i.e., logic 1 is +5V and logic 0 is 0V. But for PC, RS232 voltage levels are considered and

they are: logic 1 is taken as -3V to -25V and logic 0 as +3V to +25V. So, in order to equal these

voltage levels, MAX232 IC is used. Thus this IC converts RS232 voltage levels to microcontroller

voltage levels and vice versa.

Interfacing max232 with microcontroller:


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SCON (serial control) register:

The SCON register is an 8-bit register used to program the start bit, stop bit and data bits of data

framing.

SM0 SCON.7 Serial port mode specifier

SM1 SCON.6 Serial port mode specifier

SM2 SCON.5 Used for multiprocessor communication

REN SCON.4 Set/cleared by software to enable/disable reception

TB8 SCON.3 Not widely used

RB8 SCON.2 Not widely used

TI SCON.1 Transmit interrupt flag. Set by hardware at the

beginning of the stop bit in mode 1. Must be

cleared by software.

RI SCON.0 Receive interrupt flag. Set by hardware at the


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beginning of the stop bit in mode 1. Must be

cleared by software.

SM0 SM1

0 0 Serial Mode 0

0 1 Serial Mode 1, 8-bit data, 1 stop bit, 1 start bit

1 0 Serial Mode 2

1 1 Serial Mode 3

Of the four serial modes, only mode 1 is widely used. In the SCON register, when serial mode 1 is

chosen, the data framing is 8 bits, 1 stop bit and 1 start bit, which makes it compatible with the

COM port of IBM/ compatible PCs. And the most important is serial mode 1 allows the baud rate

to be variable and is set by Timer 1 of the 8051. In serial mode 1, for each character a total of 10

bits are transferred, where the first bit is the start bit, followed by 8 bits of data and finally 1 stop

bit.

8051 Interface with any External Devices using Serial Communication:


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3.5 GSM Technology:

Definition of GSM:

GSM (Global System for Mobile communications) is an open, digital cellular technology used for

transmitting mobile voice and data services.

GSM (Global System for Mobile communication) is a digital mobile telephone system that is

widely used in Europe and other parts of the world. GSM uses a variation of Time Division

Multiple Access (TDMA) and is the most widely used of the three digital wireless telephonetechnologies (TDMA, GSM, and CDMA). GSM digitizes and compresses data, then sends it down

a channel with two other streams of user data, each in its own time slot. It operates at either the 900

MHz or 1,800 MHz frequency band. It supports voice calls and data transfer speeds of up to 9.6

kbit/s, together with the transmission of SMS (Short Message Service).


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GSM Frequencies

GSM networks operate in a number of different frequency ranges (separated into GSM frequency

ranges for 2G and UMTS frequency bands for 3G). Most 2G GSM networks operate in the 900

MHz or 1800 MHz bands. Some countries in the Americas (including Canada and the United

States) use the 850 MHz and 1900 MHz bands because the 900 and 1800 MHz frequency bands

were already allocated. Most 3G GSM networks in Europe operate in the 2100 MHz frequency

band. The rarer 400 and 450 MHz frequency bands are assigned in some countries where these

frequencies were previously used for first-generation systems.

GSM-900 uses 890915 MHz to send information from the mobile station to the base station

(uplink) and 935960 MHz for the other direction (downlink), providing 124 RF channels (channel

numbers 1 to 124) spaced at 200 kHz. Duplex spacing of 45 MHz is used. In some countries the

GSM-900 band has been extended to cover a larger frequency range. This 'extended GSM', E-

GSM, uses 880915 MHz (uplink) and 925960 MHz (downlink), adding 50 channels (channel

numbers 975 to 1023 and 0) to the original GSM-900 band.

Time division multiplexing is used to allow eight full-rate or sixteen half-rate speech channels per

radio frequency channel. There are eight radio timeslots (giving eight burst periods) grouped into

what is called a TDMA frame. Half rate channels use alternate frames in the same timeslot. The

channel data rate for all 8 channels is 270.833 Kbit/s, and the frame duration is 4.615 ms.

The transmission power in the handset is limited to a maximum of 2 watts in GSM850/900 and 1

watt in GSM1800/1900. GSM operates in the 900MHz and 1.8GHz bands in Europe and the

1.9GHz and 850MHz bands in the US. The 850MHz band is also used for GSM and 3G in

Australia, Canada and many South American countries. By having harmonized spectrum across

most of the globe, GSMs international roaming capability allows users to access the same services

when travelling abroad as at home. This gives consumers seamless and same number connectivity

in more than 218 countries.

Terrestrial GSM networks now cover more than 80% of the worlds population. GSM satellite

roaming has also extended service access to areas where terrestrial coverage is not available.


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Mobile Telephony Standards

Standard Generation Frequency band Throughput

GSM 2G

Allows transfer of voice or low-

volume digital data. 9.6 kbps

9.6

kbps

GPRS 2.5G

Allows transfer of voice or

moderate-volume digital data. 21.4-171.2 kbps48 kbps

EDGE 2.75G

Allows simultaneous transfer of

voice and digital data. 43.2-345.6 kbps

171

kbps

UMTS 3G

Allows simultaneous transfer of

voice and high-speed digital data. 0.144-2 Mbps

384

kbps

1G

The first generation of mobile telephony (written 1G) operated using analogue communications

and portable devices that were relatively large. It used primarily the following standards:

AMPS (Advanced Mobile Phone System), which appeared in 1976 in the United States,

was the first cellular network standard. It was used primarily in the Americas, Russia and

Asia. This first-generation analogue network had weak security mechanisms which allowed

hacking of telephones lines.

TACS (Total Access Communication System) is the European version of the AMPS

model. Using the 900 MHz frequency band, this system was largely used in England and

then in Asia (Hong-Kong and Japan).

ETACS (Extended Total Access Communication System) is an improved version of the

TACS standard developed in the United Kingdom that uses a larger number of

communication channels.

The first-generation cellular networks were made obsolete by the appearance of an entirely digital

second generation.

Second Generation of Mobile Networks (2G)


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The second generation of mobile networks marked a break with the first generation of cellular

telephones by switching from analogue to digital. The main 2G mobile telephony standards are:

GSM (Global System for Mobile communications) is the most commonly used standard in

Europe at the end of the 20th century and supported in the United States. This standard uses

the 900 MHz and 1800 MHz frequency bands in Europe. In the United States, however, the

frequency band used is the 1900 MHz band. Portable telephones that are able to operate in

Europe and the United States are therefore called tri-band.

CDMA (Code Division Multiple Access) uses a spread spectrum technique that allows a

radio signal to be broadcast over a large frequency range.

TDMA (Time Division Multiple Access) uses a technique of time division of

communication channels to increase the volume of data transmitted simultaneously.

TDMA technology is primarily used on the American continent, in New Zealand and in the

Asia-Pacific region.

With the 2G networks, it is possible to transmit voice and low volume digital data, for example

text messages (SMS, forShort Message Service) or multimedia messages (MMS, forMultimedia

Message Service). The GSM standard allows a maximum data rate of 9.6 kbps.

Extensions have been made to the GSM standard to improve throughput. One of these is the GPRS

(General Packet Radio System) service which allows theoretical data rates on the order of 114

Kbit/s but with throughput closer to 40 Kbit/s in practice. As this technology does not fit within the

"3G" category, it is often referred to as 2.5G

The EDGE (Enhanced Data Rates for Global Evolution) standard, billed as 2.75G, quadruples the

throughput improvements of GPRS with its theoretical data rate of 384 Kbps, thereby allowing the

access for multimedia applications. In reality, the EDGE standard allows maximum theoretical

data rates of 473 Kbit/s, but it has been limited in order to comply with the IMT-2000

(International Mobile Telecommunications-2000) specifications from the ITU (International

Telecommunications Union).

3G
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The IMT-2000 (International Mobile Telecommunications for the year 2000) specifications from

the International Telecommunications Union (ITU) defined the characteristics of3G (third

generation of mobile telephony). The most important of these characteristics are:

1. High transmission data rate.

2. 144 Kbps with total coverage for mobile use.

3. 384 Kbps with medium coverage for pedestrian use.

4. 2 Mbps with reduced coverage area for stationary use.

5. World compatibility.

6. Compatibility of 3rd generation mobile services with second generation networks.

3G offers data rates of more than 144 Kbit/s, thereby allowing the access to multimedia uses such

as video transmission, video-conferencing or high-speed internet access. 3G networks use different

frequency bands than the previous networks: 1885-2025 MHz and 2110-2200 MHz.

The main 3G standard used in Europe is called UMTS (Universal Mobile Telecommunications

System) and uses WCDMA (Wideband Code Division Multiple Access) encoding. UMTS

technology uses 5 MHz bands for transferring voice and data, with data rates that can range from

384 Kbps to 2 Mbps. HSDPA (High Speed Downlink Packet Access) is a third generation mobile

telephony protocol, (considered as "3.5G"), which is able to reach data rates on the order of 8 to 10

Mbps. HSDPA technology uses the 5 GHz frequency band and uses WCDMA encoding.

Introduction to the GSM Standard

The GSM (Global System for Mobile communications) network is at the start of the 21st century,

the most commonly used mobile telephony standard in Europe. It is called as Second Generation

(2G) standard because communications occur in an entirely digital mode, unlike the first

generation of portable telephones.

When it was first standardized in 1982, it was called as Group Special Mobile and later, it became

an international standard called "Global System for Mobile communications" in 1991.

In Europe, the GSM standard uses the 900 MHz and 1800 MHz frequency bands. In the United

States, however, the frequency band used is the 1900 MHz band. For this reason, portable


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telephones that are able to operate in both Europe and the United States are called tri-band while

those that operate only in Europe are called bi-band.

The GSM standard allows a maximum throughput of 9.6 kbps which allows transmission of voice

and low-volume digital data like text messages (SMS, forShort Message Service) or multimedia

messages (MMS, forMultimedia Message Service).

GSM Standards:

GSM uses narrowband TDMA, which allows eight simultaneous calls on the same radio

frequency.

There are three basic principles in multiple access, FDMA (Frequency Division Multiple Access),

TDMA (Time Division Multiple Access), and CDMA (Code Division Multiple Access). All three

principles allow multiple users to share the same physical channel. But the two competing

technologies differ in the way user sharing the common resource.

TDMA allows the users to share the same frequency channel by dividing the signal into different

time slots. Each user takes turn in a round robin fashion for transmitting and receiving over the

channel. Here, users can only transmit in their respective time slot.

CDMA uses a spread spectrum technology that is it spreads the information contained in a

particular signal of interest over a much greater bandwidth than the original signal. Unlike TDMA,

in CDMA several users can transmit over the channel at the same time.

TDMA in brief:

In late1980s, as a search to convert the existing analog network to digital as a means to improve

capacity, the cellular telecommunications industry association chose TDMA over FDMA.

Time Division Multiplex Access is a type of multiplexing where two or more channels of

information are transmitted over the same link by allocating a different time interval for the

transmission of each channel. The most complex implementation using TDMA principle is of

GSMs (Global System for Mobile communication). To reduce the effect of co-channel


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interference, fading and multipath, the GSM technology can use frequency hoping, where a call

jumps from one channel to another channel in a short interval.

TDMA systems still rely on switch to determine when to perform a handoff. Handoff occurs when

a call is switched from one cell site to another while travelling. The TDMA handset constantly

monitors the signals coming from other sites and reports it to the switch without callers

awareness. The switch then uses this information for making better choices for handoff at

appropriate times. TDMA handset performs hard handoff, i.e., whenever the user moves from one

site to another, it breaks the connection and then provides a new connection with the new site.

Advantages of TDMA:

There are lots of advantages of TDMA in cellular technologies.

1. It can easily adapt to transmission of data as well as voice communication.

2. It has an ability to carry 64 kbps to 120 Mbps of data rates. This allows the operator to do

services like fax, voice band data and SMS as well as bandwidth intensive application such

as multimedia and video conferencing.

3. Since TDMA technology separates users according to time, it ensures that there will be no

interference from simultaneous transmissions.


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4. It provides users with an extended battery life, since it transmits only portion of the time

during conversations. Since the cell size grows smaller, it proves to save base station

equipment, space and maintenance.

TDMA is the most cost effective technology to convert an analog system to digital.

Disadvantages of TDMA:

One major disadvantage using TDMA technology is that the users has a predefined time slot.

When moving from one cell site to other, if all the time slots in this cell are full the user might be

disconnected. Likewise, if all the time slots in the cell in which the user is currently in are already

occupied, the user will not receive a dial tone.

The second problem in TDMA is that it is subjected to multipath distortion. To overcome this

distortion, a time limit can be used on the system. Once the time limit is expired, the signal is

ignored.

The concept of cellular network

Mobile telephone networks are based on the concept ofcells, circular zones that overlap to cover a

geographical area.

Cellular networks are based on the use of a central transmitter-receiver in each cell, called a "base

station" (orBase Transceiver Station, written BTS). The smaller the radius of a cell, the higher is

the available bandwidth. So, in highly populated urban areas, there are cells with a radius of a few

hundred meters, while huge cells of up to 30 kilometers provide coverage in rural areas.


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In a cellular network, each cell is surrounded by 6 neighbouring cells (thus a cell is generally

drawn as a hexagon). To avoid interference, adjacent cells cannot use the same frequency. In

practice, two cells using the same frequency range must be separated by a distance of two to three

times the diameter of the cell.

Architecture of the GSM Network

In a GSM network, the user terminal is called a mobile station. A mobile station is made up of

a SIM (Subscriber Identity Module) card allowing the user to be uniquely identified and a mobile

terminal.

The terminals (devices) are identified by a unique 15-digit identification number

called IMEI (International Mobile Equipment Identity). Each SIM card also has a unique (and

secret) identification number called IMSI (International Mobile Subscriber Identity). This code

can be protected using a 4-digit key called aPIN code.

The SIM card therefore allows each user to be identified independently of the terminal used during

communication with a base station. Communications occur through a radio link (air interface)

between a mobile station and a base station.


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All the base stations of a cellular network are connected to a base station controller (BSC) which

is responsible for managing distribution of the resources. The system consisting of the base station

controller and its connected base stations is called the Base Station Subsystem (BSS).

Finally, the base station controllers are themselves physically connected to the Mobile Switching

Centre (MSC), managed by the telephone network operator, which connects them to the public

telephone network and the Internet. The MSC belongs to a Network Station Subsystem (NSS),

which is responsible for managing user identities, their location and establishment of

communications with other subscribers. The MSC is generally connected to databases that provide

additional functions:

1. The Home Location Register (HLR) is a database containing information (geographic

position, administrative information etc.) of the subscribers registered in the area of the

switch (MSC).

2. The Visitor Location Register (VLR) is a database containing information of users other

than the local subscribers. The VLR retrieves the data of a new user from the HLR of the


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user's subscriber zone. The data is maintained as long as the user is in the zone and is

deleted when the user leaves or after a long period of inactivity (terminal off).

3. The Equipment Identify Register (EIR) is a database listing the mobile terminals.

4. The Authentication Centre (AUC) is responsible for verifying user identities.

5. The cellular network formed in this way is designed to support mobility via management

ofhandovers (movements from one cell to another).

Finally, GSM networks support the concept ofroaming i.e., movement from one operator network

to another.

Introduction to Modem:

Modem stands for modulator-demodulator.

A modem is a device or program that enables a computer to transmit data over telephone or cable

lines. Computer information is stored digitally, whereas information transmitted over telephone

lines is transmitted in the form of analog waves. A modem converts between these two forms.

Fortunately, there is one standard interface for connecting external modems to computers called

RS-232. Consequently, any external modem can be attached to any computer that has an RS-232port, which almost all personal computers have. There are also modems that come as an expansion

board that can be inserted into a vacant expansion slot. These are sometimes called onboard or

internal modems.


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While the modem interfaces are standardized, a number of different protocols for formatting data

to be transmitted over telephone lines exist. Some, like CCITT V.34 are official standards, while

others have been developed by private companies. Most modems have built-in support for the

more common protocols at slow data transmission speeds at least, most modems can communicate

with each other. At high transmission speeds, however, the protocols are less standardized.

Apart from the transmission protocols that they support, the following characteristics distinguish

one modem from another:

Bps: How fast the modem can transmit and receive data. At slow rates, modems are

measured in terms of baud rates. The slowest rate is 300 baud (about 25 cps). At higher

speeds, modems are measured in terms of bits per second (bps). The fastest modems run at

57,600 bps, although they can achieve even higher data transfer rates by compressing the

data. Obviously, the faster the transmission rate, the faster the data can be sent and

received. It should be noted that the data cannot be received at a faster rate than it is being

sent.

Voice/data: Many modems support a switch to change between voice and data modes. In

data mode, the modem acts like a regular modem. In voice mode, the modem acts like a

regular telephone. Modems that support a voice/data switch have a built-in loudspeaker and

microphone for voice communication. Auto-answer: An auto-answer modem enables the computer to receive calls in the absence

of the operator.

Data compression: Some modems perform data compression, which enables them to send

data at faster rates. However, the modem at the receiving end must be able to decompress

the data using the same compression technique.

Flash memory: Some modems come with flash memory rather than conventional ROM

which means that the communications protocols can be easily updated if necessary.

Fax capability: Most modern modems are fax modems, which mean that they can send

and receive faxes.

GSM Modem:


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A GSM modem is a wireless modem that works with a GSM wireless network. A wireless modem

behaves like a dial-up modem. The main difference between them is that a dial-up modem sends

and receives data through a fixed telephone line while a wireless modem sends and receives data

through radio waves.

A GSM modem can be an external device or a PC Card / PCMCIA Card. Typically, an external

GSM modem is connected to a computer through a serial cable or a USB cable. A GSM modem in

the form of a PC Card / PCMCIA Card is designed for use with a laptop computer. It should be

inserted into one of the PC Card / PCMCIA Card slots of a laptop computer.

Like a GSM mobile phone, a GSM modem requires a SIM card from a wireless carrier in order to

operate.

A SIM card contains the following information:

Subscriber telephone number (MSISDN)

International subscriber number (IMSI, International Mobile Subscriber Identity)

State of the SIM card

Service code (operator)

Authentication key

PIN (Personal Identification Code)

PUK (Personal Unlock Code)


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Computers use AT commands to control modems. Both GSM modems and dial-up modems

support a common set of standard AT commands. In addition to the standard AT commands, GSM

modems support an extended set of AT commands. These extended AT commands are defined in

the GSM standards. With the extended AT commands, the following operations can be performed:

Reading, writing and deleting SMS messages.

Sending SMS messages.

Monitoring the signal strength.

Monitoring the charging status and charge level of the battery.

Reading, writing and searching phone book entries.

The number of SMS messages that can be processed by a GSM modem per minute is very low i.e.,

about 6 to 10 SMS messages per minute.

Introduction to AT Commands


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AT commands are instructions used to control a modem. AT is the abbreviation of ATtention.

Every command line starts with "AT" or "at". That's the reason, modem commands are called AT

commands. Many of the commands that are used to control wired dial-up modems, such as ATD

(Dial), ATA (Answer), ATH (Hook control) and ATO (Return to online data state) are also

supported by GSM modems and mobile phones.

Besides this common AT command set, GSM modems and mobile phones support an AT

command set that is specific to the GSM technology, which includes SMS-related commands like

AT+CMGS (Send SMS me

Documents

Atm Card Security System