ARM Processor Overview

Prof. Taeweon SuhComputer Science Education

Korea University

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ARM (www.arm.com)

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ARM

3Source: 2008 Embedded SW Insight Conference

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ARM Partners

4Source: 2008 Embedded SW Insight Conference

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ARM (as of 2008)

5Source: 2008 Embedded SW Insight Conference

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ARM Brief

• ARM architecture was first developed in the 1980s by Acorn

• Spin off from Acron in 1990• Released ARM6 in early 1992• …• As of 2013, ARM architecture is the most widely used 32-

bit ISA in terms of quantity produced• In 2010 alone, 6.1 billion ARM-based processors shipped,

representing 95% of smartphones 35% of digital TV and set-top boxes 10% of mobile computers

6Source: Wikipedia

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ARM Architecture

• ARM is RISC (Reduced Instruction Set Computer) x86 ISA is based on CISC (Complex Instruction Set

Computer) even though x86 internally implements RISC-like microcode and pipelining

• Suitable for embedded systems Very small die size (low price) Low power consumption (longer battery life)

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ARM Processor Portfolio

8Source: 2008 Embedded SW Insight Conference

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Product Code

• T: Thumb• T2: Thumb-2 Enhancement• D: Debug• M: Multiplier• I: Embedded ICE (In-Circuit Emulation)• E: Enhanced DPS Extension • J: Jazelle

Direct execution of 8-bit Java bytecode in hardware• S: Synthesizable core• Z: Should be TrustZone?

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ARM Cortex Series

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• ARM Cortex-A family: Applications processors for feature-

rich OS and 3rd party applications

• ARM Cortex-R family: Embedded processors for real-time

signal processing, control applications

• ARM Cortex-M family: Microcontroller-oriented processors

for MCU, ASSP, and SoC applications Unp

aral

lele

d A

pplic

abili

ty

12k gates...

Cortex-M4SC300

Cortex-M3Cortex-M1

Cortex-M0

SC000

...2.5GHz

Cortex-A5x1-4

Cortex-A8Cortex-A9

x1-4

Cortex-A15x1-4

Cortex-R51-2

Cortex-R4

1-2

Cortex-R7

Source: ARM Processor Portfolio 2011

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ARMv7-A

11www.arm.com

SCU: Snoop Control Unit ACP: Accelerator Coherency Port

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ARM Processor Brief

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#pipeline stages

Frequency

Architecture

Process

ARM6 (1992) 3 ~33MHz ARMv3 1.2μm

ARM7TDMI 3 ~70MHz ARMv4 0.13nm

ARM920T 5 ~400MHz ARMv4 90nm

ARM1136J 8 ~1Ghz ARMv6 65nm

Cortex-A9 8~11 (OoO) ~2GHz ARMv7 32nm

Cortex-A15 15~24 (OoO) ~2.5GHz ARMv7 22nm

OOO: Out Of Order

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ARM Instruction Overview

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• ARM is a RISC machine, so the instruction length is fixed In ARM mode, instructions are 32-bit wide In Thumb mode, instructions are 16-bit wide

• Most ARM instructions can be conditionally executed It means that they have their normal effect only if the N

(Negative), Z (Zero), C (Carry) and V (Overflow) flags in the CPSR satisfy a condition specified in the instruction

• If the flags do not satisfy this condition, the instruction acts as a NOP (No Operation)

• In other words, the instruction has no effect and advances to the next instruction

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ARM Instructions

• For the complete instruction set, refer to the “ARM Architecture Reference Manual”

• We are going to cover essential and important instructions in this course If you completely understand one CPU, it is

pretty straightforward to understand other CPUs

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Essential Instructions• Instruction categories

Data processing instructions: add, sub, cmp, and, or Memory access instructions: ldr, str Branch instructions: b, bl Miscellaneous instructions:

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CPU

North Bridge

South Bridg

e

Main Memor

y(DDR)

FSB (Front-Side Bus)

DMI (Direct Media I/F)

Real-PC system

Memory(Instruction,

data)

ARM CPU

Address Bus

Data Bus

Simplified

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A Memory Hierarchy

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DDR3 HDD

2nd Gen. Core i7(2011)

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A Memory Hierarchy

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On-Chip Components

L2

CPU CoreSecondary

Storage(Disk)Re

g File

MainMemory(DRAM)

Speed (cycles): ½’s 1’s 10’s 100’s 10,000’s

Size (bytes): 100’s 10K’s M’s G’s T’s

Cost: highest lowest

L1I (Instr )

L1D (Data)

lower levelhigher level

L3

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ARM Registers

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• ARM has 31 general purpose registers and 6 status registers (32-bit each)

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ARM Registers

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• Unbanked registers: R0 ~ R7 Each of them refers to the same 32-bit

physical register in all processor modes. They are completely general-purpose

registers, with no special uses implied by the architecture

• Banked registers: R8 ~ R14 R8 ~ R12 have no dedicated special

purposes• FIQ mode has dedicated registers for fast

interrupt processing R13 and R14 are dedicated for special

purposes for each mode

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R13, R14, and R15• Some registers in ARM are used for special

purposes R15 == PC (Program Counter)

• x86 uses a terminology called IP (Instruction Pointer) R14 == LR (Link Register) R13 == SP (Stack Pointer)

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ARM9 Register File• A set of architectural (programmer-

visible) registers inside CPU is called register file Register file can be implemented with

flip-flops or SRAM ARM9 register file has 16 32-bit

registers• 3 read ports• 2 write ports

Register file access is much faster than main memory or cache because there are a very limited number of registers and they reside inside CPU

So, compilers strive to use the register file when translating high-level code to assembly code

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Register File32 bits

R0R1R2R3

R14R15

…

src1data

32

src2data

32

src3data

32dst1 addr

write1 data 32

4

dst2 addr

write2 data 32

4

write2write1

src1 addr

src2 addr

4

4

src3 addr 4

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CPSR

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• Current Program Status Register (CPSR) is accessible in all modes• Contains all condition flags, interrupt disable bits, the current

processor mode

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CPSR in ARM

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CPSR bits

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CPSR bits

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• ARM: 32-bit mode• Thumb: 16-bit mode• Jazelle: Special mode for JAVA acceleration

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ARM Instruction Format

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Memory Access Instructions (Load/Store)

Branch Instructions

Software Interrupt Instruction

Arithmetic and Logical Instructions

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ARM Instruction Fields

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opcode operation codeRn 4-bits first source registerRm 4-bits second source

registerRs 4-bits third source

registerRd 4-bits destination registershift 2-bits shift type*shift amount 5-bits shift by how many

bits

32-bit

* Shift type: Arithmetic, logical (left, right)

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Condition Field

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Overview of ARM Operation• ARM arithmetic in assembly form

add R3, R1, R5 # R3 = R1 + R5

R1 and R5 are source operands, and R3 is destination # indicate a comment, so assembler ignores it

• Operands of arithmetic instructions come from special locations called registers inside CPU or from the immediate field in instructions All CPUs (x86, PowerPC, MIPS, ARM…) have registers inside

• Registers are visible to the programmers ARM has a register file consisting of 16 registers

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ARM CPU

Simplified Version of CPU Internal

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R0R1R2R3

R14R15

…

32 bitsRegisters

R1

R5

R3+

add R3, R1, R5 # R3 = R1 + R5

MemoryAddress Bus

Data Bus

add R3, R1, R5

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ARM Register Convention

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Name Usage

R0~R3• Arguments passed to a subroutine• Results returned from a subroutine

R13 Stack pointerR14 Link RegisterR15 Program Counter

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Backup Slides

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ARM Processor Family

33Source: Wikipedia

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NEON & VFP

34www.arm.com

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Register Mapping

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• NEON Advanced SIMD and VFP use the same register set

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NEON

• Advanced SIMD (Single Instruction Multiple Data)• It supports 8, 16, 32 and 64-bit integer and single-

precision (32-bit) floating point data• Up to 16 operations at the same time

1B x 16 = 16B (= 1 quad word)

36http://en.wikipedia.org/wiki/ARM_architecture

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VFP (Vector Floating Point)

• FPU (Floating Point Unit) coprocessor extension to ARM architecture

• Single-precision and double-precision FP computation Compliant with IEEE 754-1985

• Intended to support execution of short “vector mode” instructions, but operated on “each” vector element sequentially Thus, did not offer the performance of true SIMD This vector mode was thus removed shortly after its introduction,

to be replaced with the much more powerful NEON Advanced SIMD

37http://en.wikipedia.org/wiki/ARM_architecture

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ARM Processor Selector

38www.arm.com