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April 2000 1
Asynchronous Communication Mechanisms Using Self-timed
Circuits
Fei Xia, Alex Yakovlev, Delong Shang,
Alex Bystrov, Albert Koelmans,
David Kinniment
Asynchronous Systems Laboratory
University of Newcastle upon Tyne
Async2000,Eilat-Israel, C
April 2000 Async2000-Eilat,Israel 2
Objectives
• To study a class of async comms previously used in (software) systems for embedded applications for potential use in SOCs
April 2000 Async2000-Eilat,Israel 3
Objectives
• To study a class of async comms previously used in (software) systems for embedded applications for potential use in SOCs
• Salient features of this class:– Bulk data transfer (medium,possibly varying,
size frames)– Between independent motive powers (clock
domains), hence need to eliminate mutual blocking
– Issues of coherence and freshness of data
April 2000 Async2000-Eilat,Israel 4
Outline
• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions
April 2000 Async2000-Eilat,Israel 5
Outline
Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions
April 2000 Async2000-Eilat,Israel 6
Asynchronous Communication
Rita (Reader)
April 2000 Async2000-Eilat,Israel 7
Asynchronous Communication
Rita (Reader)Wendy (Writer)
News
April 2000 Async2000-Eilat,Israel 8
Asynchronous Communication
News
April 2000 Async2000-Eilat,Israel 9
Asynchronous Communication
News
April 2000 Async2000-Eilat,Israel 10
Asynchronous Communication
News
April 2000 Async2000-Eilat,Israel 11
Asynchronous Communication
Is it really AsynchronousCommunication?
April 2000 Async2000-Eilat,Israel 12
Asynchronous Communication
News 1
April 2000 Async2000-Eilat,Israel 13
Asynchronous Communication
News 1
April 2000 Async2000-Eilat,Israel 14
Asynchronous Communication
News 1
April 2000 Async2000-Eilat,Israel 15
Asynchronous Communication
News 1
April 2000 Async2000-Eilat,Israel 16
Asynchronous Communication
News 1
April 2000 Async2000-Eilat,Israel 17
Asynchronous Communication
News 1
April 2000 Async2000-Eilat,Israel 18
Asynchronous Communication
News 1
April 2000 Async2000-Eilat,Israel 19
Asynchronous Communication
News 1
April 2000 Async2000-Eilat,Israel 20
Asynchronous Communication
News 2
April 2000 Async2000-Eilat,Israel 21
Asynchronous Communication
News 2
April 2000 Async2000-Eilat,Israel 22
Asynchronous Communication
News 2
April 2000 Async2000-Eilat,Israel 23
Asynchronous Communication
News 2
April 2000 Async2000-Eilat,Israel 24
Asynchronous Communication
News 2News 3
April 2000 Async2000-Eilat,Israel 25
Asynchronous Communication
News 3 News 2
April 2000 Async2000-Eilat,Israel 26
Asynchronous Communication
News 3 News 2
April 2000 Async2000-Eilat,Israel 27
Asynchronous Communication
News 3 News 2
News 4
April 2000 Async2000-Eilat,Israel 28
Asynchronous Communication
News 3 News 2
News 4
April 2000 Async2000-Eilat,Israel 29
Asynchronous Communication
News 3 News 2
News 4
April 2000 Async2000-Eilat,Israel 30
Asynchronous Communication
News 3
News 4 News 2
April 2000 Async2000-Eilat,Israel 31
Asynchronous Communication
News 3News 4
News 2
April 2000 Async2000-Eilat,Israel 32
Asynchronous Communication
News 3News 4
April 2000 Async2000-Eilat,Israel 33
Asynchronous Communication
News 3News 4
April 2000 Async2000-Eilat,Israel 34
Asynchronous Communication
Is it really AsynchronousCommunication?
April 2000 Async2000-Eilat,Israel 35
Asynchronous Communication
News 2News 3
Bounded buffer is still Synchronous Communication!
April 2000 Async2000-Eilat,Israel 36
Asynchronous Communication
News 2News 3
Solution ?
News 4
April 2000 Async2000-Eilat,Israel 37
Outline
• Asynchronous CommunicationMechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions
April 2000 Async2000-Eilat,Israel 38
Mechanisms for Async Comm
News 2News 3
Solution1: Writer bins the new item when buffer is full
News 4
April 2000 Async2000-Eilat,Israel 39
Mechanisms for Async Comm
News 2News 3
Solution1: Writer bins the new item when buffer is full
News 4
April 2000 Async2000-Eilat,Israel 40
Mechanisms for Async Comm
Solution1: Reader re-reads the old item when buffer is empty
April 2000 Async2000-Eilat,Israel 41
Mechanisms for Async Comm
Solution1: Reader re-reads the old item when buffer is empty
News 3
April 2000 Async2000-Eilat,Israel 42
Mech’s for Async Comm
Solution1 implemented as a “non-blocking FIFO”
(IEEE TC VLSI Newsletter Fall 1998)
April 2000 Async2000-Eilat,Israel 43
Mech’s for Async Comm
News 2News 3
Solution2: Writer overwrites the item when buffer is full
News 4
April 2000 Async2000-Eilat,Israel 44
Mech’s for Async Comm
News 2News 4
Solution2: Writer overwrites the item when buffer is full
But this involves locking the whole buffer!
April 2000 Async2000-Eilat,Israel 45
Mech’s for Async Comm
News 3News 4
Is a (non-blocking) FIFO buffer a proper solution for the News type of data?
April 2000 Async2000-Eilat,Israel 46
Mech’s for Async Comm
News 3News 20
No! News maybe out of date when it reaches Reader
April 2000 Async2000-Eilat,Israel 47
Mech’s for Async Comm
Required Properties:
Total Asynchrony – Reader and Writer, independent motive powers cannot wait
Coherence – no data corruption, thus items cannot be written/read in part
Freshness – Reader must read the item written most recently by Writer
April 2000 Async2000-Eilat,Israel 48
Data Coherence
30
Dec
99
28
Dec
99
April 2000 Async2000-Eilat,Israel 49
Data Coherence
30
Dec
99
30
Dec
99
April 2000 Async2000-Eilat,Israel 50
Data Coherence
30
Dec
99
April 2000 Async2000-Eilat,Israel 51
Data Coherence
30
Dec
99
April 2000 Async2000-Eilat,Israel 52
Data Coherence
30
Dec
99
30
April 2000 Async2000-Eilat,Israel 53
Data Coherence
30
Dec
99
30
Dec
03
Jan
00
April 2000 Async2000-Eilat,Israel 54
Data Coherence
30
Dec
00
30
Dec
03
Jan
April 2000 Async2000-Eilat,Israel 55
Data Coherence
30
Dec
00
03
Jan30
Dec
00
April 2000 Async2000-Eilat,Israel 56
Data Coherence Violation
03
Jan
00
30
Dec
00
April 2000 Async2000-Eilat,Israel 57
Data Freshness
30
Dec
99
April 2000 Async2000-Eilat,Israel 58
Data Freshness
30
Dec
99
April 2000 Async2000-Eilat,Israel 59
Data Freshness
30
Dec
99
April 2000 Async2000-Eilat,Israel 60
Data Freshness
30
Dec
99
03
Jan
00
April 2000 Async2000-Eilat,Israel 61
Data Freshness
30
Dec
99
03
Jan
00
April 2000 Async2000-Eilat,Israel 62
Data Freshness
30
Dec
99
03
Jan
00
April 2000 Async2000-Eilat,Israel 63
Data Freshness Violation
30
Dec
99
03
Jan
00
April 2000 Async2000-Eilat,Israel 64
Async Comm Mechanisms
How to maintain Asynchrony, Coherence and Freshness?
April 2000 Async2000-Eilat,Israel 65
Async Comm Mechanisms
How to maintain Asynchrony, Coherence and Freshness?
Control variables
Data slot 1 Data slot n
ACM
April 2000 Async2000-Eilat,Israel 66
Outline
• Asynchronous Communication
• Mechanisms for Async CommunicationThree and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions
April 2000 Async2000-Eilat,Israel 67
Slot Mechanisms
How many slots is enough?
April 2000 Async2000-Eilat,Israel 68
Slot Mechanisms
How many slots is enough?
One – cannot be both async and coherent
April 2000 Async2000-Eilat,Israel 69
Slot Mechanisms
How many slots is enough?
One – cannot be both async and coherent
Two – can be made async and coherent
but no freshness
April 2000 Async2000-Eilat,Israel 70
Slot Mechanisms
Three or Four Slots are sufficient to achieve freshness
We used algorithms due to Hugo Simpson (BAe)
April 2000 Async2000-Eilat,Israel 71
Three-slot ACMWriter: Reader:
s2
30.12
23.12
27.12
new
read
s1
s3
last
02.01
April 2000 Async2000-Eilat,Israel 72
Three-slot ACMWriter: Reader:
s2
30.12
02.01
27.12
new
read
s1
s3
last
April 2000 Async2000-Eilat,Israel 73
Three-slot ACMWriter: Reader:
s2
30.12
02.01
27.12
new
read
s1
s3
last
April 2000 Async2000-Eilat,Israel 74
Three-slot ACMWriter: Reader:
s2
30.12
02.01
27.12
new
read
s1
s3
last02.01
April 2000 Async2000-Eilat,Israel 75
Three-slot ACMWriter: Reader:
s2
30.12
02.01
27.12
new
read
s1
s3
last02.0103.01
April 2000 Async2000-Eilat,Israel 76
Three-slot ACMWriter: Reader:
s2
30.12
02.01
03.01
new
read
s1
s3
last02.01
April 2000 Async2000-Eilat,Israel 77
Three-slot ACMWriter: Reader:
s2
30.12
02.01
03.01
new
read
s1
s3
last02.01
April 2000 Async2000-Eilat,Israel 78
Three-slot ACMWriter: Reader:
s2
30.12
02.01
03.01
new
read
s1
s3
last02.01
05.01
April 2000 Async2000-Eilat,Israel 79
Three-slot ACMWriter: Reader:
s2
05.01
02.01
03.01
new
read
s1
s3
last02.01
April 2000 Async2000-Eilat,Israel 80
Three-slot ACMWriter: Reader:
s2
05.01
02.01
03.01
new
read
s1
s3
last
April 2000 Async2000-Eilat,Israel 81
Three-slot ACMWriter: Reader:
s2
05.01
02.01
03.01
new
read
s1
s3
last
April 2000 Async2000-Eilat,Israel 82
Three-slot algorithm
Writer: Reader:
wr: d[n]:=input
w0: l:=n
w1: n:=differ(l,r)
r0: r:=l
rd: output:=d[r]
n (new), l(last), r(read) – 3-valued var’s
April 2000 Async2000-Eilat,Israel 83
Three-slot algorithm
differ:
1
2
3
1 2 3
2 3 2
3 3 1
2 1 1
April 2000 Async2000-Eilat,Israel 84
Four-slot ACMWriter: Reader:
newread
23.12
d[0,0]
last
02.01
28.12
d[0,1]
24.12
d[1,0]
30.12
d[1,1]
s[0] s[1]
v[0] v[1]
April 2000 Async2000-Eilat,Israel 85
Four-slot algorithm
Writer: Reader:
wr: d[n,¬s[n]]:=input
w0: s[n]:= ¬s[n]
w1: l:=n || n:=¬r
r0: r:=l
r1: v:=s
rd: output:=d[r,v[r]]
n (new), l(last), r(read) – binary var’s
April 2000 Async2000-Eilat,Israel 86
Outline
• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMsSpeed-independent implementation
• Comparison with FM solutions
• Conclusions
April 2000 Async2000-Eilat,Israel 87
Implementation of ACM
writer readerACM data path (slots)
Writecontrol
Statementlogic
(mutex,latches,
selectors)
startdone start done
Data In Data Out
steering
wr-reqwr-ackw0-reqw0-ackw1-reqw1-ack
r0-reqr0-ack
rd-ackrd-req
ReadcontrolACM control part
April 2000 Async2000-Eilat,Israel 88
Implementation of ACM
writer readerACM data path (slots)
Writecontrol
Readcontrol
Statementlogic
(mutexes,latches,
selectors)
startdone start done
Data In Data Out
steering
wr-reqwr-ackw0-reqw0-ackw1-reqw1-ack
r0-reqr0-ack
rd-ackrd-req
n,r,l
April 2000 Async2000-Eilat,Israel 89
Write Control STG
start+ done- start-
w0-req+ w0-ack+ w0-req- w0-ack+
done+
wr-req+ wr-ack+ wr-req- wr-ack+
w1-req+ w1-ack+ w1-req- w1-ack+
April 2000 Async2000-Eilat,Israel 90
Write Control logic: direct translation from STG
April 2000 Async2000-Eilat,Israel 91
3-slot ACM design
write control mutex read control
differ ® n
reg l reg r
l
rn l r
Rw0Gw0 Gr0
Rr0
w1-req/ack
w0-req/ack
r0-req/ack
April 2000 Async2000-Eilat,Israel 92
3-slot ACM design
write control mutex read control
differ ® n
reg l reg r
l
rn l r
Rw0Gw0 Gr0
Rr0
w1-req/ack
w0-req/ack
r0-req/ack
April 2000 Async2000-Eilat,Israel 93
Differ and register logic
l1
l2
l3
r1
r2
w1-req
r3
differ register
w1-ackn2
n3
n1
April 2000 Async2000-Eilat,Israel 94
3-slot ACM design
write control mutex read control
differ ® n
reg l reg r
l
rn l r
Rw0Gw0 Gr0
Rr0
w1-req/ack
w0-req/ack
r0-req/ack
April 2000 Async2000-Eilat,Israel 95
Write control circuit: STG
INPUTS: wr,Gw0,w0_ack,w1_ackOUTPUTS: w0,wa,w0_req,w1_req
w1_req-
w1_ack- wa+ w0- w1_ack+
wa-
wr- Gw0- w0_ack- w1_req+
w0_req-
wr+
w0_ack+
w0+
w0_req+
Gw0+
April 2000 Async2000-Eilat,Israel 96
Write control ckt: from Petrify
wa
wr Gw0
csc2bcsc2
csc1bcsc1
The writer control circuits of the three-slot ACM
Rw0
w0_reqw0_ack
w1_reqw1_ack
April 2000 Async2000-Eilat,Israel 97
Analogue simulation
April 2000 Async2000-Eilat,Israel 98
3-slot vs 4-slot performance
statements 3-slot min time
ns
4-slot min time ns
w0+w1 4.19 9.39
r0+(r1) 1.38 3.47
Time for control statements
April 2000 Async2000-Eilat,Israel 99
Other analyses of ACM designs
• Response time analysis for Write and Read using stochastic Petri nets (tool PET by Xie and Beerel):
The circuit response varies with the relative frequency of Write/Read, e.g. higher Write frequency increases the chance for Read to hit arbitration and hence be delayed.
April 2000 Async2000-Eilat,Israel 100
Response time analysis
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
r_other/w_other
AC
Mtim
e [n
s]
w r i t e r
r ea d e r
April 2000 Async2000-Eilat,Israel 101
Other analyses of ACM designs
• Digital simulation using Verilog models for Writer, Reader and ACM:
The circuit is a coherent, fresh and non-blocking mechanism. Clear indication of data over-writing (skipping) and re-reading (olding)
April 2000 Async2000-Eilat,Israel 102
Digital simulation
time (ns)400.0 450.0 500.0 550.0 600.0 650.0 700.0
Din
Dout
00 01 02 03 04 05 06
00 01 00 01 00 03 00 04 00 04 00 06
time (ns)2700.0 2750.0 2800.0 2850.0 2900.0 2950.0 2994.7
Din
Dout
20 21 22 23 24 25
00 21 00 24 00 24
April 2000 Async2000-Eilat,Israel 103
Digital simulation
time (ns)400.0 450.0 500.0 550.0 600.0 650.0 700.0
Din
Dout
00 01 02 03 04 05 06
00 01 00 01 00 03 00 04 00 04 00 06
time (ns)2700.0 2750.0 2800.0 2850.0 2900.0 2950.0 2994.7
Din
Dout
20 21 22 23 24 25
00 21 00 24 00 24
April 2000 Async2000-Eilat,Israel 104
Digital simulation
time (ns)400.0 450.0 500.0 550.0 600.0 650.0 700.0
Din
Dout
00 01 02 03 04 05 06
00 01 00 01 00 03 00 04 00 04 00 06
time (ns)2700.0 2750.0 2800.0 2850.0 2900.0 2950.0 2994.7
Din
Dout
20 21 22 23 24 25
00 21 00 24 00 24
April 2000 Async2000-Eilat,Israel 105
Digital simulation
time (ns)400.0 450.0 500.0 550.0 600.0 650.0 700.0
Din
Dout
00 01 02 03 04 05 06
00 01 00 01 00 03 00 04 00 04 00 06
time (ns)2700.0 2750.0 2800.0 2850.0 2900.0 2950.0 2994.7
Din
Dout
20 21 22 23 24 25
00 21 00 24 00 24
April 2000 Async2000-Eilat,Israel 106
Digital simulation
time (ns)400.0 450.0 500.0 550.0 600.0 650.0 700.0
Din
Dout
00 01 02 03 04 05 06
00 01 00 01 00 03 00 04 00 04 00 06
time (ns)2700.0 2750.0 2800.0 2850.0 2900.0 2950.0 2994.7
Din
Dout
20 21 22 23 24 25
00 21 00 24 00 24
April 2000 Async2000-Eilat,Israel 107
Digital simulation
time (ns)400.0 450.0 500.0 550.0 600.0 650.0 700.0
Din
Dout
00 01 02 03 04 05 06
00 01 00 01 00 03 00 04 00 04 00 06
time (ns)2700.0 2750.0 2800.0 2850.0 2900.0 2950.0 2994.7
Din
Dout
20 21 22 23 24 25
00 21 00 24 00 24
April 2000 Async2000-Eilat,Israel 108
Other analyses of ACM designs
• Stochastic analysis of skipping and olding using Generlised SPN (GSPN) tool:
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
0 10 20 30 40 50
rd_extra_ACM / wr_extra_ACM
Pro
bab
ilit
y
data loss
data re-reading
April 2000 Async2000-Eilat,Israel 109
Outline
• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementationComparison with FM solutions
• Conclusions
April 2000 Async2000-Eilat,Israel 110
Comparison with FM solutions
• Fundamental Mode designs for 4-slot were proposed by H. Simpson and E. Campbell
• Writer and Reader time (with individual motive powers) their wr, w0, w1 and r0, r1, rd operations, allowing enough time for potential m/stability to settle on control variables n, r, l
April 2000 Async2000-Eilat,Israel 111
Comparison with FM solutions
Self-timed (I/O mode) design: • can potentially run faster than the FM design• makes it possible to operate in FM with
“practically bounded” Read and Write control actions
Theoretical possibility of unbounded metastability => trade-off between temporal independence and data coherence
April 2000 Async2000-Eilat,Israel 112
Outline
• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutionsConclusions
April 2000 Async2000-Eilat,Israel 113
Conclusions
• Speed-independent VLSI (AMS 0.6m CMOS) implementation of 3- and 4-slot ACMs for News (reference) data transfers
• Minimum granularity of “blocking” – a binary variable
• “Practical boundedness” of Slot Acquisition Time• For non-handshake interfaces “done’s” can be
dropped• What is the right size of data blocks for such
ACMs?
April 2000 Async2000-Eilat,Israel 114
VLSI design layout
April 2000 Async2000-Eilat,Israel 115
VLSI Design layout
April 2000 Async2000-Eilat,Israel 116
And now …
April 2000 Async2000-Eilat,Israel 117
Hag Sameah!
Everybody to the
C