Approaches for Power Management Verification of SoC Having Dynamic Power and Voltage Switching

7/31/2019 Approaches for Power Management Verification of SoC Having Dynamic Power and Voltage Switching

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Approaches for Power Management verification of SoC

having dynamic power andvoltage switching

Prabhu Bhairi

Texas Instruments


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Agenda

Overview of low power design

Why low power verification?

Limitation of traditional simulators.

Tools and flows at various stages of design cycle Flow details Pros cons

Conclusion


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Typical Low Power Design Desc. Design Size > 20 Million gates

Multiple Voltage Domains and Power Domains

Many Always ON Paths

Lots of Power Switches, Isolations and Level Shifters and Always On buffers

Many Retention Flops

Power Management : Shutdown/Sleep: Voltage Domains and Power Domains Retention Schemes: Multiple retention flops

IP Intensive More than 100 IPs


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Dynamic Power and voltage switching

PD2

Alwayson

PD1

PD3

On State

VD2

VD1

OFFON

PD2

Alwayson

PD1

PD3

LP State1

VD2

VD1

VD2

VD1PD2

Alwayson

PD1

PD3

LP State2

PD2

Alwayson

PD1

PD3

LP State3

VD1


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Limitations There is no mechanism to partition design into multiple voltages and

domains.

Traditional simulators insensitive to power states of the device. Simulator engines does not recognize

1. Voltage changes.2. Retention behavior of logic/memory

Limitations of Traditional Simulators


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What is power aware Simulation?

What is Power Aware Simulation ? Mimicking the power down/wakeup behavior at RTL/Gate level simulation.

Why is Power Aware Simulation needed ? Todays complex SoC designs have considerable logic implemented for

Power Management. Most of the PM logic can be implemented at RTL/Gate level. Important to find the critical bugs at early stages in the design cycle .


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Approaches of Low power verification

1. Dynamic/simulator based verification

2. Static/Structural Verification

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Dynamic/simulator based verification approaches

1. Simulator platforms RTL level(PARTL) : Power Aware RTL simulations-UPF/PCF/CPF Gate Level(PAGLS): Power Aware gate level simulations

2. Emulator platform RTL Level : Power aware verification UPF/PCF/CPF based Gate Level: Power aware gate on accelerator platforms (Zero delay )

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External IP flow

SoC flow

Top Level SoCRTL+ Internal

IPs

Simulation

External IPRTL

CompilationCompiled

RTL

IP level

Flow

Deliverableto SoC team

Compilation


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External IP flow

SoC flow

Top level SoC RTL

+ internal IPs

Compile

PA generator

Simulator + PLI

External IPRTL

Compiled library

Compiled

library

HM Power Intent

Assertions

IP Level

FlowCompile

Top levelPower Intent


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Requirement of PARTL tools for SoC

1. Standard, inheritable and reusable (across all phases of the design cycle)power constraint specification

2. The constructs to have robust power intent specification3. Handling Multi Vendor IPs (simulator specific Compiled RTL) with in-house

logic in mixed HDL mode.4. The Multiple Retention scheme, schemes could be vendor specific.5. Low coverage at SoC level, cannot cover every flip flop and every signal by

SoC level self checking scenario simulation.1. Support of assertions

6. Extract the info about Retention flops, Latches, always on signals etc fromRTL using the tool

7. Handling behavioral models.


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Pros and Cons of PARTL

Pros . Highlight issues very early in design cycle- Before RTL freeze. Easy to debug compared to other platforms. Run times are better than PAGLS

Cons No mechanism to validate the PCF files. Run time 2 to 3x slower than normal RTL simulation Tools are not very robust yet.

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What is power aware Gate

What is Power Aware gate? It is a netlist with power switches and cells with power

pins

Why is Power Aware gate? Lot of power management features will be implemented

by BE tools .

This netlist has all the switches and power connection socan catch any potential issue in power featureimplementation


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External IP flow

SoC flow

Top Level SoCPower Netlist

Simulation

External IPpower Netlist

CompilationCompiled

library

IP level

Flow


Compile

Power awaremodeled cell

libraries


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Pros and Cons of PAGLS

Pros . Very close to final design hence best candidate to catch issues. Will catch any issue in BE implementations and power constraint file issues No Power constraint creation effort

Cons Run time and memory foot print 4 to 5x slower compared to PARTL

Netlist is ~2 times bigger than normal netlist Very late in the design cycle. Debugging is very difficult. Developing the power aware library models is effort intensive.

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Faster run time ?Run application

scenarios ?

Enable better PM feature spacecoverage! How?

Use an emulation platform!!!

Power aware emulations with RTL


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Power-Aware Emulation

Target cycletime

reductionhere


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External IP flow

SoC flow

Top Level SoCPower netlist

Emulator run

External IPpower netlist

CompilationEmulatordata base

IP level

Flow


synthesis

Power awareEmulator lib

cells


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Advantages Randomized values may create a worst case scenario compared to x in

simulations

Inherently faster platform.

System level use-cases for PA features can be planned and executed faster.

Enables us to do full coverage due to the speed the platform offers.

Limitations There is no real x hence few fails may be masked

Many features not yet fully supported on production version in Emulations

platforms Debugging is tedious

Vulnerable to power constraints issues like PARTL if Emulation RTL flow isused


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Static/Structure verification

1. Lint tools to verify PM connectivity

2. Static low power verification on power netlist

3. STA based static checks

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Conclusion

Low power requirements have undoubtedly exposed a new challenge inDV/EDA community.

Lot of flows and EDA support already exist. Each of them have there own benefit and limitations

Given all this Silicon still remains the best platform for low power verification,

Pre SI DV: we just do not have a perfect solution today because of enormous complexity in the design. we should continue focus onimprovement on flows and tools.

Simulation speed with low power enabled worsens even more.

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BACK UP

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Key words in low power implementation Power domain

Voltage domain

Isolation cell Tie cell, ISO latch

Level shifter

Retention flip/flop, latch

Retention memory

Power switch

Wakeups

Always on logics/domains

IO iso/wakeup23


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Low Power Verification Challenges atSoC level and solutions

1. Standard, inheritable and reusable (across all phases of the design cycle)power constraint specification

Soln:- Supports the standard power specification format (like UPF) If any legacy power intent is specified for an IP

Ex: APF->UPF, PCF->UPF conversion is seamless to user .


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Low Power Verification Challengesat SoC level and solutions

2 Support of constructs to have robust power intent specification.

Soln:- Support for wild character

Ex *iso_cel* for specifying always on signals

Support of expressions for power control signals Ex: A xor B for shutdown.

Supports specifying the source, destination and cell kind of constructs for always

on path tracing.


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3 Handling Multi Vendor IPs (simulator specific Compiled RTL) with in-houselogic in mixed HDL mode.

Soln:- RTL cannot be provided from external IP vendors Flow should not demand RTL

Supports simple flow for delivery of IP DB readable by tool. Generation of power aware DB needs to be simple and no major changes to

the existing IP flow required. UPF at IP level to be reusable in top level simulations


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4 Support for Multiple Retention scheme, schemes could be vendor specific.

Soln:-

Tool should be able to read the asic cell models of retention flops and generatethe Power Intent. Input could also be given by a generic UPF format in the early stages of the

design


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5 Low coverage at SoC level, cannot cover every flip flop and every signal bySoC level self checking scenario simulation.

Soln:- Use of built in assertions for the following cases can reduce the debugging timeand help in capturing bugs, which can be missed by self checking testcases X propagation on always on paths Retention flop/Latch protocol violations during save or restore. Low Voltage wiggling indicators. Power Islands States and Sequence of Switching.


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6 Cross check with gate netlist.

Soln:-

Extract the info about Retention flops, Latches, always on signals etc from RTLusing the tool Extract similar info from a back end tool, Compare the two to confirm the implementation.


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7 Handling behavioral models and initial blocks

Soln:-

Corrupting behaviar models not required as it takes unnecessary toll onperformance Only output corruption is good enough Initial blocks need to be reevaluated on each wakeup

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Approaches for Power Management Verification of SoC Having Dynamic Power and Voltage Switching