DesignCon 2013

Applying Microwave Techniques to Digital Systems: A Simple Case Study

Andrew Becker, Cray Inc.andyb@cray.com

Michael Higgins, Cray Inc.mfh@cray.com

Dr. Michael Steinberger, SiSoft Inc.msteinb@sisoft.com

Paul Wildes, SiSoft Inc.pwildes@sisoft.com

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AbstractTechniques well known in the field of RF/microwave analysis can be applied with good effect in high speed digital design. Often the greatest obstacles are not technical, but arise from differences in methodology and terminology in the microwave area. This paper seeks to help bridge that gap with a case study, demonstrating the application of a long-established microwave filter design (drawn from a classic RF text) to a very current problem in high speed digital design: the conditioning of a processor’s clock source to obtain high duty-cycle accuracy. The solution, a four-pole Chebyshev filter, is robust and compact. It is implemented in standard PCB technology, without any unusual spacing or handcrafting techniques, and with no discrete components. Measured data is presented from a proof-of-concept test board, and from the final production board.

Authors’ BiographiesAndrew Becker currently works for Cray Inc. as a senior signal integrity engineer where he has been employed since 2004. Previously he has worked on 40Gbps long-haul transceivers for StrataLight Communications (now Opnext) in the SF Bay area, and for Lucent Technologies, Bell Laboratories in Murray Hill, NJ. Mr. Becker has a Master's Degree in Electrical Engineering from Stevens Institute of Technology in Hoboken, NJ and a BS in Physics from Binghamton University, State University of New York.

Michael Higgins is a Principle Engineer at Cray Inc. He has over 20 years of experience designing, analyzing, and validating custom processors, memory subsystems, and high-speed communication channels for supercomputers while working for Cray Research, Inc., Silicon Graphics, Inc., and Cray Inc. Mr. Higgins holds a B.S.E.E. from the University of Minnesota.

Michael Steinberger, Ph.D., Lead Architect for SiSoft, has over 30 years experience designing very high speed electronic circuits. Dr. Steinberger holds a Ph.D. from the University of Southern California and has been awarded 14 patents. He is currently responsible for the architecture of SiSoft's Quantum Channel Designer tool for high speed serial channel analysis. Before joining SiSoft, Dr. Steinberger led a group at Cray, Inc. performing SerDes design, high speed channel analysis, PCB design and custom RAM design.

Paul Wildes is a consulting engineer with SiSoft Inc. where his work focuses on signal integrity in high-end communications and networking platforms. He spent more than twenty years designing circuits and channels at Cray Inc. Mr. Wildes received the BS and MS degrees in Electrical Engineering from the University of Wisconsin, and has been awarded 2 U.S. patents. Previously he developed semi-custom IC chips at Bell Labs, and did Unix kernel development at Astronautics Corporation in Madison, Wisconsin.

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IntroductionUsing as a guide the publication of key reference works and the growth of commercial applications, one could say that the RF/microwave field came of age during the 1940s and 50s, with the advent of radar, satellite communications and broadcast television, systems operating in the 100MHz to a few GHz range [1][2]. Similarly, digital electronic systems began to flourish in the 1960s and 70s, as mainframe and supercomputers were joined by minicomputers and the soon-to-be ubiquitous microprocessor. These digital systems had clock speeds of 10-80MHz [3]. Clearly, although sharing a common basis of fundamental electronics, these two disciplines inhabited very different space in terms of frequency content.

In recent years, however, the frequencies of digital systems have begun to overlap the RF/microwave space, in clock rate and in communications technologies such as SerDes transceivers. SerDes circuits now commonly operate in the 3-5GHz region (6-10 gigabits/second) and designs are being demonstrated in the 14-20GHz range (28-40Gb/s) [4].

20G

15G

10G

5G

1G

Satellite KU band

RF StandardsDigital Communication Standards

Satellite X band

Satellite C band

Police radar

Microwave oven

TV VHF (ch 7-13)

DDR3 datarates

PCIe 2.0 raw bitrate

PCIe 3.0

10GigE

25G

ECR-90 radar

Surface Movement Radar K band (to 40G)

SATA 3.0

IEEE P802.3bj

Figure 1: Frequency ranges for select RF and digital standards

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Although RF/microwave design is a well-developed and mature field, there are factors that can make it difficult to apply RF techniques to digital design. The terminology that has developed in the two fields is very different, both for communicating concepts and for documenting specifications. For example, the deviation from ideal in a clock source is often discussed by digital designers (and component suppliers) as jitter, specified in picoseconds RMS; output levels are defined in terms such as ‘ECL’ or ‘low-voltage CMOS’, with voltage levels specified. However, in RF design, specifying essentially similar components, variance in a frequency source is usually called ‘phase noise’, and is specified in dBc/Hz (power in decibels, relative to carrier power, integrated over a one-hertz band); output is expressed not in voltage levels but in dBm (output power expressed in decibels relative to 1 mW). Converting between these two sets of specifications is nontrivial, and often the additional information required to make the conversion is not readily available. This makes the comparison and evaluation of similar function components problematic.

A further hindrance to using RF tools for digital design is the sheer size and scope of RF problems and techniques. A quick tour of a typical RF engineering text shows major sections devoted to waveguides, three-dimensional structures such as resonators and power dividers, vacuum tube devices, antenna design, and so forth. The information relevant to digital communication design is a very narrow slice through this field, and sometimes difficult to discern. CAD tools conceived and optimized for use in designing cell phones, satellite antennae, or three-dimensional waveguide structures, are often simply too complex, feature-rich and difficult to learn (and too expensive) for a typical digital designer to consider.

Hence, while the math and physics behind the two fields is the same, there is a significant gap between the design worlds of RF/microwave and digital systems. This paper seeks to help bridge that gap, by demonstrating the application of a long-established microwave filter design technique (drawn from a classic RF text) to a very current problem in high speed digital design: the conditioning of a processor’s clock source to obtain high duty-cycle accuracy. And while the analysis and design techniques are drawn from the RF world, the implementation is classic standard digital PCB design. In fact, this is one of the most intriguing aspects of this particular case study: the solution was implemented with essentially no additional cost to the compute system involved.

Design Challenge Part 1: Digital ViewSpecifications for clock sources are a key part of any digital system design. In addition to the targeted frequency, a critical parameter is the duty cycle D, defined as the ratio of the clock ‘high’ time to ‘low’ time. Ideally duty cycle is exactly 50%; duty cycle error will degrade any circuit that utilizes both edges of the clock, since the performance will be limited by the shorter of the two time segments or ‘phases’ (clock high and clock low). Common circuits that may utilize both edges of a clock source are processor pipeline

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stages and SerDes transceivers. Figure 2 shows how pipelined logic may be designed with logic clouds (labeled ‘A’ and ‘B’) separated by latch stages that use alternate edges of the clock having duty cycle D. It can easily be seen that the overall system performance will be limited by the shorter of the two clock phases; hence the direct dependence upon duty cycle accuracy.

A B𝛕

T

D = 𝛕/T

Figure 2: Duty Cycle Impact on Pipelined Logic Performance

In the Spring of 2006, supercomputer maker Cray Inc. completed the design of a new large system code-named BlackWidow [5]. This system featured a fully-custom processor chip designed at Cray, which incorporated multi-core floating-point custom blocks. The custom block design was highly pipelined, and consecutive stages utilized alternating edges of the core clock. System floating-point performance depended upon duty cycle accuracy of this clock.

The clock source for the processor core was required to be in the 1.2-1.6GHz range. At the time, components targeted at RF applications were in the range of 2-3GHz and higher, and also tended to be less suitable for processor board use: they were generally found in large, hermetic packages, using through-hole technology. Some required higher voltages than typically available in a digital system (or some non-standard voltage); and they were also quite expensive. Components targeted for digital communications systems were available in smaller surface-mount packages, at reasonable cost, based on SAW (Surface Acoustic Wave) oscillator technology. These components, however, were only available in the 500-900MHz range.

The solution developed for this project was to build a clock-doubling circuit, and use a commonly available SAW oscillator running at half the target reference rate. This was accomplished with a simple wave-shaping circuit. Two copies of the clock are fed into an exclusive-OR gate. One of the legs has additional routing, equal to one quarter of the clock period. The resulting output is a double-frequency signal (Figure 3).

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clockdelayed clock

XOR - 2x clock

Figure 3: Clock Doubling Circuit

This circuit now satisfies the frequency requirement of 1.2-1.6GHz, using a commonly-available 600-800MHz SAW oscillator as the frequency source. The problem that must then be solved is duty-cycle distortion, a critical issue for this particular design. At any particular center frequency f0 the circuit can introduce some distortion due to process variability of the delay line or differences in rise/fall delays. Furthermore, a requirement for the system was to be able to accommodate the entire range of possible clock frequencies, in order to achieve the highest possible performance when the system was brought up. With a fixed delay in the doubling circuit, running at any frequency other than the target f0 used for the delay line layout would necessarily introduce significant duty cycle error.

At this point the processor chip was already designed, and the readily-available clock source and doubling circuit described produced unacceptable duty cycle distortion. So the question is: Can the duty cycle distortion be corrected on the PCB, before delivery to the processor chip? In order to answer that question, we must first look at the problem in the frequency domain.

Design Challenge Part 2: Recasting the Problem in the Frequency DomainAt this point, viewing the problem in the frequency domain sheds considerable light on the problem and points to a possible solution. A perfect single-frequency clock source would simply be a sine wave with all the energy at the fundamental frequency (i.e. the first harmonic). Additional energy at the higher order odd harmonics (3rd, 5th, etc) gives the clock waveform sharper edges, more closely approximating a square wave. An ideal square wave has frequency components at all odd harmonics. When duty cycle distortion is introduced (duty cycle not equal to 50%), unwanted energy begins to appear in the even harmonics [6][7].

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-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

Duty Cycle != 50% - Nonzero Energy in Even Harmonics

Signal Harmonics

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

Duty Cycle = 50% - Odd Harmonics Only

Signal Harmonics

f t( ) = 4π

1nsin 2nπ t

T⎛⎝⎜

⎞⎠⎟n=1,3,5,...

∞

∑

f t( ) = τT+ 2π

1nsin nπτ

T⎛⎝⎜

⎞⎠⎟n=1

∞

∑ cos 2πnT

t⎛⎝⎜

⎞⎠⎟

Figure 4: Pulse Wave Harmonic Content Due to Duty Cycle Variation

An ideal band-pass filter passes signal energy with frequencies inside the pass band, and rejects frequencies in the stop band. Certain filter designs have pass bands that repeat at multiples of the center frequency; these are periodic bandpass filters. This brings us to a key observation, and the basis for the corrective design:

A microwave bandpass filter can be made periodic, passing odd harmonics and suppressing even harmonics. Therefore - passing a clock signal through a (periodic) bandpass filter will

suppress duty cycle distortion.

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The Solution, Part 1: Microwave Filter DesignThis section is intended solely as a brief introduction to the design of microwave bandpass filters; the subject is covered in depth in chapter 8 of [8], as well as in numerous other well written texts.

As shown in Figure 5, a microwave bandpass filter is modeled either as a set of series resonators connected by impedance inverters or shunt resonators connected by admittance inverters. The resonators are expected to all have the same resonant frequency, resulting in what is called a synchronously tuned filter design. The design process is a matter of choosing the structures and dimensions for the resonators and impedance/admittance inverters.

K45K01RAX(ω)

K34

X(ω)K23

X(ω)K12

X(ω)RB

a. Series resonators and impedance inverters

GA J01 B(ω) J12 B(ω) J23 B(ω) J34 B(ω) J45 GB

b. Shunt resonators and admittance inverters

Figure 5: General configuration for synchronously tuned four pole bandpass filters

The concept of an impedance/admittance inverter is not as widely used as that of a resonator, and therefore will be introduced first. The idea behind an inverter is that the impedance or admittance presented by the inverter’s input to the rest of the circuit is the reciprocal of the impedance/admittance at the output of the inverter, as shown in Figure 6. Therefore if there is an open at the output of the inverter, the input to the inverter presents a short to the rest of the circuit; if there is a short at the output of the inverter, the inverter presents an open to the rest of the circuit.

K ZbZa = K2/Zb

Impedance Inverter

J YbYa = J2/Yb

Admittance Inverter

Figure 6: Impedance inverter and admittance inverter

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The filter bandwidth is determined by the source/load resistance, the characteristic impedance of the resonators, and the values of the impedance or admittance inverters. Larger values for the inverters create more coupling between the resonators and therefore wider filter bandwidths.

Table 1 shows some of the circuits that approximate an impedance or admittance inverter over at least a narrow frequency band. Some of the inverter types use a negative value for an inductor or capacitor. These circuit elements are not implemented directly. Instead, they represent inductance or capacitance that needs to be removed from the resonator the inverter is attached to. For example, if a capacitor type impedance inverter with capacitance value C is used to connect two series resonators, then C farads of capacitance must be removed from each of those resonators.

Impedance Inverters Admittance Inverters

λ/4 λ/4

λ/4 λ/4

-L -L

L

L

-L -L

-C -C

C -C -C

C

Table 1: Impedance and admittance inverters

The quarter wave transmission line admittance inverter was chosen for the design reported in this paper because it tends to produce strong coupling between resonators, and therefore comparatively wide filter bandwidths. When implemented as printed structures in a PC

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board, it would not have been possible for the other types of inverters to produce the required inverter values.

At its quarter wave frequency, the value of an admittance inverter built using a transmission line with characteristic impedance Z will have a value J = 1/Z.

Table 2 shows a few of the circuits that could be used as resonators. Many other choices are possible, especially if one includes resonant waveguide cavities.

Series Resonators Shunt Resonators

λ/4 λ/4

λ/2 λ/2

Table 2: Series and shunt resonators

The shorted quarter wave resonator was chosen for this design because it resonates at every frequency for which its length is an odd multiple of a quarter wavelength. This property therefore meets the design requirement identified in the previous section.

Synchronously tuned microwave bandpass filters are designed from a unity impedance, unity bandwidth prototype low pass filter. The resonant frequency of the resonators in the bandpass filter is taken to correspond to DC for the low pass prototype, and the fractional bandwidth is used to scale the element values. The fractional bandwidth is the bandwidth of the filter divided by the center frequency. For the design in this paper, the fractional bandwidth ωf = (1.6-1.2)/1.4 = 0.29. For a four pole filter, the low pass prototype is shown in Figure 7.

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g0

g1 g3

g2 g4 g5

Figure 7: Four pole prototype low pass filter

Reference [8] gives the normalized low pass filter element values for a 0.01 dB ripple Chebychev filter and a 0.1 dB ripple Chebychev filter, whereas the design target chosen was a 0.05 dB ripple Chebychev filter, thus providing a minimum passband return loss of 20 dB. The low pass prototype element values are:

Ripple g0 g1 g2 g3 g4 g50.01 dB 1.000 0.7128 1.2003 1.3212 0.6476 1.10070.1 dB 1.000 1.1088 1.3061 1.7703 0.8180 1.3554

Table 3: Chebychev filter low pass prototype element values

The configuration chosen for the filter is shown in Figure 8 in the next section. This is a bandpass filter with shunt resonators and admittance inverters, as shown in Figure 5b. To minimize the number of circuit elements, we chose to couple the outer resonators directly to the input and output. In effect, this sets J01 = J45 = 1/50Ω. In order for this element value to work, the impedance of the resonator, Zstub, must be chosen to obtain the desired bandwidth. Evaluating the equations from Figure 8.02-4 of [8], the resulting transmission line impedances are:

Filter Zstub Zinv1 Zinv20.01 dB ripple Chebychev 60Ω 61.8Ω 84.2Ω0.1 dB ripple Chebychev 40Ω 53.6Ω 67.8Ω

Table 4: Transmission line impedances for four pole filter

The Solution, Part 2: Filter Implementation

Filter Implementation - General Characteristics

It was shown in the previous section that a microwave filter may be created by alternating stages of resonators and impedance inverters. The choice of resonator/inverter designs is made to obtain odd-harmonic resonance; wide bandwidth is obtained through strong coupling. The filter prototype chosen is a direct-coupled bandpass filter using quarter-wavelength (i.e. λ/4) connecting lines and stubs. In this design, the connecting lines act as impedance inverters, and the stubs are resonators.

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Since the goal of this design is to filter a clock source for a digital processor residing on a standard printed circuit board, a filter implementation should be chosen that is well-suited to PCB technology. Buried stripline is an obvious choice, since impedance and routing length can be tightly controlled, and the nearby ground planes will contain the fields.

A four-stage filter of this type would have the following general form:

All filter sections are λ/4 in length

Zstub

normal 50Ω lead-in route

Zinv1 Zinv2 Zinv1

normal 50Ω lead-out route

ground vias

Figure 8: General form of PCB filter implementation

As can be seen in the above figure, every section of the filter is a stripline segment of length one-quarter wavelength. The design target for the center frequency f0 was 1.2-1.6GHz, which translates to a wavelength of approximately 3.6-4.8” (93-123mm), or a λ/4 of 0.9-1.2” (23-31mm). Since the physical length of the segments can be controlled to a fraction of a percent of the length, the only significant variation in f0 will arise from error in propagation velocity, which is proportional to dielectric constant dk. Even in inexpensive PCB materials dk is controlled well enough to not significantly degrade the performance of the filter.

For more efficient layout, it can easily be seen that the general form of the PCB implementation may be collapsed by folding the stub sections to be in-line. With careful layout, the connecting sections can be slightly modified to connect the folded sections, without increasing the total routed length from the λ/4 target. The following diagram shows two possible configurations.

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Folded filter: stacked

Folded filter: flat

Figure 9: Folded forms for PCB filter: stacked (top), flat (bottom).

Simulating Filter Performance

Since this filter is simply a series of transmission lines, network simulation is used to examine alternatives and tradeoffs. The filter characteristics will be determined by the relative values of the section impedances as shown in Figure n above, namely Zinv1, Zinv2 and Zstub. The impedances will be changed by changing the respective trace widths. Due to the well-behaved nature of this filter design, optimization can begin with a simple assumption of matching widths (all impedances the same). The baseline chosen was 10mil line width, yielding an impedance of 41Ω. The key filter characteristics of bandwidth and 3dB frequency can be read directly from an insertion loss plot; return loss is also easily found. Since this filter is strongly coupled and fairly wide bandwidth, there is significant flexibility in the values chosen for the filter design parameters. In fact, the naive choice of 10mils for the widths of all three section types gives a reasonable result:

Figure 10: Simulated Filter Response - Initial Design

Varying the resonator width from 10-30mils, and sweeping the widths of the connecting segments from 4.0 to 10.0mils, we can see a distribution of bandpass characteristic shapes:

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Figure 11: Simulated Filter Response - Parameter Sweep

Keeping in mind the nature of the incoming signal and the desired effect, the filter was optimized to have the greatest stop-band rejection and the sharpest rolloff. Within the confines of the PCB design parameters, the resulting values chosen were 7.0mils (Zinv1=50Ω), 5.5mils (Zinv2=56Ω) and 30mils (Zstub=19Ω). The resulting filter response is shown below, with key measurements indicated. The filter has a 3dB bandwidth of 580MHz (𝜔c/𝜔0 = 0.4), with return loss lower than -20dB in the pass-band. Evaluating the stop-band where the filter has the same bandwidth shows a rejection of greater than 50dB. This is excellent performance for this application.

Figure 12: Simulated Filter Response - Optimized Design to 4GHz

Since this filter is based on fractional-wavelength design, the response is periodic; the response up to 10GHz is shown in Figure 13.

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Figure 13: Simulated Filter Response - Optimized Design to 10GHz

Filter Prototype

As a proof-of-concept, a prototype was fabricated using an inexpensive quick-turn PCB service; hence the following limitations were in effect:

1. Built with FR4 material2. Six layers or fewer3. Simple through-via construction4. No multiple vias for ground connections5. Minimum trace width 7mil

Due to the minimum trace limitation, the target trace widths were all scaled up; the prototype was implemented with widths of 7, 9, and 40mils. The prototype board contained test circuits for the clock doubling and fan-out circuits, as well as the test four-pole filter. The filter could be connected to the output of the clock doubler, or tested stand-alone by a network analyzer. The layout chosen was the folded/stacked design shown above. The board specifications and layout are shown below.

Filter Test Board ConstructionFilter Test Board ConstructionFilter Test Board ConstructionDimensions Material Stackup

3x5” (76x127mm) FR4 6 layers: top/vcc/sig1/sig2/gnd/bot

Table 5: Filter Test Board Construction

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Figure 14: Filter Test Board Layout

Filter Final Design

To improve the filter performance over the prototype, two key design features were employed. The first improvement was in the signal reference planes. For SerDes performance, the board design had ground planes both above and below the signal layers that were dedicated to SerDes routing. So to obtain the best filter results, the filter was laid out on a single layer of one of the high-performance signal layers. Therefore it had a close reference plane both above and below, the reference planes were ground (not a power plane, which would yield sub-optimal performance) and there were no intermediate vias in the direct-coupled signal path.

The second design improvement was in the ground vias at the end of the resonators. On the prototype board, there was only a single (large diameter) via for each resonator. The significant parasitic inductance of the via at gigahertz frequencies caused noticeable degradation of the filter performance, especially in the stop-band. In the production design, there was a field of six small diameter vias surrounding the end-cap of each resonator. The reduced impedance of this scheme made a very large improvement in filter performance.

Figure 15: Resonator grounding: prototype (top), final design (bottom)

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The final layout was implemented in the folded/flat configuration, shown in Figure 16.

Figure 16: Bandpass Filter, Final Design

The folded/flat configuration was chose because the design fit into a narrow segment of space along the edge of the board that was vacant. Because of the density of the compute board routing, and the large number of through-vias used for grounding the resonators, it was highly desirable to keep the filter out of the main part of the board. The following graphic shows how small the filter is on the scale of the full board.

Figure 17: Final compute board with filter

Filter Performance - Measured Data

Measurements were taken on both the test board and the final production board. The test board demonstrated that the design should operate as intended, although the stop-band response was poor due to the inefficient grounding structures in the resonators. With the layout improvements described in the previous section, the production circuit achieved very good correlation to the optimized simulation results. Figure 18 shows measured data in the dark colors, with simulated results overlaid.

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Figure 18: Measured Filter Response - Prototype (top), Final Design (bottom)

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Microwave Designer’s NotebookThis section offers additional ideas for applying microwave circuits to digital designs. These ideas are not necessarily suited for extensive application in a single design, but may offer practical solutions to unusual problems. None of these ideas are fully worked out, as the details will depend upon the application; this is beyond the scope of this paper. Instead, the goal is to point readers toward additional resources that may prove useful in special cases.

Directional Coupler

A directional coupler is simply a short length of coupled transmission line. This structure samples the electromagnetic wave going in one direction while ignoring any wave going in the opposite direction. Thus it is generally used either to measure the signal from a source, independent of its load, or to measure the waves reflected from a load.

As illustrated in Figure 19, a directional coupler has four ports: input, output, coupled, and isolated. While most of the energy incident at the input port travels to the output port, some of that energy is coupled to the coupled port. None of the energy incident at the input port is coupled directly to the isolated port. However, energy incident from the output port is coupled to the isolated port (but not directly to the coupled port). Thus, the isolated port is almost always terminated with the characteristic impedance of the coupler so as to sup- press the effects of waves reflected from the output port back into the coupler.

Input Port Output Port

Coupled Port Isolated Port

Figure 19: Edge coupled directional coupler

A directional coupler might be useful, for example, to detect whether a card is present at the other end of a cable or backplane connection driven by a source on a PC board. Figure 20 shows a directional coupler placed near the edge of a PC board with its coupled port facing the connector. A diode detector connected to the coupled port drives a low frequency amplifier to provide an indication of the energy being reflected back from the connector. If a load is present at the opposite end of the connection, then relatively little energy will be reflected back toward the board and coupled into the diode detector, producing a logic “0” at the output of the amplifier. If, however, no load is present, then a great deal more energy will be reflected back toward the board, producing a logic “1” at the output of the amplifier.

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Board Not Connected

Figure 20: Board-edge reflection detector

The design parameters for a directional coupler are its length, dielectric thickness, conductor width, and conductor spacing. The length is determined by the frequency at which maximum coupling is desired. Maximum coupling will occur at frequencies for which the length of the coupler is an odd multiple of λ/4, and essentially zero coupling will occur when the length is an even multiple of λ/4. So, for example, when detecting a data signal, it would be a good idea to make the coupler a quarter wavelength long at a frequency equal to half the data rate, or in other words a half wavelength long at a frequency equal to the data rate.

The characteristic impedance of the coupler and the maximum coupling are determined by a combination of the dielectric thickness, conductor width, and conductor spacing. Since all three design parameters have a significant effect on both the characteristic impedance and the coupling, they need to be determined jointly. The design procedure is given in [8], section 13.02, and uses nomograms from section 5.05 in that book.

Low Pass and Notch Filters

Other types of microwave filters are practical in a PC board. Figure 21 is the configuration for a low pass filter using quarter wave sections of transmission line. Such a filter might be useful for suppressing higher frequency harmonics or mixer products at the output of a nonlinear process such as an exclusive OR.

λ/4 λ/4 λ/4 λ/4

Inline low pass filter

Impedance matched via

Figure 21: Low pass filters

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An impedance matching network can be an instance of a low pass filter. Suppose that it is desired to improve the impedance match of a relatively low impedance structure such as a via under a package or connector. One way to improve the impedance match of the structure would be to precede it with a section of higher impedance transmission line. The excess inductance in the transmission line will then counteract the excess capacitance of the low impedance structure. Be aware, however, that the impedance matched via will be a low pass filter. Therefore, while impedance matching will improve the response up to some cutoff frequency, it will severely degrade the response at higher frequencies.

Figure 22 is an example topology for a notch filter. The open circuit quarter wave resonator is coupled to the through path by a quarter wave coupler that acts as an impedance inverter. This might be useful for suppressing clock leakage, for example.

Figure 22: Simple notch filter

Amplifiers

There is an old saying among microwave amplifier designers: “Amplifiers will, and oscillators won’t.” They’re referring the tendency for microwave amplifiers to oscillate, usually at frequencies that are very different from the intended frequency of operation, and for oscillators to refuse to oscillate at all.

Thus, under most circumstances, the design of high performance microwave amplifiers should be left to those who have apprenticed as an amplifier designer. There may be situations, however, in which only modest performance is required, and a small amplifier would solve a problem.

This section offers two amplifier configurations that tend to be broadband and stable, at the expense of limited performance.

Figure 23 shows a common base or common gate amplifier. The lefthand side of the figure shows the basic amplifier topology and the righthand side of the figure shows an example of a fully executed design. The primary advantage of the common base/gate configuration is that it has excellent isolation from output to input because the Miller effect capacitance is connected to ground. This helps keep the amplifier stable, and the reverse isolation can be a direct benefit of its own.

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Optional Low Frequency Input Port

Figure 23: Common base/gate amplifiers

In the common base/gate amplifier, the transistor presents a relatively low input impedance; so the input impedance of the amplifier is determined primarily by the input resistor, thus making it relatively easy to achieve a matched input impedance across a broad frequency band. The input resistor also introduces a loss mechanism that can help keep the amplifier stable.

The common base/gate amplifier can also be useful for combining a low frequency and a high frequency signal. As described above, the common base/gate topology is a good choice at high frequencies while the common emitter/source topology is a good choice at low frequencies. Thus, the high frequency input should be applied to the emitter/source while the low frequency input should be applied to the base/gate, as shown in Figure 23.

Another topology that has proven useful at RF frequencies is the common base/gate, resistive feedback amplifier shown in Figure 24. As was the case with the common base/gate amplifier, an input resistor is used to define the input impedance. For this amplifier, however, the low impedance at the other end of the input resistor is produced by negative feedback from the feedback resistor. The net result is relatively well controlled gain across a modest frequency range and relatively well controlled input impedance. One of the authors built an amplifier of this type using an MRF901 microwave bipolar transistor, intended to operate at 60 MHz as part of a noise figure test set. The amplifier exhibited a noise figure of 1.8 dB and a gain of 20 dB - a pleasing result for an afternoon’s work.

500

50

Figure 24: Simple feedback amplifier

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One final word of advice about amplifier design: keep the design absolutely as simple as possible, with the minimum number of components, the simplest circuit topology and the most compact layout possible.

AcknowledgementsThe authors wish to thank Doug Carlson, Brick Stephenson and Dave Kiefer at Cray and Todd Westerhoff at SiSoft for their support. Many thanks to Jim Fitzke, Rich Janda and Tim Holden at Cray for excellent technical support; without their contributions this work would not have been possible.

References[1] H. M. Davis, 1st Lt., Signal Corps, “The Signal Corps Development of U.S. Army Radar Equipment, Part 1: Early Research and Development - 1918 - 1937”, March 1943

[2] Nakajima, S., “The history of Japanese radar development to 1945,” in Russell Burns, Radar Development to 1945, Peter Peregrinus Ltd, 1988

[3] Microprocessor clock information from http://www.intel.com/pressroom/kits/quickrefyr.htm, http://processortimeline.info, and http://en.wikipedia.org/wiki/Microprocessor_chronology

[4] Wikipedia contributors, "List of device bit rates," Wikipedia, The Free Encyclopedia, http://en.wikipedia.org/w/index.php?title=List_of_device_bit_rates&oldid=521723475

[5] Abts, D, A. Bataineh, S. Scott, G. Faanes, J. Schwarzmeier, E. Lundberg, T. Johnson, M. Bye, G. Schwoerer, “The Cray BlackWidow: A Highly Scalable Vector Multiprocessor”, Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, November 10-16, 2007, Reno, Nevada

[6] Ziemer, R.E., W.H. Tranter, D.R. Fannin, “Signals and Systems, Continuous and Discrete”. Macmillan Publishing Company, 1983

[7] Weisstein, Eric W. "Fourier Series--Square Wave." From MathWorld--A Wolfram Web Resource. http://mathworld.wolfram.com/FourierSeriesSquareWave.html

[8] Matthaei, G., L. Young, and E.M.T. Jones, “Microwave filters, Impedance-matching Networks, and Coupling Structures”. Menlo Park, CA: Stanford Research Institute, 1963

[9] Steinberger, Michael S., Paul Wildes, Mike Higgins, Eric Brock, Walter Katz, “When Shorter Isn’t Better”, paper 7-TA3, DesignCon 2010

[10] Pozar, D.M., “Microwave Engineering”, Second Edition. Wiley and Sons, 1998

[11] Wadell, Brian C., “Transmission Line Design Handbook”. Artech House, 1991.

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