Application Notes

Active-HDLCopyright © Aldec, Inc.

Application Notes

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Table Of ContentsStarting Active-HDL ......................................................................................................................... 1

Design Entry Overview .................................................................................................................. 15

Design Management Overview ..................................................................................................... 27

Handling Libraries in VHDL, Verilog, and EDIF............................................................................. 37

Simulator Overview........................................................................................................................ 45

BASIC Scripting Capabilities ......................................................................................................... 54

Tcl/Tk Scripting .............................................................................................................................. 61

Creating FPGA and CPLD Designs............................................................................................... 71

How to Simulate Designs .............................................................................................................. 77

Using Stimulators........................................................................................................................... 85

VHDL Testbench ........................................................................................................................... 91

Glitches and Delta Cycle Handling ................................................................................................ 99

VHDL Debugging......................................................................................................................... 107

Building and Debugging Handel-C Projects ................................................................................ 115

Co-simulation of Handel-C Projects in Active-HDL ..................................................................... 125

Using Celoxica Flowchart ............................................................................................................ 133

Using TestBencher Pro™ with Active-HDL™ ............................................................................. 141

Building PLI Applications ............................................................................................................. 149

Building VHPI Applications .......................................................................................................... 157

Debugging C/C++ Applications ................................................................................................... 167

Using Design Profiler ................................................................................................................... 175

Using Toggle Coverage............................................................................................................... 179

Co-simulating VHDL and System-C ............................................................................................ 183

Co-simulating Verilog and System-C........................................................................................... 187

Index ............................................................................................................................................ 191

1

Starting Active-HDL

Installation

The installation of the Active-HDL system is invoked automatically by running the setup.exeprogram from the CD-ROM drive after you put the installation CD. The Install Shield Wizard thatassists you in the installation process will ask you to enter registration and configuration dataincluding your name, the company name and the destination folder that will store the Active-HDLcomponents.

During the installation process, all Active-HDL files are copied into their destination folders. Mostfiles are copied into the default Active-HDL folders. A number of files are copied into theWINNT\SYSTEM32 subfolder (Windows NT/2000/XP).

Installation steps:

1. Launch the setup.exe file from the installation CD. This will invoke the Installation Wizard.

Installation Wizard

2. In this window, you are prompted with the license agreement text. After accepting by clickingthe Accept button you will see the next dialog.

License agreement window.

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3. Enter user personal data to work with the Active-HDL software.

Entering personal data

After entering all required information, click the Next button.

4. You can install several editions of Active-HDL. In the Setup Type dialog, you can choose thefollowing options:

· Vendor-Independent EditionThis version allows installing Verilog, VHDL, both types of libraries.

· Altera/XilinxEditionThe vendor-specific editions allow you to install only Verilog or VHDL libraries.

Selection of the Active-HDL edition

After you have selected the edition of Active-HDL, click the Next button.

Starting Active-HDL

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5. When you advance to the next window, you will be able to select which program components(vendor libraries) will be installed.

Selecting vendor libraries for installation

The components not installed during the first installation cannot be added later and they willrequire a reinstallation procedure. Click the Next button when you have selected the requiredfiles.

6. Specify the installation folder and the folder for user-created designs.

Specifying the folders for user designs and the installation of Active-HDL

By default, the software is installed in the C:\Program Files\Aldec\Active-HDL 6.2 folder and thedesigns are stored in the C:\My_Designs folder on the disk. To change the destination folders,click the Browse buttons.

7. In the next step specify the license environment for Active-HDL.

During the installation procedure of Active-HDL 6.2 you can select the license environment thatwill be used to protect the program. The license environment settings should be related to thetype of the license you have purchased. The following settings are available in the ChooseLicense Environment window:

Application Notes

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Specify the license environment for Active-HDL

· Evaluation licenseThis option allows you to use Active-HDL 6.2 in evaluation mode for 20 days without anyadditional license. The evaluation version features the full functionality of a registeredcopy with some limitations.

· Hardware keylock/dongle (Parallel port)This option allows you to use a keylock-protected version of Active-HDL 6.2 based on thelicense stored in the device attached to the parallel port of your computer. The type of thelicense requires the Sentinel drivers to be installed on your computer.

· Hardware keylock/dongle (USB port)This option is a new type of the license supported by Active-HDL. It allows you to use akeylock-protected version of Active-HDL 6.2 based on the license stored in the deviceattached to the USB port of your computer. The type of the license requires the SentinelUSB drivers to be installed on your computer. Before you choose this type of Active-HDLlicensing make sure your workstation supports the USB standard. The installationprogram will copy all required drivers to your computer. Additionally, make sure thatduring the installation the USB keylock device is not attached to the USB port of yourcomputer.

· Network floating licenseThis option allows you to use a version of Active-HDL that is protected by the networklicense manager. During the installation procedure the ACTIVE62_LICENSE_FILEvariable is set. This variable should point to the location of the License.dat file or thelicense server.

Starting Active-HDL

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8. In the final step of the installation, you can create file associations for the Active-HDLenvironment.

Selecting file extensions for Active-HDL

Click the Next button, the setup program is ready to start copying files. The dialog displaysinformation about the selected components for installation and their target folders. Startinstallation by clicking the Install button.

9. You can register your software or finish the installation by pressing the Finish button.

Finishing the installation

Evaluation Version

When you install Active-HDL for the first time on your computer, it will work in evaluation mode for20 days without any additional license files or keylocks. The evaluation version provides the fullfunctionality of a registered copy with the following limitations:

· Printing is disabled.

· The maximum simulation time is 10 us.

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· The maximum amount of memory allocated per VHDL, Verilog or mixed VHDL-Verilogdesign is 5MB. This limitation decreases to 2 MB for any designs employing EDIF-baseddesign units.

· Block diagrams containing more than 15 fubs and/or symbols cannot be saved.

Single User

If you purchased the Active-HDL software for a single user, then you have been supplied with ahardware keylock or a license file. The keylock is a device that plugs into the parallel port of thecomputer. While the Active-HDL software is loaded, the parallel port is automatically tested toverify whether you have a valid keylock to run the program. In case of a license file, the FlexLMlicense manager checks whether a valid license LICENSE.DAT file is stored in the DAT subfolderof the Active-HDL installation folder.

Network Version

Active-HDL 6.2 supports the new licensing capability that enables user to have different productconfigurations on one Floating License. With the new licensing the separate users can access theoptions available for the different product configurations. The change in licensing forces theexisting users of previous versions of Active-HDL to update their license before running the newrelease. If a user has purchased Active-HDL 6.2 with network licensing containing severalproduct configurations, he/she will be able to switch among these configurations each time theprogram starts. If a user has purchased the network license with only one product enabled in alicense file, he/she has the possibility to use only one given configuration. In this case theLicense configuration window can be omitted during the Active-HDL start-up. To do so, the Donot display this dialog again box must be checked. All products enabled in a license file can beseen after pressing the License information button.

Uninstall

To uninstall Active-HDL, click the Start button in the Windows task bar and select Settings |Control Panel. In the Control Panel window, click the Add/Remove Programs icon.

NOTE: You should not uninstall Active-HDL manually.

Modification of previous installs

With Active-HDL already installed in your computer you cannot add previously omittedcomponents at any time. To do this, you need to run the installation software again.

NOTE: User projects are not removed during uninstall and will be visible in a new version ofActive-HDL.

Starting Active-HDL

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Hardware and Software Requirements

Active-HDL 6.2 requires:

· A Pentium PC or higher/compatible

· 128 MB physical memory (256 MB recommended)

· Microsoft Windows NT 4.0® with Service Pack 6 , Windows 2000® with Service Pack 3(recommended), or Windows XP® with Service Pack 1 (recommended)

· Microsoft Internet Explorer™ version 4.0 or higher (see Notes)

· Hard disk drive with at least:§ Vendor-Independent Edition and Synplicity Edition360MB of free space for minimal installation (2GB for full installation including allavailable libraries).§ Altera Edition460MB for VHDL or 390MB of free space for Verilog installation.§ Xilinx Edition490MB for VHDL or 440MB of free space for Verilog minimal installation940MB for full VHDL or 890MB of free space for full Verilog installation (including allschematic libraries).

NOTES:

· The hard disk drive requirements are approximate and depend on both your operatingsystem and chosen file system.

· The amount of available physical memory limits the maximum size of the design thatcan be simulated in Active-HDL.

· For full functionality, Active-HDL 6.2 requires that the Microsoft Internet Explorer™version 4.0 or higher is installed on your system. If not, the following systemcomponents will not be available:

· Dataflow window

· Query window in Block Diagram Editor

· On-line documentation

· If you have a different Internet browser (other than Internet Explorer) installed on yoursystem, you can continue to use it without any problems. Internet Explorer can beinstalled as a non-default browser and be used only by Active-HDL.

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Folder Structure

Active-HDL 6.2 is the default root folder for all Active-HDL 6.2 files. The Active-HDL 6.2 folderstructure is shown below.

The structure of the Active-HDL folder

The Active-HDL installation folder includes:

Active - Active-CAD executables and auxiliary files necessary to import Active-CAD designs toActive-HDL environmentBin - Active-HDL executables, Profiler, Code Coverage, debugger, and auxiliary filesBooks - Help and documentation filesDat - License filesDenali - Denali interface filesDrivers - Sentinel drivers for the keylockEtc - Debussy interface filesEvita - Evita interactive tutorial filesFlows - Design Flowchart configuration filesIP CORE - IP CORE Generator files and documentationLicense - Network licensing software and keylock utilitiesMATLAB - MATLAB interface filesMinGW - Gcc compiler and gdb debugger filesNetSetup - Active-HDL network installation filesPerl - Perl executable and auxiliary filesPli - Verilog PLI auxiliary filesScript - Sources of scripts used in Active-HDLSWIFT_LMTV - Files required to build the swift_lmtv.dll library that allows using the LMTVinterface.Synopsys - Interface to Synopsys FlexModelsSystemC-2.0.1 - SystemC Class Library files (ver. 2.0.1)Tcl - Tcl’s scriptsTemplate - Language Assistant filesTraining - Sample training designs and PowerPoint format presentation filesVlib - VHDL, Verilog, and vendor-specific libraries

Starting Active-HDL

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Files Installed in Windows Directories

The following files are copied to the \SYSTEM32 subfolder (Windows NT/2000/XP):

Atl70.dllMfc70.dllMfc30.dllMfcd30.dllMfcn30.dllMfco30.dllMfcoleui.dllMfcuia32.dllMsvcr70.dllMsvcp70.dllMsvcp50.dllSaxbasic.hlpSbpro32.ocxStlport_vc745.dllWw_cu232.dllWw_mc232.dllWw_0a232.dll

Active-HDL Components

All Active-HDL components are embedded into a unified graphical environment referred to as aframework. The framework provides workspace and is a communication environment for allsystem components. Except for the simulation kernel, each Active-HDL tool is implemented in aseparate window. The following is a brief description of Active-HDL components:

Console

The Console window is an interactive input-output text device that:

· Provides entry for Active-HDL commands.

· Outputs messages generated by Active-HDL tools.

Design Browser

The Design Browser window displays the current design contents, including:

· Resource files attached to the design.

· The contents of the design default working library.

· The structure of the design unit selected for simulation.

· Signals and variables declared within a selected region of the current design.

HDL Editor

The HDL Editor is a text editor designed for HDL source files. It displays specific syntaxcategories in different colors. The editor is tightly integrated with the simulator to enable easysource code debugging.

Language Assistant

The Language Assistant is an auxiliary tool that provides a number of VHDL/Verilog templatesmodeling typical logic primitives and functional blocks. It is integrated with the HDL Editor so thatyou can automatically insert the desired templates into edited source files. The LanguageAssistant also allows you to define your own templates.

State Machine Editor

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The State Machine Editor is a graphical tool used to created and edit state machine diagrams.The editor automatically implements translation of graphically designed diagrams intoVHDL/Verilog code.

Block Diagram Editor

The Block Diagram Editor is a graphical entry tool for creating and editing top-level schematicfiles. This tool automatically generates EDIF and VHDL/Verilog code.

Waveform Editor

The Waveform Editor displays the results of a simulation run as signal waveforms. It allows you tographically edit waveforms so as to create desired test vectors.

List

The List window displays the results of a simulation run in a tabulated text format. It allows you totrace simulation results with delta-cycle accuracy.

Watch

The Watch window displays the current values of selected signals and variables duringsimulation.

Processes

The Processes window displays the current status of concurrent processes in the elaborateddesign during simulation.

Call Stack

The Call Stack window is a debugging tool that displays a list of subprograms (procedures andfunctions) being executed in the currently executed process.

Dataflow

The Dataflow window is a tool providing a graphical view of signals flowing in and out ofprocesses during simulation.

Library Manager

The Library Manager is designed to manage VHDL/Verilog libraries and their contents.

Workspace/Design Explorer

The Workspace/Design Explorer facilitates the management of Active-HDL designs. It is notnecessary to remember the physical locations of design files.

Design Flow Manager

The Design Flow Manager is a tool that allows you to automate processes of simulation,synthesis, and implementation by using third-party EDA tools.

Memory View

The Memory View window is a debugging tool that has been designed to display the contents ofmemories defined in a design (e.g. objects of the two-dimensional array type).

Server Farm

Server Farm is an advanced and independent tool working on the local network that allows usersto schedule tasks and then execute them automatically on the selected computers available onthe network.

Code Coverage

Code Coverage is a program that allows you to test testbenches and determine how your sourcecode is executed.

Source Revision Control

Active-HDL provides a powerful enhancement that allows you to communicate with externalprofessional Source Revision Control systems. The built-in interface allows operating on previousversions of source files directly from the Active-HDL environment.

Starting Active-HDL

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Design Files

During the design development, a number of files are created in the design folder. They areworkspace and design configuration files, VHDL, Verilog, or EDIF source files, waveform files,script files, log files, library files, etc. The list of files used in Active-HDL designs along with theirextensions is available in Release Notes.

Workspace and Design Structure

Every workspace and design is stored in a separate folder called the workspace/ and designfolder, respectively. Both the workspace/design folder and the workspace/design have the samename. The workspace folder ($wsp) contains the workspace description file (AWS), the$wsp\library.cfg file that stores information on global libraries visible to every Active-HDL designand working libraries of all designs attached to the current workspace. Each design foldercontains the SRC, LOG, and COMPILE subfolders as well as the design description file (ADF)which name is the same as the name of the design.

The SRC subfolder may contain VHDL, Verilog, EDIF source files, block or state diagram files,macros and other source files.

The COMPILE subfolder contains, among others, the generated from block or state diagramsVHDL or Verilog source codes.

The LOG subfolder stores log files created while evaluating s design.

The workspace/design configuration and status are described in the following files:

· AWS, ADF, CFG - workspace/design description and configuration files, respectively.Contain information on a workspace, a design currently set as active and design'sstructure: source files and libraries that belong to individual designs, compilation status,attached libraries, which files are open, what is the cursor position in each file, whatbookmarks have been toggled, which windows are undocked, etc.

· WSW, WSP - files containing additional workspace/design data, e.g. on openedtoolboxes, value of the simulation step set for each design. They can be restored even ifthey are deleted or corrupted.

NOTE: Since the workspace file describes the current design status, it may also contain suchadditional information as instability of the design resulting from an error. In such a case, thedesign may fail to open because of the unstable status written to the workspace file. If so, deletethe corrupted workspace file to open the design with the default workspace settings.

Active-HDL Configuration Settings

Active-HDL configuration settings apply to both the current design (local settings) and the entiresystem (global settings). Local settings are stored in the workspace and design files stored in thedesign and workspace folders, respectively. Global settings include the user interface settingsthat are not the design related settings, e.g. the Console window state (docked or undocked).Global settings are stored in the avhdl.xml file (\Bin).

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Active-HDL Libraries

Active-HDL libraries include system libraries and workspace/design libraries. System libraries areshipped with the Active-HDL software and are stored in the \VLIB subfolder. They have the read-only attribute set by default. Workspace and design libraries are created for particular designsand stored in design folders. The library structure is common for both design and system libraries.

Each library consists of two files:

· LIB - the library index file

· MGF - the library main file, containing data used by the Active-HDL's compiler and codeused by the Active-HDL simulator.

There are also two library configuration files - LIBRARY.CFG. The first one (mentioned above) isstored in the \VLIB subfolder and the second file is created along with a workspace and it storesinformation on workspace global libraries, that is, the libraries treated as global until theworkspace is loaded.

System libraries, stored in the \VLIB subfolder are pre-compiled standard libraries containingstandard packages and primitives.

Built-in Standard Packages

Built-in packages contain subprograms whose code is embedded directly into the simulationkernel rather than generated by the VHDL or Verilog compiler. The code is optimized toaccelerate the execution of such subprograms. The following is a list of packages for which theActive-HDL simulation kernel provides the built-in acceleration:

Standard Libraries Packages/Description

ALDEC Aldec Library with procedures for calling FSDB tasks from VHDL

STANDARDSTD

TEXTIO

VL Standard Verilog Library

VITAL_MEMORY

VITAL_PRIMITIVESVITAL2000

VITAL_TIMING

STD_LOGIC_1164

VITAL_TIMING (VITAL 2000)*

VITAL_PRIMITIVES (VITAL'95)

VITAL_MEMORY*

NUMERIC_BIT

NUMERIC_STD

STD_LOGIC_ARITH (also available in the SYNOPSYS library)

STD_LOGIC_SIGNED (also available in the SYNOPSYS library)

IEEE

STD_LOGIC_UNSIGNED (also available in the SYNOPSYS library)

* Active-HDL provides the IEEE library that includes the packages specified by Standard VITALASIC Modeling Specification, version 95 (IEEE Std 1076.4-1995) and 2000 (IEEE Std 1076.4-

Starting Active-HDL

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2000). After the installation, the IEEE library containing packages coming from IEEE Std 1076.4-2000 is mapped by default.

To use the IEEE library containing packages coming from IEEE Std 1076.4-1995:

1. Choose the Execute macro option from the Tools menu.

2. In the Execute macro window, go to the $ALDEC\Vlib\vital95\src directory and point tothe remap_ieee.do macro.

3. Click the Open button. As a result of the macro execution, the IEEE library containingpackages specified in IEEE Std 1076.4-1995 is mapped. To re-map the library, repeatstep #2 selecting the remap_ieee.do macro stored in the $ALDEC\Vlib\ieee\src directory.

NOTE: The pre-compiled vendor libraries delivered with Active-HDL 6.2 require the IEEE librarycontaining packages coming from IEEE Std 1076.4-2000. After the IEEE library is re-mapped,you will need to re-compile the vendor libraries.

On-line Documentation

Active-HDL provides the updated on-line documentation in the Compiled HTML (*.chm) format.Microsoft Internet Explorer™ 4.0 or higher is required to view the documentation in this format (itdoes not have to be set as the default Internet browser on your system). To open the on-linedocumentation, choose On-line Documentation from the Help menu. You can also load it bydouble-clicking the Umbrella.chm file stored in the \Books subfolder.

The following on-line documentation files (\Books\*.chm) are shipped with Active-HDL:

· Active-HDL Main Help Page (Umbrella.chm)

· Active-HDL Help Topics (Avhdl.chm)

· Release Notes (Relnotes.chm)

· VHDL Language Reference Guide (Refguide.chm)

· Verilog Language Reference Guide (Vlogref.chm)

· VSimSA Standalone Simulation Environment Manual (Vsimsa.chm)

· HDL Entry and Simulation Tutorial (Tutavhdl.chm)

· PLI Reference Guide (PLIRef.chm)

· VHPI Reference Guide (VHPIRef.chm)

· Handel-C Reference Manual (HandelC.chm)

· Mixed Mode Entry and Simulation Tutorial (Tutbde.chm)

· State Machine Entry and Debugging Tutorial (Tutfsm.chm)

· VHDL Testbench Tutorial (Tuttbch.chm)

· VHDL Entry and Simulation Tutorial (Tutvhdl.chm)

· Verilog Entry and Simulation Tutorial (Tutvlog.chm)

· Mixed VHDL-Verilog Tutorial (Tutmixed.chm)

· Code Coverage Tutorial (TutCC.chm)

· VHDL Configuration Tutorial (Tutconf.chm)

· Post Simulation Debug Tutorial (TutPSD.chm)

· Server Farm Installation Tutorial (Tutsfadm.chm)

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· Active-HDL Application Notes (Appnotes.chm)

· Using new features of Active-HDL macro commands and scripts (M42v5.chm)

· STD_LOGIC_1164 IEEE Package Reference (Stdlogic.chm)

· STD_LOGIC_ARITH IEEE Package Reference (Stdarith.chm)

· STANDARD Package Reference (Standard.chm)

· TEXTIO Package Reference (Textio.chm)

· Sax Basic™ Language Reference Guide (Saxbasic.hlp, in the Windows' System orSystem32 subfolder)

· Tcl/Tk™ Reference Manual (Tcl80.hlp)

· License Utility Help (Licutil.hlp)

Unless specified otherwise, all documentation files reside in the \Book subfolder of the Active-HDL installation folder. In addition, Active-HDL provides an Enhanced VHDL or Verilog Tutorial(EVITA).

NOTE: The updated Active-HDL On-line Documentation is not limited and provides the helpsystem for all features available in the full version of Active-HDL (Expert Edition (EE)). If you havea limited version of Active-HDL (Standard Edition (SE) or Plus Edition (PE)), you are still able toget the information on all available features. Contact Aldec for more information on licenseupdates and new Active-HDL features.

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Design Entry Overview

Introduction

Active-HDL is a new generation VHDL, Verilog, EDIF simulator. Its context graphical userinterface is easy to use and makes your work easy in all stages of design development, startingfrom a hardware description, through synthesis, implementation, and debugging to designsimulation.

The HDL design entry process is supported by the following tools:

· HDL Editor - non-formatting text editor that includes a Language Assistant with a set ofVHDL language templates.

· State Diagram Editor - a tool for creating FSM diagrams, which can be automaticallyconverted into the corresponding HDL code.

· Block Diagram Editor - is a new graphical design entry tool. It allows you to createhierarchical block diagrams as an alternative to writing HDL code directly.

HDL Editor

The HDL Editor is a tool for creating HDL codes, testbenches, macros, scripts, and other textfiles. Active-HDL offers you several automated tools for a VHDL/Verilog code creation such asNew Source File Wizard.

The HDL Editor

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New Source File Wizard

Active-HDL allows you to create VHDL and Verilog files by selecting the Add New File commandfrom the Design Browser window. The window that appears will give you a choice of commands.

· Block Diagram

· State Diagram

· VHDL Source Code

· Verilog Source Code

· Add Existing File

The Add New File Window.

You can also choose from the following list of wizards:

· Block Diagram Wizard

· State Diagram Wizard

· VHDL Source Code Wizard

· Verilog Source Code Wizard

The Add New File Window - Wizards

The Wizards facilitate design entry by introducing several steps. Each step requires some specificinformation about the file that is being created.

STEP1: Specify whether the created code is to be added to the current project.

STEP2: Choose the language that will be generated from a block or state diagram (only for BDEor FSM files).

STEP 3: Enter the file name, entity and architecture or module name. The file names fields aremandatory.

STEP3: Provide information about unit's ports.


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The New Source File Wizard.

Language Assistant

The Language Assistant aides in speeding up HDL source code and script development. Itprovides a number of templates with prepared segments of code. There are several groups oftemplates:

· Code Auto Complete templates of HDL keywords or the whole constructs are insertedafter typing the first initial letters and pressing the Space key.

· Language templates with basic language constructs.

· Simulation templates with sample processes useful while creating Testbenches, suchas clocking signals, file accessing, etc.

· Synthesis templates with synthesis-oriented basic functional blocks, such asmultiplexors, flip-flops, counters, etc.

· Tutorial with four templates that include counter, decoder, testbench, and sample top-level specification.

· User templates where the user-defined templates are stored.

The Language Assistant Window.

You can insert a selected template into a document being edited in the active HDL Editor windowby dragging its name into the HDL Editor window. You may need to slightly edit the code toadapt it to your specific needs.

Another method of inserting templates is to right-click the template label and select the Usecommand from context menu. The template will be inserted into the HDL Editor at the cursorposition therefore you need to remember to place the cursor at insertion position. You can click

the icon on the Language Assistant toolbar to insert the template.

Application Notes

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Inserting the template

The left panel of the Language Assistant window displays a hierarchical list of templates. Thelist is displayed in a tree-like form. Templates can be grouped into folders, added or deleted byusers. A shortcut menu is available in the left panel. Its commands options duplicate the functionsof the buttons. The right panel allows you to preview the contents of the currently selectedtemplate. You can assign a read-only attribute to templates to prevent accidental modification.

Color Preferences

The HDL Editor allows you to distinguish keywords, comments and constants from the rest of thetext by displaying each item in a different color. The color selected for each keyword definition, aswell as font type, may be specified in the Preferences | Environment | Appearance window.The color-coded file is much easier to follow. This feature is particularly useful for those userswho are not strong in the HDL language. The HDL Editor checks the code syntax interactivelysince each keyword changes its color when correctly typed.

The Preferences Window.

The syntax of the HDL file is checked every time the Compile command is executed. The HDLEditor will prompt you if any error occurred in the file. All error messages are logged into a file anddisplayed in a Compile window simultaneously.

Additional code formatting features of HDL Editor improve the code readability. The icons forthese actions are located in the left hand part of the window:

- allows the selected text (code) indentation,

- removes the indentation from the selected text,

- converts the selected text into HDL comments,


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- uncomments the selected text,

- generates the structure for the selected text, which in result can be expanded or collapsedfor improving the code readability. Thus created structure is displayed with the color background,

- removes the structure generation from all groups,

- generates the structure for the entire text along with automatic group partition. Such groupsas VHDL entity port declaration, or IF .. THEN constructs are automatically collapsed. Particulargroups are displayed with different colors,

- automatically formats the selected code regarding the indentation,

- adds the link (in a form of a comment to allow compilation) to a file located on the disk or onthe Internet. By adding the link to the Internet page containing the detailed model specificationyou have direct access to the required information. (For example information on person using theproject),

- places the named bookmark in the code for better code navigation with the button.

Placing common bookmarks and navigating between them is facilitated by theicons located in the upper part of the editor window: These icons allow you to place a bookmark,jump to the next one, jump to the previous one and to remove a bookmark, respectively.

Similar to color-coding the HDL keywords, you can define your own colors for the generatedstructure groups.

HDL Editor containing structures.

Active-HDL speeds up writing the HDL code facilitating the completion of the following items:

· Reserved words - you can auto-complete only keywords after typing a few initial lettersand pressing the Space or right arrow key. The keyword will be automatically expanded.

· The whole HDL constructs - you can auto-complete the whole VHDL or Verilogconstruct after typing a few initial letters and pressing the Space key. The template will beautomatically expanded.

The following picture shows the code for the CASE template.

Application Notes

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Code Auto Complete

State Machine Editor

The Finite State Machine Editor allows users a simple and easy graphical design entry. Sincestate designs can be easily retargeted to any devices, the state editors are becoming verypopular with designers who value technological independence.

The State Machine Editor

The State Machine Editor allows a graphical design entry in the form of state machines. In short,a finite state machine (FSM) represents behavior and functionality of a process in a limitednumber of "states". An FSM design contains the following attributes:

· A list of states

· A list of commands that can be accepted in each state

· A list of actions to perform for each command

· Actions can be of the following kind:

· send a command to another component (asynchronously and synchronously)

· execute a piece of code (user routine)

· set the state of the FSM design

· A list of conditions for each state that cause the listed actions. Conditions remain active inthe associated state and are reevaluated whenever a component changes its state,starts, or stops.


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New Source File Wizard

Beginners should choose the New Source File Wizard to create a template of a state machine.The Wizard helps in a design creation process. When using the Wizard you will supply the sametype of information as you would to the HDL code creator. The difference between a file createdby the Wizard and an empty state machine file created by invoking the Add New File command,is that signal names and declared ports are automatically inserted into the Wizard's generatedfile. However, those names must be manually entered when using the Add New File command.

State Machine Toolbars

You can create any state machine in the State Machine Editor. By clicking on the correspondingicon in the State Machine toolbar, you can place any of the following items on the state machinediagram:

· standard and hierarchical state

· transition

· entry action

· state action

· exit action

· transition action

· machine or diagram action

· signal or variable

· junction

· input port

· output port

· bi-directional port

· hierarchy entry and exit

· link

· constant, generic, or parameter

· diagram or machine declaration

· reset or initial state

· text and graphical elements

The State Machine Toolbars.

The State Machine Editor provides free editing. You can adjust the shape of a state circle or atransition arrow by dragging them in the desired direction. If an item cannot be placed in a certainarea, the editor will not allow you to leave it there. For example, you cannot place a new diagramdeclaration in a state machine area.

To change the machine properties, right-click and select the Properties option from the contextmenu. You can choose the clock for the state machine and specify if the machine isasynchronous or synchronous or it should work on a rising or falling edge. There are optionscontrolling the decoding of the state machine, default states, reset conditions, and the machinebehavior when conditions are not met.

Application Notes

22

The Machine Properties Window.

The most important feature of the State Machine Editor is its ability to generate HDL code for thestate machine diagram. You can perform this by selecting the Generate HDL Code option fromthe FSM menu or by clicking the Generate HDL code icon on the FSM toolbar. You can view thegenerated code by selecting the View HDL Code option from the FSM menu. Moreover, you mayadd a library clause when necessary. For example, when performing mathematical operationsyou can add the following library clause (VHDL):

use IEEE.std_logic_arith.all library clause.

Block Diagram Editor

The Block Diagram Editor is a graphical design entry tool. It allows you to create hierarchicalblock diagrams as an alternative to writing a HDL code directly. The editor supports automaticgeneration of HDL from the diagram along with the advanced design rule checking (DRC). Itallows you to mix all design description methods (pure HDL code, state diagrams and blockdiagrams).

Block Diagram Editor Window

Similar to typical schematic based tools, the Block Diagram Editor lets you place, rotate andarrange the I/O ports, symbols, wires, buses, etc., The toolbar, with basic action buttons, islocated in the upper part of the window.

- switches to the editing mode for arranging the objects, etc.


23

- creates an empty macro symbol and places it in the schematic.

- buttons for drawing wires and buses and naming them respectively. These buttonsallow you to create the connections between the components.

- buttons for creating the I/O pads of the following type: input, output, bidirectional, andbuffer respectively. Used for terminating wires and buses.

- buttons used for entering additional instructions or declarations.

- symbols placed in the schematic representing VCC and Ground.

- buttons for global signals and buses declaration.

- opens the Symbols Toolbox containing available macros. Each VHDL entity or Verilogmodule from a library has automatically generated symbol here.

Symbols Toolbox window.

You can place the symbol in the schematic by dragging it over the editor window and dropping inthe desired location.

- buttons for placing additional elements such as text, drawings, and graphic files.

You can edit the symbol placed in the schematic by selecting the desired symbol and choosingthe Push command from the context menu.

Application Notes

24

Switching between symbol and its code.

As you can see in the previous picture, by right-clicking the selected symbol, you have access toseveral different commands. You can, for example rotate or mirror the symbol, zoom it, etc. Asmentioned before, each VHDL entity (Verilog module) description is represented by theautomatically created symbol which can be placed in the schematic. To create an empty symbolin the schematic and generate its code later, you can draw a fub (Diagram | Fub (F) or the Fubicon) and choose the already mentioned Push command. You can then select between severaldifferent architecture description methods:

· Hierarchical schematic sheet using the Block Diagram Editor

· State Diagram using the State Machine Editor

· VHDL code using the HDL Editor

· Verilog code using the HDL Editor

· EDIF netlist using the HDL Editor

Defining the symbol architecture


25

Active-CAD Schematics

Active-HDL can import Active-CAD designs into the Active-HDL environment. Active-CADschematics are converted to Active-HDL block diagrams. Multi-sheet schematics are converted tomultiple-page block diagrams. Diagrams resulting from the conversion are set up for EDIFsimulation, which means the Block Diagram Editor generates EDIF netlist from them instead ofVHDL or Verilog. Hence, they benefit from the fast EDIF compilation in the Active-HDLenvironment.

Conclusion

HDL files guarantee that your code is portable and exchangeable between HDL editors. Havingyour projects written in the HDL makes you independent from vendor-specific layout tools. On theother hand, schematic files are generally stored in vendor-specific formats and cannot be appliedto parts from other vendors. HDL files are much more flexible when the design you develop isdescribed behaviorally. In this case you do not need to know anything about the structure of thedevice being developed. You only need to describe the behavior of the design model.

When drawing a schematic you may be able to use some vendor's macro libraries containing themost popular devices such as counters, decoders, encoders, etc., and therefore avoidunnecessary efforts developing those basic structures. But on the other hand you may obtainvendor-specific HDL libraries containing the same basic structures and at the same time preservefull independence from any vendor. It is worth stressing that very large designs are moreefficiently managed with files written in the HDL because you can have library files containinglarge numbers of components, while the schematic macro libraries usually use one file for eachmacro structure. This way, you can quickly run out of disk space having all the macros stored inseparate files, especially when a large project is designed.

Finite State Machines are excellent for control circuits. They represent the control flow in a projectthat is similar to the human way of thinking. Thus, they are very easy to follow and almost self-explanatory. In addition, they automatically generate HDL code that precisely describes the statemachine behavior and avoids any unexpected states. Active-HDL provides you with a StateMachine Editor, that quickly and effectively converts any state machine into an HDL code.

In real, working on large designs you will need all types of files:

· Schematics which are excellent for the top-level hierarchy model because of theirreadability.

· State machines which are perfect for the control flow description.

· HDL files which are universal and exchangeable.

Since a combination of all the available techniques gives you the best results, you shouldfamiliarize yourself with each of them.

27

Design Management Overview

Introduction

The design process may seem simple when there are only a few files to manage. However, whena design is comprised of many different files located in different folders, you may easily lose track.

Active-HDL has several specialized tools for managing your design files. With the Design Wizard,you can create new files, avoiding hard work and confusion. In the Design Browser window youcan easily attach old files and create new files or folders, the Workspace/Design Explorer inActive-HDL will help you to easily navigate between different designs.

Design Wizard

The New Design Wizard is a tool that helps in creating the skeleton of new design and addingnew files to a project.

The New Design Wizard Window

Users who have created designs in the Active-CAD software can import them to Active-HDL. Byselecting Import a design from Active-CAD a whole design can be imported to the Active-HDLenvironment for additional modifications.

Application Notes

28

The Resource Files Window

A new design does not mean completely new files. The New Design Wizard allows you to addexisting files to the design. The New Design Wizard window also allows you to configure thesynthesis and implementation tools that will be used during the design evaluation process. In thiswindow you can also specify the default HDL language and the Block Diagram configuration.

The Additional information window.

In the next window you can specify the design name, location of the design folder, and the nameof the default working library.


29

This Wizard is a very handy tool that saves time at the initial stage of the design developmentprocess.

Design Browser

The Design Browser window displays the contents of the entire design in a user friendlyenvironment. This is the place where you can add or remove any source files. With one glance atthe model hierarchy tree you can check which files are out of date and which contain errors. TheDesign Browser window allows you to select the top level design of the model hierarchy. Allfunctional macro files are executed from here by invoking simple context menu commands. Bydouble-clicking selected files, the Design Browser displays its contents in the appropriate editorwindow. During the compilation and verification process the Design Browser window displays allsignals and signal values for the selected entity.

The Design Browser window consists of three tabs:

· this tab shows resource files attached to the design and the contents ofthe default working library.

· this tab displays the HDL structure of the design extracted from thesource files and HDL objects (signals and variables) within the selected design region.

· this tab displays folders containing the simulation log files and savedwaveform files.

The Files Tab

The upper part of the Files tab shows resource files of the current design. Each file isrepresented by a separate icon. The shape of the icon depends on the resource file type asshown above. In the case of HDL source files and state diagram files, the color of the icons bringsadditional information about the file status:

· Successfully compiled

· Not compiled or modified after the last compilation

· Errors occurred during the last compilation

· Compiled with warnings

Application Notes

30

The Files tab shows design units contained in various specific source files. The name of thedesign unit currently selected for simulation is displayed in bold. The bottom part of the Files tabdisplays design units contained in the default working library.

The list box located at the very top of the tab allows you to select the top-level design unit from alist of design units available in the default working library. The top-level design is displayed inbold. As always, you can also choose the top-level design in another way, by right-clicking any ofthe source files.

The Design Browser Window

The attached resource files are:

· VHDL Source Code (vhd;vhdl;vhq;tvhd;vho;vhm;vhi), configurations, and testbenches

· Verilog Source Code (v;vei;veo;vo;vm;vmd;vlb;vlg) and testbenches

· C/C++ Source Code (cpp;c;h)

· Verilog Value Change Dump (.vcd)

· State Diagram (.asf)

· Block Diagram (.bde)

· BDE Symbol (.bds)

· Waveform File (.awf)

· List File (.lst)

· Macro (.do)

· SDF File (.sdf, .sdo)

· EDIF Netlist (.edf, .edn, .edo)

· Viewlogic Schematic (.1)

· TCL Script (.tcl)

· Active-CAD Test Vector (.asc)

· Active-CAD Project (.pdf)

· XNF Netlist (.xnf)

· Basic Script (.bas)

· Perl Script (.pl)

· Drawing (.afc)

· Bitmap (.bmp)

· HTML Document (.htm)


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· Text (.*)

· External file

State Diagram and Block Diagram files are displayed together with the associated generatedcode.

The context menu invoked by right-clicking from within the Files window allows compilation of theentire project or just selected folders. It also allows for removing files either from the project ordisk. In case files contain macros, you can execute them from within the Files tab window.

The Structure Tab

The Structure tab is divided by a horizontal split bar. The upper part shows the hierarchicalstructure of the top-level design unit. The lower part displays objects defined within the designregion selected in the upper part of the tab. It is divided into several columns which show theobject name, VHDL type or net type, current value, previous value, and last event time. The kindof the object (signal, variable, constant, port, generic, file, net, register, parameter) is indicated bythe appropriate icon displayed next to the object name. To view objects from a specific region ofthe design, you must select the appropriate hierarchy branch in the upper part of the Structuretab.

The Design Hierarchy Structure (VHDL)

The labels displayed next to the icons are extracted from the source code. You may also view thesource code of the entity or process by right-clicking and selecting the Open command from thecontext menu.

The Structure window has such editing features as dragging signal names from this window anddropping them into the Watch, Waveform, and List windows.

Application Notes

32

The Resource Tab

The Resource tab is comprised of three default folders:

· List - with list files generated during simulation

· Logs - with log files from Console, Simulation, Find and Compile windows

· Waveforms - with waveform files

You may add new folders, for example containing different document files, by right-clicking in theResources window. Different document types are displayed with different icon shapes.

Workspace/Design Explorer

The Workspace/Design Explorer window provides a means for efficient management ofprojects, so that you do not have to worry about the physical location of design files on yourcomputer. There are functions that allow you to create and remove folders, add shortcuts toexisting projects, create new ones and copy any project to a new destination folder. TheWorkspace/Design Explorer is invoked by selecting the Open Workspace option from the Filemenu. By default, all sample designs are stored in the /My_Designs/Samples_61/ folder, createdduring the installation.

The Workspace/Design Explorer Window

Each design/workspace is represented in the Workspace/Design Explorer window by a shortcuticon. A design/workspace may have several shortcuts. The Workspace/Design Explorer allowsyou to group the shortcut icons into folders. Note that these folders have nothing to do with filefolders in which designs/workspace are stored. The left panel of the window displays thehierarchical structure of the shortcut folders. The right panel shows the contents of the currentlyselected folder. The status bar displays the name and path to the design/workspace descriptionfile of the design icon currently selected.


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Design Menu

The Design menu allows you to perform the same operations as the context menu. In addition,there are unique commands providing for new libraries creation and customization of the projectsettings. You can also add currently opened documents to the design project folder.

The Design Menu

In the Design Settings window you can set additional options. The window is divided into thefollowing tabs:

· General - selecting the top-level design unit for simulation and block/state diagram HDLconfiguration

· VHDL/Verilog - setting the working parameters for the VHDL and Verilog compiler

· SDF - displays files with timing specifications and sets the target region of the design

· Simulation - provides specific options for VHDL and Verilog simulation, disabling VITALglitches and warnings from the SDF file reader, as well as memory management settings

· Trace/Debug - provides settings for the Post Simulation Debug mode

· Verilog PLI - handles DLL libraries for PLI Applications

· EDIF - handles libraries needed for compilation and simulation in the current design

· Code Coverage/Profiler - allows you to specify the Code Coverage and Profiler options

Application Notes

34

The Design Settings Window

Another useful option in the Design menu is the Backup Revision. It is often necessary tobackup a design in its current state, especially when you are going to make major changes. Youmay even accidentally delete some files that are needed for simulation. It is recommended tokeep backup files for your own protection.

Having backup revisions saved at different stages of the development process allows you to tracechanges in the design and develop several design versions, etc. Active-HDL allows you to savean unrestricted number of revisions for each design. Each revision is identified by its numberautomatically assigned during creation of a revision. You can also add an optional label andcomments to each design.

It is impossible to mix revisions created in Active-HDL for different designs. When you need torestore one of the previous revisions, you should use the Restore Revision command. Theoperation replaces the current design with the selected revision. Note, that this operation willremove the current design. If you plan to return to it, save it as a new revision before using theRestore Revision command.

The Backup Revision Window

The Create Library option from the Design menu invokes the New Library Wizard window. Thewizard simplifies the library creation process. You can insert files with VHDL code or statediagrams to the new library or create an empty one. The Wizard helps you locate the desired filesand guides you through the whole process.


35

Archiving designs

To prevent any accidental design file deletions and to provide you with the additional exchangeand backup options, Active-HDL comes with the Archive Design feature that allows archiving thedesign in a single ZIP archive file. By default, the file name is identical with the design name.

Archiving the design

As you can see in the figure above there is a check list where you can specify what files shouldbe included in the archive file. To restore the design use any tool that accepts the ZIP archiveformat.

Conclusion

In a typical design, resource files are created at different stages of the design process. Many ofdesigners first create behavioral HDL files and testbenches, then import the structural design filesand timing specifications for the simulation. Without a smart plan the user may end with stacks offiles in one folder and no idea where the required ones may be found.

As described in this application note, Active-HDL provides for efficient design management. In asituation when there are various design versions, you may lose the track of files that belong toeach design version. Active-HDL allows you to create any number of project backups to preventaccidental file removals or modifications. The user can change the settings of the entire projectwith minimum effort, by checking appropriate options in the Settings window. The top-leveldesign model can be changed within the Design Browser window, invoked from the contextmenu.

Active-HDL offers the user several ways for executing the same commands. Less experiencedusers may prefer the menu commands and the more experienced ones may find the contextmenu the fastest way for executing any action. Whatever the user’s experience with CADsoftware is, he or she will certainly find the Active-HDL environment user-friendly and efficient.

37

Handling Libraries in VHDL, Verilog, and EDIF

Introduction

This chapter describes how to handle libraries in the Active-HDL environment. The purpose ofthis note is to familiarize you with the concept of the library and to teach you how to efficientlymanage the library contents. The simulator does not simulate the HDL code directly. First thedesign sources must be compiled into a working library which is then simulated.

Libraries in VHDL

A design entity you are going to simulate must be compiled into a library first. Only the datastored in a library after successful compilation can be read by the simulator.

A library can be a working library, a resource library, or both. A working library is the library intowhich the library units resulting from the analysis of a source file are placed. A resource library isa library containing library units that are referenced within the source file being analyzed. Onlyone library may be the working library during the analysis of a source file; in contrast, any numberof libraries (including the working library itself) may be resource libraries during such an analysis.

Logical names of resource libraries are listed in the library clause preceding a design unit insource code. For example, the following statement:

library IEEE,PRIMITIVES;

makes all design units residing in libraries IEEE and PRIMITIVE visible to the design unit thatfollows the statement. In addition, each design unit is assumed to be preceded by the followingimplicit statements, even if they do not appear in source code:

library STD, WORK;use STD.STANDARD.all;

The first statement makes visible design units residing in the standard library STD and in theworking library. The logical name WORK always stands for the working library, that is, the libraryinto which the source file is currently being compiled, irrespective of the actual logical name ofthis library. The second statement makes visible all declarations in the package STANDARD.

As for the working library, you can set it individually for each source file of a design using the FileProperties dialog box. By default, all source files are compiled into the default working library.

Example

Assume the file Simple.vhd contains source code listed below and is compiled into the libraryTEST:

library IEEE, PRIMITIVES;use WORK.GLOBAL_SIGNALS.all;use PRIMITIVES.GATES.all;entity CELL_X is...end entity CELL_X;

The CELL_X entity can reference design units residing in libraries: IEEE, PRIMITIVES, TEST(here TEST = WORK). All declarations contained within packages GATES (in libraryPRIMITIVES) and GLOBAL_SIGNALS (in library TEST) are also visible.

Application Notes

38

Libraries in Verilog

Neither the existence nor the rules of use of libraries is defined in the currently available Veriloglanguage standard. Some tools use Verilog libraries while others do not need them. Active-HDL isa simulation environment supporting several different HDLs (VHDL, Verilog, and EDIF netlists).To keep possibly uniform rules for all the supported HDLs, Active-HDL requires use of librariesalso for Verilog and EDIF.

A Verilog module you are going to simulate must be compiled into a library first. Only the datastored in a library after successful compilation can be read by the simulator. Specific modules of ahierarchical Verilog design can be compiled separately and in any order. Compilation of eachmodule creates a single library unit in the target library.

Like in VHDL, the target library into which a source file is being compiled is said to be the workinglibrary for this file.

When the simulator loads the top-level module, it must also load all the modules instantiatedtherein and in the underlying hierarchy levels. Verilog itself does not provide mechanisms forspecifying the resource library or libraries from which the hierarchically lower modules are to beloaded. Instead, Active-HDL searches the default working library and the libraries listed on theVerilog Libraries tab of the Design Settings dialog box. You can add any attached library to thislist. If a library you want to add is not attached, you must attach it first using Library Manager.

Libraries in EDIF

If you want to simulate an EDIF netlist with Active-HDL, you must compile it into a library first.Compilation of hierarchical netlists produces separate library units for the top-level cell and for thecomponent cells. All the library units are inserted into the default working library of the currentdesign.

Like in VHDL, the target library into which a netlist file is being compiled is said to be the workinglibrary for this file.

When the simulator loads the top-level cell, it must also load all the cells instantiated therein andin the underlying hierarchy levels. Non-primitive cells are searched for in the default workinglibrary of the current design. As for the primitive cells, EDIF netlists contain explicit specification oflibraries from which they are to be loaded. The simulator uses this information to load thecomplete design.

NOTE: To enable simulation of EDIF netlists generated by different tools, Active-HDL allowsremapping of cell names, pin names, and library names appearing in primitive cell instantiations.Such a remapping allows the use of reduced set of universal primitive libraries and is performedautomatically during compilation of netlist files. The description of the remapping rules resides inthe Edfmap.ini file stored in the $Aldec\Dat folder ($Aldec is an Active-HDL environment variablethat stands for the Active-HDL installation folder).

A tool that allows you to view and edit libraries and their contents, is Library Manager, describedin greater detail later in this chapter.


39

Library Units

The structure of Active-HDL libraries evolved from VHDL. A library is a storage for library units,that is, compiled design units that can be loaded into the simulator and simulated. There are twocategories of library units: primary and secondary. Secondary library units are inseparablyconnected with primary units. In other words, a secondary design unit cannot exist in a librarywithout its primary unit. The following is a list of library unit types in Active-HDL.

Language Primary Units Secondary Units

Entities

Entities result from the compilation ofentity declarations. An entity can besimulated only in conjunction with itsarchitecture.

Architectures

Architectures result from the compilationof architecture bodies. An architecturedescribes the contents of thecorresponding entity. A single entity canhave several optional architectures.

Packages

Packages result from the compilation ofpackage declarations.

Package Bodies

Package bodies result from thecompilation of package bodies. Apackage body is an extension of thecorresponding package.

VHDL

Configurations

Configurations result from thecompilation of configurationdeclarations.

–

Verilog

Modules

Modules result from the compilation ofVerilog modules.

–

EDIF

Cells

Cells result from the compilation ofEDIF netlists.

–

The icons displayed in the above table are used to represent library units (=compiled designunits) in Design Browser and Library Manager.

Each library unit is identified by its logical name. The following rules apply to library unit naming:

· Primary unit names must be unique within a single library.

· Architecture names must be unique for a given entity. If two architectures describedifferent entities, they can have the same name.

· Package body names must be the same as the names of the corresponding packages.

Application Notes

40

Block Diagram Symbols

In addition to simulation data, Active-HDL libraries store graphical symbols, which are used torepresent design units on block diagrams. Only primary units (except packages) can havesymbols. Library Manager indicates for each primary library unit whether it has a symbol or not.

Library Units without Simulation Data

It is intuitive to regard a library unit as a result of compilation of a design unit, that is, a portion ofHDL source code. However, Active-HDL allows insertion of library units into libraries also indifferent ways, which do not involve compilation at all. Library units inserted in that way do nothave simulation data and cannot be simulated. The library contains only the information that thelibrary unit identified by a given logical name exists and that the simulation data will probably becreated later on.

This mechanism is designed chiefly to enable creating new block diagram symbols in the top-down designing. When you employ the top-down methodology, you need to create symbolsbefore defining their contents (empty symbols and fubs). Defining an empty symbol or fub createsa new primary library unit in the default working library. This unit not only has no simulation databut its type, which can be either VHDL entity, Verilog module, or EDIF cell, is not defined either.The type will get defined the moment you push into the symbol/fub to create its implementation. Ifit is a VHDL entity, you will also create a new architecture. Still, the library unit(s) correspondingto the symbol will have no simulation data because you have not compiled the implementationyet.

NOTE: The VHDL compiler treats units without simulation data as if they did not exist. For thisreason, if you compile VHDL code referencing such units, the compiler will issue warnings thatyou have unbound components.

Physical Implementation

In Active-HDL, each design library consists of the following files:

· The library index file (with extension LIB), which contains a list of library units stored in alibrary.

· The library data files with fixed names 0<project_name>.mgf, 1<project_name>.mgf,2<project_name>.mgf or 3<project_name>.mgf which contain the simulation data as wellas symbols for the library units contained in the library.

The name of the library index file (without the extension) is said to be the physical name of thelibrary.

Libraries are referenced in source code by their logical names. Active-HDL associates logicalnames with physical names using the library list. This list contains assignments of logical namesto library index files (with full file paths). A single library can have several different logical names,but one logical name can be assigned only to one library. You can edit the library list usingLibrary Manager.

Example

The following entry appearing on the library list:

loadable_counter C:\My_Designs\Loadable_Counter\Loadable_Counter.lib


41

associates the logical name loadable_counter with a library comprised of four files:loadable_counter.lib, 0loadable_counter.mgf, 1loadable_counter.mgf,3loadable_counter.mgf residing in the folder C:\My_Designs\Loadable_Counter.

System Libraries vs. Design Libraries

All Active-HDL libraries can be divided into two functional categories: system libraries and designlibraries. The category of system libraries comprises:

· Standard VHDL libraries describing the predefined language environment (library STD)and multi-value logic system (library IEEE).

· FPGA Vendor-specific libraries and synthesis libraries.

System libraries are stored in the Vlib subfolder of the Active-HDL installation folder. This foldercan be referenced in the Active-HDL environment by using the predefined $Vlib variable.

Default Working Library

Each design in Active-HDL has at least onededicated library referred to as the defaultworking library. The name stems from the factthat all design source files are compiled into thislibrary be default. The logical name of thislibrary is the same as the name of the design.The library content is displayed on the Files tabof the Design Browser window. If you wish asource file to be compiled into another library,you should change the target library setting inthe File Properties dialog box. The defaultworking library is created automatically witheach new design you create.

Post-Synthesis and Post-Implementation Libraries

A single design library may be an insufficientsolution for certain designs. Some third-partytools used for synthesis and place-and-routeprocessing generate VHDL or Verilog filescontaining design unit whose names areidentical to the design unit names occurring inthe original pre-synthesis source files. Theproblem with such files is that you cannotcompile the post-synthesis and/or post-implementation VHDL files without overwritingthe library units obtained from the compilation ofthe pre-synthesis files. One possibleworkaround is to manually rename the designunits in the post-synthesis/post-implementationfiles. However, this is a rather awkwardsolution, especially when you want toimplement batch processing of the design.Active-HDL allows you to resolve the problemby setting up one or two additional designlibraries dedicated to post-synthesis and post-

Application Notes

42

implementation files.

The additional libraries are created automatically in designs that use design flowcharts employingthird-party synthesis and/or implementation tools. Clicking the button launching synthesisautomatically creates a new library in the design. Similarly, if you click the implementation button,a library for post-implementation files will be added to the design.

The contents of both libraries can be viewed on the Files tab of Design Browser.

The post-synthesis library resides in the Synthesis subfolder of the design folder. Its name is aconcatenation of the design name and string "_post_synthesis".

The post-implementation library resides in the Implement subfolder of the design folder. Its nameis a concatenation of the design name and string "_timing".

NOTE: If you use a single third-party tools for both synthesis and implementation processing, youwill need only one additional library.

Library Manager

Library Manager is designed to allow you manage Active-HDL libraries. You can perform thefollowing operations on libraries and their contents:

· Creating new libraries and setting up their working mode.

· Attaching, detaching and deleting libraries.

· Editing logical names of libraries.

· Compacting end emptying libraries.

· Viewing the contents of libraries.

· Viewing source files of specific library units.

· Deleting specific library units.

The Library Manager window is shown below:

The Library Manager Window

The Library Manager window contains two panels. The left panel shows a list of currentlyattached libraries and their parameters. It has four columns:

· Library - displays the logical name of the library.

· Mode - displays the working mode of the library. There are two modes: Read/Write (R/W)and Read/Only (R/O).

· Comment - displays an optional comment providing short description of the librarycontents.


43

· Directory - displays the library index file with the full path.

Standard libraries are attached to the list during installation. When you create a new library it isalso automatically attached to the list. Default working libraries appear on the list the moment youopen appropriate designs.

The right panel shows library units contained within the library selected in the left panel. Inaddition, if you select a package, a list of object defined therein will be displayed beneath ahorizontal split bar. The right panel contains the following columns:

· Unit Name - displays primary library units contained in the selected library. The library isselected in the left panel of the Library Manger window.

· Secondary Unit Name - displays secondary library units contained in the selectedlibrary. The only primary units that may have secondary units are entities and packages.For the remaining unit types, the column repeats the name displayed in the Unit Namecolumn. This is logically justified because when such units are referenced from VHDLcode in mixed designs, they are assumed to have "virtual" secondary units with the samename.

· Source Type - displays the type of the source document containing description of aspecific library unit. If the primary unit is a VHDL entity, this column displays the type ofthe source file describing a specific architecture, not the entity itself. In the case of non-VHDL units, the information in the column applies directly to the primary library unit. Theavailable source types are: Source Code (if the unit is described directly in VHDL orVerilog source code), Netlist (if the unit is described directly by an EDIF netlist), StateDiagram, and Block Diagram.

· Target Language - indicates the language of the source code from which the library unitwas effectively compiled. If the source type is either Block Diagram or State Diagram, thelanguage displayed here is that of the source code that was generated from the diagramfile. The available target languages are VHDL, Verilog, and EDIF.

· Symbol - indicates if the primary library unit has a block diagram symbol in the library.This information applies only to VHDL entities, Verilog modules, and EDIF cells.

· Simulation Data - indicates whether the library unit has simulation data or nor. Librariesmay include library units that have no simulation data. For details on such units, see thetopic Library Units without Simulation Data. If the primary library unit is a VHDL entity, theinformation in the column applies to its architectures, not to the entity itself.

Standard and user-defined libraries are denoted by a generic icon. Vendor-specific libraries aredenoted by their own unique icons.

Conclusion

As described in this chapter, the VHDL libraries are the backbone of any design. Because youcan use the already tested and verified standard libraries, the design process is simpler and moreefficient. By using vendor-specific libraries containing optimized entities, your design is far betterthan the one created from scratch and you obtain the best results while working with vendor-specific libraries.

Each design is compiled into the project's library before it is simulated, therefore the need for anefficient and easy-to-use library management tool is imperative. The Library Manager fromActive-HDL fulfills these requirements, allowing you for fast and reliable administration of libraryfiles. By executing simple context commands you can create, attach or remove selected librariesin a short time. To prevent libraries from accidental modifications by assign to them the ReadOnly attribute.

45

Simulator Overview

Introduction

The design verification process can be tedious and time-consuming. It gets worse when thedesign is developed over a period of time and the intermediate simulation results are saved intext files, which are often difficult to read and follow. To ease your work, Active-HDL provides youwith a graphical simulator that has many outstanding features. Even the most powerful simulationtool would be of limited value to design verification if it did not provide a user-friendly graphicalformat for viewing simulation results. Active-HDL has its own Waveform Editor with many built-inviewing features, these can enhance the management of simulation results.

Outstanding Functionality:

The Active-HDL is a context and easy to use tool equipped with many powerful features. To makeyour work easier, Active-HDL provides simplified operations for:

· adding and removing signals

· applying stimulators

· constraining the set of toggled values

· editing waveforms

· loading, saving and printing waveforms

Adding and Removing Signals

Before you start any simulation you must select signals that represent the input and output portsof the tested model or internal signals. There are several different methods of adding signals to aWaveform Editor. You can add them by dragging their names from the Design Browser windowwhile the Structure tab is selected. You can also select signal names in the same way you selectfiles in the Explorer window of the Windows system.

Another method of adding signals and ports is to right-click in the Waveform Editor window andselect the Add Signals option. For those who prefer typing commands, there is a way to addsignals from the Console window by typing Wave signal_name and pressing the Enter key. Youmay then add one signal at a time, including all signals from a process or all signals of your rootdesign.

Application Notes

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The Active-HDL Environment

If you added a wrong signal or want to remove one, you can do it by selecting the desired signalname in the Waveform Editor window and while it is highlighted pressing the Delete key. Theother way to delete a signal is to right-click on its name and select the Delete option.

By right-clicking the mouse in the right-hand side of the Waveform Editor window the signalsnames are displayed which gives you access to the following commands:

· Stimulators - allows the selection of a stimulator for the selected signal

· Add Signals - allows adding the signals to the Waveform Editor window

· Merge Signals/Split Signals - allows grouping and collapsing signals to/from virtualbuses

· Insert Empty Row - allows to separate two waves by inserting an empty row

· Create Expression Signal - allows to insert to the waveform a logical expression (signal)

· Cut/Copy/Paste - standard edition operations

· Hide/Show - allows to hide or display the selected signal(s)

· Delete - allows deleting selected signal(s)

· Clear Waveform - Clears selected waveforms currently displayed in the Waveform Editorwindow

· Compare selected - allows to compare two selected signals in the current window

· Find - allows to find the specified value or text in the currently opened waveform window

· View Declaration - displays the declaration of the selected signal in a code

· View in Dataflow - displays the selected signal in the Dataflow window

· Properties - enables specification of the properties for the selected signal

· Follow Object - opens the pull-down menu that contains the list of processes to follow

· Previous/Next Object - allows to browse the history of followed objects

BASIC Scripting Capabilities

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The context menu in the Waveform Editor window

Applying the Stimulators

Having all signals needed for simulation selected in the Waveform Editor window, you can nowassign stimulators to them. To do so select any signal name in the Waveform Editor window,right-click and select the Stimulators option. The same result is achieved by clicking theStimulators icon. In the Stimulators window (Figure) you can choose between differentstimulator types. Stimulators will drive your selected signals with the desired values.

The Stimulators Window

To learn more about different types of stimulators please refer to the Using Stimulators chapter.

Constraining the Set of Toggled Values

If you chose a Hotkey stimulator for a signal you may have to constrain the set of values betweenthe hot key toggles. The default set of values is comprised of ‘0’ and ‘1’. However, you mayexpand it by adding any valid logical values for the signal. For example if the signal A is of theStd_Logic type you can add additional logical levels such as ‘X’, ‘U’, ‘Z’, etc. But if a signal is ofBit type then the default set cannot be altered, because the Bit type has only two logical levels ‘1’and ‘0’. When applicable, should you select more than two logical values, toggling of the Hotkeywould select the available values in a sequence.

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The Default Set of Toggled Values

File Operations

In the process of design verification, you can develop signal waveforms that may be useful forfuture applications. Active-HDL allows saving such waveforms in a file. To save waveforms in afile, select the Save as option from the File menu. Saving results in a file is great fordocumentation purposes. Those files can be used in repetitive design verifications as testvectors. To load a file with waveforms, select the Open option from the File menu. You can printthe simulation results and attach them to your reports by selecting the Print option from the Filemenu.

Exporting simulation runs

The results of the simulation run can be exported into a text file either in the tabled format (.vec)or as the VHDL or Verilog processes describing the signal behavior. Such signal descriptions canbe used for automatic testbench generation. To export the waveforms into a file, use the ExportWaveforms option from the Waveform menu.

Rich Viewing Capabilities:

Active-HDL provides many viewing options that can be customized to your own needs:

· arranging signal sequence

· expanding and collapsing buses

· changing the signal display mode

· changing signal colors

· adding comments

· adding expressions

· overlapping results

· changing cursors

· changing time scales

· displaying glitches

· measuring time events

· snapping to grid or event

Arranging the Sequence of Signals

Since simulation results are independent from the sequence of signals in the Waveform Editor,you can rearrange these signals in a free manner, preserving all results and not stopping thesimulation. To rearrange signals, drag the selected signal to its new position. If it is done properly,the red line above the dragged signal moves along as you drag the signal. You can also arrange


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signals the ascending or descending alphabetical order. Click the Names tab several times andwatch the behavior of the window. You can also sort the signals with decreasing or increasingvalues by clicking the Value tab.

The Alphabetical Order

Expanding and Collapsing Buses

Having all signals displayed in proper order allows you to expand or collapse such compositesignals as buses. Some users find it easier to follow the changes when all bus wires areindependently displayed in the Waveform Editor. Others prefer to track the behavior of acomposite signal when it is collapsed into one piece. Active-HDL allows you to do either with justone click. Composite signals are displayed differently because they have a little square to the leftof them. When such a signal is expanded it displays a minus sign. One click on that sign makesall the sub-signals collapse. Collapsed signals display a plus sign allowing you to then expand thebus.

Bus And Signal Display

Changing the Signal Display

Changing the signal display is another useful feature of Active-HDL. There are three shapeformats for signals: analog, literal and logical. The literal and logical formats can also bedisplayed with different radix: hexadecimal, decimal, octal and binary. You can choose betweenoptions by right-clicking the selected signal and choosing the Properties option from the invokedcontext menu. That is, however, not all of your options. You can change the colors of thesimulation Viewer. By choosing Preferences in the Tools menu you can customize the look ofthe Waveform Editor to meet your needs. By default, all signals are drawn as dark blue lines onyellow background. However, you can draw any signal in the desired color by selecting theProperties option from the Edit menu. The same window appears after right-clicking any signaland selecting Properties from the context menu.

Adding Comments

To enhance the display of the simulation results making it more friendly and readable, Active-HDLallows you to add comments to the displayed waveforms. This allows you to keep track of thedesign in an organized manner. You may use the same waveforms in the future and intuitively

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recognize what the purpose of the original simulation was. When different people test the samedesign, it is simpler to have all the comments displayed on the waveforms.

To add a comment to a waveform, browse the contents of the Waveform Editor to the desiredlocation. Then click on the signal where you want to add the comment and select the Insert

comment option from the Waveform menu or click the Insert comment icon on the toolbar.Type the text that will be added to the waveform and press the Enter key.

Simulation With Comments

Overlapping the Results

Continuous verifications can be tedious and after a certain amount of time your perception maynot be as sharp as at the beginning. Some of the details may be overlooked. To prevent thissituation Active-HDL allows overlapping results from a previous simulation with the currentsimulation. To differentiate between the two simulation data, the previous results are displayed inwhite background while the new ones are drawn on yellow.

Overlapping Simulations

Changing Time Scale

If you test your design with different clock frequencies, this may result in an unreadable display.Fortunately, Active-HDL can display signals in a user-selectable time scale to zoom on timing

details. You can do it in several ways, either clicking the Zoom in or Zoom out icons orswitching to Zoom mode. The Zoom mode can be selected by choosing the Zoom mode option

from the context menu or from the Waveform menu and by clicking the Zoom mode icon inthe Waveform Editor toolbar. Another way to switch to a Zoom mode is to right-click in theWaveform Editor and select the Zoom mode option. Finally, you can decrease or increase thetime scale with simple clicks. If you left-click with your mouse then the time scale increases.However, if you left-click while holding down the Control key then the action is reversed and thetime scale decreases. The same operations can be performed by right-clicking the waveformdisplay and selecting either Zoom in or Zoom out from the context menu. The scope of the

zooming area can be also entered using the keyboard, to do so click the Zoom range icon.


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Zoom Mode

Displaying Glitches

If you find results that you cannot explain, it is not necessarily an error. Active-HDL has a built-inoption which displays glitches in the Waveform Editor. You can turn it on by disabling the Ignoreglitches option in the Waveform field of the Preferences window. For example, with this optionenabled, you can trace any errors that are due to incorrect setup or hold times. However, thisoption, if enabled, affects the comparison of simulation results.

Measuring Time Events

Sometimes you may wish to measure a time period between some events. To perform such ameasurement switch to the Measurement mode either by clicking the Measurement mode

icon or selecting the Measurement mode option in the Waveform menu or the context menuwhich is invoked by right-clicking. Typically, measuring time between two events would be difficultconsidering the precision with which the simulation results are displayed. You can, however, do itas precisely as needed because Active-HDL has an option that snaps the cursor to events. Thisoption is enabled by checking the Snap to event option in the Waveform field of thePreferences window. You can also check the Snap to grid option in the same window whichsnaps the cursor to the invisible mesh in the Waveform Editor window. To customize the grid,specify the grid options in the Preferences window.

The Preferences Window

If you are not sure what each icon does, point to it with the cursor and wait for a second. A shortmessage will appear describing the operation that the icon performs. On the other hand, if youpoint with the cursor on a signal in the Waveform Editor window and wait a while a signal

Application Notes

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declaration type will appear. To switch to the Select mode, choose the Select mode option fromthe Waveform menu or from the context menu.

Search Tools

After some time you may accumulate so many simulation results that you will not be able to easilymanage them yourself. However, Active-HDL has options that allow you to quickly locate anyevent in the signal’s history. There are several options that allow to find a specific value or browseby selected items:

· by page

· by bookmark

· by value

· by text in comments

· by difference mark

· by time

· by signal event

· by rising or falling edge

· by constraint

Search by Value or Text

You may find the desired signal value with minimum effort, by invoking the Find option from theSearch menu. The same window will appear when the Find option from the context menu isselected. There are two options you can choose from. First, you may find the entered value byselecting the Find value option. Selecting the Find text in the comments will start a search of allcomments for the text you have entered in the Find field. There is also an option for the directionof the search; click Forward or Backward to select the search direction.

The Find Window

Search by Time

If the results you are looking for should occur at a specific time you may go to that point by

invoking the Go to Time window. It can be done by clicking the Go to icon in the toolbar orselecting the Go to option either from the Search or context menu.

The Go to Time Window


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For details on searching or browsing waveforms refer to the Basic Operations on Signals andWaveforms and Navigating and Measuring Timing chapters in the Waveform Viewer/Editor |Procedures section.

Search by Event

Sometimes it is better to browse simulation results not by pages but by signal events. To perform

this operation, click the Next event or Previous event icons in the Waveform Editortoolbar. It is also possible to switch between bookmarks which you can leave at any time duringsimulation, by clicking with the pointer on the time scale, leaving a blue marker. To switch

between bookmarks, click the Next bookmark or Previous bookmark icons in thetoolbar.

Comparison of Simulation Results

The Waveform Editor also allows comparison of the simulation results. Signals for which thedifference was detected are displayed in the Waveform Editor window with the red color. The

icon enabling the comparison of signals is located in the upper part of the window. Theprevious simulation run results must be first saved in the project folder. In the case of differencesin simulation runs an appropriate message is displayed.

Comparing simulation runs

Conclusion

Simulation is designed to accurately verify the behavior of logical circuits, so that you can be surethat they will operate properly after they are manufactured. The results on the other hand, thoughcorrect, may be hard to check if not presented in a graphical manner. A graphical simulatordisplay provides a lot of well organized information and is user friendly. With rich viewing options,the Waveform Editor is a complete verification environment that allows you to freely customizethe look of the simulation results. At the same time it provides for instant verification of the designchanges.

You can save time by working with graphical tools instead of text files. Having all resultspresented in the preferred graphical helps find errors within seconds, you do not even have tobrowse the results by pages. Active-HDL allows you to browse the simulation by events.Moreover this lets you find any value, text or time of simulation with no extra effort.

Some users prefer to perform all the operations with the mouse, others find shortcut keyssuperior to menu commands. The Active-HDL commands will suit everyone, because eachoperation can be performed in several different ways. Each time an action is performed, it isverified by the change of the shape of the cursor.

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Introduction

This chapter describes how to create and execute files containing macro commands and BASICscript files. The Active-HDL macro command language is based on execution of BASIC scripts.By typing the command in the Console window you are actually executing the correspondingBASIC file. Every action and command menu in Active-HDL can be executed from the Consolewindow. You can execute a macro file containing sequences of macro commands to performcomplete simulation runs. Active-HDL also provides you with a graphical BASIC debugger thatallows you to create and modify embedded script files.

Console Window

The Console window is an interactive input-output screen for entering of Active-HDL commandsand displaying messages generated by Active-HDL tools. The Console window includes severaltabs to separate messages generated by different tools. The Console tab displays messagesgenerated by various tools. This tab also serves as an input for Active-HDL commands, whichallow you to perform various operations in the application without using the GUI menus andtoolbars.

The Console Window

List of Available Commands

Most of the implemented Active-HDL commands are invoked with parameters such as file names,signal names, line numbers, etc. After typing the help <macro_command> command in theConsole window you will switch to the Active-HDL Help window with the list of all availablecommands. Here is the list of selected macro commands with a short description of theirfunctions1):

abort stops the execution of a macro file that has been interrupted by abreakpoint.

acom invokes the VHDL compiler.

addvar adds variables defined by the set command.

addfile adds the specified file to the current design.

adel deletes a design unit from a design library.

adir displays the contents of the selected library.


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alib creates a new design library.

amap assigns a logical name to a design library.

architecture selects the specified architecture for the top-level design entity.

asim invokes the simulator.

bd deletes the specified below breakpoint.

bpallows you to set and view breakpoints. If command parameters areomitted, the command will list all currently set breakpoints. Otherwise, thecommand sets a breakpoint in the specified file and at the specified line.

bs sets a signal breakpoint.

bsd deletes a signal breakpoint.

cd changes the current working directory.

changemodifies the value of a variable. The simulator can do it only at abreakpoint or when it is paused after a step command.

clearclears the contents of the specified tab of the Console window or theConsole log file (Console.log) or document window (List Viewer orWaveform Viewer/Editor).

clearfile clears the contents of the specified file.

clearlibrary clears the contents of the specified library.

close closes the specified document window.

code2graphics launches the Code2Graphics converter.

compactlibrary defragments and deletes obsolete data from the specified design library.

compcompiles a specific source file or all source files attached to the currentdesign.

configuration sets the specified configuration as the top-level design unit.

continuerestarts the simulation after a step or step-over command or a breakpoint.The continue command can be entered manually. It can also be includedas the last command in a bp command string.

copyfile creates a copy of the specified file.

createdesign creates a project with the specified file name, configuration and path.

decdecrements the value of the specified variable defined with the setcommand.

des, describedisplays information about the type of the specified signal, variable orconstant

disablebp disables code breakpoints (without removing).

do executes commands contained in the associated macro file, which can

Application Notes

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have any name and extension. Any error encountered during theexecution of a macro file will interrupt its execution.

driversdisplays in the Console window the current and scheduled future valuesfor all drivers of the specified VHDL signal. If this signal is a type record orarray, only the drivers for the first sub-element will be displayed.

echo displays the requested message in the Console window.

echofile sends the specified message to the specified text file.

edfcomp invokes the EDIF netlist compiler.

enablebp enables breakpoints that have been disabled by the disablebp command.

endsimwaits for the end of simulation. Useful when you need to hold execution ofa macro until the end of current simulation.

entitysets the specified entity as the top-level design unit. To set thearchitecture, use the architecture command. By default, the last compiledarchitecture is used.

env, environmentprovides for changing and displaying the current region/signalenvironment.

ex, exa, examineanalyzes the specified item and displays its current value in the Consolewindow. This operation can take place at any time, but only if the simulatorhas paused at a breakpoint or after a step command.

expwave exports a waveform file into VHS or VEC format files.

fccompares two list files and saves the result of the comparison to a text file.The list files can contain up to 250 signals.

findstring searches a file specified by the <input_file> parameter for a text string.

forceis used for interactive assignment of stimuli to VHDL signals. There is nolimit on the number of stimuli in a macro file.

format list

creates a macro command file containing a sequence of list commandswith the names of the currently listed items and options for each signal.This file may be invoked with the do command to recreate the list windowformat on a subsequent simulation run.

format wave

creates a macro command file containing a sequence of wave commandswith the signal names in the Waveform window including their displayoptions. You can reproduce the Waveform window format on thesubsequent simulation runs by invoking the do command.

fsm2vhd generates VHDL code from a state machine diagram.

generatetb generate a test bench for the selected design entity.

gettime displays the system clock time in the Console window.

goto jumps to the line labeled with the specified parameter.

help Displays help on a specific Active-HDL command.


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if

executes the listed commands if the specified expression is true. Placingthe command in a macro file requires that the keywords if, else, and endifare the first tokens on a line. The entire command must be entered on thesame line when used in an interactive mode or in a breakpoint.

inc increases the value of the variable.

label see goto.

list (add list)

lists all HDL items (VHDL variables) and their values in the List window. Ifno port mode is specified in the list specifications, all interface and internalitems will be listed. If no arguments are listed, the command will displaythe List window.

noforcecancels effect of any active force commands on the associated HDL itemsand causes reevaluation of their values.

nolist deletes all listed HDL items from the List window.

nowave removes the specified item from the Waveform window.

onbreak

used exclusively within macros. It specifies a command that will beexecuted upon encountering a breakpoint in the source code. If thiscommand has no arguments, then no command will be executed when abreakpoint is detected in the macro source code. Instead, the associatedbp command string will be executed.

onerror

used exclusively within macros. It specifies a command that will beexecuted upon encountering an error in a source code. If the onerrorcommand has no arguments then no command will be executed when amacro encounters an error. A combination of the onerror and resumecommands will print an error message without halting the execution of themacro file.

open opens a file in the specified window.

opendesign opens the existing project.

pausewhen detected, the pause command halts execution of the associatedmacro.

pwd displays the name of the current working directory for Active-HDL

quietdisables or enables the quiet mode. In the quiet mode, message boxesare not displayed during execution of a macro.

quitexits the simulator without saving data. However, prior to exiting thesimulator, you will be asked for confirmation.

radixspecifies the default radix for all commands (change, examine, force, etc.).It is also used for displayed values in the List, Watch, and Waveformwindows.

removedesign erases specified design from the disk.

removefile erases specified file from the disk.

restart reloads the design sections that have been changed and resets the

Application Notes

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simulation time to zero. The design sections that remain unchanged willnot be reloaded by this command. This speeds simulation on subsequentruns.

run forces the simulator to perform the specified number of time steps.

runexe runs an executable (*.exe) or batch (*.bat) file.

runscript executes a script from the Console window

savealltabssaves information from all tabs of the Console window to a log file(Console.log).

setproduces user-defined variables. Returns a list of all user-definedvariables, if used without arguments. Use a dollar sign ($) any time youreference a command line to a user-defined variable.

setlibrarycomment attaches a comment to the specified library.

setlibrarymode sets the access mode for the specified library.

sourcedisplays the selected HDL source file in the HDL Editor window and isused for setting a breakpoint in a file other than the one currentlydisplayed in the HDL Editor window.

step

forces the simulator to step to the next or desired HDL statement(descending into the subprogram body). Optionally, the VHDL proceduresand functions can be skipped. Time advances to the next scheduledactivity.

stop stops the current simulation.

sub subtracts variables defined by the set command.

trace

logs the history of selected signal in an internal data base. The base is thesource of data for the List and Waveform Editor output windows. Signalsthat are displayed using the list and wave commands are automaticallyrecorded in the data base. A signal which has been logged and issubsequently added to the List or Waveform Editor window will have itscomplete history back to the start of logging.

tran, transcriptechoes commands executed in a macro file. The current setting isreported if no argument is specified.

viewopens the specified window. In case of non-document windows (Console,Watch, Processes, Library Manager, Design Browser), the commandalso closes the specified window (if opened).

vlcomp invokes the Verilog compiler.

wave used for adding signals to the Waveform window.

wavecompare compares currently loaded waveform with a waveform saved in a file.

wheredisplays information about the system environment, which is useful fordebugging problems when the simulator cannot find the required librariesor support files.


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write Saves the contents of the List window, Waveform Editor window, or BlockDiagram Editor window to a file in its native format.

1) See the updated list of macro commands in the Active-HDL Macro Language chapter.

Files with Macro Commands

Active-HDL allows you to create macro files that contain sequences of macro commands. Byexecuting such a file you can run an entire simulation provided you had earlier prepared all therequired files such as model description, test vectors, etc. Let's look at the example macro fileused for verification of the Counter project that is included with Active-HDL. The upper part of thefile rebuilds the project in quiet mode, loads counter description files COUNTER8.VHD and testbench file TESTBENCH.VHD, and selects the TESTBENCH_ARCH as the top architecture. Thelower part of file initializes the simulator, adds the signals to the Waveform Viewer and runssimulation. As you can see, a macro file is rather easy to follow once you know the macrocommands.

Example:

A macro file FUNCTIONAL.DO included in project Counter

# rebuild whole projectsavealltabsquiet onacom counter8.vhdacom testbench.vhdasim testbench TESTBENCH_ARCH

# initialize simulationwavewave CLKwave RESETwave CEwave LOADwave DIRwave DINwave COUNTrun -allendsimquiet off

Software execution

The Console window allows you to execute external files such as system commands, softwaretools, etc. You may even run the placement and route tools for the project being developedwithout invoking the GUI of the appropriate software. This is a good way of developing designlayouts, because it saves time. This method, however, requires proficiency in using the softwaretools, because you have to have in-depth knowledge of the software you are using.

Conclusion

All macro commands in Active-HDL are based on BASIC script files stored in the SCRIPTSdirectory. You can invoke any menu command from the Console window. There is also an option

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allowing you to execute a script file containing sequences of commands that can perform theentire simulation process. Moreover, by using the BASIC programming language you can developscripts for the frequently used routines and common operations. For example, when testingdesign behavior at different stages of development, you can improve your productivity by creatinga BASIC script file that automates the execution of repeatedly invoked commands such asopening the project, initializing the simulation, applying the stimulators, saving the results in thefile, etc.

BASIC language is not hard to learn, however, it requires a good knowledge of the systembehavior. Users may relay on the macro commands provided with Active-HDL, moreover, theymay try to enhance the functionality of Active-HDL with self-written scripts.

The script files are not easy to write, but the effort you put in developing them will return higherproductivity in future. For example you may save a lot of time testing libraries, where the sameactions are performed over and over. However, you may spend some time developing the scriptswhich will allow automatic testing of these libraries.

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Tcl/Tk Scripting

Introduction

Tcl (Tool Command Language) is a simple scripting language for controlling and extendingapplications. Tcl together with its extension, Tk, provides a programming system for developingand using graphical user interface (GUI) applications. The interpreter engine built in Active-HDLsupports version 8.0 of the Tcl/Tk standard. Tcl scripts can be invoked directly from the Consolewindow as well as from the GUI (using user-defined menu items and buttons). The HDL Editorsupports keyword coloring for Tcl/Tk scripts. However, there is no built-in mechanism fordebugging these scripts.

Using Tcl/Tk Scripts

A Tcl/Tk script is a single text file containing a program created in the Tcl language (ToolCommand Language). Such a script can be executed from the Console window by therunscript macro command :

runscript <scriptname> [ <parameter_value> ...]

You can pass optional command line arguments (separated by spaces) into the script, providedthat a script expects them. If you are going to run this script from the Console window, the scriptfile should be stored in the $DSN/src folder ($DSN is the Active-HDL environment variable thatspecifies the path to the directory of the current design). Otherwise, you will have to specify a fullpath to the script. If you are going to link a script to a user-defined menu item, the script file canbe located anywhere since, in this case, you always specify the path. By creating your ownscripts, you can extend the functionality of the Active-HDL macro language.

In the Active-HDL environment, scripts are considered resource files. As such, they can beattached to designs like other resource files, e.g., source files. For more details, see DesignBrowser help (Files tab).

You can create Tcl scripts using any non-formatting text editor. However, the built-in HDL Editoris the best suited editor for this purpose because it supports the keyword-coloring of the Tcl/Tksyntax. Note, however, that Active-HDL provides no debugging mechanisms for Tcl/Tk scripts.

Controlling Active-HDL from Tcl/Tk Scripts

By using the Tcl/Tk scripts you can achieve the same functionality as the one provided by theActive-HDL macro language.

The following Active-HDL macro commands are implemented as Tcl functions inside themacros.tcl package:

· acom

· addadvdataflow

· add list

· add mem

· copyfile

· coverage

· createdesign

· dec

· des

· help

· if

· inc

· label

· list (add list)

· sm_reset

· sm_session_cmd

· sm_win

· sm_prepare(VHDL)

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· add wave

· addfile

· addvar

· adel

· adir

· alias

· aliaspar

· aliasswitch

· alib

· alog

· amap

· architecture

· asim

· bd

· bp

· bs

· bsd

· cc merge

· change

· clear

· clearfile

· clearlibrary

· code2graphics

· comp

· compactlibrary

· configuration

· describe

· design

· disablebp

· do

· drivers

· echo

· echofile

· edfcomp

· enablebp

· endsim

· entity

· env

· environment

· examine1)

· expwave

· fc

· findstring

· flushlogs

· force

· fsm2vhd

· generatemacro

· generatetb

· gettime

· goto

· gototime

· makeup (ucase)

· noforce

· nolist

· notrace

· nowave

· onbreak

· onerror

· opendesign

· pause

· psd

· quiet

· quit

· radix

· removedesign

· removefile

· restart

· run

· runexe

· runscript

· savealltabs

· set

· setactivelib

· setlibrarycomment

· setlibrarymode

· sm_cmd

· sm_prepare(Verilog)

· step

· stop

· sub

· tran

· transcript

· ucase (makeup)

· vcom

· vdel

· vdir

· view

· vlcomp

· vlib

· vlog

· vmap

· vsim

· vsimsado

· wave (add wave)

· wavecompare

· where

· workspace

· write

(*) Function examine in Tcl returns the value of the specified VHDL object in decimal format. Noradix specification is allowed.

All the functions listed above have the same arguments as their counterparts in Active-HDLmacro language.

A Tcl script can call another script of any type (BASIC, Perl, Tcl) as well as a macro file. Toenable this, the following line should be included in the Tcl script file:

package require ::aldec::scripter 1.0

To execute a BASIC script, use the following statement:

::aldec::scripter::ExecuteScript "runscript -bas <script_filename><parameters>"

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To execute a Tcl script, use the following statement:

::aldec::scripter::ExecuteScript "runscript -tcl <script_filename><parameters>"

To execute a Perl script, use the following statement:

::aldec::scripter::ExecuteScript "runscript -perl <script_filename><parameters>"

To execute the macro file, use the following statement:

::aldec::scripter::ExecuteScript "runscript -do <script_filename><parameters>"

In the above examples, <script_filename> stands for the name of the script file with the extensionand a path. <parameters> denotes the optional list of parameters (if the script requires any).

NOTE:

· The Tcl/Tk language syntax requires double backslashes in the path specifications.

· You don't need to provide a path to the script file if it is attached to the active designor it is located in the $DSN\src directory.

Example 1

# Use ::aldec::scripter package (access to scripter interface)package require ::aldec::scripter 1.0# Hide the main window

wm withdraw .# Execute a macro startup.do that is normally executed during# Active-HDL startup:package require ::aldec::scripter 1.0::aldec::scripter::ExecuteScript "runscript -do\$aldec\\script\\startup.do"

Example 2

package require ::aldec::scripter 1.0

# prevent from echoing commands to the Console window::aldec::RunCommand "transcript off"

# turn on the "quiet" mode (no message boxes will be displayed)quiet on

#initialize the simulation for the and2 moduleasim and2 and2

#add a0, a1, and y signals to a waveform windowwave a0 a1 y

# set stimulators for a0 and a1 signalsforce a0 0 0 ns, 1 100 ns, 0 130 ns, 1 150ns, 0 200nsforce a1 1 0 ns, 0 110 ns, 1 140 ns, 0 200ns

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# perform simulation as long as Y signal value does not equal 1# (and stop if simulation time exceeds 200 ns)set k 0while {[examine Y] != "1" && $k < 20} {set k [expr $k+1]run 10 ns}# end the simulationendsim

# turn off the "quite" modequiet off

# turn on command transcriptions::aldec::RunCommand "transcript on"

Modulator Example

Active-HDL comes with a Modulator example, which employs a Tcl/Tk script to run an automaticsimulation. Tcl/Tk scripts are executed in Active-HDL similarly to the macro command files. Thisis done by selecting the Tcl/Tk file in Design Browser window and then choosing the Executecommand from the context menu.

Executing the Tcl/Tk script.

After executing the Modulator.tcl script you will see the following window displayed in the centerof the Active-HDL environment. The simulation is thus controlled from within the window byappropriate buttons and scroll bars. This method of providing simulation stimuli is more intuitiveand efficient.

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Simulation window created in Tcl/Tk script language

The remaining part of this application note explains the particular elements of the Modulator scriptresponsible for creation of the window described above.

Initialization

Instead of manually forcing the input signal values in the Modulator example you can use thewindow described above. By clicking the appropriate buttons and sliding the scroll bars you canforce required input stimuli and perform a 100 ns simulation steps. Each user action (sliding ascroll bar or pressing a button) is also signaled with a sound stored in a WAV file attached to thedesign. The initial part of the Modulator script contains declarations of the packages used lateron. Apart from the scripter package containing Active-HDL macro commands, the mmediapackage is declared as well. This package allows to use multimedia files such as graphics orsounds in the script. The set command sets the global dsn variable, which stores a path to thedesign (the value for this variable is taken from the Active-HDL environment by theGetVariable function stored in the scripiter package). The square brackets surrounding the setfunction call replace the call with its result.

## BEGIN SETTINGS ##wm withdraw .package require mmediapackage require ::aldec::scripter 1.0set dsn [::aldec::scripter::GetVariable "dsn"]

Compilation and Simulation

The acom is a Active-HDL macro command that compiles the design files while the asiminitializes the simulation of the Modulator design.

## COMPILATION AND INITIALIZATION ##acom SinusGenerator.vhdacom CosinusGenerator.vhdacom SawGenerator.vhdacom Multiplier.vhd

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acom Modulator.bdeasim Modulator

The following code executes the open macro command that opens the wave1.awf file in theWaveform Editor window. The force command sets up a stimulator for the CLK signal.

## PREPARING FOR SIMULATION ##::aldec::scripter::ExecuteScript "open" {-wave $dsn\src\wave1.awf}force CLK 0 0, 1 500 ps -r 1000 ps

Setting Up Windows

Tcl/Tk scripts can contain single line commands as well as procedures. Below are the proceduresresponsible for:

· positioning the simulation window shown earlier - positionWindow

· playing the selected sounds - ButtonSound

· removing the signal stimuli bound to the signals and ending the simulation - ExitProc

## GUI SETTINGS ##proc positionWindow . {

wm geometry . +300+300}

proc ButtonSound {SoundNumber} {global dsnswitch $SoundNumber {

1{sndPlay -async -nodefault [file join $dsn src2 sounds"Default.wav"]}

2{sndPlay -async -nodefault [file join $dsn src2 sounds"Minimize.wav"]}

3{sndPlay -async -nodefault [file join $dsn src2 sounds"Recycle.wav"]}

4{sndPlay -async -nodefault [file join $dsn src2 sounds"Exclamation.wav"]}

5{sndPlay -async -nodefault [file join $dsn src2 sounds"Question.wav"]}

6{sndPlay -async -nodefault [file join $dsn src2 sounds"WindowsExit.wav"]}

}}

proc ExitProc {} {noforce sinfreqnoforce sinenablenoforce sawfreqnoforce sawenablenoforce cosfreqnoforce cosenablenoforce clkendsim

}

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The code lines below represent a sequence of Tcl/Tk commands that create a simulation windowwith appropriate labels displayed. The positionWindow procedure sets the position of thewindow, next the ModulatorIcon.gif file is loaded by the image command. The frame commandsets frames inside the window containing separate functional parts of the window. For example:labels, buttons, scroll bars, etc.

wm iconify .wm deiconify .set . .buttonset . .label

wm title . "MODULATOR ON Tcl/Tk"wm iconname . "button"wm iconname . "label"positionWindow .

frame .labels -relief raised -bd 1image create photo Modulator \-file [file join $dsn src2 images ModulatorIcon.gif]label .labels.image -image Modulator

label .labels.msg -wraplength 5i -justify left -text"The Modulator contains three oscillators.The buttons labeled SIN, COS and SAW activate appropriate oscillatorswhose frequencies are controlled by the sliders located below thebuttons.RESTART - restarts simulation.100ns - advances simulation by 100 ns.EXIT - ends simulation and exits the dialog."

pack .labels.image .labels.msg -side left -expand yespack .labels -side top -pady 1 -expand yes

frame .sinus -relief raised -bd 1frame .cosinus -relief raised -bd 1frame .saw -relief raised -bd 1frame .buttons -relief raised -bd 1pack .sinus .cosinus .saw .buttons -side left -expand yes -pady 1

Buttons

The buttons are created with use of the bitmap files stored in the project directory. Each button inthe example has two positions: on - SinIn and off SinOff. To employ the button images youcan use the image command. The image command is used to create, delete, and query images.

image create photo SinOff \ -file [file join $dsn src2 imagesSinOff.gif]image create photo SinOn \ -file [file join $dsn src2 imagesSinOn.gif].sinus.b1 configure -selectcolor [.sinus.b1 cget -background].sinus.b1 select

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Sounds

Depending on the current button state: pressed or released, the appropriate bitmap is displayedand a required sound is played as well. The button sounds are indexed and bound with theButtonSound procedure. In the following example the ButtonSound command is invoked with2 as a parameter, which means that the "Minimize.wav" wave file will be played every time thebutton is pressed.

checkbutton .sinus.b1 -image SinOff -selectimage SinOn -variableSinEnable\-indicatoron 0 -command "ButtonSound {2}"

Scroll bars

To create a vertical bar in the window you can use the following scale command:

scale .sinus.scale -font system -orient vertical -length 200 -from 1-to 200 -tickinterval 99 -label "MHz" -variable SinFreq -command"ButtonSound {1};set temp1"

Controlling the simulation

With the simulation window set up the user is able to control the simulation by clicking theappropriate buttons. The RESTART button executes the Restart Simulation command from theSimulation menu. Each 100NS button click invokes the Run100ns procedure that performs asimulation step. Below is the code that creates, binds the appropriate sounds (from the sound setdefined previously) and controls the behavior of the RESTART and 100NS buttons.

button .buttons.restart -font system -text "RESTART" -width 13 -height 3 \

-command "ButtonSound {4};::aldec::scripter::ExecuteScriptrestart;"button .buttons.100ns -font system -text "100NS" -width 13 -height 3\

-command "ButtonSound {5};Run100ns;"

The Run100ns procedure uses globally set variables to force appropriate signals and advancethe simulation for 100 ns.

proc Run100ns {} {global SinFreq CosFreq SawFreq SinEnable CosEnable SawEnable force sinfreq $SinFreqforce cosfreq $CosFreqforce sawfreq $SawFreqforce sinenable $SinEnableforce cosenable $CosEnableforce sawenable $SawEnablerun 100 ns}

label .buttons.label1 -text "" -width 10label .buttons.label2 -text "" -width 15 -height 3

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label .buttons.label3 -text "" -width 10label .buttons.label4 -text "" -width 10

The EXIT button allows the user to end the simulation by invoking the ExitProc procedurewhich removes the bound signal stimulators and executes the endsim Active-HDL macrocommand.

button .buttons.exit -font system -text "EXIT" -width 13 -height 3 \-command "ButtonSound {3};ExitProc; destroy ;set end_tcl true"pack .buttons .buttons.restart .buttons.label1 .buttons.100ns.buttons.label2 .buttons.label3 .buttons.label4 .buttons.exit -sidetop -expand 1

wm protocol . WM_DELETE_WINDOW "ExitProc; set end_tcl true"

tkwait variable end_tcl

Conclusion

The example described in this application note shows only several aspects of the Tcl/Tk scripting.See the Tcl/Tk Reference Manual in the Active-HDL Online Documentation (Help | On-lineDocumentation | References | Tcl/Tk Reference Manual) to find out more about powerfulabilities of the language.

As you may conclude, the Tcl/Tk scripts allow you to control the Active-HDL environment fromwithin one file. There are lots of benefits of creating Tcl/Tk scripts. Once created, they can beeasily modified to supply other designs with required stimuli. Projects containing Tcl/Tk scriptscan be controlled easily by beginners as well as advanced users.

71

Creating FPGA and CPLD Designs

Introduction

This chapter describes typical approach to designing FPGA and CPLD devices in Active-HDL.The purpose of this note is to provide you with a basic understanding how Active-HDL operatesas a complete design environment, including an HDL editor, State Editor, Block Diagram Editor,simulation and design implementation or synthesis. The document does not focus on any specificFPGA or CPLD vendor. Detailed guidance on designing vendor-specific parts is the subject ofvendor-specific tutorials.

Resource Files

In a typical FPGA/CPLD design, Active-HDL operates on resource files such as source files, SDFfiles, macro files, etc., created at different stages in the design process. Most designers firstcreate behavioral VHDL files (used for synthesis) and test bench files that are used for modelverification. After implementation or logic synthesis of the behavioral files next step is to importinto Active-HDL the structural design (i.e. netlists) and timing files (i.e. SDF) generated by thesynthesis and Place&Route tools for timing simulation. Since all these files reside within the samedesign it is a good idea to group files into folders for better clarity:

· Functional - contains groups of files created at the initial stage of the design process. Itincludes source files intended for synthesis and test benches used for design verification.

· Timing - contains groups of files generated by the FPGA/CPLD implementation tools.They are used for timing simulation and usually comprise:

· Structural VHDL files modeling the physical netlist

· SDF files containing timing data used to annotate timing models.

· Simulate - contains groups of macro files launching functional and timing simulations.These macro files contain Active-HDL commands.

· Implement – contains groups of macro files used for launching synthesis andPlace&Route programs (see section on Synthesis).

The Design Browser allows you to create any number of folders. You can name these folders tobest describe their contents.

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The Design Browser Window

Behavioral Simulation (Functional)

The initial VHDL description of the design undergoes functional verification in the behavioral HDLsimulator. The most important task at this stage of the design process is creation of appropriatetest vectors. Test vectors provide simulation input for the design, in response, the simulatorproduces design outputs. Evaluation of the output response provides the answer to whether ornot the model’s behavior satisfies the designer’s expectations.

In Active-HDL, you can apply stimulus to the input models in three different ways:

· By using the Stimulators tool in the Waveform Editor window. The dialog supportsseveral different techniques of defining the stimulus waveforms. The contents of theWaveform Editor window are saved to a file, which can be used later on in othersimulations and to generate test bench files.

· By creating a macro file containing sequences of force commands.

· By creating a VHDL test bench file. A test bench file contains a design entity/module asa host environment for the tested design entity. Depending on the degree of designcomplexity, the test bench can automatically produce input stimulus and compare theoutput response with the previously defined output vectors.

Creating Test Benches

The figure following illustrates the concept of a test bench.

The Test Bench Structure

A test bench forces the desired stimuli on the inputs to the tested design unit (Unit Under Test =UUT) to enable functional verification of the design. In addition, advanced test benches canperform a comparison of the output response with a previously defined test pattern.

Active-HDL supports automatic generation of test benches based on waveforms that have beenpreviously created in the Waveform Editor window and saved to a file. The test bench file


73

contains a test bench entity declaration and its own architecture body. The architecture bodycontains:

· Component instantiation for the UUT entity.

· Local signals mapped to ports of the UUT entity.

· A process statement that forces stimulus on the local signals connected to input ports ofthe UUT entity. This statement is included only if a waveform file was specified as asource of test vectors. Otherwise, the user has to supply the appropriate process.

Re-using Test Benches from Functional Simulation

It is possible to use the same test bench for timing simulation that has been used for functionalsimulation. The shortest way to do so is to write a configuration declaration that binds thearchitecture body obtained from the Place and Route tool to the UUT entity. Such an approach isapplicable only if the entity obtained from the Place and Route tool matches the UUT entity in theinitial VHDL description with respect to ports and generics.

Interface to Logic Synthesis in Active-HDL

After the design has been verified at the behavioral level, it should be synthesized in order toobtain a netlist for physical implementation. Active-HDL provides an interface to synthesis tools -the Console window. The user can write macros, executed in the Console window, that will callexternal synthesis programs (Exemplar, Synplify, FPGA Express) and pass data to and fromthem. Moreover, it is possible to extend the macro language by adding user-defined basic scriptsthat implement new commands. In this way, it is possible to create a user-customizable interfaceto external synthesis and Place&Route tools. The only restriction arises from the fact that externalprograms are called along with parameter specification from the command line. Not all programscan work in such a mode.

The Design Flow Diagram

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Different synthesis tools have their specific sets of options. The information on these options isavailable in proprietary documentation for specific tool.

To facilitate calling up the external software the user can specify new Tools option invoking thesynthesis tool.

New option for FPGA-Express execution

Some synthesis tools can export synthesized netlist in the VHDL format. Simulation of suchVHDL code, and comparison with the functional simulation results of the initial behavioraldescription gives you additional verification of the design.

Active-HDL provides direct interfaces to a variety of synthesis and Place and Route tools formany vendors and target devices. Active-HDL can import Active-CAD projects into itsenvironment.

Design Implementation

The netlist produced by synthesis tools is an input for Place and Route tools. The final result ofrunning a Place and Route tool is a bitstream file that can be downloaded into a programmableFPGA device. Most FPGA/CPLD vendors place and route tools generate a physical VHDL model(Vital) of the implemented design which can be used for timing simulation. The model is structuraland based on primitive models supplied in the vendor-provided VHDL libraries. (Appendix Aprovides a list of vendor-specific libraries shipped with Active-HDL.)

Most libraries with timing primitive models are based on VITAL procedures.

Primitive models used for timing simulation possess a set of timing parameters (passed on to themodel through generics). Two methods are used for defining the value of these generics:

· The actual values are defined directly in the VHDL code by the “generic map aspect.”· The actual values are specified in separate files, provided in the SDF (Standard Delay

Format) format.

Adding Post Place-and-Route Files to Design

Using Design Browser, attach to the files obtained from the Place and Route tool to the design.These files usually are:

· VHDL file(s) containing a structural model for timing simulation.

· SDF file(s) containing timing parameters (if SDF generation is supported).

You can also create a separate and new design for files obtained from the Place&Route tool.


75

Simulating designs after Place-and-Route

The Place-and-Route tools generated VHDL file contains an entity-architecture pair (designentity) describing the design implemented in an FPGA /CPLD device. In general, the entity andarchitecture in the generated file can have any names. Note that if these names are identical tothose of the design units in the initial design description, compilation of the post-Place-and-Routefiles will cause the same design units to be overwritten in the default design library.

It is also important that the ports of the post-Place-and-Route entity match those of the entity inthe initial description, otherwise the simulator using the test bench file may not be able togenerate proper results.

Performing Timing Simulation (SDF)

To simulate the timing model obtained from the Place&Route tool, you must:

· Select the entity-architecture pair from the post Place&Route file.

· Active-HDL automatically seeks the region for which the SDF file is to be loaded.

Checking the automatic region seek option for the SDF file

Creating VHDL Code for Logic Synthesis

When you create a model intended for synthesis, you should have in mind a general notion of itsstructure. If you do not use this approach, the resulting VHDL code may contain constructs thatare not acceptable for synthesis tools. Moreover, if the synthesis of a VHDL model is successful,the results of functional simulation for the netlist in a gate level simulator may differ from theresults of VHDL simulation of the initial model. This may result from the fact that:

A) Synthesis tools impose specific constraints on the range of available VHDL constructs andcontexts in which they can appear.

B) Synthesis tools also infer the logic from the context in which specific VHDL constructs appear.

Before you begin writing the VHDL code, consult the documentation of the particular tool you aregoing to use for logic synthesis.

· Test bench files are intended only for simulation and thus they do not have to comply withthe constraints imposed on VHDL syntax by synthesis tools.

· Each synthesis tool provides packages with functions, procedures and attributes useful increation of synthesizable models. Particularly, attributes defined in such packages areused to pass specific information to the synthesis tool (e.g. the pin numbers, machineencoding methods, etc.).

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· If a design is targeted for an FPGA /CPLD device from a specific vendor, you can uselibraries of functional modules and primitives prepared by the vendor. For most vendors,Active-HDL provides libraries in the compiled format. By adding appropriate libraries anduse clauses into your VHDL files, you can use modules contained in these libraries.Appendix A contains a list of all vendor-specific libraries shipped with Active-HDL.

· In addition to libraries of modules, some Place and Route tools also acceptparameterized modules. Parameterized modules can be instantiated directly by the userin the VHDL code, or by synthesis tools in the netlist.

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How to Simulate Designs

Introduction

This chapter describes how to stimulate input signals in the Active-HDL simulator. All examplesused in this document are based on the COUNTER sample design which is included with thesupplied software. Active-HDL supports the following methods of stimulating or forcing inputsignals during the simulation:

· Manually selected stimulators from the Active-HDL resources

· VHDL Testbench files that have been created by the Testbench Wizard

· User created created VHDL testbench files

· VHDL WAVES Test Bench files (as per IEEE WAVES specification 1029.1)

· Simulation commands entered from the console window

· Files containing simulation macro commands

· Test Vector files imported from Active-CAD

· Simulation input based on waveforms edited by the user

All these methods providing design stimuli can be combined in the same design. You can choosea method which is best suited for your specific design needs and be assured of a good balancebetween the time required to create simulation input and the complexity of the design verification.

Stimulators

The easiest way to create simulation stimuli is adding the desired signals to the WaveformEditor and assigning stimulators that are available from the Stimulators option. There areseveral types of stimulators you can choose from. The following stimulator types are supported:

Value stimulators allow you to assign a value to the selected signal. The values can beforced on any signals and buses (vectors) and can be applied at any time duringsimulation. The simulator performs a signal type check to verify that the specified valueis allowed for the selected signal type.

Formula stimulators allow entering signal waveforms using special formula expressionsthat can describe asynchronous signals by specifying their transition times and values.For example a formula “0 0, 1 10" describes a waveform that starts with value '0' attime 0 and changes to '1' after 10 simulation units.

Hotkey stimulators allow you to control signal values directly from the keyboard. Youcan select any keyboard key as the hotkey stimulator and assign it to any desiredsignal. Toggling this hotkey will toggle signal values. For example, if you assign 'R' as ahotkey to the “reset” signal, then you can toggle the value of the “reset” signal duringthe simulation by pressing the R key on your keyboard.

Clock stimulators are designed for modeling of clock waveforms. The Active-HDLgraphical clock editor allows you to specify clock frequency, duty cycle, etc.

Counter stimulators enable defining counters for signals of vector type. Different countradix are available as well as direction and time period for signal changes.

Predefined stimulators are clocks with predefined frequency and duty cycle andformulas created by you for the most frequent applications.

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formulas created by you for the most frequent applications.

Custom stimulators are created by assigning graphical waveforms displayed in theWaveform Editor as the simulation input. These waveforms are displayed in theWaveform Editor by using waveform editor, formula or hotkey stimulators.

The Stimulators window

Advantages of Stimulators:

· The quickest and easiest method of forcing signals to the desired states.

· Interactive assignment of stimulators allows instant viewing of the simulator's response.

· Stimulators can be applied to any signal and port in the design hierarchy.

· Handy in debugging low level processes and architectures.

Disadvantages:

· VHDL Test Bench can only drive signals at the top design level.

· Stimulators are saved as waveform files.

· Stimulators are not sufficient for performing such complex simulations as reading datafiles, etc.

Stimulators are proprietary to Active-HDL and will not work in other VHDL simulators.

Waveform Editor

The Waveform Editor allows you to graphically edit any waveform by using dragging, copying,pasting and drawing new waveform signals. These waveforms can be used as custom stimulatorsby assigning them to the desired signals.

Graphically edited waveforms can also be used as simulation input in conjunction with the TestBench Wizard, described later in this document, which generates a VHDL test program that isbased on the edited waveforms.


79

Sample Simulation Run.

Comparison of Simulation Results

Waveform Editor also allows comparison of the simulation results. Signals for which thedifference was detected are displayed in the Waveform Editor window with the red color. The icon

enabling the comparison of signals is located in the upper part of the window. The previoussimulation run results must be first saved in the project folder. In case of indifferences insimulation runs an appropriate message is displayed.

Comparing simulation runs

Simulation Macros

Macros Entered in the Console Window

Active-HDL provides a macro command language for manual entering of such simulationcommands as forcing signal values, assigning formulas and executing simulation steps. You canforce a value on a signal at any time during simulation by entering the appropriate macrocommand in the Console window. You can also use macro commands to add forced signals tothe Waveform Editor, etc.

The Console window

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Example:Wave — creates an empty waveformWave CE — adds CE signal to waveformWave RESET — adds RESET signal to waveformWave LOAD — adds LOAD signal to waveformWave DIN — adds DIN signal to waveformWave DIR — adds DIR signal to waveformForce LOAD 1 0ns, 0 10ns— changes LOAD to 1 at 0nsand to 0 at 10nsForce CE 1 — changes CE to 1

Files Containing Macros

The simulation macro commands can be executed from a file, saving you time on manual entry ofevery command in the Console. Simulation macros not only can force input signals but they canalso execute other commands in the Active-HDL environment. This allows complete automationof the design verification process, particularly that it can be combined with other simulation entrymethods. For example, you can write a script to run a number of simulations using several TestBench files one after another. Macro scripts can execute external programs such as a synthesisprogram, batch files, etc. You can also invoke custom commands developed in Script Basic whichis included with Active-HDL for automation purposes.

Advantages of Macro commands:

· Fast stimulator entry, directly from keyboard.

· No need to use GUI windows.

· Familiar to Model Technology simulator users.

· Allows automation of the entire simulation process.

Disadvantages

· Proprietary format of the simulation commands.

· Requires knowledge of the macro language commands.

The Macro Command File


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VHDL testbench

The VHDL testbench is a VHDL program that describes simulation inputs in standard VHDLlanguage. There are a variety of VHDL specific functions and language constructs designed tocreate simulation inputs. You can read the simulation data from a text file, create separateprocesses driving input ports, and more. The typical way to create a Test Bench is to create anadditional VHDL file for the design that treats your actual VHDL design as a component (UnitUnder Test) and assigns specific values to this component input ports.

The Testbench Model

The VHDL Test Bench can provide simulation inputs and also test the design outputs. Forexample, you can create a VHDL program that writes design outputs to a text file and compares itagainst a reference file having the expected values. This methodology provides the most robustdesign verification with minimum user interaction.

Testbench Created with the Test Bench Wizard

Creating testbenches is a tedious process. The Test Bench Wizard automates this process byguiding you through the process. First, it asks you to select the top level design entity to betested. Next, you need to enter the name of the waveform file with the desired input and outputports. After answering a few additional questions, the Test Bench wizard gathers the necessaryinformation and creates a template for the test program. You can edit the wizard-generated file;adding your own test scenario and additional inputs, if required.

Test Bench Wizard

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Example:Begin— Unit Under Test port mapUUT : counter8port map( CLK => CLK,RESET => RESET,CE => CE,LOAD => LOAD,DIR => DIR,DIN => DIN,COUNT => COUNT );end TB_ARCHITECTURE;configuration TESTBENCH_FOR_counter8 of counter8_tb isfor TB_ARCHITECTUREfor UUT : counter8use entity work.counter8(COUNTER8_ARCH);end for;end for;end TESTBENCH_FOR_counter8;

VHDL Testbench in IEEE WAVES Format

The Test Bench Wizard allows you to create a template compliant with the IEEE WAVES 1029.1specification. WAVES is a specification for creating testbench files in the VHDL language. Itdescribes simulation inputs with a specific language implemented as a set of VHDL libraries. Itsupports verification and testing of hardware designs at any level of abstraction. You do not haveto be familiar with the WAVES specification to create these files. If you select this option the TestBench Wizard will automatically format your testbench program using the WAVES specification.The main benefits of using this format is the ability to format simulation input and output files sothat they can be used interchangeably between various simulators. The WAVES format alsocontains some very useful high level functions for comparing simulation outputs without writing alot of VHDL code. The standard testbench functions are provided in a compiled WAVES libraryand allow reading and writing of testbench files in the WAVES format.

The difference between the WAVES Test Bench and other testbench files are:

· It provides a standard file format for waveform data, including formula expressions andstimulator types

· It has some very useful high level functions for typical testbench operations

VHDL Testbench Created by the User

The VHDL testbench that you create will be treated as one of the VHDL files in the design. Youcan import existing testbench files and create the new ones from scratch. There are some VHDLpackages provided with Active-HDL which include testbench functions. The Language Assistantprovides some examples of using simulation specific VHDL constructs. For more informationabout writing your own simulation testbench please refer to the VHDL literature. Some of themore useful titles are listed at the end of this document.

Advantages of Test Benches:

· This advanced-code simulation input has powerful capabilities

· Its non proprietary format allows you to run the same simulation on any VHDL simulator.

· Test Bench can provide simulation inputs and check design outputs at all design stages.


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Disadvantages:

· Writing Test Benches is a time consuming process, particularly during the initial designverification.

· Writing a Test Bench requires good VHDL knowledge

Example:— Read cycle for rams with memfilesIF (MEMFILE)THEN FOR i IN 0 TO number_of_iterations LOOPa_bus <= conv_std_logic_vector(i, addr_width); wr_en_pin <= '0';clock_low(wr_clk_pin);spo_bus_exp := conv_std_logic_vector(conv_integer(a_bus)MOD(2**bus_width),bus_width);clock_high(wr_clk_pin);FOR k IN 0 TO bus_width-1 LOOPIF (spo_bus_exp(k) /= spo_bus_behv(k)) THENASSERT FALSEREPORT “ERROR: Wrong output while reading mem file.”SEVERITY ERROR;exit;END IF;END LOOP;END LOOP;END IF;

Conclusion

As demonstrated in this chapter, Active-HDL provides a variety of methodologies for stimulatingdesigns. For optimal results, use the most appropriate type for each design stage. In thebeginning of the design cycle you may want to use interactive stimulators to quickly createsimulation inputs and view the design responses instantly. As you develop a better plan fortesting your design, you may want to convert the stimulators to a VHDL testbench using the TestBench Wizard. You can add to it any additional VHDL test functions you may desire. At the endyou can add some simulation scripts to automate the verification process and invoke yourtestbench in the batch mode along with other design tasks such as synthesis, implementation,and comparison of results from different design stages. For more detailed information how tocreate simulation inputs, please refer to the on-line documentation in Active-HDL.

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Using Stimulators

Introduction

One of the main advantages of simulation over hardware breadbording is that you don’t have todo any logic analyzer setups. All data is automatically captured and analyzed by the simulator,however, you need to apply input signals to the tested model to verify it’s operation. Signals thatyou use for circuit simulation are key to effective testing. Some designers prefer to stimulate theirdesigns with signal waveforms, others prefer to use test vectors. For optimal design verificationyou will probably need both.

The Active-HDL tools are derived from more than a decade of comprehensive simulationproducts from Aldec. Because of this it offers a broad range of stimulator options that have beenfield tested and proved invaluable in device and system designs.

Available Stimulators

Stimulators are specialized signal waveform generators that can produce any desired legalvalue on the model inputs. Using stimulators you can easily and quickly define signal patternsthat are needed for thorough model verification. They allow you to interactively change any signalvalue to create the desired testing conditions for the Unit Under Test (UUT). These changes areinstant and can be performed during simulation. The simplest way to create simulation inputs isadding the desired ports or signal names to the Waveform Editor and then assigning stimulatorsto those signals, using the Stimulators option. There are several types of stimulators to choosefrom:

· Value

· Formula

· Hotkey

· Clock

· Counter

· Custom

· Predefined

Signal Drivers

Application Notes

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Each stimulator can be forced into being one of the three types:

· Override - the stimulator overrides the signal value permanently until the next FORCEcommand.

· Deposit - the stimulator sets the signal value which remains there until a subsequentdriver transaction (e.g. from process P1 or P2) and the associated FORCE command.

· Drive - attaches a virtual driver to the signal and this driver forces it with the value untilthe next FORCE command. This type of stimulator is used for resolved signal types onlysuch as std_logic.

Defined Forcing Types

Value

Value stimulators allow you to assign a permanent value to the selected signal, (e.g. ‘1’, ‘0’). Thevalues can be forced on any signals, buses (vectors) and any port type (in, out, inout, buffered),and can be applied at any time during the simulation. The simulator performs a signal type checkto verify that the specified value is allowed for the selected signal type. Values for signals of one-dimensional array types can be specified either as character literals or as a based numbers withradix of 2, 8, 10 or 16.

Examples:

1011 character literal sequence

2#1011 binary radix

10#11 decimal radix

16#F hexadecimal radix

The Stimulator field of the Waveform Editor window (in the figure at the end of this chapter)displays the appropriate signal assignments.

Value Stimulator

Formula

Formula stimulators define the signal waveform using formula expressions. Formulas candescribe asynchronous signals by specifying their transition times and values. Formulaexpressions use the following syntax:

value time [,value time] [-r period]

where the -r option allows you to automatically repeat the entered formula after the specifiedperiod of time. The default time unit is ps (picosecond). However, you may explicitly assign anyone of the following:

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· ps - picosecond

· ns - nanosecond

· us - microsecond

· ms - millisecond

Examples:

0 0, 1 10, 0 20 defines a logic "1" that starts at 10 (ps) and ends at 20 ps

1 0, 0 5 ns, -r 20 ns defines a pulse wave with period of 20 ns and 25% duty cycle

If the entered formula is correct it is assigned and the "formula" word is displayed in theStimulator field of the Waveform Editor window.

NOTE: The time unit must be separated from the time value by a space.

Formula Stimulator

Hotkey

Hotkey stimulators allow you to control signal values directly from the keyboard. A hotkeystimulator defines a key that will be used to toggle between values available for the given signal.For example, if you assign a hotkey ‘R’ to a “reset” signal, you can then toggle the value of thissignal during the simulation by pressing the R key on your keyboard.

Hotkey Stimulator

The values available for a given signal depend on its type. The default values are '0' and '1'. Youmay, however, add additional signal values in the Sequences field of the Simulators/Hotkeyswindow.

Application Notes

88

Values Available for Hotkeys

The Stimulator field displays the keyboard key name that has been assigned to the signal name,which in our example is the "R" keyboard key.

Clock

The Clock stimulators are provided for modeling of the clock waveforms. The graphical clockeditor allows you to specify clock frequency, duty cycle, initial value and delay. The word “Clock”is displayed in the Stimulator field, to the right of the clock signal name.

Clock Stimulator

Counter

Another powerful stimulator type is the counter stimulator that forces signal values after thespecified time periods. You can choose from the available counters modes:

· binary code

· Gray’s code

· Johnson’s code

· Circular one

· Circular zero

You need also to specify the counter direction, initial value, in some cases the step of increment,and time period after which the value will be changed. You can also modify the display of thecounter in the Waveform Editor window and also change the bits order.

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Counter Stimulator

Custom

The Custom stimulators allow assigning graphical waveforms displayed in the Waveform Editorwindow as the simulation inputs. The Custom waveform stimulators can be used only after youhave created some waveforms using either the waveform editor, formula or hotkey stimulators.Custom stimulators give you the ability to create very complex waveforms and reuse them asoften as required. They combine all the advantages of a Formula and Hotkeys stimulators. TheStimulator field indicates assignment of a custom stimulator with “CS” letters (CustomStimulator).

Custom Stimulator

Predefined

The Predefined stimulators are clocks with predefined frequency and duty cycle or formulascreated for frequent reuse.

Predefined Stimulator

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There are eight Predefined clocks which can be altered for the desired frequency and duty cycle.You also have the ability to create any number of your own formulas and assign them to anysignal name or port.

User Created Predefined Formula

Conclusion

One of the key issues in design analysis is the use of signal waveforms and test vectors. A signalwaveform gives you a better view of the selected signal behavior over time. The test vectors onthe other hand give you the exact relationship between signals at any selected time instance.Since Active-HDL allows testing designs both in the test vector and signal waveform domains,everyone will be able to effectively use Active-HDL.

It is important to underscore the benefits of using stimulators, they allow you to interactivelychange the signal values at any point during simulation. Once created, they may be reused asoften as desired, saving you time during repetitious verifications of the same design at differentdesign stages. There are such simple stimulators as Hotkeys which are great for simplestimulation, and as complex ones as Formula and Custom which allow you to describe complexand irregular signal patterns (pulse bursts, variable duty cycle clocks, etc.) ideal for verification ofcomplex designs (FPGAs, ASICs, etc). User defined clocks are not necessary in Active-HDL aspredefined clock formulas may be assigned to any signal.

Another benefit of using stimulators is the flexibility of combining different types of stimulators. Itis easier from time to time to create your signal patterns using graphical tools and save them asCustom designs for future simulation purposes. You can see below how different stimulator typeslook in a sample counter waveform window.

The Waveform Editor Window

91

VHDL Testbench

Introduction

The VHDL testbench is a VHDL program that describes simulation input using standard VHDLlanguage procedures. Simply speaking, the testbench is a top level hierarchical model whichinstantiates the Unit Under Test (UUT) and drives it with a set of test vectors and compares thegenerated results with expected responses. A typical VHDL testbench is composed of three mainelements:

· Stimulus Generator; driving the UUT with certain signal conditions (correct and incorrecttransactions, minimum and maximum delays, fault conditions, etc.)

· Unit Under Test (UUT); representing the model undergoing verification.

· Verifier; automatically checking and reporting any errors encountered during thesimulation run. It also compares model responses with the expected results.

The Test Bench Model.

To verify and report fault conditions in the most efficient way, Stimulus Generator and Verifieruses textual files which store test vectors and simulation results. With that basis, we candistinguish three testbench configurations.

Off-line Configuration

In this configuration the Stimulus Generator and Verifier take advantage of a file access, andread all needed information (test vectors, expected results) from the previously saved files. TheStimulus Generator reads all input signals from a file and provides clock processes. TheVerifier on the other hand compares the UUT responses with the expected results and reportsany faulty behavior. VHDL constructs allow logging all responses in a file for documentationpurposes and future verification. For example, you can use the same testbench (with the sametest vectors files) to verify any changes in a model at different stages of development (logical,pre-layout, P&R) by exchanging the instantiated component.

The Off-line Test Bench Structure.

On-line Configuration

Test Benches also allow you to interactively verify any model changes at different stages ofdesign development. The Stimulus Generator provides the same input signals to each testedmodel. Thus the response of all models are simultaneously generated and without any userinteraction such as exchanging the components. The Verifier operation is much simpler than in

Application Notes

92

the off-line configuration, because it only gathers the simulation results from each model andcompares them, detecting any differences and deciding whether to continue the simulation or not.

The On-line Test Bench Structure.

Adaptive Configuration

Unlike on-line and off-line configurations, the adaptive testbench configuration requires a goodknowledge of VHDL constructs and capabilities. Here, the stimulus generator uses high-levelabstraction techniques to adapt test vectors to the changing conditions and responses of a testedmodel. As a result test vectors are generated in response to feedback from the UUT and Verifier.For example: effective testing models containing such communication protocols as UART or PCIbus. For more information about writing your own simulation testbenches, please refer to theVHDL literature.

The Adaptive Test Bench Structure.

Example:architecture TESTBENCH_ARCH of testbench iscomponent GENERATOR isport ( A : in STD_LOGIC;B : in STD_LOGIC;CLOCK : in STD_LOGIC;RESET : in STD_LOGIC;S : in STD_LOGIC;Y : out STD_LOGIC);end component;shared variable end_sim : BOOLEAN := false;signal RESET,Y : STD_LOGIC;signal A,B,S,CLOCK : STD_LOGIC;begin UUT: GENERATORport map ( A => A,B => B,CLOCK => CLOCK,RESET => RESET,S => S,Y = >Y);CLK_IN: processbeginif end_sim = false then

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93

CLOCK <= '0';wait for 10 ns;CLOCK <=’1';wait for 10 ns;else wait;end if;end process;S_IN: processbeginif end_sim = false thenS <='0';wait for 250 ns;S <='1';wait for 250 ns;else wait;end if;end process;A_IN: processbeginif end_sim = false thenA<= '0';wait for 500 ns;A <='1';wait for 500 ns;else wait;end if;end process;B_IN: processvariable time0 : TIME := 0 us;beginwhile time0 <20 us looptime0 := time0 + 1000 ns;B <='0';wait for 1000 ns;B '1';wait for 1000 ns;end loop;end_sim := true;wait;end process;

end TESTBENCH_ARCH;

Excerpt from a Generator testbench file to be found in Active-HDL Projects directory.

VHDL Test Bench Wizard

Test Bench files created with the Test Bench Wizard are compliant with the standard VHDLlanguage. The wizard allows creation of a testbench from existing waveforms or creation of atemplate file where all signal inputs are inserted later.

It is sometimes easier to modify a waveform in a graphical editor than to formally describe anirregular pattern. For those who prefer formal methods of forcing signal inputs, the Test BenchWizard provides a fast and reliable template development environment where all componentshave been pre-instantiated, saving you time and effort.

Application Notes

94

You can invoke the Test Bench Wizard by choosing the Generate Test Bench option from theTools menu. In the Entity field, select the design for which you want to generate a testbench fileand click Next.

The Test Bench Wizard

Choose in the next window whether you want to generate a testbench from an existing waveformfile or just an empty testbench file for later modifications. In the latter case simply clear the Testvectors from file checkbox and click Next.

The Test Bench Wizard Step 2

The next window allows you to change the name of the testbench entity, architecture and atestbench file. You may also specify the folder where the generated files will be placed.

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95

The Test Bench Wizard Step 3

The last window displays the names of the files that will be generated. The first is a testbench filewith test vectors. Second is an optional file with timing configuration and the last one is asimulation macro file which automates the entire process of waveform generation, and executionof a testbench file. Click Finish to generate testbench files.

The Test Bench Wizard step 4

Depending on the selected options, the Test Bench Wizard will either create a testbench file withprocesses driving input signals converted from a waveform or a testbench template file, whichallows manual insertion of the desired input signal values.

Summary

The Test Bench wizard automates the tedious process of creating VHDL testbench files. It issometimes much easier to graphically create the desired waveforms and then reuse them withthe same model at different stages of development. Creating a testbench from waveforms is insome cases superior to formal description of irregular patterns, and its a great time saver.

Application Notes

96

VHDL Test Bench In IEEE WAVES format

The Test Bench Wizard allows you to create templates compliant with the IEEE WAVES 1029.1specification. WAVES is a specification for creating testbenches in the VHDL language. Itdescribes simulation input using specific language constructs implemented as a set of VHDLlibraries. It supports verification and testing of hardware designs at any level of abstraction.

The WAVES testbench file is a sequential program that when executed generates a waveform forall signals that are described in a testbench file. These waveforms define the sequence of events(timing, logic, value, and direction) for signals during a test. The WAVES testbench in context of aVHDL simulation is simply one or more concurrent process.

A WAVES testbench file is comprised of two or more WAVES files, optional external files and aheader file. The header file contains information about the testbench configuration andconstruction.

The WAVES testbench requires a number of information pieces to fully specify a testbench file.These include the names associated with each of the UUT pins, logic values and their timing. Youneed to make the following declarations:

· Logic value - defines all of the legal values that the signal of the waveform may exhibit.The sequence of signal logic values creates the waveform shape.

· Logic vector - is a composite type that gathers all of the signals of the generatedwaveform within one object.

· Pin codes - is a string constant that defines the legal characters that may appear in pincode strings that are applied to the signal waveforms. These characters may representone event or sequences of events on a signal.

· Maximum frame events - is a constant named max_frame_events that constrains datastructures in the WAVES standard package WAVES INTERFACE.

· Frames and frame sets - is a sequence of zero or more events and a direction specifier.These events are logic value-time pairs. Frames aggregate events into waveformsegments or shapes and define direction of the events within a frame. Similar framesmay be grouped together into frame sets. The number of elements in a frame set is givenby the number of characters in the pin code string declaration.

· Test pins - contain one enumeration value for each pin specified by the test set. Theidentifiers enumerated here represent names of the signals of the UUT. The order of thedeclaration defines the order of the waveform signals.

· Waveform generator procedure (WGP) - declares the interfaces between the WAVEStestbench and its environment. By using information defined in other declarations,standard packages, and optional external files, the WGP completely describes theconstruction of the waveform.

A WAVES testbench also provides interfaces which allow synchronization with events occurringin tested environment. There are two mechanisms called match and handshake. This is similar tothe adaptive configuration of a normal testbench file.

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97

Example:ARCHITECTURE counter_test OF test_bench IS-- CONFIGURATION SPECIFICATIONCOMPONENT counterPORT ( clk : IN std_ulogic;Data_out : OUT std_ulogic_vector( 0 to 3 ));END COMPONENT;FOR ALL:counterUSE ENTITY work.counter(behavioral);-- stimulus signals for the waveforms mapped into UUT -- INPUTSSIGNAL clock :std_ulogic := '1';—- Expected signals used in monitoring the UUT-- OUTPUTS SIGNALWAV_EXPECT_Data_out :std_ulogic_vector( 0 to 3 );-— UUT Output signals used In Monitoring ACTUAL-- ValuesSIGNAL ACTUAL_Data_out :std_ulogic_vector( 0 to 3 );-— WAVES signals OUTPUTing each slice of the waves -- port listSIGNAL wpl : WAVES_port_list; SIGNAL wmr : WAVES_match_request;SIGNAL MATCH_ACK : WAVES_MATCH_ACK;SIGNAL WHR : WAVES_HANDSHAKE_REQUEST;SIGNAL HNDSHK_ACK : WAVES_HANDSHAKE_ACK;BEGIN-— process that generates the WAVES waveform WAVES: waveform(wpl,wmr, match_ack, whr, hndshk_ack);-— processes that convert the WPL values to 1164-- Logic Valuesclock <= not clock after 10 ns when NOW=1us else '0';WAV_EXPECT_Data_out wpl.signals( 2 to 5 );-— UUT Port Map - Name Semantics Denote Usageul:counterPORT MAP( Clk = clock,Data_out = ACTUAL_Data_out);-— Monitor Processes To Verify The UUT Operational-- Response Monitor_Data_out :PROCESS(ACTUAL_Data_out, WAV_expect_Data_out)BEGINif MATCH_ACK = TRUE thenassert Compatible(actual =ACTUAL_Data_out,expected = WAV_expect_Data_out )report “Error on Data_out output”severity WARNING;end if;END PROCESS;Handshake : Processbeginwait until WHR.REQUEST'transaction'event;if WHR.REQUEST = TRUE thenHNDSHK_ACK TRUE;wait until clock'event and clock = WHR.VALUE;HNDSHK_ACK FALSE;end if;end process;Match_Data_out : processvariable RESULT : Boolean;begin

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wait until WMR.REQUEST'eventand WMR.REQUEST = TRUE;MATCH_ACK FALSE;RESULT := TRUE;wait for WMR.SAMPLE;for I in WAV_EXPECT_Data_out'range loopRESULT := RESULT andACTUAL_Data_out(I) = WAV_EXPECT_Data_out(I);end loop;MATCH_ACK<= RESULT;end process;END counter_test;

Summary

You do not have to be familiar with the WAVES specification, to create these files. The TestBench Wizard automatically formats your testbench program using the WAVES specification ifyou select this option. The main benefits of using this format is the ability to format simulationinput and output files so that they can be interchanged between different simulators. The WAVESformat also contains some very useful high level functions to compare simulation outputs withoutwriting extensive code in VHDL. The standard testbench functions are provided in a compiledWAVES library and allow reading and writing of testbench files in the WAVES format. Ascompared to other testbench files, the WAVES testbench provides:

· Standard file format for waveform data including formula expressions plus stimulatortypes.

· Higher level functions for typical testbench operations.

Conclusion

The Main advantage of testbench files is that they automate design verification. They allow fastand accurate verification that the UUT responses are as expected and the UUT interfaceprotocols meet their specifications. Manual verification through visual inspection of waveforms isinefficient and prone to errors. Because of the VHDL language capabilities, testbench files arepowerful tools for interacting with tested models where stimulators are not efficient enough tokeep up with changing conditions.

Another advantage of using testbench files instead of test vectors is portability between differentsimulation tools. A file written in a VHDL language is compatible with any VHDL compliantsimulator. Thus the same testbench architecture can be reused and shared on many vendor-independent platforms.

However, a thorough knowledge of VHDL language is required to get the best results. It may besometimes easier to use simple stimulators or test vectors, as the design size may notnecessitate complex testbench files. Furthermore, writing a testbench file is a time consumingprocess and is not recommended for situations where only initial verification is needed. In thatcase simple test vectors may be sufficient.

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Glitches and Delta Cycle Handling

Introduction

This chapter describes how Active-HDL handles glitches and delta cycles. The purpose of thisdocument is to familiarize you with the terminology, basic simulation procedure and means forfinding causes of glitches. Active-HDL provides you with handy graphical tools that simplify thedesign verification process. The Design Browser windows allows quick design review andsimplifies locating instances that cause the design misbehavior.

Delta Time

One of the requirements of simulation is execution order independence for each of the concurrentstatements. Thus if a signal X is inverted by process "A" from '0' to '1' and the signal X value isread by the process "B" at the same time, it is important that process "B" reads the old and notthe inverted value of '0', regardless of the process execution order. See the VHDL code below. Toachieve this goal, the simulator tags each signal for an update when all current processes havebeen completed for the current time period. This time is called Delta Time.

A delta time is an infinitesimally small amount of time that represents a time greater then zero,but it is zero when added to a discrete amount of time. Thus if a signal assignment is made attime "100ns + 1 delta time" and the model discrete delay is 10ns, the new signal value isassigned at 100ns + 10ns + 0 delta time = 110ns.This is because the 1 delta time * 1 = 0ns.

The VHDL code for our example:

signal X : std_logic := '0';signal Y : std_logic;

A: processbegin

wait for 100 ns;X <= not X;

end process;B: process (X)begin

Y <= X after 10 ns;end process;

The Simulation Results.

Active-HDL has a List window that allows displaying signal values with the corresponding timeevents. The List window has two default columns:

· Time - displaying signal event time

· Delta - displaying the number of delta times for current delta cycle

All signal values are presented in text format and each signal has its own column. You can addsignals to the List window by dragging them from the Design Browser window or clicking theAdd signals icon on the toolbar. Any signal changes during the simulation run are automatically

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100

updated in the List window. You can add or remove signals from the List window while thesimulation is in progress. By clicking the Collapse delta icon you can toggle delta cycles displayfor the current time.

The List Window

Glitches

Since propagation of electrical signals through actual device takes some time, the actual deviceand circuit behavior may be quite different from the one expected, based on the functionalsimulation. Actual devices have a number of restrictions on their input signals. For example, if theinput signals change much faster than the device can respond, the responses may not be asexpected. Glitch is a short pulse on the signal waveform, that is usually undesired and maycause an unexpected design behavior.

When a simulator produces output signal waveforms for no reason, you may enable the display ofglitch warnings in the Design/Settings window. To see the glitches on the display, your designproject library must contain design units with described unit delays or the project should include afile with timing descriptions for devices used in the design. A file is created after the placementand routing process. This file contains a netlist of the design after the netlist file is fitted into thevendor-specific part. It is usually written in the Standard Delay Format and has the SDFextension. To better understand glitches and their influence on the design behavior we will nowreview an example from the Active-HDL Projects directory. For this purpose we will use theXilinx_Counter project.

Entering the Xilinx_Counter design you will create a simple 4-bits synchronous counter withasynchronous reset. The target device for the design will be 4003EPC84-4. First, you have toopen the project using the Project Explorer invoked from the File menu. If you are not familiarwith the design management please see the Design Management Features in Active-HDLchapter. In the Design Browser window navigate to the Implement folder and execute theImplement.Do macro file. This will invoke the Active-Synthesis software that creates the netlist filefor the Xilinx_Counter design. Next, the same macro file will automatically launch the Xilinx placeand route tools that will map and fit your netlist files into the desired Xilinx part. For those userswho do not have the Xilinx software, all necessary timing specification files are included in theTiming subdirectory. These files have been generated by the Xilinx place and route tools andhave been provided here for your convenience.

To run the timing simulation you need to execute the run_timing.do macro file that creates thenew Waveform Viewer window and performs the simulation process. Below you will find thecontents of the run_timing.do macro file:


101

Savealltabsquiet onvcom counter_tim.vhdvcom counter_TB.vhdvcom timing_cfg.vhdvsim -sdfmin \UUT=$DSN\src\timing\counter_tim.sdf TIMING_FOR_counterwave CLKwave RESETwave Qrun -allendsimquiet off

During the simulation you should observe the warning messages displayed in the Consolewindow. An example of a warning is presented next:

WARNING: VitalGlitch: GLITCH Detected on port O ;

Preempted Future Value := 0 @ 261.714 ns;

Newly Scheduled Value := 1 @ 261.749 ns;

Time: 259049 ps, Iteration: 2,

Instance: \UUT\Q_2_INT_FGBLOCK_LUTRAM_GLUT_OR2.

Active-HDL allows you to disable glitch detection by checking the Ignore VITAL glitches option inthe Simulation tab of the Design Settings window.

The Design Settings Window

The VITAL glitch detection mechanism displays glitch warnings. According to the VITALspecification a glitch occurs when a new transaction is scheduled to occur at an absolute timethat is grater than the absolute time of a previously scheduled pending event. Glitch handling in aVITAL model is incorporated into the signal scheduling mechanism. In the Xilinx_Counterexample the Waveform Viewer does not display glitches, because of the VitalInertial transportdelay mode. To better understand the transport modes and the simulation behavior that theycause we should consider the figure below, that displays the buffer behavior.

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102

Transport Delay Types

The first two transport delays VitalInertial and VitalTransport are identical to inertial andtransport VHDL modes. The OnEvent and OnDetect modes are especially useful for glitchhandling. In the OnEvent mode the glitch causes an 'X' value to be scheduled on the output at thetime when the event was to occur. As you can see in the figure above the glitch is displayed afterthe Delay time from the moment the glitch started. In the OnDetect mode, a glitch causes the 'X'value to be scheduled on the output at the time of glitch detection. As seen in the figure above the'X' value is forced on the output for the Delay time from the moment that glitch detectionmechanism detected the signal glitch.

In our example the glitch has been detected on the output O port of the\UUT\Q_0_INT_FGBLOCK_LUTRAM_GLUT_OR2 instance. To find out why it is not displayed inthe Waveform Viewer window, check if it is not caused by the unit transport delays.

To quickly locate the listed instance, use the Design Browser window. Select the Structure taband expand the hierarchy structure. At first you will only see the top level hierarchy of yourdesign. Active-HDL displays two kinds of icons within the design structure. The rectangular iconsrepresent blocks resulting from the design elaboration and the circular ones represent concurrentprocesses. As you can see from the figure below, the top-level hierarchy is timing configurationfor the counter. In the hierarchy tree there are two branches:

· UUT:counter - the unit under test containing all design components

· Stimulus - the active stimulus process

The Design Structure

Next, you should expand the block named UUT (Unit Under Test) : Counter to see the designcomponents. You need to locate the Q_0_INT_FGBLOCK_LUTRAM_GLUT_OR2 gate. Byclicking on it, the Design Browser displays additional information in the lower part of the window.


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Timing Specifications in the Design Browser Window

What interests us the most is the lower part of the Design Browser window. As you can seeabove, there are four time structures of the VitalDelayType01 type. Each of these structurescontains two time values:

· first, containing the time for signal transition from 0 to 1

· second, containing the time for signal transition from 1 to 0

The tipd_I1_O and tipd_I0_O structures hold time values for the input delays. This is the timeafter which a signal change is propagated from the input to the circuit.

The tpd_I1_O and tpd_I0_O structures hold time values for the output delays. This is the timeafter which signal change is propagated through the circuit to the output.

The Input and Output Delays of the OR Gate

The tpd time values for the Q_0_INT_FGBLOCK_LUTRAM_GLUT_OR2 gate (figure above) are2700ps and the tipd values are 0ps. Therefore there is no input delay, which means that signalchanges are instantly propagated to the circuit. A default time unit for each component is insertedinto the SDF file and in this example it is picosecond - ps.

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104

Keeping in mind all the above information, we can now explain what causes the glitch. In thewarning displayed in the Console window the time of the glitch detection is 259049 ps (259.049ns). This is specified in the line beginning with the Time: clause:

WARNING: VitalGlitch: GLITCH Detected on port O ;

Preempted Future Value := 0 @ 261.714 ns;

Newly Scheduled Value := 1 @ 261.749 ns;

Time: 259049 ps, Iteration: 2, Instance:\UUT\Q_2_INT_FGBLOCK_LUTRAM_GLUT_OR2.

The next preempted value for the output O port is '0' at 261.714 ns. However, the newlyscheduled value for the output O port is '1' at 261.749 ns. We should keep in mind that thecurrent output value for the O port is '1'. The absolute time period between those two transactionsequals 35ps and we know that the output delay for this particular gate is 2700ps. If we add thepresent time value of 259049ps and the output delay of 2700ps then we will have the result of261749ps. This is the time of newly scheduled value for the output O port.

Output Signal with Glitch

The value of this port will not change on the display because of the inertial delay type specifiedfor our design, which does not transport any signal changes having time duration smaller then theoutput delay tpd. However, because the project is compliant with the VITAL standard, the glitchdetection mechanism will generate the glitch warning. This is due to the short spike on the outputsignal for the port O with time duration of 35ps. The cause of the glitch can be easily explained.As you can see in the above figure, the I1 signal changes from '1' to '0' at the 259.014ns and theI0 signal changes from '0' to '1' at the 259.049ns. The time period between those two events isexactly 35ps. Those transitions on the inputs of the OR gate should cause at first a short changeon the output from '1' to '0', and after 35ps from '0' to '1'. However, the design operates in theVitalInertial transport mode where all input changes that have duration time shorter than theoutput delay tpd are not propagated to the output and no glitch will appear at the output. Thesimulator therefore does not display the glitch on the waveform, however, generates the warningthat the glitch has been detected. Consequently all glitch warnings can be explained this way.

Conclusion

The timing simulation is used to verify that a circuit will operate properly under the worst-case ofpropagation delays and input signal conditions. Since the actual propagation delays are knownafter the device have been laid out, the Active-HDL simulator allows to include the timingspecifications, contained in the SDF file, for accurate verification of the design. Functional


105

simulation allows you to verify functional behavior of the tested model. However, it is the timingsimulation that verifies proper design operation under any timing conditions.

Active-HDL takes advantages of the VITAL specifications and mechanisms for glitch detectionand allows you to verify the design operation under the worst-case propagation conditions. Inmost cases the glitch is caused by input signal transitions with too short time duration. As shownin this chapter, Active-HDL allows you to quickly locate and verify the timing specifications for anyinstance by clicking on their corresponding icons in the Design Browser window. At first, theglitch information may seem incomprehensible but with a little experience it is easy to read andunderstand. Active-HDL allows testing designs step-by-step. You may even follow the simulationchanges with the delta precision. By switching to the List window and enabling the Delta timemode, you can view signal changes for each simulation cycle.

107

VHDL Debugging

Introduction

The design verification process typically involves a lot of tedious work as well as a goodunderstanding of the models behavior. However, since the VHDL language guarantees that anymodel description is vendor-independent and exchangeable, the design verification efforts canhave long lasting results. Because it is human nature to make an occasional mistake, you need tocheck the design for errors. Active-HDL provides several mechanisms for debugging VHDL code:

· Syntax Checking - performed with the every Compile command.

· Code tracing - VHDL code is executed either statement-by-statement or traced byprocesses, subprograms and procedures.

· Value verification - variable values are displayed in additional Watch and List windows.

Syntax Checking

Active-HDL provides you with an interactive VHDL code debugger. After each execution of theCompile command an error list is displayed in the Console window. Each error is displayed withadditional information:

· name of the source file

· internal error number

· line and column number location of the error in the code

· a short description of the error

Double clicking on any of these errors takes you directly to the line of VHDL code where the errorhas occurred. Furthermore, the line is underscored with red zigzag line and a red marker isplaced to the left of the line. Pointing on a line with the cursor for a second, invokes the sameshort error description as reported in the Console window.

Interactive Debugging

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The Compile command automatically checks the VHDL source code for compliance with VHDL‘93 LRM. There is, however, an option for checking compliance with the VHDL ‘87 LRM codesyntax.

By default, the compiler stops syntax checking after the 100th error, however, you can changethat value in the Compiler tab of the Preferences window.

The Preferences window allows customization of the debugging options as well. In the Debugtab window you can specify your preferences for code tracing. Document Type allows you toselect the source document from VHDL code or State machine. Bring active source windowto top invokes the source code window currently being debugged. Show component instances inspecifies the way each component is viewed. They allow you to display a Separate view for eachcomponent or a Single view for all components.

The Preferences Window

Active-HDL allows checking the State Machine generated VHDL code for errors. In the samewindow you can select one of the two options:

· trace the original state machine

· trace VHDL code generated from a state machine

Code Tracing

When the code syntax is error-free you can start verifying the models behavior. Active-HDLprovides you with Waveform Editor, where all results are presented in the form of waveforms.You can quickly find any faulty and undesired design responses.

To get more specific information on the Waveform Editor please refer to the chapter: WaveformEditor Features.

Active-HDL provides an interactive graphical environment for design development andverification. When necessary, you can trace the VHDL source code statement-by-statement.There are four functions that allow you to trace the code:

· Trace into - executes a single VHDL statement. If a subprogram call is encountered,the execution descends into the subprogram body.

· Trace over - executes a single VHDL command. If a subprogram call isencountered, the statements contained within the subprogram body are executed in asingle step.

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· Trace out - executes as many VHDL statements as are required to complete theexecution of a subprogram. If subprograms are nested, the command completes theexecution of the innermost subprogram only.

· Trace over transition - executes as many VHDL statements as are required toperform a transition between states.

To perform any of these commands, choose the appropriate options from the Simulation menuor click the Trace icons. The last transition option is available only while verifying state machines.

State Machine Code Debugging

The Trace over Transition option from the Simulation menu handles the State Machines.Active-HDL offers you a graphical editor for entering and editing of State Machines. Furthermore,the real-time State Machine editor allows you to interactively trace the behavior of the statemachine, highlighting in yellow the currently active state. All Trace commands are active duringthe design debugging and so are the other tools described in this chapter. Therefore, you maytrace any single statement in the VHDL code and observe its influence on the model’s behavior.

The State Machine Editor

Breakpoints

Another useful feature of Active-HDL is its ability to insert breakpoints into VHDL code.Breakpoints allow you to stop the verification process when some desired condition(s) occurred.All processes are suspended and signal values are displayed in the Watch window. The VHDLEditor allows inserting breakpoints only in the lines where appropriate, for example: statementscontaining assignment expressions, etc.

Simulation Breakpoint

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The Breakpoint Editor has three columns for Code breakpoints. The first column has acheckbox for enabling the breakpoint, the second has a path to the source file where thebreakpoint is inserted and the third has a line number in the breakpoint’s source file. TheBreakpoint Editor allows manual toggling of the breakpoints.

Moreover, there is also a dialog window where you can add signals that you want to trace. Thereare three columns displaying the Name of the signal, the Condition at which the simulationshould stop, and the Value of the signal. In the Condition tab there are three options:

· Event - the simulation stops when the signal event occurs

· Value - the simulation stops when the specified value is generated for the signal or it isforced by the simulator

· Transaction - the simulation stops when the signal transaction occurs

You may quickly jump to the location of the breakpoint by clicking the Show code button in theSignal and Code breakpoint tabs. This is a very convenient method of locating breakpoints insituations where multi-file projects are verified.

The Code Breakpoints

Results Verification

You can use additional tools during tracing the VHDL model’s code that will help you to verify thedesigns overall responses. In addition, there may be some specific conditions that the modelshould be tested for, these could cause certain behavior of the model. Sometimes it is best tolook for the specific signal values which can be displayed not only in the Waveform Editor but inadditional windows as well.

List Window

The List window displays all results in a tabulated form. The window is used only as a viewer forsimulation results. Because of that you cannot define stimulators here. The contents of thewindow can be saved to a text file. Each signal is represented by a column with correspondingevent times. The window can display signal values in two ways:

· For all simulation cycles executed for the specified time step.

· Only for the last simulation cycle within the specified time step.


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The List Window.

Watch Window

To find the last value or current signal’s value, you may use the Watch window. The Watchwindow displays values of selected signals (including ports) and variables.

The Watch Window

The window is divided into four columns that show:

· names

· types of the selected objects

· current value

· last value

All signals viewed in this window can be dragged and dropped here, from the Design Browserwindow. You can also drag a signal name from the VHDL source code itself.

Processes Window

The Processes window displays a list of processes in the elaborated model along with theircurrent status. This window is available only while the simulator is running.

The Process Window

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The processes are displayed in three columns that show the process label, hierarchical path andstatus of each process. Each concurrent statement modeling a sequential process is representedin the window. There are:

· process statements

· concurrent signals assignment statements

· concurrent assertion statements

· concurrent procedure call statements

For processes without explicit labels, the compiler generates default labels that show the linenumber of the source file in which a process is located (e.g., line__25). In case of processesdeclared within generate statements, their labels are modified by a suffix showing the instancenumber.

A process listed in the Process window can have one of the following status:

· Ready; indicates that the process is scheduled to be executed within the currentsimulation cycle.

· Wait; indicates that the process is suspended and waiting to resume.

The Processes window can show either:

· All processes in the selected region of the elaborated design irrespective of their status inthe current simulation cycle.

· Only active processes in the selected region of the elaborated design, that is thosescheduled to be executed within the current simulation cycle.

In addition, you can choose a region of the design whose processes you want to trace.

Call Stack Window

The Call Stack window is a debugging tool that displays a list of subprograms (procedures andfunctions) and variables being currently executed. The term process is used here to mean anyconcurrent statement modeling a sequential process in the elaborated model. Such statementsare process statements, concurrent signals assignment statements, concurrent assertionstatements, and concurrent procedure call statements (exactly the same as for the Processeswindow). For each subprogram the window displays the following information:

· Formal parameters along with their actual values.

· Variables, constants and files declared locally in subprogram bodies along with theircurrent values.

If there is more than one process in the simulated design, you can use the Processes window toselect the process whose subprograms you want to watch. The Call Stack window is availableonly while the simulator is running.

The Call Stack Window

Data Flow Window

The Data Flow window is a tool providing a graphical view of signals flowing in and out ofprocesses during simulation. The term process is used here to mean any concurrent statement


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modeling a sequential process in the elaborated model. Such statements are process statements,concurrent signals assignment statements, concurrent assertion statements, and concurrentprocedure call statements (exactly the same as for the Processes window). The window providestwo different views:

· with a process in the center of the window,

· with a signal in the center of the window.

When a process is displayed in the center, it is represented as a rectangular box with inputsignals on the left side and output signals on the right. Input signals are those read by theprocess and output signals are those updated by the process.

Data Flow Window - 1

When a signal is displayed in the center, it is represented as a vertical thick line with processesconnected to it on both sides. Processes on the left side update the signal. Processes on the rightside read the signal. You can switch between these two views by clicking items in the Dataflowwindow.

Data Flow Window - 2

In both views, signals are displayed with their names and processes are displayed with theirlabels (either assigned explicitly by the user or generated automatically by the simulator). Forsignals, the Dataflow window also displays their current values.

Conclusion

Active-HDL has much to offer for both beginners and more advanced users. Some developersprefer to use commands invoked from menus and some find it easier to use shortcut keys. At thebeginning you will probably use the menus. As you familiarize yourself with the program, you willprobably use the shortcut keys, which is usually the fastest method to get the job done.

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As stated in this chapter, Active-HDL offers a number of options that will help you to effectivelydebug any errors in your design. Those tools are not limited to checking of the VHDL code butthey let you efficiently verify the behavior of your design as well. Active-HDL has a number ofoptions that let you quickly trace the desired statements in VHDL code, processes andprocedures. There are also options for tracing signal behavior and for checking and savingsimulation results in files. Moreover, Active-HDL allows you to stop simulation at any time whenuser defined conditions are met. You can insert the breakpoints in the VHDL code to stop thesimulation when the specified code line is entered. Finally since the Active-HDL environment isinteractive, you can execute the debug functions while the simulation is in progress.

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Building and Debugging Handel-C Projects

Introduction

Active-HDL, except features dedicated to verification of HDL designs, also provides an advancedbuilt-in debugging tool that allows you to debug simulation models based-on the Handel-Clanguage. The option is a feature that allows you to debug in the Active-HDL environment. TheHandel-C Code Debug option provides extended verification capabilities for debugging Handel-Csource code and DLL libraries built in the Celoxica DK Design Suite environment.

NOTES:1. In order to use the Handel-C Code Debug option, this feature must be enabled in your license.2. This feature is not included in the vendor-specific editions of Active-HDL.

The Handel-C Code Debug option requires:

· Active-HDL 6.1 SP2 or higher

· Library containing a source code to debug must be built by using Celoxica DK DesignSuite 2.0 SP2 or higher. The compiler must build a library with debug informationenabled. See the Compiler tab of the Project Settings dialog box in the on-linedocumentation for additional information (Active-HDL Help | Dialog Box Reference).

This application note will help you get familiar with creating and importing Handel-C projects andshow you how to debug them in Active-HDL. In this application note, we will import the Celoxica'ssample project Example1. The sample describes an accumulator that reads data and writesresults to a file. It is stored in the <DK_directory>\Examples\Handel-C\Example1\ subdirectory.

Creating new design

1. Start Active-HDL by opening the Start | Programs group and clicking the Active-HDL icon. TheActive-HDL Welcome screen appears and then the Getting Started dialog opens.

2. Select the Create new workspace option and click the OK button. You can alternatively usethe File | New | Workspace option to open the New Workspace window.

3. The New Workspace Wizard appears. In the wizard's dialog, you can enter the name andlocation of the workspace. Enter acc in the Type the workspace name field. Make sure that theAdd New Design to Workspace checkbox is selected.

4. Click the OK button. After the New Workspace Wizard window has closed, the New DesignWizard dialog box appears.

5. Select Create an empty design in the New Design Wizard window and press Next. In thedialog box where synthesis and implementation tools are set, click Next.

6. Enter a new design name acc in the Type the design name filed.

7. Finish creating the empty design by clicking Next and then the Finish button. The new accworkspace/design is created in the C:\My_Designs\ directory and displayed in the DesignBrowser window as it is shown in the figure below.

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Importing Handel-C Project

8. Open the File | Import menu and choose the Celoxica DK Project option. The SelectCeloxica DK Project window opens. Go to the \Examples\Handel-C\Example1\ subdirectory ofthe DK installation directory and choose the Example1.hp Handel-C project file.

9. Click Open, which imports the entire Handel-C project into the Celoxica subfolder. After theHandel-C project has been attached, the new project folder (the name of the subfolder is inheritedfrom the name of the *.hp file) is created and it contains links to the original Handel-C source filesof the imported project. The imported project is presented in the figure below.


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NOTE: If required, you can create a new Handel-C project from scratch. To do so, open the File |New menu and choose the Handel-C Project option that runs the New Handel-C Project Wizard.After the project file (*.hp) is attached to the design, you can add new source files and modifyappropriate settings in the Project Settings dialog box. See item #10 below or the on-linedocumentation for more information on changing project settings.

Specifying Project Settings

10. After the project has been imported, you can specify settings for the compiler, linker,debugger, paths to additional objects or libraries, etc. This can be done by using the ProjectSettings option. To open the Project Settings dialog box, right-click the Example1.hp file andchoose the Handel-C Project Settings option from the pop-up menu.

As it was mentioned above, sum.hcc describes the Handel-C model that reads data from a textfile. The sum_in.dat file is stored in the <DK_directory>\Examples\Handel-C\Example1\subdirectory. The file and information on its location is used while building the Handel-C projectand initializing the debugging session. The newly created acc sample design is stored in theC:\My_Designs\acc subdirectory. Thus, to avoid errors, you should specify the path to thesum_in.dat file before you compile the project. Otherwise, you may encounter the read outproblem and you will see the following message in the Console window:

# Handel-C Code Debug: Could not open input file 'sum_in.dat'

In this example you can solve this issue by modifying the source code or specifying a workingfolder for the debugger.

11. To specify the settings for the debugger, click the Debugger tab and enter the path tosubfolder where the sum_in.dat file is stored.

Setting the path to the working folder of the debugger is equivalent to the specification of theabsolute path to the sum_in.dat file in the Handel-C source code.

12. If you want to modify it, double-click the sum.hcc source file, which opens the HDL Editorwindow. Then, find and replace the following lines of the code:

chanin input with { infile = "sum_in.dat" };

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chanout output with { outfile = "sum_out.dat" };

with (provided that the DK software was installed with the default installation path and the accdesign was created in the above specified directory):

chanin input with { infile = "C:/ProgramFiles/Celoxica/DK/Examples/Handel-C/Example1/sum_in.dat" };chanout output with { outfile = "C:/ProgramFiles/Celoxica/DK/Examples/Handel-C/Example1/sum_out.dat" };

This change allows your imported Handel-C model to read data from and save them to thespecified location without the necessity to copy the sum_in.dat file after importing the project intoActive-HDL. Otherwise

13. Save the changes and compile the source code. To build the Handel-C project, right-click theExample1.hp Handel-C project file and choose the Build Handel-C Project option or type in thefollowing command to the Console window:

buildc example1.hp

The compilation results are displayed in the Console window.

After the compilation, you should specify the Handel-C library to be debugged (this library is alsoused while co-simulating HDL units and Handel-C models). This information can be enteredeither in GUI or by using an environment variable.

14. If you want to set it by using GUI, open the Design menu and choose the C/Handel-C CodeDebug Settings option. It opens the dialog box that allows you to specify debugging settings foreither C/C++ or Handel-C applications.

15. Open the Handel-C Code Debug and Co-simulation Settings tab.

16. Enter manually the path to the Example1.dll library in the Select Handel-C Library forDebugging and Co-simulation field or use the Browse button to find the library.

17. Click OK to close the dialog box.

By default, after you have successfully compiled the Handel-C project, the path to the library isset automatically. If the path is not set or you change it, pressing OK or Apply will save thechange and the Console window will display the current location of the library:

# set HANDELC_SIMULATOR C:\Program Files\Celoxica\DK\Examples\Handel-C\Example1\Debug\Example1.dll


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18. If you want to use the environment variable, you need to specify the value of theHANDELC_SIMULATOR variable. To do so, issue the following command in the Console window:

set HANDELC_SIMULATOR "C:\Program Files\Celoxica\DK\Examples\Handel-C\Example1\Debug\Example1.dll"

Issuing the command sets the path in the Select Handel-C Library for Debugging and Co-simulation field too.

Now, the Handel-C project is ready to debug and you can initialize the debugging session.

Debugging Handel-C Project

19. Open the Simulation menu and choose the Initialize Handel-C Code or type the followingcommand in the Console window:

hcdebug $HANDELC_SIMULATOR

The Console window reports the status of the Handel-C debugger displaying the followingmessage:

# Handel-C Code Debug: Initialized

and the sum.hcc file is loaded to the HDL Editor window. The yellow debug line is visible in thewindow, which means that you proceed to debug the Handel-C source code.

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Before you start tracing the code, you need to add variables to watch and, if you want to save theresults to a waveform file, select objects to be traced. The built-in debugger provides the Handel-C Code Debug window that allows you observe objects of the debugged model. To open thiswindow, choose Handel-C Code Debug from the View menu or press Alt+F9.

The Source tab displays all (re)sources files compiled into the library

The Clock/Thread tab displays information on the clocks declared in the project, threads inoperation during debug, the current number of clock cycles, and the current location of the debugline in the source code.

The Call Stack tab lists the functions and macro procedures called on the way to the currentfunction. The current function or macro procedure appears at the top of the list, followed by thosethat have not yet completed.

The Watch tab shows program's variables.

20. To add a variable, click the Watch tab.

21. Double-click an empty row in the Expression column (or select it and press F2). This turnsthe editing mode on and you can enter the name of the item you want to observe e.g. sum.

22. Press Enter to complete.

You can also add variables directly from the source code displayed in the HDL Editor window.


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23. Select the name of the variable and right-click the selection.

24. Choose the Add to Handel-C Code Debug Watch option from the pop-up menu. Thisoperation is reported to the Console window:

# Handel-C Code Debug: Variable added to watch - "data"

Depending on the visibility scope i.e. the function being currently debugged, you may see<Unavailable> displayed in the Value column. Additionally, while entering the name manually,pay attention to the proper use of the character case since identifier names are case sensitive.Now, you should see two variable added to the Watch tab as it is shown in the figure below.

The next step is to select objects to be traced during debug and saved to the waveform file.

25. Click the Variables tab.

26. Check the variables you want to trace and save to the waveform file.

27. In the Step time field, enter 100ns. The value specified in this field is the time of theexecution of subsequent lines of the source code during debug. This parameter is equivalent tothe time step required to execute one line of the source code, which also allows a graphicalrepresentation of debugging results on the waveform. The name of the wavefom file is displayedin the Waveform path field and can be changed (manually or by using the Browse button) onlybefore the initialization of the debugger. After the initialization, both fields are unavailable.

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Now, you can start debugging the source code. The integrated Handel-C debugger allows using

the Active-HDL Trace In , Trace Over , or Trace Out options from the main toolbar.Each step of the debugger is reported to the Console window.

You can also set breakpoints while debugging the Handel-C code.

28. To do so, press F9 or choose Toggle Breakpoint from the Simulation menu. Settingbreakpoint will be reported in the Console window. The list of breakpoints that have been set isavailable in the Edit Breakpoints window (Simulation | Edit Breakpoints).

After several steps, you can see the new values of the variables on the Watch tab.

The sum_in.dat file stores data read during debug. When the debugger reads data=0 then itexecutes the last line of the code and the debugging session is closed. Obviously after you havereached the end of the debugging process, you may finish the session at any time.

29. To close the debugging session, choose End Simulation from the Simulation menu or typein the endsim command in the Console window. When the session is closed, you can open thewaveform file and verify the results. The waveform window is presented in the figure below.


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The debug session ends at 11th cycle. As it was mentioned above, each change occurs after100ns, which is equivalent to the execution of one line of the source code. On the waveformpresented above, you can see that the first read out of data is at 100ns, then the value isprocessed by the accumulator and written to the output at 200ns. At 300ns the read out cyclestats again but the new value is added to 1 (stored in the accumulator) and at 400ns written tooutput. These operations are repeated until 0 is encountered in the sum_in.dat file. The valuestored in the accumulator in the last cycle of debug is written to the sum_out.dat file after thesession is finished.

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Co-simulation of Handel-C Projects in Active-HDL

Introduction

Handel-C projects that have been attached to Active-HDL can be verified by using its nativesimulation environment and built-in debugging tools. You can not only build and debug a Handel-C source code, but also instantiate a Handel-C-based model within an HDL design and co-simulate such a mixed-language project.

Active-HDL provides a built-in co-simulation interface that allows you to co-simulate Handel-Cmodels with both VHDL and Verilog units. The built-in interface allows you to:

· Use Active-HDL to initialize the co-simulation process if the HDL unit is top-levelinstantiating a Handel-C block. If the HDL block is instantiated in Handel-C then Active-HDL plays the role of the co-simulator.

· Observe co-simulation results in the Active-HDL Waveform Viewer

· Debug Handel-C code in the Active-HDL HDL Editor

· Watch Handel-C variables in the Handel-C Code Debug window

NOTES:1. In order to run co-simulation in Active-HDL, it must be enabled in the license file.2. This feature is not included in the vendor-specific editions of Active-HDL. See the on-linedocumentation for details.

This application note will present how to prepare and co-simulate both models (HDL and Handel-C) and carry out the co-simulation process in Active-HDL. As an example, we will use the accsample design that is described in details in the Building and Debugging Handel-C Projectsapplication note. That document presents how to create or import a Handel-C project into Active-HDL, then build it and debug the simulation library.

Requirements

To run co-simulation, the interface requires the following tools to be installed:

· Active-HDL 6.1 SP2 or higher

· Celoxica DK Design Suite 2.0 SP2

· Celoxica Platform Developer's Kit 2.1

Additionally, before you start simulating any design, you will need:

· Project-specific wrappers that will connect inputs and outputs of your HDL unit to aHandel-C model

· Handel-C code with a definition of a "simulation interface" that will allow ports of theHandel-C model to be accessed by the HDL simulator

· HDL/Handel-C co-simulation plug-in

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Preparing Handel-C Source File for Co-simulation

In this example, we will instantiate a Handel-C model within an HDL unit, which means thatActive-HDL will play the role of the master simulator. First, we will present how to create aninterface that allows ports of the Handel-C model to be accessed by Active-HDL.

1. Load the acc sample design. This example has been described in the Building and DebuggingHandel-C Projects application note.

2. Open the sum.hcc source file. The original interface of the accumulator coming from the DK'sHandel-C sample project uses input and output channels that read and write data to the files(sum_in.dat, sum_out.dat). In this application note, we will replace the channels with a simulationinterface that can be accessed through input and output ports during simulation by Active-HDL.

3. Replace the original description of the accumulator with the following source code:

The simulation interface for the acc model defines the Handel-C interface sort (_acc), input(data_in) and output (data_out) ports of the accumulator, and the specification of the interfaceused for co-simulation. The with construct points to:

· co-simulation plug-in (extlib = "AldecHandelC.dll")The $PATH system variable must point to the $ALDEC\Bin subdirectory of the Active-HDL installation. Otherwise, you need to specify the absolute path to the DLL file.

· co-simulated model (extinst = "modelname=wrapper; delay=100000")extinst defines arguments that are passed to the simulator. It provides information on

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the name of the co-simulated HDL unit (modelname=wrapper) and the "sampling unit"for a combinatorial logic (delay=<delay_value>). <delay_value> is as a positiveinteger value expressed without the base unit. The delay time after which data issynchronized is a result of multiplication <delay_value> by the current simulationresolution.The syntax of the extinst specification is dependent on your HDL design unit. If theHDL unit represents a sequential logic, the Clock signal should be specified(clock=<clock_name>). It synchronizes both simulators and data exchange on therising edge. If the HDL unit represents a combinatorial logic then the clock parametercan be omitted. Otherwise, it is required and delay can be skipped.

NOTE: Refer to the Interface definition and Handel-C interface for co-simulation chapters inthe Handel-C Reference Manual and the Platform Developer's Kit documentation,respectively for detailed information on the Handel-C Interface specification. For additionalinformation on co-simulation, refer to the Active-HDL on-line documentation.

In the body of the main() function, the sum_out variable has been added. It passes the value ofthe internal variable sum to the output port of the accumulator (data_out). In the original Handel-Cmodel, this variable read data stored in the sum_in.dat file. In the modified code, the read out ofdata from the file has been replaced by the specification of the input port (data_in).

4. Save the changes to sum.hcc.

5. Right-click the Example1.hp project file and choose the Build Handel-C Project option fromthe pop-up menu.

Preparing HDL Source Files for Co-simulation

After the Handel-C model has been re-built, you need to create an HDL wrapper for the Handel-Cmodel that will be instantiated in an HDL design. A wrapper file will pass values of inputs andoutputs between a VHDL or Verilog unit and the co-simulated Handel-C model. You can createeither a VHDL or Verilog wrapper. To create the wrapper:

6. Add a new HDL source file (File | New VHDL/Verilog Source) or run the New Source FileWizard. If you want to use a VHDL wrapper, you will need to define a communication interfacebased on VHPI. If you prefer Verilog, you will need to create an interface based on PLI.

The VHDL wrapper communicates with the Handel-C model by using a foreign architecture andthe built-in VHPI interface. In this method, the entity of the wrapper contains additionaldeclarations of constants that specify parameters for the communication interface required to bindthe Handel-C model with the HDL design. These constants are required (they cannot berenamed) to pass two parameters to the simulator: the name of the library (*.dll) containingcompiled Handel-C model (HANDELC_SIMULATOR) and the name of the VHDL wrapper for thismodel (MODELNAME), respectively. The value of both variables can be set by using the setmacro command or specified on the Handel-C Code Debug and Co-simulation Settings tab ofthe C/Handel-C Code Debug Settings window.

NOTES:1. The names of ports declared in the wrapper's entity must match the names of ports of theHandel-C model.2. It is recommended to use the STD_LOGIC, STD_LOGIC_VECTOR, SIGNED, orUNSIGNED type for the ports of the wrapper. If the unit uses other types, you will need tocreate another VHDL wrapper containing type conversions to the listed types.

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The attribute foreign declared in the handelc architecture indicates that the wrapper has a VHPI-based implementation and specifies the VHPI interface that will be used during co-simulation.AldecHandelC.dll points to the co-simulation plug-in. This file is delivered along with Active-HDLand it is stored in the $ALDEC\Bin subdirectory. The system variable $PATH must point to thissubdirectory. Otherwise, you will need to specify the absolute path to the DLL file.cosim_handelc identifies a VHPI-based implementation for a foreign architecture. See theVHPI Reference Guide or the Active-HDL Interfaces and Application Notes chapters for moreinformation on the built-in VHPI interface. The example of the VHDL wrapper is presented below.

The Verilog wrapper communicates with the Handel-C model by using the PLI interface. In thismethod, the module of the wrapper contains an initial statement that specifies the$cosim_handelc PLI task. $cosim_handelc is a non-standard system task that initializes thecommunication interface during the simulation startup. Its parameters (they cannot be renamed)are passed to the simulator: the name of the library (*.dll) containing compiled Handel-C model(HANDELC_SIMULATOR) and the name of the Verilog wrapper (MODELNAME) for the Handel-C model, respectively. You can specify both the name of the model and the path to the DLL fileby using the $MODELNAME and $HANDELC_SIMULATOR variables, respectively (the value of thevariable can be set by using the set macro command) or set them on the Handel-C Code Debugand Co-simulation Settings tab of the C/Handel-C Code Debug Settings window. Using theVerilog wrapper requires the specification of the co-simulation plug-in (AldecHandelC.dll). InVHDL designs, it is defined by the foreign attribute while in Verilog you need to specify it on theVerilog PLI tab of the Design Settings window. See the PLI Reference Guide or the Active-HDLInterfaces and Application Notes chapters for more information on the built-in PLI interface. Theexample of the Verilog wrapper is presented below.

7. Save the wrapper and compile the source file.

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Specifying Co-simulation Settings

The next step is to setup the co-simulation environment (co-simulated unit and library).

8. Open the C/Handel-C Code Debug Settings window and switch to the Handel-C CodeDebug and Co-simulation Settings tab.

9. Enter the name of the wrapper unit in the Define Model Name field. The simulation library(Example1.dll) should already be specified in the Select Handel-C Library for Debugging andCo-simulation filed. The dialog box is shown in the figure below. Then, close the dialog box.

Setting the name of the wrapper generates the following message to the Console window:

# set HANDELC_SIMULATOR C:\Program Files\Celoxica\DK\Examples\Handel-C\Example1\Debug\Example1.dll# set MODELNAME wrapper

You can also set these arguments by using the set macro command.

Preparing Testbench

After you have modified the source code of the Handel-C model, created the wrapper, andspecified the co-simulation settings, you can proceed to simulate the design. To do so, you willneed a testbench that will stimulate your mixed-language project. You can use the followingexample of the VHDL ...

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library IEEE;use IEEE.std_logic_1164.all;

entity testbench isend entity;

architecture testbench of testbench issignal data: STD_LOGIC_VECTOR(7 downto 0);signal result: STD_LOGIC_VECTOR(15 downto 0);

component wrapper isport (data_out : out STD_LOGIC_VECTOR (15 downto 0);data_in: in STD_LOGIC_VECTOR (7 downto 0));

end component;beginSTIMUL: processbegindata <= "00000000";wait for 200ns;data <= "00000001";wait for 200ns;data <= "00000010";wait for 200ns;data <= "00000011";wait for 200ns;data <= "00000100";wait;

end process STIMUL;

UUT: wrapperport map (result,data);

end architecture;

or Verilog testbench:

`timescale 1ps/1psmodule testbench();

wire [15:0] result;reg [7:0]data;initialbegin#0 data = 8'b0000000;#200000 data = 8'b00000001;#200000 data = 8'b00000010;#200000 data = 8'b00000011;#200000 data = 8'b00000100;

end

wrapper UUT (data,result);

endmodule

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10. Copy the source code presented above to a new empty window in the HDL Editor and add itto the design. To do so, choose the Add Current Document option from the Design menu.

11. Enter testbench in the File name field and click Save in the Save As dialog box.

12. Compile the testbench.v(hd) file and set the testbench unit as the top-level unit.

If you use the Verilog wrapper, before you initialize the simulation, you need to define the path tothe co-simulation plug-in ($ALDEC\Bin\AldecHandelC.dll). In VHDL designs, it is defined by theforeign attribute while in Verilog, you need to specify it on the Verilog PLI tab of the DesignSettings window that is shown in the figure below.

Running Co-simulation

13. Initialize the simulation by choosing the Initialize Simulation command from the Simulationmenu.

14. Click the Structure tab and select the testbench unit.

15. Open a new waveform window.

16. Add the data_in and data_out signals by dragging the UUT instance to the waveform or byselecting the signals and choosing Add to Waveform from the pop-up menu.

17. Choose the Run Until option and enter 1.2us in the dialog box. Then, click OK. You can alsotype in the run 1.2us command in the Console window and press Enter. The simulation willadvance to 1.2us.

Depending on the language used to describe the wrapper, the figures shown below present thesimulation results for the co-simulated Handel-C unit instantiated in the VHDL ...

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or Verilog wrapper, respectively.

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Using Celoxica Flowchart

Introduction

With the growing complexity of today's designs, the methodology of a hardware description ischanging and it forces designers to search for new solutions, design tools, or even descriptionlanguages that could be used to specify the behavior of digital devices.

The Active-HDL's Design Flow Manager provides a flowchart and interface to Celoxica's Handel-C-to-hardware DK Design Suite©. Introducing the flowchart allows the DK Design Suite users torun the tool directly from Active-HDL and "translate" their Handel-C-based designs to VHDL,Verilog, or EDIF that can be then verified in the integrated simulation environment.

This application note will help you get familiar with the Celoxica flowchart and show you how touse it in Active-HDL. In this application note, we will use the Celoxica's sample project of a FIRfilter stored in the <DK_Design_Suite_directory>\examples\vhdl\example3 subdirectory.

Creating a sample design

1. Start Active-HDL by going to the Start | Programs group and click the Active-HDL icon. TheActive-HDL Welcome screen appears and then the Getting Started dialog opens.

2. Select the Create new workspace option and click the OK button. You can alternatively usethe File | New | Workspace option to open the New Workspace window.

3. The New Workspace wizard appears. In the wizard's dialog, you can enter the name andlocation of the workspace. Enter filter in the Type the workspace name field. Make sure that theAdd New Design to Workspace checkbox is selected.

4. Click the OK button. When you close the New Workspace wizard, the New Design Wizardwill be loaded.

5. Select Add existing resource files and press Next.

6. Add the following source files and then click Next:

· receiver.hcc

· filter.vhd

· wrapper.vhd

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7. Choose the settings as it is shown in the figure below.

8. In the last wizard's window, specify the name of the design, disable the Compile source filesafter creation option, and click Finish. The design tree is presented below.

Setting Options for Celoxica Flowchart

9. Go to the Design menu and choose Flow Settings.


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10. From the C Synthesis section, choose Celoxica. Next, close the Flow ConfigurationSettings window.

11. Before you run Celoxica, you need to specify the C-synthesis settings. To do so, press theCeloxica's Options button in the Design Flow window.

12. In the Celoxica Options window, specify the top-level unit, target format, family, device, andspeed grade. Click OK to complete.

13. Now, you have specified in Active-HDL all the settings required to run C-synthesis with theCeloxica's environment. Pressing the Celoxica button in the Design Flow window starts DKDesign Suite and loads the Example3 sample design. The design contains only one source file -receiver.hcc.

14. Before you start building, you should select the VHDL configuration. In order to select it,choose Set Active Configuration from the Build menu or use the pull-down menu as it is shownin the figure below

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15. After the active configuration has been set, you can build the project by using the Build (F7)

command from the Build menu or clicking from the toolbar. When the project is built, you canfind on the Build tab information on an estimated usage of resources.

16. Close DK Design Suite and switch to Active-HDL. After the project has been built, theCeloxica subfolder is created in the design folder. In this folder, the files generated by DKDesign Suite will be stored. The Refresh File List button in the Design Flow window (next tothe Celoxica button) allows you to point to the files that should be added to the filter design.Press the browsing button (...) in the Choose Source File dialog box and then select the requiredfiles from $DSN\Celoxica\Vhdl. The design tree containing all the files is presented below.

Synthesizing the Design

17. Open the Synthesis Options window. In this window, specify the name of the top-level unit(wrapper) and other options on the General tab as it is shown below.


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18. Open the Libraries tab and specify a library (alias) used by the synthesis tool. Click AddAlias, type in HandelC and press OK. In the Add File window, browse to the$ALDEC\Vlib\handelc\src subfolder and select the handelc.vhd file. Next, press the Open button.

19. Close the Synthesis Options window by clicking OK. When you specify all settings you canrun the synthesis by pressing the Synthesis button in the Design Flow window. After thesynthesis has finished, you can view the synthesis report in the window shown below or byopening the log file.

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The post-synthesis subfolder is added to the design tree. It contains two files: wrapper.edf usedby the implementation tool and wrapper.vhm that can be used to run post-synthesis simulation.Now, we can proceed to start an implementation process.

Implementing the Design

20. You can run the implementation with the default settings or modify them in theImplementation Options window. In this window, after you specify all settings you can run theimplementation by pressing the Implementation button in the Design Flow window.


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You can review the implementation report in the window shown below or open the log file in theHDL Editor window.

After the implementation has completed, you can compile time_sim.vhd and run the timingsimulation of the filter design, which allows you to check the implementation results.

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For more information on using the Design Flow Manager during compilation, post-synthesis, andtiming simulation, see the Post-Synthesis and Timing Simulation topic in the on-linedocumentation.

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Using TestBencher Pro™ with Active-HDL™

Introduction

Active-HDL provides the built-in testbench generation, however, it also allows using testbenchescoming from external verification tools. This application note will show you how to useSynaptiCAD’s TestBencher Pro™ with Active-HDL™.

In this application note, we will create a testbench for the V_FMeter sample design that isinstalled along with Active-HDL.

Creating a New Project

1. Start TestBencher Pro and choose the New Project option from the Project menu.

2. In the New Project Wizard window, specify the settings as it is shown in the figure below.

3. Choose default settings in subsequent dialogs and in the last dialog press Finish to completethe creation of the new design. The Project - V_FMeter_Testbench.hpj window opens.

Now, we will add the source files of the V_FMeter design to the TestBencher Pro project.

4. Right-click the User Source Files folder and choose Add Files to User Source File Folderfrom the pop-up menu.

5. In the Add File(s) window, open the folder where the V_FMeter sample design is stored(C:\My_Designs\Samples\V_FMeter\src).

NOTE: In this application note, we use a non-default location of the sample design.

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6. Select Bin2bcd.v and Hex2led.v. Click OK to add the selected files.

7. Change the path to C:\My_Designs\Samples\V_FMeter\compile and select remaining sourcefiles generated from the Block and State Diagram Editor: cnt10b.v, control.v, and freq_m.v. TheProject window is shown below.

8. Click the Extract the MUT ports into Diagram button, which starts parsing the design andextracts Model Under Test (MUT). Extracting MUT allows then choosing the top-level module forwhich the testbench is to be created. After the structure has been parsed, the top-level module(freq_m) is extracted and displayed in the Simulated Model folder of the Project window. TheProject window is presented in the figure below.

The results of project parsing are generated during the compilation and displayed in the Reportwindow.

Using TestBencher Pro(TM) with Active-HDL

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Creating Stimuli

Before the testbench is generated, we need to create stimuli for input signals by editing the newlyopened timing diagram window containing the extracted top-level signals.

9 To mark the signal as observed (FULL, LED_A, LED_B, LED_C, and LED_D), double-click itand set the Watch check box in the Signal Properties window. All signals that will be forced(inputs) are displayed in black whereas all observed signals cannot be edited and they aredisplayed in gray. The window with the selected signals is presented below.

10. Next, we create timing transactions for the input signals and save them in the stimulus.btimfile. The window presenting transactions for the F_CONV, RESET, START, F_INPUT, andF_PATTERN signals is shown below.

After the transactions have been specified, we need to add a time marker that points to the “endsimulation” time.

11. To add the time marker, click the Marker button and go to the “end simulation time” point.Click with the right-mouse button to insert the time marker. The vertical line is inserted.

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12. Double-click it and set the options in the Edit Time Marker window as it is shown in the figurebelow.

13. Click OK to apply the settings and then save the file. The Diagram - stimulus.btim window ispresented in the figure below.

NOTE: For more information on creating timing transactions and adding time markers, refer toWaveformer Pro’s on-line documentation.

14. Add stimulus.btim to the Transaction Diagrams folder by right-clicking the list of signals in theDiagram - stimulus.btim window and choosing the Add Diagram To Transaction DiagramFolder option. The Project window with stimulus.btim added to the Transaction Diagrams folderis shown below.


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Now, you can generate the testbench file for the freq_m simulated model. The testbench will begenerated into the V_FMeter_Testbench.v file. Before it is used during simulation, you need tospecify the task that calls a subroutine generating test vectors for MUT.

15. First, generate the testbench by clicking the Generate Test Bench button or right-clickComponent Model (V_FMeter_Testbench.v) and choose the Generate Test Bench option.

16. Next, double click Component Model (V_FMeter_Testbench.v) to open the testbench file andinsert the cursor in the code as it is shown in the figure below.

17. Choose the Insert Diagram Calls option from the context menu. The Insert DiagramSubroutine Call window shown below will open.

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18. You can use the default settings (Run Once, Wait for Completion) and then click Insert.After the task has been inserted to the code, save the testbench file and close it. The modifiedcode is as follows:

Now, the testbench is ready-to-use. However, before you compile the TestBencher project, youneed to specify the target simulator that will be used to simulate MUT (freq_m) with the generatedtestbench.

19. To set the simulator, go to the Options menu and choose the External Program Settingsoption. After the External Program Settings window opens, set the Enable External ProgramIntegration checkbox and choose Active-HDL from the Simulator list box. In the Target OS listbox, choose Windows based and then point to the \Bin subfolder of the Active-HDL installation inthe Simulator Path field. The settings are presented below.


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20. Press OK to apply the settings.

Now, all the TestBencher Pro settings are specified and you can compile the project.

21. Press the Compile Model and Test Bench toolbar button or choose Build (F7) from theSimulate menu. This option starts VSimSA and the process of the design compilation. You canobserve compilation results on the simresult.txt tab of the Report window.

After the design has been compiled, you can run the simulation with the newly created testbench.

22. To start the simulation, click the Run/Resume Simulation button or choose Run from theSimulation menu. The simulation report is displayed during the simulation on the simresults.txttab of the Report window.

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Simulation data is saved in the waveform file that can be loaded to the Active-HDL WaveformViewer window. The waveform window is presented in the figure below.

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Building PLI Applications

Introduction

The Verilog PLI, or Programming Language Interface, provides a standard mechanism thatallows designers to access and modify data in a simulated Verilog model. The PLI interfaceallows creating user-defined tasks and functions that interact with Active-HDL. Then, they can beplaced directly in HDL source code or called interactively from the Console window.

Active-HDL provides both the PLI interface linking applications to the simulator and tools thatallow designers to compile and debug them within one integrated environment.

This application note will show you how to create, compile, and build a PLI application in Active-HDL by using the PLI Wizard, PLI Interface, and C-related built-in features and tools.

Building PLI Application

Active-HDL loads PLI applications dynamically during the initialization of simulation. Therefore,they must be compiled and linked to a shared library. The PLI applications are loaded by usingoperating system calls and their building process may differ on different operating systems.

In this application note, we will focus on the platform used by Active-HDL.

Header Files

The \PLI\Include subdirectory of the Active-HDL installation directory contains header files thatmust be included in every PLI application.

#include <veriuser.h>#include <aldecpli.h>

The aldecpli.h header file contains an include directive for the acc_user.h header file. The PLIapplications must be registered through an array of s_tfcell structures. The structure is defined inthe aldecpli.h file.

typedef struct t_tfcell{

short type;int data;int (*checktf)();int (*sizetf)();int (*calltf)();int (*misctf)();char* tfname;/* The following fields are ignored */int forwref;char *tfveritool;char *tferrmessage;int hash;struct t_tfcell *left_p;struct t_tfcell *right_p;char *namecell_p;int warning_printed;

} s_tfcell, *p_tfcell;

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Compiling and Linking Sources

To compile a PLI application, you can use any C/C++ compiler e.g. Microsoft Visual C++®. IfMicrosoft Visual C++ is used, the aldecpli.lib library needs to be added to the Resource Filesfolder. It is located in the \PLI\Lib subdirectory of the Active-HDL installation directory.

Next, add a definition file to the Header Files folder. The definition file should contain the followingentry:

EXPORTSveriusertfs DATA

Assuming that the source code for your PLI application is located in the mypli.c file, the projectworkspace will look like in the figure below:

To use a PLI application in Active-HDL, you can compile source files by using any C/C++compiler. However, to be able to debug the application in Active-HDL, it needs to be compiledwith a tool producing Gdb-compatible debug information. The installation of Active-HDL providesthe Gcc compiler and the Gdb debugger that can be used to compile and debug PLI applicationsthat will then be loaded to the simulation environment.

This application note is based on Active-HDL’s hex2bin_bde sample design. The purpose of thisexample is to show how to create and compile C/C++ applications in Active-HDL and how to linkthem to HDL designs. In this design, we will create a simple application that lists in the Consolewindow the structure of the design.

Loading sample design

1. The first step is to load the hex2bin_bde sample design. To open it, choose OpenWorkspace/Design Explorer from the File menu. Then, double-click the hex2bin_bdeworkspace icon (\Samples\Verilog_Designs).


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2. The workspace you have just opened contains the design that needs to be compiled before

you proceed with the simulation. To compile it, choose the Compile All command from theDesign menu.

3. After the successful compilation, set top-level by clicking the Top-Level selection list box andselecting the UUT_PLI unit as it is shown in the figure below.

Creating PLI Application

After you have specified the design top-level, you can proceed to create a PLI application. ThePLI Wizard is a tool that simplifies the creation of PLI applications in the Active-HDLenvironment. The wizard will help you select the name of the PLI task/function, its parameters,values, and it will fill the veriusertfs table stored in the veriuser_aldec.cpp file. As an output, thePLI Wizard will create C templates for PLI routines.

In our sample design, we will use a single PLI routine stored in a single C source file. The PLIWizard option is available from the Tools menu and it can be run only when the design is loaded.

4. To start creating the PLI routine template, choose VHPI/PLI Wizard from the Tools menu.

5. Switch to the PLI Wizard tab and type in structure in the System task/function name andCalltf routine fields.

6. Set the remaining options as it is shown in the figure below.

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7. When the settings are specified, press Modify list, then Generate, and close the window byclicking OK.

8. Except the C source file, the PLI Wizard also generates additional files into the \PLI subfolder.They are required while compiling a C source code by using Microsoft Visual Studio. SinceActive-HDL provides the Gcc compiler, we will use only the generated C source files.

The Console window lists all files that have been create by the PLI Wizard.# Design: Created file C:\My_Designs\HEX2BIN_BDE\src\PLI\pli.set# Design: Created file C:\My_Designs\HEX2BIN_BDE\src\PLI\veriuser_aldec.cpp# Design: Created file C:\My_Designs\HEX2BIN_BDE\src\PLI\structure_pli.cpp

The design tree with the new \PLI subfolder is shown in the figure above. The generatedstructure_pli.cpp file contains only an empty template of the calltf routine. In order to achieve ouraim and allow displaying the structure of the design, we will add one more function and modifythe calltf one. Since we are going to use the Gcc compiler, we will pay our attention only to theupdate of the structure_pli.cpp source file.

9. Double-click structure_pli.cpp to load the file into the HDL Editor window. The template file isshown in the figure below.

10. Add the following header file declaration at the beginning of the source file:

#include "aldecpli.h"


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11. Enter the following code below the line starting with //--Enter your function here--//:

int level=0;void printNextBranch(handle module_handle){

handle child_handle = null;// scan recursively beginning with top-level moduleswhile (child_handle = acc_next_child(module_handle, child_handle)){

io_printf("%s\n", acc_fetch_fullname(child_handle));printNextBranch(child_handle);

}}

The modified User function section of structure_pli.cpp is shown in the figure below.

12. Modify the structure routine by adding the following code:

int structure ( ){// -- Enter your statements here -- //

// initialize environment for access routinesacc_initialize();printNextBranch(null);acc_close();return (0);

}

The modified routine is shown in the figure below.

13. Save the source file.

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The structure_pli.cpp sample PLI application allows printing in the text mode the structure of thedesign to the Console window. The application is registered in the veriusertfs array. The entry inthe array registers usertask. The task is registered as a calltf routine. Every time Active-HDLencounters a $structure task in the Verilog code, it will execute the structure function. Thefunction calls printNextBranch() that scans recursively the structure of the design. Handles tosubsequent modules are obtained with acc_next_child(). Once you have the module handle, youcan get the name of the module with acc_fetch_fullname().

Active-HDL provides an interface to the Gcc compiler that can be used to build user-defined PLIor VHPI applications. Before you compile any C/C++ source code, you may want to check aconfiguration file for your application. In this case, the configuration is stored in theHEX2BIN_BDE.dlm file that contains information on source files to compile along with includefiles, required libraries, compiler and linker options.

To check the configuration:

14. Double-click the HEX2BIN_BDE.dlm file. The C/C++ Configuration dialog window opens,which allows you to specify all options required to build the PLI application. These options are:the name and location of the DLM configuration file (Configuration Name), the name and path tothe DLL file (it will be set automatically, however, if required you can specify another settings forboth files by entering them manually or by using the Browse buttons), the type of the applicationto be built (selected from the Library type list box), the list of source files and libraries as well ascompiler and linker options.

15. Enter structure.dll in the C/C++ library name field.

When all the options are specified, click Save to apply the changes.

16. Click HEX2BIN_BDE.dlm with the right-mouse button and choose Build from the contextmenu. After structure.dll has been built, you need to point to this file in order the simulator to loadit during the simulation.

17. Choose Settings from the Design menu.


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18. Switch to the Verilog PLI tab and add structure.dll to the PLI Applications list. The DesignSettings window is presented below.

19. Initialize the simulation by selecting the Initialize Simulation option from the Simulationmenu. During the initialization of the simulation, the simulator loads the PLI application, which isreported to the Console window.

# KERNEL: PLI/VHPI kernel's engine initialization done.# PLI: Loading library 'c:\My_Designs\HEX2BIN_BDE/src/structure.dll'

In order to display the structure of the hex2bin_bde sample design, you should call the$structure task. You can call it interactively from the Console window. To print the structure ofthe design to the Console window, type in the following command:

$structure

This calls the $structure task and prints the design structure in the Console window:

# UUT_PLI# UUT_PLI.CNV# UUT_PLI.CNV.U1# UUT_PLI.CNV.U2# UUT_PLI.CNV.U3# UUT_PLI.CNV.U3.U1# UUT_PLI.CNV.U3.U2# UUT_PLI.CNV.U3.U3# UUT_PLI.CNV.U3.U4# UUT_PLI.CNV.U4# UUT_PLI.CNV.U5# UUT_PLI.CNV.U5.U0# UUT_PLI.CNV.U5.U1# UUT_PLI.CNV.U5.U2# UUT_PLI.CNV.U5.U3# UUT_PLI.CNV.U6

The execution of the task is reported by the simulation kernel in the Console window:

# KERNEL: Task "$structure" execution completed

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Introduction

VHPI, or VHDL Procedural Interface, provides a standard mechanism that allows designers toaccess data in a simulated VHDL model. The interface is implemented as a library of C functions.The VHPI implementation in Active-HDL complies with the standard being developed by theIEEE.

The VHPI interface in Active-HDL provides the following functionality:

· Access to Static VHDL DataThis provides access to behavioral and structural parts of the elaborated model. A userapplication can, for example, traverse the hierarchy of a VHDL design, fetch properties ofVHDL objects or navigate between objects of a specific type.

· Access to Dynamic VHDL ObjectsThis functionality enables reading values of VHDL objects such as signals or variables. Avalue can be fetched in a few different formats described by the VHPI specification.

· Simulation Interaction and ControlThe simulation interaction is achieved by registering callbacks to happen for specificconditions. A callback is a communication mechanism between the Active-HDL simulatorand user’s C code.

· Foreign Model Instantiation and Intercommunication MechanismVHPI user applications have to be registered during simulation startup in order to workproperly. The registration mechanism uses VHPI foreign architectures.For general information on VHPI, refer to VHPI Standard Specification. For moreinformation on the VHPI support and a list of constructs supported by Active-HDL, seethe Active-HDL on-line documentation.

Active-HDL provides both the VHPI interface linking applications to the simulator and tools thatallow designers to compile and debug them within one integrated environment.

This application note will show you how to create, compile, and build a VHPI application in Active-HDL by using the VHPI Wizard, VHPI Interface, and C-related built-in features and tools.

Building VHPI Application

Active-HDL loads VHPI applications dynamically during the initialization of simulation. Therefore,they must be compiled and linked to a shared library. VHPI applications can be registered eitherthough a foreign model, that is a foreign architecture or a foreign subprogram.

In this application note, we will focus on a registration based on a foreign architecture

Header Files

The \PLI\Include subdirectory of the Active-HDL installation directory contains header files thatmust be included in every VHPI application.

#include <vhpi_user.h>#include <aldecpli.h>

The aldecpli.h header file contains the include directive for the acc_user.h header file(\PLI\Include). The aldecpli.lib file needed to link VHPI libraries under Windows is located in the\PLI\Lib subdirectory.

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Registering VHPI Applications

Each VHPI library must include at least one function to register VHPI tasks. A pointer to thisfunction is located in the vhpi_startup_routines array. The array must be null terminated. Namesof the registering functions are arbitrary, for example:

PLI_VOID (*vhpi_startup_routines[])() = {startup_1,startup_2,null

};

Functions that register VHPI tasks, for example startup_1, use the standard VHPI functionvhpi_register_foreignf(). The vhpi_register_foreignf() function must be passed a pointer to thevhpiForeignDataT structure, for example:

PLI_VOID startup_1() {vhpiForeignDataT foreignDatap = {

vhpiArchFK,"myvhpi","myvhpitask",elabf_1,execf_1

};vhpi_register_foreignf(&foreignDatap);

}

The vhpiForeignDataT structure is defined in the vhpi_user.h header file. It includes fiveelements:

· vhpiArchFKThis constant specifies that the foreign model is an architecture. The following constantscan be used depending on the foreign model:- vhpiArchFK specifies that the foreign model is an architecture- vhpiProcFK specifies that the foreign model is a procedure- vhpiFuncFK specifies that the foreign model is a function

· char *libraryNameThe name of the library containing VHPI routines. The name can be either absolute orrelative to the Active-HDL current directory. If you omit the extension, Active-HDL willautomatically add the default .dll extension. If the library cannot be found in the currentdirectory, Active-HDL will check the locations pointed by the PATH system variable.

· char *modelNameThe name of the VHPI task that appears in the VHDL foreign attribute string.

· void (*elabf) (const vhpiCbDataT* cbdata)Pointer to the callback function for the elaboration of the foreign architecture. Thisfunction can only reference objects within the instance of the architecture that called thefunction.

· void (*execf) (const vhpiCbDataT* cbdata)Pointer to the callback function for initialization of the foreign architecture. This functioncan access the whole VHDL design.


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Compiling and Linking Sources

To use a VHPI application in Active-HDL, you can compile source files by using any C/C++compiler. However, to be able to debug the application in Active-HDL, it needs to be compiledwith a tool producing Gdb-compatible debug information. The installation of Active-HDL providesthe Gcc compiler and the Gdb debugger that can be used to compile and debug VHPIapplications that will then be loaded to the simulation environment.

This application note is based on Active-HDL’s datapath sample design. The purpose of thisexample is to show how to create and compile C/C++ applications in Active-HDL and how to linkthem to HDL designs. In this design, we will create a simple application that will search for designsignals, components, and processes and then list them in the Console window.


1. The first step is to load the datapath sample design. To open it, choose OpenWorkspace/Design Explorer from the File menu. Then, double-click the datapath workspaceicon (\Samples\VHDL_Designs).

2. The workspace you have just opened contains the design that needs to be compiled before

you proceed with the simulation. To compile it, choose the Compile All command from theDesign menu.

3. After the successful compilation, set top-level by clicking the Top-Level selection list box andselecting the top_testbench (tb_architecture) unit as it is shown in the figure below.

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Creating VHPI Application

After you have specified the design top-level, you can proceed to create a VHPI application. TheVHPI Wizard is a tool that simplifies the creation of VHPI applications in the Active-HDLenvironment. The wizard will help you select the name of the VHPIarchitecture/function/architecture name, its parameters, values, and it will fill theforeignDataArray table stored in the vhpiuser_aldec.cpp file. As an output, the VHPI Wizard willcreate C templates for VHPI routines.

In our sample design, we will use a single VHPI routine stored in a single C source file. The VHPIWizard option is available from the Tools menu and it can be run only when the design is loaded.

4. To start creating the VHPI routine template, choose VHPI/PLI Wizard from the Tools menu.

5. On the VHPI Wizard tab, type in dump_hierarchy in the VHDLprocedure/function/architecture name field.

6. Set the remaining options as it is shown in the figure below.

7. When the settings are specified, press Modify list, then Generate, and close the window byclicking OK.

8. Except the C source file, the VHPI Wizard also generates additional files into the \VHPIsubfolder. They are required while compiling a C source code by using Microsoft Visual Studio.Since Active-HDL provides the Gcc compiler, we will use only the generated C source files.

The Console window lists all files that have been create by the VHPI Wizard.# Design: Created file C:\My_Designs\Datapath\src\VHPI\vhpiuser_aldec.cpp# Design: Created file C:\My_Designs\Datapath\src\VHPI\dump_hierarchy_vhpi.h# Design: Created file C:\My_Designs\Datapath\src\VHPI\dump_hierarchy_vhpi.cpp# Design: Created file C:\My_Designs\Datapath\src\VHPI\dump_hierarchy_vhpi.vhd


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The design tree with the new \VHPI subfolder is shown in the figure above. The generateddump_hierarchy_vhpi.cpp file contains only an empty template of the execf routine pointer. Inorder to achieve our aim, we will add one more function and modify the execf one. Since we aregoing to use the Gcc compiler, we will pay our attention only to the update of thedump_hierarchy_vhpi.cpp source file. The dump_hierarchy_vhpi.cpp sample VHPI application willsearch for signals, components, and processes, then count and list them in the Console window.

9. Double-click dump_hierarchy_vhpi.cpp to load the file into the HDL Editor window. Thetemplate file is shown in the figure below.

10. Add the following header file declaration at the beginning of the source file:

#include "stdio.h"

11. Enter the following code below the line // put your code here:

vhpiHandleT rootInstHdl = NULL; // handler to rootInst componentvhpiHandleT iteratorSigHdl = NULL; // iterator for SigDeclsvhpiHandleT Hdl = NULL; // handlervhpiHandleT archBodyHdl = NULL; // handler to archBodyvhpiHandleT entityDeclHdl = NULL; // handler to entityDecl

int numObjs = 0; // initialize objects countervhpi_printf("\nUsing VHPI application as Foreign Architecture tocount declared signals...");//1.if ( rootInstHdl = vhpi_handle(vhpiRootInst, NULL) ){

//2// signal declarationsif ( iteratorSigHdl= vhpi_iterator(vhpiSigDecls, rootInstHdl) )

//3.while ( Hdl = vhpi_scan(iteratorSigHdl) ){

// handler points to object of type vhpiSignalDeclK(signal)

vhpi_printf("found signal: %s ", // signal name

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vhpi_get_str(vhpiNameP, Hdl));numObjs++;

}

traverse_hierarchy(rootInstHdl, &numObjs);// fetching some information about analyzed design:// name of architecture of top level designif ( archBodyHdl = vhpi_handle(vhpiDesignUnit, rootInstHdl) ){

// name of entity of top level designif ( entityDeclHdl = vhpi_handle(vhpiPrimaryUnit,archBodyHdl) ){vhpi_printf("==============================================================");

vhpi_printf("SUMMARY:");vhpi_printf("Analyzed entire design '%s' contains %dsignal(s)", vhpi_get_str(vhpiNameP, entityDeclHdl),numObjs);

}}

}

vhpi_printf("\nEnd of Your VHPI application.......");

The modified routine is shown in the figure below.

12. Add the auxiliary traverse_hierarchy routine below the line with the header file declarations:

PLI_VOID traverse_hierarchy(vhpiHandleT ScopeHdl, int *numObjs){vhpiHandleT iteratorSigHdl = NULL; // iterator for SigDeclsvhpiHandleT iteratorRegHdl = NULL; // iterator for InternalRegionsvhpiHandleT Hdl = NULL; // handlervhpiHandleT SigHdl = NULL; // handlerif (ScopeHdl==NULL) return;


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if ( iteratorRegHdl = vhpi_iterator(vhpiInternalRegions, ScopeHdl))

//1.while ( Hdl = vhpi_scan(iteratorRegHdl) ){

//2.vhpi_printf("%s [%d]: %s ",vhpi_get_str(vhpiKindStrP, Hdl),vhpi_get(vhpiKindP, Hdl),vhpi_get_str(vhpiNameP, Hdl) );// signal declarationsif (iteratorSigHdl= vhpi_iterator(vhpiSigDecls, Hdl))

//3.while ( SigHdl = vhpi_scan(iteratorSigHdl) ){

// handler points to object of type vhpiSignalDeclK(signal)vhpi_printf("found signal: %s ", //signal namevhpi_get_str(vhpiNameP, SigHdl));(*numObjs)++;

}traverse_hierarchy(Hdl, numObjs);}

}

The modified dump_hierarchy_vhpi.cpp is shown in the figure below.

VHPI applications can be registered by using subprograms or through architecture with a foreignattribute (declared in the standard package of the std library). This example will show how toregister the VHPI application by using the foreign architecture.

The VHPI Wizard provides the dump_hierarchy_vhpi.vhd file that contains the declaration of theforeign attribute. To load the VHPI application during the initialization of simulation, we need tocreate an auxiliary entity/architecture pair that stores the declaration of the attribute. To do so:

13. Double-click dump_hierarchy_vhpi.vhd.

14. Modify the code of dump_hierarchy_vhpi.vhd by adding the entity and architecturedeclarations. The modified code is listed below.

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-------------------------------------------------------------------------------------------------------------------------------------------- Please put this declaration in architectureentity dump_hierarchy isend entity dump_hierarchy;architecture dump_hierarchy of dump_hierarchy isattribute foreign of dump_hierarchy : architecture is "VHPIVHPI\dump_hierarchy.dll; dump_hierarchy_model";begin

end architecture dump_hierarchy;------------------------------------------------------------------------------------------------------------------------------------------

15. Compile the file.

Since we are going to proceed with registering the VHPI application through foreign architecture,we need to instantiate the dump_hierarchy unit within the selected top-level.

16. Open the testbench.vhd file.

17. Add the declaration of the dump_hierarchy component as it is shown in the figure below.

18. Next, add the component instantiation statement:

APPLICATION_FROM_VHPI : dump_hierarchy;

as it is shown in the figure below.

19. Save and compile the testbench.vhd file.

Active-HDL provides an interface to the Gcc compiler that can be used to build user-defined PLIor VHPI applications. Before you compile any C/C++ source code, you need to specify aconfiguration file for your application. In this case, the configuration is stored in the datapath.dlm


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file that contains information on source files to compile along with include files, required libraries,compiler and linker options.

To check the configuration:

20. Double-click the datapath.dlm file. The C/C++ Configuration dialog window opens, whichallows you to specify all options required to build the VHPI application. These options are: thename and location of the DLM configuration file (Configuration Name), the name and path to theDLL file (it will be set automatically, however, if required you can specify another settings for bothfiles by entering them manually or by using the Browse buttons), the type of the application to bebuilt (selected from the Library type list box), the list of source files and libraries as well ascompiler and linker options.

21. Enter dump_hierarchy.dll in the C/C++ library name filed.

When all the options are specified, click Save to apply the changes.

22. Click dump_hierarchy.dlm with the right-mouse button and choose Build from the contextmenu. After dump_hierarchy.dll has been built, you can initialize the simulation.

23. Choose the Initialize Simulation option from the Simulation menu. During the initialization,the application is registered through the VHDL foreign architecture, which is reported to theConsole window.

# KERNEL: PLI/VHPI kernel's engine initialization done....# VHPI: Loading library 'VHPI\dump_hierarchy.dll'

Loading vhpiuser_aldec.dll starts analyzing the design and prints information on found signals,components, processes to the Console window:

# : Using VHPI application as Foreign Architecture to count declaredsignals# : found signal: CLK# : found signal: RESET# : found signal: START# : found signal: CODE

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# : found signal: DATA_IN......

After the entire design has been “scanned”, the Console window displays information on theanalyzed unit and the total number of found signals:

# : ==============================================================# : SUMMARY:# : Analyzed entire design 'top_testbench' contains 29 signal(s)# :# : End of Your VHPI application....# Simulation has been initialized# Selected Top-Level: top_testbench (tb_architecture)

167

Debugging C/C++ Applications

Introduction

Active-HDL provides a debugging tool for users who need to verify VHPI/PLI applicationsattached to VHDL or Verilog designs. The C Code Debug option allows designers to debug DLLsbeing a part of the design. The simulation of the design along with the VHPI/PLI application isperformed within the VSimSA environment through the built-in VHPI/PLI interface. The VHPI/PLIapplications can be debugged by using the HDL Editor and C Code Debug windows and thesimulator's output can be observed in the VSimSA window.

The HDL Editor allows inserting breakpoints and tracing C/C++ code while the Console windowallows entering and executing Gdb commands as well as viewing messages generated during thedebugging session. To debug a DLL file, it should be compiled with the Gcc-compatible compilerproducing the Gdb-compatible debug data.

The installation program of Active-HDL installs tools that allow compiling and debugging C/C++source code. The compiler (gcc.exe) and the debugger (gdb.exe) are parts of MinGW (MinimalistGNU for Windows Edition ver. 2.0.0) and they are installed in the \MinGW\bin subdirectory of theActive-HDL installation.

This application note will guide you through the process of C/C++ code debugging and allows youto familiarize with capabilities of C/C++ compilation in Active-HDL. For additional information oncompiling C/C++ applications, see the Building PLI Applications or Building VHPI Applicationsapplication notes.

This application note is based on the hex2bin_bde sample design installed with Active-HDL.

NOTE: In order to use the C Code Debug option, the license for the batch mode simulation(VSimSA) is required.


1. The first step is to load the hex2bin_bde sample design. To open it, choose OpenWorkspace/Design Explorer from the File menu. Then, double-click the hex2bin_bdeworkspace icon (\Samples\Verilog_Designs).

2. The workspace you have just opened contains the design that needs to be compiled beforeyou proceed with the simulation. To compile it, choose the Compile All command from theDesign menu.

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3. After the successful compilation, set top-level by clicking the Top-Level Selection list box andselecting the UUT_PLI unit as it is shown in the figure below.

Setting C Code Debug Options

4. Choose the C/Handel-C Code Debug Settings option from the Design menu. The C/Handel-C Code Debug Settings dialog window opens. It provides configuration options that will be usedwhile initializing the debugging session of your C/C++ or Handel-C application. Now, we will setoptions for the C/C++ debugging session (C Code Debug Settings tab).

5. Use the settings as it is shown in the figure below.

In this window, we specify options that among others will create and automatically add thegenerated macro to the design.


169

In the PLI Applications section, the list of DLL files is displayed. A PLI application is displayed inthis section if you have added a DLL file to the Verilog PLI tab in the Design Settings window.

In VHDL designs, VHPI applications are registered through architecture with a foreign attribute.The attribute is declared in the standard package of the std library. The foreign architecture couldbe defined as follows:

architecture <architecture_name> of <entity_name> isattribute FOREIGN of <architecture_name>: architecture is"VHPI <library_name>; <model_name>";

For additional information on the options of the C Code Debug Settings and Design Settingswindows or Using VHPI Applications, see the Active-HDL on-line documentation.

6. Click OK to close the dialog.

After the settings of the debugging session have been specified and you have closed theC/Handel-C Code Debug Settings window, the run_cdebug.do macro file that have beenspecified in the Startup Macro field is attached to the design tree, which is presented in thefigure above.

Initialization of Debugging Session

7. To initialize the debugging session, choose the Initialize C Code Debug option from theSimulation menu. It starts the VSimSA simulator in a separate command prompt window andopens the C Code Debug window in Active-HDL as well as the HDL Editor window with a C/C++source code. During the initialization of the debugging session, VSimSA displays in the commandprompt window information on simulation environment, working library, and loaded VHPI/PLIlibrary.

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The Console window displays additional messages related to breakpoints that have been set:

# C Code Debug: Automatic breakpoint insertion enabled.

# C Code Debug: C Code Debug session has been started.

The Source files tab of the C Code Debug window lists all source files that have been compiled.By double-clicking a source file, you can open it in the HDL Editor that supports C/C++ syntaxand keyword coloring, allows setting breakpoint and tracing a code.

After the debugging session has been initialized, the C/C++ source file is loaded and breakpointsare set automatically.

If required, you can set your own breakpoints by pressing F9 or choosing Toggle Breakpoint

from the Simulation menu. Setting breakpoint will be reported in the Console window:

# C Code Debug: C breakpoint id c.11 has been set: file:'C:\My_Designs\HEX2BIN_BDE\src\external\read_byte_ex.c' line '74'function 'read_byte_ex_misctf'


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The list of breakpoints that have been set is available in the Edit Breakpoints window(Simulation | Edit Breakpoints) shown below.

The initialization of the debugging session is denoted by the C Code Debug status that is shown

in the Simulation Time/Status field .

Executing Gdb Commands

The C Code Debug window allows entering the Gdb commands to control the debuggingsession. In this application note, we will start the session by using the continue Gdb command.

8. Type in continue in the Gdb command field and press Execute. The command continues aprogram being debugged that has been suspended by a breakpoint. When the command isissued, the debugger starts and the HDL Editor displays the yellow debug line that is set on thefirst encountered breakpoint in the C/C++ source code. The HDL Editor window is presented inthe figure below.

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Each command executed from the C Code Debug window is echoed into the Console window. Italso displays values returned by executed commands, which is shown in the figure below.

You can also debug the C/C++ source code in the HDL Editor window by using the Trace Into

, Trace Out , or Trace Over options from the Simulation menu or from the toolbar.

9. The C Code Debug window also allows you to observe functions and variables used in theC/C++ source code. The Call Stack tab allows you to view detailed information on subprogramsand selected call stack objects declared in the code along with their values.

NOTE: To enable displaying objects on the Call Stack tab, you need to check the Enable CallStack functions list option in the C Code Debug Settings dialog window.

In the Watch tab, you can add variables and observe their values during the debugging session.To add a variable:

10. Switch to the Watch tab.

11. Double-click the Expression column. This turns the editing mode on and you can enter thename of the item you want to observe e.g. in_file.

12. Press Enter to complete.

13. Repeat step #11 to add subsequent items e.g. chr, vec_size, and val (all the variables aredefined in the read_byte_ex_calltf() function).

Depending on the visibility scope i.e. the function being currently debugged, you may see Error:Not available displayed in the Value column.


173

When you start debugging the read_byte_ex_calltf() function the Value column will display thecurrent values of individual variables. The Watch tab displaying added variables is shown above.

After you have reached the end of the debugging process, you may want to finish the session.

14. To close the debugging session, choose End Simulation from the Simulation menu or typein the endsim command in the Console window.

NOTE: Closing the VSimSA command prompt window does not terminate the debugger and it isnot allowed during the debugging session.

Compiling C/C++ Source Code

The hex2bin_bde sample design delivers the read_byte_ex.c source file and the pre-compiledread_byte_ex.dll library that just has been debugged. All the files are stored in the \externalsubfolder.

However, if you wanted to modify this PLI application or debug another DLL you would need to(re)compile a C/C++ source file. Active-HDL also provides an interface to the Gcc compiler thatcan be used to build user-defined VHPI/PLI applications.

Before you compile any C/C++ source code, you need to specify a configuration file for yourapplication. This configuration is stored in a DLM file that contains information on sources tocompile along with include files and all required libraries, compiler and linker options. Thehex2bin_bde sample design delivers the pre-defined configuration file.

15. Expand the \external subfolder.

16. Double-click the read_byte_ex.dlm file. It opens the C/C++ Configuration window (if youwould like to create a new configuration file, choose C/C++ Configuration from the File | Newmenu.

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In the C/C++ Configuration window, you can specify the name for the configuration file (DLM),your application (DLL), specify sources to be compiled including all required libraries, compiler,and linker options. When these options are specified, click Save to apply the changes. The DLMfile is updated or, if you have just started creating a new configuration file, it is attached to thedesign tree as it is shown in the figure below.

17. To (re)compile the application click the DLM file with the right-mouse button and chooseBuild from the context menu. This option starts the compilation of sources files specified in theFiles pane of the C/C++ Configuration window. When the compilation is completed, the DLL fileis updated or, if you have just started creating a new application, it is attached to the design tree.

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Using Design Profiler

Introduction

The design profiler included in Active-HDL allows to identify the portions of the design whichconsume most CPU power during simulation. Such information may give a valuable insight onhow to reduce verification time. The profiler is built into the simulation kernel. The profilingprocess is completely non-intrusive.

This document shows how to collect profiling data and how to identify portions of the design thatare most expensive in terms of simulation time. Replacing a unit which puts a heavy strain on thesimulator with another functionally equivalent implementation may result in a considerableperformance improvement. If the design is run against many testbenches, the verification timecan be considerably reduced.

NOTES:

· The machine on which you run the design profiler should not be performing any othercomputationally intensive tasks.

· You may expect slight variations in the profiling results each time you run the samesimulation. This is inevitable in the profiling process.

Collecting profiler data

To collect toggle coverage data for the project do the following:

1. Open the profiler_example workspace. The workspace contains two designs: modulator andprofiler_example.

2. Load the runme_0.do macro in the HDL Editor and review its contents. The macro compilesdesign source files and then initializes and runs simulation. Note that the simulator is invoked withthe following command:

asim -profiler -tbp_dest $DSN/profiler_0 -profiler_hierarchy -profiler_all modulator_0

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The -profiler switch enables profiling during simulation. The profiler will run in the hierarchicalmode (-profiler_hierarchy). Profiling data will be saved to the profiler_0 subdirectory (-tbp_dest $DSN/profiler_0).

3. When the simulation is complete, the macro starts the Profiler Viewer that shows the profilingdata collected during simulation. The Profiler Viewer shows a design tree and several columnswith profiling data. (Columns can be turned on or off by right-clicking on the column title andselecting column names from the pop-up menu.)

4. Focus on the Share with children and Time with children columns. The columns show howmuch CPU time each unit (and its subcomponents) occupied during simulation. The root level ofthe design shows statistics for the whole design. The total time (i.e. 100% share) is 69 362.44time units.

The multiplier_00 unit, one level below root, accounts for more than 70% of CPU usage duringsimulation. Accelerating this unit will have the largest impact on performance increase.

5. Click on the U3 unit in the design tree. The Profiler Viewer will display the source file formultiplier_00.

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The multiplier_00 unit was compiled from the muliplier_00.vhd file. The implementation is fullysynthesizable and consists of a number of adders and other basic components.

In the next section multiplier_00 will be replaced with another, faster implementation.

Running the design with a modified multiplier

In this section you will run the design again with a modified version of the multiplier. Themultiplier, previously compiled from the muliplier_00.vhd file will be replaced by a simplerimplementation that can be simulated much faster:

architecture multi_arch of multiplier_01 is

begin

Q <= A * B;

end multi_arch;

To see how the new multiplier impacts the performance of the simulator, do the following:

1. Select the runme_1.do macro in the Files tab on the Design Browser. Right-click on the fileand choose Execute from the pop-up menu. The macro will compile required files, initialize andrun simulation and then display profiling data in the Profiler Viewer. The profiling data will besaved to a different directory so that results generated in the previous run are not be overwritten.

2. Compare the total number of CPU ticks or the number of microseconds in the currentsimulation with the numbers obtained in the previous simulation run.

The profiling data shows that the total simulation time was reduced more than four times. Themultiplier unit required less than 1.5 mln CPU ticks compared to well over 40 mln in the previousimplementation. It now accounts for less than 10% of the total simulation time.

Optimizing the write process

The design includes two additional macros that run two other versions of the design. Therunme_2.do macro uses modulator_1 instead of modulator_2.

The modulator_2 contains an additional process that writes data to a file. The process is shownbelow in the Advanced Dataflow window. The profiling data is displayed below the dataflowview.

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The runme_3.do macro uses modulator_3 instead of modulator_2. The modulator_3architecture contains an optimized write process. The sensitivity list has been reduced to onesignal only: Q_int. After running the runme_3.do macro you can check the effect of theoptimization. The time the simulator needed to simulate the process was reduced by as much as80%.

Conclusion

The design profiler can be used to make simulations run faster. Optimizing the design or the datadumping routines can yield manifold performance improvements. This can be a critical factor inan efficient verification process.

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Using Toggle Coverage

Introduction

Toggle coverage reports describe design activity in terms of changes in signal values. Togglecoverage reports can identify a variety of issues in the design and the testbench, for example:

· Identify signals which were not initialized

· Locate areas of the design which are not properly tested by the testbench

· Measure power usage

This document shows how to collect toggle coverage statistics for the v_bjack project and how tocorrelate toggle coverage with code coverage.

Collecting toggle coverage data

To collect toggle coverage data for the v_bjack project do the following:

1. Start Active-HDL and open the v_bjack workspace. The v_bjack workspace is located in theActive-HDL\Samples\Verilog_Designs branch.

2. Compile all source files. Source files should be compiled in the following order: Gates.v,Bin2bcd.v, Bcd2led.v, Bjack_c.v (this file should be generated from Bjack_c.asf), Gen.v,Johnson8.v, Mux.v, V_bjack.v and Tb.v.

This can be done either in the GUI or with the following command:

alog -dbg $DSN\src\Gates.v $DSN\src\Bin2bcd.v $DSN\src\Bcd2led.v$DSN\src\Bjack_c.v $DSN\src\Gen.v $DSN\src\Johnson8.v $DSN\src\Mux.v$DSN\src\V_bjack.v $DSN\src\Tb.v

3. Locate the Tb.v file on the Files tab, select the V_Bjack_tb top-level module icon below andselect Set as Top-Level from the pop-up menu.

4. Select Initialize Simulation from the Simulation menu. Active-HDL will load the design.

5. The toggle coverage engine can be controlled from the command-line with simple macrocommands. To initialize toggle coverage for the v_bjack project, use the following command:

toggle -xml v_bjack.xml -toggle_type full -type -rec UUT/*

The command specifies that data for the toggle coverage report should be collected from allsignals in the UUT region and all its subregions (-rec UUT/*). Information about signal typeswill be included in the report (-type).

The toggle report will be created in the full mode (-toggle_type full). In the full mode, thereport shows if both a rising and a falling edge occurred on monitored signals.

The report format will be saved to the v_bjack.xml file (-xml v_bjack.xml).

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6. To run simulation, select the Run command from the Simulation menu. The simulator will runsimulation until there are no more events to process. When simulation finishes, select the EndSimulation command from the Simulation menu. Toggle coverage report will be savedautomatically to the toggle subdirectory.

7. You can display the XML report in any browser supporting XML, as shown in the picture below.

8. Starting with Active-HDL 6.2, toggle coverage data can be viewed in a dedicated ToggleCoverage Viewer. The functionality of the Toggle Coverage Viewer is much enhanced over aregular browser.

To start the toggle coverage report in the Toggle Coverage Viewer, select Toggle Coveragefrom the View menu. A stand-alone Toggle Coverage Viewer window will be displayed.

9. Select the Open command from the File menu, go to the toggle subdirectory and open thev_bjack.xml report.

The Filter button and the neighboring combo box allow to filter out signals depending onwhether they toggled during simulation.

10. By default the Toggle Coverage Viewer displays all signals in a flat view. To group signals

by the hierarchy region, click the Show/hide hierarchy browser button on the toolbar.

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Correlating code coverage data with toggle coverage data

If you want to verify how well your design was exercised by the testbench, you may confront codecoverage results with toggle coverage results. The code coverage viewer shows how many timeseach HDL statement executed during simulation. Code coverage data for the v_bjack project isshown below. (For details on using code coverage consult Active-HDL documentation.)

The Code Coverage Viewer shows statistics for a Johnson counter located in the UUT/I17region. All executable statements defining the counter were executed at least once.

Toggle coverage data for the same region is displayed below.

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Toggle coverage reveals that several signals in the examined region (e.g. the tmp register) didnot toggle.

The example shows that combining toggle coverage with code coverage can provide the mostcomprehensive information about how well the design was exercised by the testbench.

183

Co-simulating VHDL and System-C

Introduction

Active-HDL allows to simulate designs containing units implemented in SystemC. Active-HDLprovides all necessary tools including:

· C/C++ build environment

· SystemC 2.0.1 installation and pre-compiled SystemC libraries. (The Systemc.a libraryfor the gcc compiler and a SystemC.lib library for the Visual Studio compiler.)

The C:\My_Designs folder contains a systemc_frequency_meter_vhdl design. The design hastwo versions:

· VHDL-only version

· Mixed VHDL-SystemC version

You will simulate both versions of the design and compare the output waveform files using theCompare Waveforms command from the Waveform menu.

Simulating VHDL-only version of the design

1. Select the Open Workspace/Design Explorer command from the File menu, locate thesystemc_frequency_meter_vhdl design and double click on its icon. The design will be loadedin Active-HDL.

2. Double-click on the hdl_simulation.do macro file in the Design Browser. The macro will beloaded in the HDL Editor:

The macro compiles VHDL files, initializes simulation, adds selected signals to the WaveformEditor and runs simulation.

3. Click the Execute Script button on the toolbar. The macro will run the simulation process.

4. Save the waveform file as hdl_simulation.awf and close the Waveform Editor window.

5. Make sure that the Structure Tab in the Design Browser is selected and expand the /UUT/U1branch:

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The /UUT/U1 unit contains four instances of the CNT_4B 4-bit counter modeled in VHDL in thecnt_4b.vhd file. In the next stage all instances of the VHDL counter will be replaced by a countermodelled in SystemC.

Simulating mixed VHDL-SystemC version of the design

1. Click the Files tab in the Design Browser, locate the systemc_cosimulation.do macro, right-click and select Execute from the pop-up menu. The macro will first recompile all design units.Note that the systemc_cnt_4b.vhd file will be compiled instead of the cnt_4b.vhd file that wasused in the VHDL-only simulation. The systemc_cnt_4b.vhd file is a wrapper for a CNT_4B 4-bitcounter implemented in SystemC.

After compilation the macro will initialize simulation, add selected signals to the Waveform Editorand run simulation.

2. Save the waveform file displayed in the Waveform Editor window assystemc_cosimulation.awf.

3. Select Compare Waveforms from the Waveform menu and compare thesystemc_cosimulation.awf file with the hdl_simulation.awf created in the HDL only simulationdescribed in the previous section.

Waveform comparison will not detect any differences. This indicates that VHDL and SystemCimplementations of the counter are equivalent.

4. Click the Structure Tab in the Design Browser and expand the /UUT/U1 branch.

Note that the previously used cnt_4b architecture of the cnt_4b entity has been replaced by thesystemc architecture.

5. Select any instance of the cnt_4b unit, right-click and select Implementation from the pop-upmenu. The source file will be displayed:

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The SystemC module is instantiated in VHDL as a foreign VHDL architecture:

attribute foreign of systemc : architecture is"VHPI $DSN\src\systemc\sc_cnt_4b.dll; sc_counter_inst";

The SystemC unit will be read from the sc_cnt_4b.dll library located in the src\systemcsubdirectory.

The sc_cnt_4b.dll library

The SystemC-based model of the counter is loaded during the initialization of simulation from thevhpi_for_ahdl.dll library. The systemc_frequency_meter_vhdl design contains a pre-compiledversion of this library. Build settings are stored in the vhpi_for_ahdl.dlm file.

To review compilation settings, locate the vhpi_for_ahdl.dlm file in the systemc subdirectory,right-click and select open from the pop-up menu. The C/C++ Configuration dialog box will bedisplayed.

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Note that the Systemc.a library is included in the list of libraries to be linked with the target VHPIlibrary. The names of source files are specified using the $DSN variable. The variable points tothe design directory.

To re-build the vhpi_for_ahdl.dll library, select the file in the sc_cnt_4b.dlm file in the DesignBrowser, right-click and select Build from the pop-up menu. The library will be built in thesystemc subdirectory.

The library is built from two source files:

· The sc_interface.cpp file defines the interface between SystemC units and the VHDLcode

· The sc_counter.cpp file contains the implementation of the counter in SystemC. Thecounter behavior is described in counter::behavior().

void counter::behavior(){

if (Reset){

// Set counter contents to 0Full=0; // FULL Flag to 0countval=0;

}else // active clock edge if rising edge of Clock 0->1{

if (Enable) // and enable equals 1{

if (countval == 9) // if COUNT=9countval=0;

elsecountval++;

}}Q=countval;Full=(countval == 9) ? 1 : 0; //FULL =1 when COUNT == 9 otherwise 0

}

187

Co-simulating Verilog and System-C

Introduction

Active-HDL allows to simulate designs containing units implemented in SystemC. Active-HDLprovides all necessary tools including:

· C/C++ build environment

· SystemC 2.0.1 installation and pre-compiled SystemC libraries. (The Systemc.a libraryfor the gcc compiler and a SystemC.lib library for the Visual Studio compiler.)

The C:\My_Designs folder contains a systemc_frequency_meter_verilog design. The designhas two versions:

· Verilog-only version

· Mixed Verilog-SystemC version

You will simulate both versions of the design and compare the output waveform files using theCompare Waveforms command from the Waveform menu.

Simulating Verilog-only version of the design

1. Select the Open Workspace/Design Explorer command from the File menu, locate thesystemc_frequency_meter_verilog design and double click on its icon. The design will beloaded in Active-HDL.

2. Double-click on the hdl_simulation.do macro file in the Design Browser. The macro will beloaded in the HDL Editor:

The macro compiles Verilog files, initializes simulation, adds selected signals to the WaveformEditor and runs simulation.

3. Click the Execute Script button on the toolbar. The macro will run the simulation process.

4. Save the waveform file as hdl_simulation.awf and close the Waveform Editor window.

5. Make sure that the Structure Tab in the Design Browser is selected and expand the /UUT/U1branch:

Application Notes

188

The /UUT/U1 unit contains an instance of the CNT_10B four bit counter modeled in Verilog in thecnt_10b.v file. In the next stage the Verilog counter will be replaced by a counter modelled inSystemC.

Simulating mixed Verilog-SystemC version of the design

1. Click the Files tab in the Design Browser, expand the SystemC subdirectory and select thecnt_10b.dlm file. The .dlm file contains build configuration for the PLI library that will be used inthe simulation process.

Right click on the cnt_10b.dlm file and select Build from the pop-up menu. Active-HDL will launchthe build process. The .dll library will be built in the systemc subdirectory. The output of thecompiler will be shown in the Active-HDL console.

2. Click the Files tab in the Design Browser, locate the systemc_cosimulation.do macro, right-click and select Execute from the pop-up menu. The macro will first recompile all design units.Note that the systemc_cnt_10b.v file will be compiled instead of the CNT_10b.v file that was usedin the Verilog-only simulation. The systemc_cnt_10b.v file is a wrapper for the CNT_4B 4-bitcounter implemented in SystemC. After compilation the macro will initialize simulation, addselected signals to the Waveform Editor and run simulation.

3. Save the waveform file displayed in the Waveform Editor window assystemc_cosimulation.awf.

4. Select Compare Waveforms from the Waveform menu and compare thesystemc_cosimulation.awf file with the hdl_simulation.awf created in the HDL only simulationdescribed in the previous section.

Waveform comparison will not detect any differences. This indicates that Verilog and SystemCimplementations of the counter are equivalent.

5. Click the Structure Tab in the Design Browser and expand the /UUT/U1 branch.

Co-simulating Verilog and System-C

189

Note that the previously used CNT_10B counter with one always block and two assignstatements has been replaced by the CNT_10B wrapper with just one initial block.

6. Select the CNT_10B unit in the UUT/U1 branch, right-click and select Implementation fromthe pop-up menu. The source file will be displayed:

The SystemC module is instantiated in Verilog as a task called from the initial block:

initial$sc_counter(CLK,RESET,ENABLE,FULL,COUNT);

The sc_cnt_4b.dll library

The simulator loads the $sc_counter task from the sc_cnt_4b.dll library located in thesrc\systemc subdirectory. All build settings are stored in the cnt_10b.dlm file. To review thesettings, select the file, right-click and select open from the pop-up menu. The C/C++Configuration dialog box will be displayed.

Application Notes

190

Note that the Systemc.a library is included in the list of libraries to be linked with the target PLIlibrary. The names of source files are specified using the $DSN variable. (The variable points tothe design directory.)

When simulation is initialized, the name of the PLI library containing the implementation of thecounter must be specified on the command line with the -pli cnt_10b.dll switch. The -pliswitch specifies that the simulator should look for unknown tasks (i.e. the $sc_counter task) inthe the cnt_10b.dll library.

The library is built from two source files:

· The sc_interface.c file defines the interface between SystemC units and the Verilog code

· The sc_counter.cpp file contains the implementation of the counter in SystemC. Thecounter behavior is described in counter::behavior().

void counter::behavior(){

if (Reset){

// Set counter contents to 0Full=0; // FULL Flag to 0countval=0;

}else // active clock edge if rising edge of Clock 0->1{

if (Enable) // and enable equals 1{

if (countval == 0x3ff) // if COUNT_I == 10'b1111111111countval=0;

elsecountval++;

}}Q=countval;Full=(countval == 0x3ff) ? 1 : 0; //FULL =1 when COUNT_I ==

10'b1111111111 otherwise 0}

191

Index

A

Active-HDL Application Notes ..1, 15, 27, 37,45, 54, 61, 71, 77, 85, 91, 99, 107, 133,141, 149, 157, 167

B

BASIC Scripting Capabilities ApplicationNote........................................................54

Building and Debugging Handel-C Projects(Application Note).................................115

Building PLI Applications (Application Note).............................................................149

Building VHPI Applications (ApplicationNote) ....................................................157

C

Celoxica (Using Celoxica FlowchartApplication Note)..................................133

compiling Handel-C projects (ApplicationNote) ....................................................115

compiling PLI applications (Application Note).............................................................149

compiling VHPI applications (ApplicationNote) ....................................................157

Co-simulating Verilog and System-C(Application Note).................................187

Co-simulating VHDL and System-C(Application Note).................................183

Creating FPGA and CPLD DesignsApplication Note .....................................71

D

Debugging C Code Application Note.......167

debugging Handel-C projects (ApplicationNote) ....................................................115

Design Entry Overview Application Note...15

Design Management Overview ApplicationNote........................................................27

Design Profiler (Using Design ProfilerApplication Note) ................................. 175

G

Glitches and Delta Cycle HandlingApplication Note .................................... 99

H

Handling Libraries in VHDL Verilog andEDIF Application Note........................... 37

How to Simulate Designs Application Note............................................................... 77

P

PLI (compiling PLI applications) ............. 149

Profiler (Using Design Profiler ApplicationNote).................................................... 175

S

Simulator Overview Application Note ....... 45

Starting Active-HDL Application Note ......... 1

T

Tcl/Tk Scripting Application Note.............. 61

TestBencher Pro(TM) (Using TestBencherwith Active-HDL Application Note) ...... 141

Toggle Coverage (Using Toggle CoverageApplication Note) ................................. 179

U

Using Celoxica Flowchart Application Note............................................................. 133

Using Stimulators Application Note .......... 85

Using TestBencher Pro(TM) with Active-HDL Application Note.......................... 141

V

VHDL Debugging Application Note......... 107

VHDL Testbench Application Note ........... 91

VHPI (compiling VHPI applications) ....... 157

Documents

Application Notes