Analysis of PCFICH Channel Architecture for LTE

Analysis of PCFICH Channel Architecture for LTE using Unfolding Technique

S.Syed Ameer Abbas Assistant Professor, Department of ECE

Mepco Schlenk Engineering College Sivakasi, India

[email protected]

R.Lakshumi Praba PG Student, Department of ECE

Mepco Schlenk Engineering College Sivakasi, India

[email protected]

S.J.Thiruvengadam Professor, Department of ECE

Thiagarajar College of Engineering Madurai, India [email protected]

Abstract— Realization of transmitter and Receiver architecture for LTE is the major research work being carried out by implementation experts. There are four Control channels available in LTE for both uplink and downlink. The uplink control channel is PUCCH. The downlink control channels are PDCCH,PCFICH and PHICH. The Physical Control Format Indicator Channel(PCFICH) is one among the downlink physical control channel and it carries the number of OFDM symbols used by the PDCCH channel, denoted as Control Format Indicator(CFI).These control channels play a key role in the correct decoding of the payload information. The CFI is the first information received by the User and so is important for the system performance. In this paper, the realization of architecture for the PCFICH are done using FPGA, and the VLSI DSP technique called unfolding is applied for optimization. The simulations are done using Modelsim and are implemented in Xilinx Spartan 3E kit.

Keywords- LTE; FPGA; CFI;Unfolding

I. INTRODUCTION Long Term Evolution (LTE) is a Fourth generation wireless

broadband technology, which is capable of providing high peak data rates (100 Mbps downlink and 50 Mbps uplink),multi antenna support, reduced cost, wide range of bandwidth(from 1.4 MHZ upto 20 MHZ),backward compatibility with existing 2G and 3G networks, increased spectrum efficiency and peak data rates at cell edges[1-3]. All these criteria are satisfied by the efficient usage of the control channels. The LTE physical layer is a highly efficient means of conveying both data and control information between an enhanced base station(e-Node B) and mobile user equipment(UE). The LTE physical layer uses OFDM as the access technology, QAM as the modulation scheme and MIMO concepts. LTE differs from its predecessors by using OFDM along with MIMO antennas. OFDM is selected ,owing to its suitability for MIMO transmission and reception, resistance of its symbol structure to multi path delay spread, no need of equalization etc[4].

The downlink physical channels correspond to a set of resource elements carrying information originating from the higher layers. There are six physical downlink channels available namely, Physical Downlink Shared Channel (PDSCH), Physical Broadcast Channel(PBCH), Physical Multicast Channel (PMCH), Physical Control Format Indicator Channel (PCFICH), Physical Downlink Control Channel (PDCCH), Physical Hybrid ARQ Indicator Channel(PHICH)[1].The first three channels are the data channels. The PDSCH carries the payload and PBCH broadcast the cell specific information. The PMCH is used for broadcasting and multicasting information from multiple cells. The latter three channels are the control channels, where PDCCH is the main control channel carrying the downlink scheduling assignments and the uplink scheduling grants. The PCFICH carries the control Format Indicator(CFI), which provides the number of OFDM symbols used by the PDCCH channel. The PHICH carries the hybrid –ARQ ACK/NACK Indicator(HI). The downlink physical signals are Reference signal and the Synchronization signal. The reference signals are of three types namely Cell Specific reference signals, MBSFN reference signals, UE-specific reference signals. The synchronization signals are primary synchronization signal and secondary synchronization signal and they provide the

Figure 1. Type I (FDD) frame structure.

.................................... 0 21 3 18 19

One sub frame

One slot Tslot=0.5ms

One radio frame Tf=10ms

Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

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information of physical layer cell identity, which ranges from 0 to 503[1].

LTE supports both Time Division (TDD) and Frequency Division Duplexing (FDD). In this paper FDD is adopted. The frame structure for FDD used in this realization is shown in Fig.1. Each downlink frame lasts for 10 ms and consists of 10 sub frames. Each sub frame consists of 2 slots. Each slot consists of seven OFDM symbols [1]. LTE specification provides capacity enhancing features such as link adaptation, Hybrid Automatic Repeat Request(H- ARQ) etc. So, control channel design and structure plays a lead role in the correct detection and interpretation of the payload information[4].

The objective of this paper is to propose transmitter and receiver architecture for PCFICH channel and to implement the architectures using FPGA. The proposed architectures is optimized using VLSI DSP techniques of folding to increase the speed and to decrease the power consumption.

The rest of the paper is organized as follows. In Section II,

a brief discussion of PCFICH channel is done, followed by block diagram and modelling of the transmitter and receiver architecture is done. Section III deals with the unfolding technique. In Section IV, assumptions are provided and the architectures for the PCFICH transmitter and receiver are proposed. Section V, provides the results and discussion. Section VI, contains some concluding remarks.

II. PHYSICAL CONTROL FORMAT INDICATOR CHANNEL The PCFICH carries the information of number of OFDM

symbols used by the PDCCH to carry the scheduling assignments and other control information. The information carried by the PCFICH is called as Control Format Indicator (CFI) and is located in the first OFDM symbol of each subframe. The CFI can take the values of 1,2,3 and 4(Reserved) and are represented using two bits. For bandwidths greater than ten resource blocks, number of OFDM

Figure 2. Block Diagram.

symbols used to contain the downlink control information is the same as the actual CFI value. Otherwise span of the downlink control information is CFI+1 symbols. The exact position of CFI in the resource grid is based on the bandwidth and physical layer cell identity. The CFI is the first information received by the User equipment and so the overall performance depends on the correctness of CFI detection.

A. PCFICH Transmitter 1) Block Coding: The original CFI value to be transmitted

is first represented in two bit format R1,R0 (01-->1,10-->2,11-->3).The CFI is first encoded using a (32,2) block code, as shown in TABLE I. The dmin between the code words is 21. In order to ensure high robustness, PCFICH use this type of encoding.

2) Scrambling: The 32 bit code words are bit wise XOR ed with a cell specific scrambling sequence, which is a pseudo random sequence generated using a length 31 gold sequence generator. The cell specific sequence is used for the purpose of inter-cell interference rejection. When a UE descrambles a received bit stream with a known cell specific scrambling sequence, interference from other cells will be descrambled incorrectly and will only appear as uncorrelated noise. The scrambling is done using

( )( ) ( ) ( ) ( ) ( )( ) 2mod

~icibib qq

q

+= (1)

Where q represents the codeword, c is the gold sequence used, b is the encoded sequence. The gold sequence is generated using the formula

2mod))(1)3(1()31(1 nxnxnx ++=+ (2)

2mod))(2)1(2)2(2)3(2()31(2 nxnxnxnxnx ++++++=+ (3)

2mod))(2)(1()( nxnxnc += (4) 3) Modulation: The scrambled sequence is then QPSK

modulated to create a block of modulated symbols. The scrambled bits are stored in a shift register and first two bits are given as control lines for the multiplexer. Based upon the control, the corresponding modulated symbols, stored in RAM table appear as output.In QPSK modulation pairs of bits are mapped to complex valued modulaed symbols I+jQ and hence

TABLE I CFI (32,2) Block Code

CFI CFI codeword < b0, b1, …, b31 >

1 <0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1>

2 <1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0>

3 <1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1>

4 (Reserved) <0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0>

Block Coding Scrambling QPSK Modulation

Layer MappingPre coding Mapping to RE

Channel

ML Detection

CFI

CFI

Demapping from RE

Decoding

Delayer mapping

Transmitter

Receiver


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Figure 3. Mapping to Resource Elements.

the 32 bits are converted to 16 complex modulated symbols. The outputs are represented by 16 bit numbers.

4) Mapping To Resource Elements: The control channels’

modulated symbols are mapped to the resource element groups(REG), and PCFICH is mapped only in the first OFDM symbol of each subframe and are transmitted through the channel. In order to obtain the largest possible frequency diversity gain, the 16 symbols are distributed in four REGs, evenly distributed in six resource blocks (LTE minimum bandwidth 1.4 MHz support 6 resource blocks),as shown in Fig. 3.

5) Channel Estimation and Noise addition: To model the channel, the modulated output is element by element multiplied with the channel estimation vector, which is represented as a 16 bit 16X1 vector. The resultant is a 32 bit 16X1 vector. Then the noise, which is represented as a 16 bit 16X1 noise vector is added .The resultant is a 32 bit 16X1 vector, which also denotes the received subcarrier vector at the antennas in the receiver side. The transmitter architecture is presented in Fig. 3.

B. PCFICH Receiver 1) Received Signal: In the receiver side, after removal of

cyclic prefix from the received signal, then FFT is performed and then resource element de mapping is done. The complex valued output at the k -th receive antenna is modelled in eqn.(5)

( ) ,kn

kk udhy +°= Kk ,,2,1 …= (5)

ky is 16x1 received subcarrier vector, ( )nd is the 16x1 complex QPSK symbol vector corresponding to the 32- bit CFI code words, where n varies from 1 to 3, kh is 16x1 complex channel frequency response and ku represents the contribution of thermal noise and interference. The received signal ky is represented in the figure 2,for single antenna case. The noise term ku is modelled as zero mean circularly symmetric complex Gaussian with covariance

[ ] IuuE uHkk

2σ= , since the interferers are uncorrelated due to independent large scale propagation, short term fading and uncorrelated scrambling sequences.

2) CFI Estimation: The ML decision rule, by maximizing the log-likelihood function of ky given kh is given in eqn(6)

( )( )2

13,2,1

min ∑=

=°−=

K

k

mkkm

dhyCFI (6)

which simplifies to

( )m

mzCFI

3,2,1maxarg

== (7)

Where the soft outputs are given by

( ) ( )∑=

=K

k

mk

m zz1

for m=1,2,3. (8)

Which is simplified as

( ){ }∑==

°=K

k

mkk

mdhyCFI

1

*

3,2,1,Remaxarg (9)

The received signal ky is element by element multiplied with the conjugate of the complex channel frequency response vector *

kh .Then this term and three possible values of ( )md undergoes inner product. The inner product is given by

*

1

, i

N

ii yxyx ∑

=

= .The real part of the resultant value is taken.

This is done for number of times as the number of antennas used to receive. Then argument max among the three values is selected as the CFI value. If CFI is maximum value when m=1, then the codeword detected is 01, when m=2, it is 10 and when m=3, it is 11.

III. UNFOLDING Unfolding is a VLSI DSP technique that can be applied to a DSP program to create a new program describing more than one iteration of the original program. Unfolding by the factor J creates a new program that describes J consecutive iterations of the original program. This is also known as Loop Unrolling and has been used in compiler theory. It has applications in designing high speed and low power VLSI architectures. The hidden concurrencies in the processing can be unraveled by using Unfolding.

A. Unfolding Algorithm 1.For each node U in the original Data Flow Graph(DFG),

draw the J nodes U0, U1,... UJ-1. 2.For each edge U-->V with w delays in the original DFG,

draw the J edges Ui-->V(i+w)%J with ⎥⎦

⎥⎢⎣

⎢ +jwi delays for

i=0,1,...,J-1.

B. Properties of Unfolding Property 1: Unfolding preserves the number of delays in a DFG.

Property 2: Unfolding a loop l with w1 delays in the original DFG leads to gcd(w1,J)loops in the unfolded DFG , and each of these gcd(w1,J) loops contains w1/gcd(w1,J) delays and J/gcd(w1,J) copies of each node that appears in l.

Property 3: Unfolding of a DFG with iteration bound T ∞ results in a J-unfolded DFG with iteration bound JT ∞ .

Frequencytim


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Figure 4.CFI Estimation .

Figure 5. CFI Estimation using unfolding J=2 .

Property 4: Unfolding preserves the precedence constraints of a DSP program.

The data flow graph for CFI estimation is shown partially in Figure.3.From the output, the real part is extracted and argument maximum is taken among the three outputs. The unfolding by a factor of J=2 is applied for Figure. 3 and the resultant DFG is shown in Figure.5.By using unfolding algorithm, 3 nodes in Figure.4 are converted to 6 nodes in Figure.5.In Figure.4, the branch with 16 delays is converted into two branches with 8 delays each in Figure.5, by application of unfolding algorithm (eg: U0 V0 with floor((0+16)/2)=8delays ).Unfolding an edge with w delays where w<J produces J-w edges with no delays and w edges with 1 delay.(eg:1<2 implies 1 edge with 0D and 1 edge with 1D). Thus we get output with 9 unit delay by applying J=2 unfolding.

Thus we get output with 9 unit delay by applying J=2 unfolding.Similarly, unfolding by a factor of 4 (J=4) is also done using 12 nodes. The 16D branch is converted into 4 branches each with 4D and so we get 2 outputs at 4 time units and the other 2 outputs are produced at 5 unit time. So, at 5 unit time we are getting all the outputs. Unfolding by higher factors increase the speed of the process, which also maintains the number of delay elements. Unfolding also helps in obtaining low power architectures.

IV. PROPOSED ARCHITECTURE FOR PCFICH TRANSMITTER AND RECEIVER

TABLE II Assumptions

Parameter Assumption Channel Bandwidth (MHz) 1.4 Number of Physical Resource Blocks 6 Sampling Frequency(Msps) 1.92 Number of occupied subcarriers 73

Cyclic Prefix Normal Number of OFDM symbols per sub frame

14 (7 in each slot)

Frame Structure Type I(FDD) CFI(bits) 2 Gold Sequence(bits) 32 dmin between CFI code words (bits) 21 Modulated Symbol(bits) 16 Channel Rayleigh fading channel frequency response vector(hk) 16 bit 16X1 vector Conjugate of channel frequency response vector(hk

*) 16 bit 16X1 vector

Noise vector(uk) 16 bit 16X1 vector

A. Transmitter Architecture The transmitter architecture is presented in Figure.6.The

transmitter architecture consists of Block Coding, Scrambling and Modulation and layer mapping. The input is the 2 bit CFI value R1, R0.The 2 bit value is converted to 32 bit value by block coding. The first two bits are same as the original bits and the third bit is the XOR value of the first two bits. The 3 bit pattern is repeated until the required 32 bits are obtained. These 32 bits form the CFI codeword. For scrambling process,

Figure 6.PCFICH Transmitter Architecture upto Layermapping .

Yk(n)

h*k(n)

d(m)(n)

16D 1D

1D

Yk(2k)

h*k(2k)

d(m)(2k)

8D 0D

1D

Yk(2k+1)

h*k(2k+1)

d(m)(2k+1)

8D 1D

0D

yk

15 14 ……... 1 0 31 30 ……... 1 0+

31 30 ……... 1 0

Channel estimation hk

X1 X2R1 R0

0

1

2

….

…..

29

30

31

0

1

2

3

31

0

1

2

3

31

2121 j−

2121 j−−

2121 j+−

2121 j+

0

1

14

15

..

..

0

1

14

15

..

..

31 30 ………. 0 1

Layer mapping

16 QPSK sym.

00-1ant

01-2ant

10-4ant

Z1

Z2,Z3

Z4,Z5,Z6,Z7

MUX


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gold sequence generation is needed. The gold sequence is produced by using the 2 sequences X1 and X2.The X1 sequence is a predefined sequence, which is “1000000000000000000000000000000”. The 31 bits of X2 sequence is assumed, since it varies according to the applications. The 32nd bit of both the sequences are calculated using the formula in section II. Then these 2 sequences are XOR ed to get the gold sequence, which is also a 32 bit value. Then scrambling is done by XOR of the block coded sequence and the gold sequence. The resultant scrambled sequence is stored in a shift register. The shift register is set to shift 2 bits per clock cycle for QPSK modulation. The shifted 2 bits are given as control lines for the multiplexer. The inputs to the multiplexer are stored in RAM table. The 4 possible complex modulated QPSK symbols are shown in figure. Based on the control, the output appears, which is represented as 16 bit value.

The 16 complex modulated symbols are then layer mapped to one, two or four layers based on the information from higher layer.Z1 is the output if one antenna is selected.Z2,Z3 are outputs if 2 antennas are selected and Z4,Z5,Z6,Z7 if 4 antennas are selected. The modulated symbol is multiplied with the complex channel frequency response vector hk, which is also represented as a 16 bit value. The resultant is a 32 bit value. Then noise which is represented using 16 bits is added. Thus the resultant signal yk is a 32 bit value.

B. Receiver Architecture The received signal is demapped from the 16 positions of

first OFDM symbol, where CFI value is available. The receiver architecture is presented in Figure.7. It is known that, there are only three possibilities of signal transmitted, namely 01,10 or 11(CFI-1,2 or 3).So, the demodulated signal will be one among the three. The received signal is yk and is multiplied with the conjugate of the complex channel frequency response vector hk

*,element by element. Then this resultant term undergoes inner product with the three possible values of d(m). The inner product is done using the formula in section II. The d(m)* is multiplied with (yk

o hk*) product .For all

the elements the multiplication is done and the results are accumulated, and the result is a 64 bit value. The real part of the accumulated value alone is taken, which is a 32 bit value. This process is done for the three values viz. d(0),d(1), d(2).Then among the three results, the codeword which has the maximum argument value is detected as the CFI.

V. RESULTS AND DISCUSSION The simulation results and the device utilization summary,

assuming that the channel response is known are presented in this section. The simulation results for the unfolding by factor of J=2 and J=4 are presented here. Figure.8 provides the simulation output for transmitter. In fig.7,two bit CFI input is given. The block coding produces 32 bit output, which on scrambling produces 32 bit output. The modulated symbols are represented using 16 bits. From the synthesis report, the number of multipliers used is one, which is a 16x16-bit multiplier. The adders used are one 16-bit carry out adder and

Figure 7.PCFICH Receiver Architecture .

one 32-bit adder. The simulation for the CFI estimation is shown in the Figure. 9.The The input to the receiver is the 16x1vector. It takes three clock pulses to get the output From the synthesis report, 18 multipliers are used. Of them,14 are 16X16 multipliers,1is 32X16 and 3 are 48X16 multipliers.20 adder/subtractors are used.Table III gives the FPGA resource utilization summary for the transmitter architecture and the Table IV gives the FPGA resource utilization summary for the receiver architecture.

Figure.10 shows the simulation result for applying J=2 unfolding and the outputs are available at 800 ps compared to the 1600 ps for the original PCFICH receiver output.Figure.11 shows the simulation result for applying J=2 unfolding and the outputs are available at 400 ps itself.

ctrl

2121 j−

2121 j−−

2121 j+−

2121 j+

MAC Re|

0

1

14

15

..

..

0

1

30

31

..

..

31 30 ………. 01

CFI 2

CFI 3

CFI 1

o/p 1

o/p 2

o/p 3

Count no.of error bits and find minimum error output

01

10

11

CFI

hk*

0

1

14

15

..

..

yk

0

1

30

31

..

..

47 46 ……... 1 0

d(m)*

0

1

2

….

…..

29

30

31

R1 R0

0

1

2

3

31

0

1

2

3

31

16 symb.

{ } { }

z4,z5,z6,z7 z2,z3 z1DeLayer

Mapping


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Figure 8. Simulation for PCFICH transmitter

Figure 9. Simulation for PCFICH receiver

Figure 10. Simulation for unfolding J=2

Figure 11. Simulation for unfolding J=4

TABLE III FPGA RESOURCE UTILIZATION SUMMARY FOR PCFICH TRANSMITTER FOR

THE XILINX SPARTAN 3E ,3S500EFT256-4 DEVICE

TABLE IV FPGA RESOURCE UTILIZATION SUMMARY FOR PCFICH RECEIVER FOR THE

XILINX SPARTAN 3E ,3S500EFT256-4 DEVICE

VI. CONCLUSION The transmitter and receiver architectures for the PCFICH

channel are proposed in this paper. The signal to be transmitted is produced, passed through channel and noise is added. In the receiver side, the CFI is estimated by maximum likelihood method. The proposed architecture was optimized using Unfolding technique, and the speed is improved. The simulations are done and the device utilization are studied. The simulations are done using Modelsim. The synthesis are done using Xilinx 8.1i and implementation is done in Spartan 3E kit. The architectures can be further enhanced by using unfolding to reduce power consumption and retiming to reduce number of registers.

REFERENCES [1] 3GPP TS36.211,”Evolved Universal Terrestrial Radio Access(E-

UTRA);Physical Channels and Modlation(Release 8)”. [2] 3GPP TS36.212,”Evolved Universal Terrestrial Radio Access(E-

UTRA);Multiplexing and Channel Coding(Release 8)”. [3] 3GPP TS36.306,”Evolved Universal Terrestrial Radio Access(E-

UTRA);User Equipment radio access capabilities (Release 8)”. [4] Keshab K.Parhi “VLSI Digital Signal Processing Systems-Design and

Implementation”. [5] S. J. Thiruvengadam, Louay M. A. Jalloul, Performance Analyis of the

3GPP-LTE Physical Control Channels,” EURASIP Journal onWireless Communications and Networking,vol.2010,Article ID 914934, 10 pages,Nov.2010.

[6] R.Love, R.Kuchibhotla, A.Ghosh et al.,”Downlink control channel design for 3GPP LTE,” in proceedings of IEEE wireless communication and Networking Conference(WCNC’08),pp.813-818,Las Vegas, Nev, USA ,April 2008.

Number of Slices 494 /4656 (10% ) Number of Slice Flip Flops 322 / 9312 ( 3%) Number of 4 input LUTs 883 / 9312 (9% )

Number of MULT18X18SIOs 11 / 20 ( 55% ) Max.Frequency 33.047MHz

Delay(Min.period) 30.260ns Total memory usage 168372 kilobytes

Number of slices 582 / 4656 (12%) Number of Slice Flip Flops 616 /9312 ( 6% ) Number of 4 input LUTs 714 / 9312 (7% )

Max. Frequency 59.830MHz Delay(min. period) 16.714ns

Total memory usage 143284 kilobytes


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Analysis of PCFICH Channel Architecture for LTE