Analysis of DC/DC Boost Converters Design Methods Madelyn

Analysis of DC/DC Boost Converters Design Methods

with Filter Application

by

Madelyn Bailey Ulferts, BS. EE

A Thesis

In

Electrical Engineering

Submitted to the Graduate Faculty

of Texas Tech University in

Partial Fulfillment of

the Requirements for

the Degree of

MASTER OF SCIENCE

Approved

Dr. Stephan Bayne

Chair of Committee

Dr. Changzhi Li

Mark Sheridan

Dean of the Graduate School

December, 2015

Copyright 2015, Madelyn Bailey Ulferts

Texas Tech University, Madelyn Bailey Ulferts, December 2015

ii

ACKNOWLEDGMENTS

I would like to express strong appreciation for my thesis committee chair, Dr.

Stephan Bayne, who helped in the decision of the scope of this thesis. I would also

like to thank my committee member, Dr. Changzhi Li, who inspired my interest in

EMI creation, control, and effect by attending his Microwave Solid State Circuits and

Modern Radar Circuits and System classes. The outstanding professors and curriculum

at Texas Tech University’s Electrical Engineering department were curtail in

providing me with the knowledge and resources to create this thesis. It was the

departments’ professors’ and their passion for educating as well as their willingness to

give time to students that allowed me to expand my knowledge on the topics covered

in this thesis.

I also would like to take this opportunity to thank my parents, Mark and Karen

Ulferts and my older sister Katelyn. It was their work in the engineering field that

inspired me to become and engineer from an early age. My dad created in me the drive

and perseverance to complete this thesis as well as the Masters program at Texas Tech

University. My mom always set a leading example to which I followed. I am grateful

to have a sister one year ahead of me in the Electrical Engineering program and was

willing to guide me through the program.


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TABLE OF CONTENTS

ACKNOWLEDGMENTS .................................................................................... ii

ABSTRACT .......................................................................................................... vi

LIST OF TABLES .............................................................................................. vii

LIST OF FIGURES ........................................................................................... viii

I. INTRODUCTION ............................................................................................. 1

1.1 EMI in Switch Mode Power Systems .................................................... 1

1.1.1 EMC for SMPS ............................................................................. 2

1.2 Issues with SMPS .................................................................................. 4

1.3 Signals ................................................................................................... 4

1.3.1 High frequency operation .............................................................. 5

1.3.2 Common Mode and Differential Mode ......................................... 6 1.3.3 Victim line, aggressor, and coupling path ..................................... 7

1.4 Aim of this study .................................................................................... 8

II. SWITCH MODE POWER SYSTEMS .......................................................... 9

2.1 Topologies ............................................................................................. 9

2.2 Components ........................................................................................ 10

2.2.1 Passive elements .......................................................................... 10

2.3 Operation ............................................................................................ 11

2.3.1 Control ......................................................................................... 11

2.4 Line impedance stabilization network ................................................ 12

2.5 Efficiency ............................................................................................ 13

III. SMPS DESIGN ............................................................................................. 15

3.1 Design process .................................................................................... 15

3.1.1 Initial parameters ......................................................................... 15 3.1.2 Calculated parameters ................................................................. 16


iv

3.1.3 Component calculation ................................................................ 18

IV. ANALYSIS I OF SMPS DESIGN ............................................................... 23

4.1 Design Values ..................................................................................... 23

4.2 Output response .................................................................................. 23

4.3 Component Values .............................................................................. 24

4.4 Results ................................................................................................. 32

V. MODIFYED DESIGN OF SMPS ................................................................. 36

5.1 Component calculation and selection ................................................. 36

5.2 Results ................................................................................................. 40

VI. FILTER APLLICATION FOR MODIFIED SMPS DESIGN ................. 45

6.1 Input filter topologies.......................................................................... 45

6.2 Design process .................................................................................... 46

6.2.1 Applied filter process .................................................................. 48

6.3 Results ................................................................................................. 49

VII. RESULTS .................................................................................................... 64

7.1 Comparison of converter A and B test results .................................... 65

7.1.1 Converter A ................................................................................. 65

7.1.2 Converter B ................................................................................. 66

7.2 Comparison of converter C and D test results ................................... 66

7.2.1 Converter C ................................................................................. 66 7.2.2 Converter D ................................................................................. 67

7.3 Comparison of converter E and F test results .................................... 67

7.3.1 Converter E .................................................................................. 67 7.3.2 Converter F .................................................................................. 68

7.4 Comparison of converter G and H test results ................................... 68

7.4.1 Converter G ................................................................................. 68 7.4.2 Converter H ................................................................................. 69


v

7.5 Conclusion .......................................................................................... 69

BIBLIOGRAPHY ............................................................................................... 71

APPENDIX

A MAGNIFIED SIMULATION RESULTS OF CONVERTERS BEFORE FILTER ......... 73

B MAGNIFIED SIMULATION RESULTS OF CONVERTERS WITH FILTERS ............ 77


vi

ABSTRACT

The research conducted in this paper is focused on DC/DC boost switch mode

power sources, also called DC/DC converters. SMPS are common issues in systems

due to their ability to create high EMI levels and prevent a system from meeting EMC

standards. EMI of a SMPS can be reduced in the designing stages of the converter.

After the initial design of the SMPS, input filters can be applied to further reduce EMI

in the system and allow the converter to be EMC compliant.

The research conducted in this thesis analyzes SMPS with switching

frequencies of 200kHz, 800kHz, 1.4MHz, and 2MHz with duty cycles of 80% and

92%. The set of SMPS under test are then designed and analyzed to determine the

effect of variables such as switching frequency, duty cycle, and load resistance have

on EMI levels SMPS. This new method for designing SMPS begins by designing the

set of SMPS on a discrete level to allow initial analyzation of how converters are

effected by the variable in question. This initial method is then modified to determine

a finite set of component values that are appropriate across the set of SMPS under test.

After analyzing the results of the modified method, a set of input filters are applied to

each SMPS under study to determine which filter will result in a passing level of EMI

for each SMPS.


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LIST OF TABLES

1.1 CISPR22/EN55022 Class B Conducted EMI LIMIT …………………………3

3.1 User Defined Input and Output Parameters………………………………..…16

3.2 Initial Parameter Calculations…………………………………………..….…17

3.3 Initial and Calculated Design Parameters…………………………………….18

3.4 Converts for Testing…………………………………………………………..19

3.5 Calculated Switching Periods…………………………………………….…..20

4.1 Effect of Load Resistance on Converter Output……………………………...24

4.2 Switch and MOSFET Operating Values………………………………...……25

4.3 Si4416DY MOSFET Data………………………………………………...….28

4.4 Component Calculations……………………………………………………...28

4.5 Statistical Component Variables ………………………………………….….31

4.7 EMI Result of Simulated Converter…………………………………….…….32

4.8 Statistical Results of EMI Levels………………………………………....…..34

5.1 Modified Component Calculation Equations…………………...…………….36

5.2 Applied Modified Calculations……………………………………………….38

5.3 EMI Results Before Filter…………………………………………………….44

6.1 Filter Parameters…………………………………….…………………..……47

6.2 Filter Component Equations………………………………………………….47

6.3 Filter Component Calculations…………………………………………….…48

6.4 Resulting EMI Range for Filter Application……………………………….…62


viii

LIST OF FIGURES

2.1 DC/DC Boost Converter Schematic………………………………..………….9

2.2 LISN Topology…………………..…………………………………………..13

2.3 On and Off Losses of the Boost Switching Converter………………………..14

5.1 Simulation Results of Converter A before Filter………………………….…40

5.2 Simulation Results of Converter B before Filter…………….………………41

5.3 Simulation Results of Converter C before Filter……………………….…….41

5.4 Simulation Results of Converter D before Filter……………………………..42

5.5 Simulation Results of Converter E before Filter…………………………….42

5.6 Simulation Results of Converter F before Filter……….……………………43

5.7 Simulation Results of Converter G before Filter………………………….….43

5.8 Simulation Results of Converter H before Filter…………………….………44

6.1 Pi Filter Schematic……………………………………...……………….…..46

6.2 L Filter Schematic…………………………………………..…..……………46

6.3 T Filter Schematic………………………………………………………...…..46

6.4 Simulation Results of Converter A with Pi Filter……………….………...…50

6.5 Simulation Results of Converter A with L Filter……………….………..…..50

6.6 Simulation Results of Converter A with T Filter…………….…………....…51

6.7 Simulation Results of Converter B with Pi Filter………………………........51

6.8 Simulation Results of Converter B with L Filter……………………………..52

6.9 Simulation Results of Converter B with T Filter………………………….....52

6.10 Simulation Results of Converter C with Pi Filter……………………….....…53

6.11 Simulation Results of Converter C with L Filter………………………...…..53

6.12 Simulation Results of Converter C with T Filter………………………….…54

6.13 Simulation Results of Converter D with Pi Filter………………………...…54

6.14 Simulation Results of Converter D with L Filter………………………….….55

6.15 Simulation Results of Converter D with T Filter………………………...….55

6.16 Simulation Results of Converter E with Pi Filter…………………………….56

6.17 Simulation Results of Converter E with L Filter…………………………..…56


ix

6.18 Simulation Results of Converter E with T Filter…………………………..…57

6.19 Simulation Results of Converter F with Pi Filter………………………..…...57

6.20 Simulation Results of Converter F with L Filter……………………………...58

6.21 Simulation Results of Converter F with T Filter…………………………..…58

6.22 Simulation Results of Converter G with Pi Filter………………………….…59

6.23 Simulation Results of Converter G with L Filter………………………….…59

6.24 Simulation Results of Converter G with T Filter………………………..........60

6.25 Simulation Results of Converter H with Pi Filter………………………….…60

6.26 Simulation Results of Converter H with L Filter…………………………..…61

6.27 Simulation Results of Converter H with T Filter…………………………..…61

A.1 Magnified Simulation Results of Converter A before Filter……………….....73

A.2 Magnified Simulation Results of Converter B before Filter……………….....73

A.3 Magnified Simulation Results of Converter C before Filter………………….74

A.4 Magnified Simulation Results of Converter D before Filter……………….....74

A.5 Magnified Simulation Results of Converter E before Filter……………….....75

A.6 Magnified Simulation Results of Converter F before Filter……………….....75

A.7 Magnified Simulation Results of Converter G before Filter……………….....76

A.8 Magnified Simulation Results of Converter H before Filter…………...……..76

B.1 Magnified Simulation Results of Converter A with Pi Filter………...……..77

B.2 Magnified Simulation Results of Converter A with L Filter……………..…78

B.3 Magnified Simulation Results of Converter A with T Filter…………….….78

B.4 Magnified Simulation Results of Converter B with Pi Filter………………..79

B.5 Magnified Simulation Results of Converter B with L Filter……………..….79

B.6 Magnified Simulation Results of Converter B with T Filter……………...….80

B.7 Magnified Simulation Results of Converter C with Pi Filter…………………80

B.8 Magnified Simulation Results of Converter C with L Filter……………....…81

B.9 Magnified Simulation Results of Converter C with T Filter…………….…..81

B.10 Magnified Simulation Results of Converter D with Pi Filter…………….….82

B.11 Magnified Simulation Results of Converter D with L Filter…………….…..82

B.12 Magnified Simulation Results of Converter D with T Filter…………….…..83


x

B.13 Magnified Simulation Results of Converter E with Pi Filter……………....…83

B.14 Magnified Simulation Results of Converter E with L Filter………………….84

B.15 Magnified Simulation Results of Converter E with T Filter………………...84

B.16 Magnified Simulation Results of Converter F with Pi Filter……………..….85

B.17 Magnified Simulation Results of Converter F with L Filter……………..…..85

B.18 Magnified Simulation Results of Converter F with T Filter……………..…..86

B.19 Magnified Simulation Results of Converter G with Pi Filter…………..……86

B.20 Magnified Simulation Results of Converter G with L Filter………….….…..87

B.21 Magnified Simulation Results of Converter G with T Filter………….……..87

B.22 Magnified Simulation Results of Converter H with Pi Filter………….…….88

B.23 Magnified Simulation Results of Converter H with L Filter……………...…88

B.24 Magnified Simulation Results of Converter H with T Filter…………………89


1

CHAPTER I

INTRODUCTION

Switched mode power supplies (SMPS) are systems that convert one voltage

level to another and are commonly called Converters. SMPS are able to step-up, step-

down, or invert a voltage. For the purpose of this paper, the DC/DC SMPS, or DC/DC

Converter, will be evaluated. Before SMPS were used, linear regulators made up the

market for power conversion. Although linear regulators are cost efficient, they have

the drawback of generating high amounts of heat which then requires an undesired

bulky heat sink to be added to the circuits. SMPS offer a reasonable solution but

comes with its own set of drawbacks. SMPS are valuable in systems where various

sub-circuits or components require different levels of voltage from one another. SMPS

are well desired in today’s industry because of their increased efficiency, smaller and

lighter size, reduced cost, and ability to operate over large input voltage ranges. The

flexibility in input voltage ranges have increased the number of applications and

topologies that SMPS are being used in for today’s modern electronics.

1.1 EMI in Switch Mode Power Systems

Electromagnetic interference (EMI) is defined as “the disruption of operation

of an electronic device when it is in vicinity of an electromagnetic field (EM field) in

the radio frequency (RF) spectrum that is caused by another electronic device.” [1]

EMI can appear in many forms, caused by many factors, and can affect circuits in

many ways. EMI has the ability to prevent circuits and components from operating the

way they were designed and intended to operate. This disturbance can interrupt

systems, lead to proximity effect, create voltage drops, eddy current losses, degrade or

limit performance, block transmissions, create hysteresis losses, create harmonic

distortion, effect permeability of materials, or even damage components or other

systems. Ideally, EMI would not exist. In reality, EMI is a growing issue with the

increasing demand for technology to increase in performance and speeds.


2

For power supply applications, there are three things that can occur to cause

EMI issues. First, a signal source can create noise. The second cause is the presence of

a transmission path for the noise to travel on. The third cause is the presence of a

receiver that is too sensitive to noise that it allows for easy distortion. The typical

method for reducing EMI is to address and remove the issue at the source of the

system, which in this case is the SMPS. For power supplies, there are two forms of

EMI that are present; conducted and radiated. Conductive EMI appears from physical

contact of the conductor components while radiated EMI appears without the need for

contact. It is agreed that 30MHz is the frequency at which conducted EMI turns into

radiated EMI. Assuming this agreement, this paper will focus on conducted EMI.

Conducted EMI occurs for frequencies below 30MHz and is driven by current.

Radiated EMI will not be addressed in this testing due to the complications of

measuring magnetic fields in free space.

There are two goals that designers wish to meet in order to find their design

acceptable. The first goal for EMI reduction is to reduce it to a level that it passes EMI

testing standards. These standards are also called electromagnetic compliance (EMC)

standards. The second goal for reducing EMI is to reduce it to a level where the design

will work reliable, efficient, and without disturbing other equipment nearby. When a

product meets these goals, it is considered to be “EMC-compliant”.

1.1.1 EMC for SMPS

Electromagnetic Compatibility (EMC) is defined as the “ability of a device, unit of

equipment, or system to function satisfactorily in its electromagnetic environment without

introducing intolerable electromagnetic disturbances to anything in that environment.” [2]

This means that EMC is in absence of EMI. EMC standards came about when the consumer

market started to demand for faster, lighter, and more efficient technology. With these

demands in SMPS designs, it created growing EMI issues. EMC standards are

designed to address two major concerns. First, the amount of radiated and/or

conducted emissions generated by a system must be limited. Second, the minimum

immunity tolerance of a system to radiated and/or conducted emissions must be set.


3

Standards typically define a systems allowable limits, setup and process for testing

EMI, equations and documentation for analyzing a system, and various measurement

methods. EMC standards are evaluated with test methods conducted in certified labs.

In order to determine if a design is EMC-compliant, the design is evaluated through all

design stages. This evaluation consists of looking for places where poor EMI designs

cause problems at other stages.

The Federal Communication Commission (FCC) is an organization that sets

rules and standards to regulate conducted emissions occurring in the frequency range

of 450 kHz to 30 MHz. CISPR is a leading organization with the same purposes as the

FCC except with focus on the 150 kHz to 30 MHz frequency range. For the purpose of

this paper, we will be focusing on the standard CISPR22/EN55022 set by FCC and

CISPR for the frequency range of 150 kHz to 30 MHz. This standard document is

focused on information technology equipment. The supply voltage of these

equipment’s must be less than 600V.

When evaluating performance at various stages in simulation, the designer my

consider component variations. In reality, a component properties and behavior can

vary from the predicted properties and behavior of simulation. This is not to say that

simulation is not needed. The conducted EMI limits are summed up in Table 1.1.

Table 1.1 CISPR22/EN55022 Class B Conducted EMI LIMIT

Emission Frequency Conducted Limit

dBµV V 9kHz – 50kHz 100 316mV

50kHz – 150kHz 90-80 32mV-10mV

150kHz – 500kHz 56-46 .63mV-.2mV

.5MHz-5MHz 46 200µV

5MHz – 30MHz 50 319µV


4

1.2 Issues with SMPS

SMPS come with increased complexity of designing systems in which they are

used. This is due to several key disadvantages of their operation. The main

disadvantage of SMPS is the noise, which they bring to a system. The switching

operation, which will be discussed and evaluated in Chapters IV and V, causes

transient spikes that require proper filtration or they will come with the consequence

of creating EMI noise. For SMPS design, external components are needed. Adding in

external components comes with the drawback of increasing the cost to design the

SMPS and space to place the components. SMPS are a complicated system to design,

therefore they need designers that are experts in SMPS which can be difficult to find.

The difficulty of design SMPS lies in the tricky aspect of reducing and ensuring the

reduction of ripple components to a level set by a standards organization. This

difficulty comes with the promise of extra time requirement to design a properly

operating system. Increasing the components, time to market, and level of expertise of

the designer all contribute to increasing the cost of SMPS. These disadvantages are

often over looked when they are compared to the benefits that SMPS offer.

1.3 Signals

Signals are the root method for communication and EMI travel in SMPS.

Signal Integrity is a field designed to ensure the proper operation and design of

systems carrying signals. Signals can be broken up into many categories based on the

characteristics that comprise them. High frequency signals relate to the speed of

frequency in which they operate. Common mode and differential mode signals are

signals that appear in systems without always being with intent. These signals relate

back to EMI and must be controlled to ensure that a system is operating in the EMI

limit set for them.


5

1.3.1 High frequency operation

For lower frequencies, EMI is caused by conduction and is simpler to control.

As frequencies increase, the ability to control EMI becomes more complicated. This

complication occurs from the effect of high frequencies ability to create radiate EMI.

Modern Switch Mode Power Supplies switching mechanisms have reduced in

switching time which has led to increased voltage and current rise and fall times. The

fast edges now present in the system and increasing frequency speeds have created an

issue of increased energy in the system. This energy is the source of EMI problems.

EMI occurring at high frequencies can turn every conductor in a system into an

antenna.

Operating SMPS at high frequencies does offer some advantages. For designs

with transformers, the transformer type will be high frequency which will be smaller

in size than those for lower speeds. When the switch operates at increasing speeds, the

ripple frequency will also increase. This will allow for a smaller size capacitor to be

used to smooth out the ripple. For designs with a square wave driving the switching

transistor, the dissipation of power will be less than those with a series regulator

transistor. This aids in the cost effectiveness and architecture of the design by allowing

lower cost and smaller size transistors to be selected. The improved architecture

allows for SMPS to be lighter and smaller which is more appealing for the architecture

of large systems needing power sources.

As frequencies increase it created ringing in all resonant tanks of these power

systems that have become more apparent and problematic. Ringing is defined as

unwanted oscillation in a signal that occurs when the fast edges cause the parasitic

inductances and capacitances to resonate at their characteristic frequency. The source

of concern with ringing present in a system is the effect it has on the power supplies

working reliability and ability to pass standards and tests. It is proposed that by

increasing switching speeds will lead to reduced losses and increased efficiency in

power supplies. It is expected that increased switching speeds should be accompanied

with increased frequency that leads to improved transient response and smaller passive

components. This promise has yet to be realized due to the cost of components


6

suitable for high frequencies such as transformers and the issues of EMI problems

accompanying high frequencies.

1.3.2 Common Mode and Differential Mode

Differential mode signals have key characteristics that aid against Signal

Integrity (SI) issues such as robust propagation on signal paths. A Differential pair is

made up of two transmission lines. Differential pairs offer key features that help

optimize transmission of high bandwidth signals. Reflections and distortions are

minimized by their uniform cross section and constant impedance. Both lines of a

differential pair must be the same length to ensure constant time delay. The edges of

the differential signals are sharp and well defined as result of the matched time delay

on the pairs. Differential signal can be converted into common mode when the time

delays between the pairs become skewed due to lack of symmetry in a pair. Coupling

between the two lines of a differential pair offer some level of noise immunity from

neighboring noise sources. If differential signals are not properly balanced or filtered

and common signals are present then the potential for EMI problems arise.

Unwanted differential noise is sourced from the current on the dc power line

that carries pulsating current from the dc power line. The coupling that occurs between

the power line and the ground is the root cause of differential noise. The input

impedance of the DM noise source is dependent on the converter topology selected

and the components that compose it. Differential noise affects circuits by dissipating

its energy into the line to neutral paths of the system. On an electrical level,

differential noise can affect a circuit by over biasing the P-N junction of diodes

leading to the rectifying diode circuit to fail to operate at intended. Capacitors are

affected by differential noise by the ability of the noise to degrade capacitors with

opposite polarity to the noise. If the differential noise level in the system is too high

then it will cause transformers isolation to breakdown.

Common mode signals propagate on both lines of a transmission line pair.

Common mode signals are equal in amplitude and phase. In ideal situations, common

signals are not problematic and serve no purpose. In reality, common mode signals


7

have the potential of causing server EMC problems. Common mode signals have

potential to cause saturation in the differential receiver input amplifier resulting in

inaccurate reading of the differential signals. If a common mode signal leaves the

board, it will exit in the form of radiation, which causes EMC issues.

Common mode noise occurs over the parasitic capacitors to ground affected by

the switching action of the system. The impedance of the common mode noise source

is dependent on the selected SMPS topology and its parasitic elements. When stray

capacitance occurs in the system, it will lead to common mode noise. Coupling of

common mode noise occurs along the coupling path of high frequency transformers

that contain parasitic capacitance. At high frequency, the noise will view the

transformers in the system as coupling capacitors. Inductors that are in series with one

another on the power line of the system typically suppress common mode noise. Y-

capacitors can also be used to suppress common mode noise that are connected form

power to ground.

1.3.3 Victim line, aggressor, and coupling path

Commonly, when analyzing a network with greater than 4 ports you must

select a victim line and the remaining lines become the aggressor lines. Simulation on

the selected victim line means that all neighboring lines (aggressors) are simulated as

active in order to create a “worst case” scenario of the victim line. This method is for

the purpose of analyzing crosstalk-coupling effects between the selected victim line

and aggressor lines of a network. The designed software tool will take into account

victim lines and aggressors and allow the user to select which line will be the victim

line in a greater than 4 port network.

Coupling path interference can exist in two forms, conductive or radiation,

which commonly co-exist together at the same time. If the path between the victim

line and the aggressor is connected then the interference is said to be conductive. If no

physical connection between the paths exists then the interference will appear in the

form of radiation. Each system paths and sources are separated into power plane (ie.

Power supply, power and ground traces, or components), signal paths, or package


8

radiation categories. Common-impedance is interference due to conduction. Near-field

interference will appear from capacitive or inductive coupling. Far-field interference is

equivalent to electromagnetic radiation.

1.4 Aim of this study

The aim of this study is to create a new method for calculating components for

Boost DC/DC Converter. Four switching frequencies will be analyzed as well as two

duty cycles for each switching frequency. The basic method for calculating

components for a Boost DC/DC Converter is introduced in Chapter III. This method is

then analyzed at the highest depth level conducted in this research for each switching

frequency, duty cycle, and load resistance step. The results of this operation is then

compared to determine how switching frequency, duty cycle, and load resistance will

affect the minimum required component values and how this effects the EMI input of

the converter. The method is then reevaluated in Chapter IV to determine component

values that are constant across all switching frequencies, duty cycles, and load

resistance. These constant component values are then analyzed with each previously

tested SMPS designs. The improved method for DC/DC converter design has larger

application by use of constant components. Input filters are then added to the modified

design to create DC/DC boost converters that pass the required EMI and EMC

standards. Three different input filters are tested with each switching frequency and

duty cycle design to determine which filter will serve the best application for the

various converters.


9

CHAPTER II

SWITCH MODE POWER SYSTEMS

2.1 Topologies

The industry most common DC/DC topologies are the buck, boost, and fly

back converter. Each topologies is used for a different purpose. The buck converter

steps down the voltage from the input to the output of the SMPS. The boost converter

steps up the input voltage to lead to a high output voltage. The fly back converter is an

inverting converter. For the purpose of this study, the DC/DC boost SMPS will be

analyze in design process. The basic design of the boost converter is shown in Figure

2.1.

Figure 2.1 DC/DC Boost Converter Schematic

Boost converters are considered indirect energy transfer converters. The

converter transfers energy by use of an energy storing phase and an energy

discharging phase. When the switch is open the energy is stored in the inductor while

the output capacitor delivers power to the load. When the switch is closed, the

inductor transfers energy to the capacitor to recharge the capacitor. The boost

converter will naturally have an offset current due to the charge time for the inductor.

The drawback to the boost converter inductive charging portion of operation is that it

is not effective when there is a sudden change in demand for increased output power.

The design of the boost converter does not allow for the inductor to rapidly reach a

higher peak voltage without causing the output voltage to drop. Therefore, boost

converters are commonly used in application where there is a need for slower charging

time phase. The benefit of the boost converter design is that the inductor is able to


10

draw current during the on and off cycles of operation which allows for a lower input

ripple design.

2.2 Components

For DC/DC SMPS a power switch, controller, diodes, and passive components

are needed. The power switch regulates voltage with the use of passive elements such

as resistors, capacitors, and inductors. Power switches are a higher efficient option for

transferring energy in a system. The control of a switch can either be voltage or

current control. The component chosen for the power switching can be either a jfets or

a MOSFETS. Diodes are also used in SMPS design for transferring of energy. SMPS

can use more than one switch to transform dc power levels.

2.2.1 Passive elements

It is known that passive components have the ability to reduce externally

induced interference. Passive components are resistors, capacitors, and inductors.

Basic RC networks are used for creating cost effective monopole low pass filters.

Resistors are useful for absorbing heat from incoming noise with the side effect of

producing thermal noise. Resistors are also ideal for creating input bias current when

places at the input of an op amp. This method creates offset voltage for minimizing dc

offset but does not affect the noise in the circuit.

Capacitors are used for switching applications in need of their ability to store

and transfer energy. Capacitors are also not able to change their voltage abruptly.

These qualities make capacitors the selected component for charge pumps in DC/DC

converters. Inductors are another element commonly chosen for application in switch

mode regulation. Inductors have the ability to transfer energy more efficiently than

other passive components such as resistors. Another key reason for using inductors is

their ability to transfer energy from one source to another regardless of their polarities.


11

2.3 Operation

Operation of SMPs is dependent on the charging and discharging abilities of

inductors and capacitors. The ability to control the capacitors and inductors voltage is

accomplished by use of a switching device. The capacitor charging property at use in

the SMPS is the current equation. For a capacitor with C capacitance and V voltage

applied over time t, the current equation will yield to be: I = CdV

dt. To review inductor

charging properties, the readier must be reminded of the inductor voltage equation. To

increase the voltage (V) across an inductor with inductance L, a current (i) is applied

over time (t). This yields to the inductor voltage equation: VL = Ldi

dt.

The charging phase of the boost converter occurs when the switch is in the

open state. If the switch has been open for a long period of time, the voltage drop of

the diode will reduce to a negative value and the capacitor will have a charge that is

equal to the input voltage of the converter. Once the switch is closed, the input voltage

passes through the inductor at a linear rate in DC/DC operation. The purpose of the

diode is to prevent the capacitor from discharging the output voltage to ground. For

common SMPS designs, a Schottky diode is used for this purpose. Once the switch

opens again, the current in the inductor must follow a circulating path by reversing

voltage. The inductor voltage will now be in series with the input voltage. The diode

has application in the off time event by passing the inductor current to the output

capacitor and transfer the inductor stored energy into the capacitor and load resistor.

2.3.1 Control

Converters commonly use components such as a power switch for the purpose

of a switching regulator that controls the transfer of energy between input and output

sources. Switching regulators are at the heart of the SMPS technology. In the

switching circuit, a voltage or current can be used to control the charge on the

capacitor or the inductor. The regulator relies on the stored energy properties of

capacitors or inductors. Switching regulators are picked over linear regulators because


12

of their higher efficiency, ability to maintain more energy during the convention

process, are operable with smaller components, and require less thermal management.

2.4 Line impedance stabilization network

Line impedance stabilization networks (LISN) are required components in

systems where EMI emission and susceptibility is present or potential and needs to be

measured. LISN creates a known impedance that allows noise measurements to be

conducted and isolated unwanted signals from the power source. In order for a device

to be tested for FCC and CISPR standards, a LISN must be placed between the AC or

DC power source and the device under test (DUT). For the purpose of this paper, the

DUT is a SMPS. Typically, LISN are composed of a low pass filter that measures

noise current on the AC or DC power line. The current on the AC or DC line is

dependent on the load or impedance of the SMPS. The impedance seen by the SMPS

on the power line will change over the frequency range of the system. LISN provides a

constant known impedance seen by the SMPS. A second benefit to LISN is the

isolation it creates between the power line and the SMPS that prevents noise on the

power line from entering the system.

For the purpose of this paper, two LISN are used for single phase conducted

emission measurements. This is because both the line and neutral lines must meet

EMC standards to be EMC compatible. Figure 2.2 shows the topology for the LISN

used in the research conducted in this paper which is sourced from standards

document CISPR 16. This LISN topology contains two 50𝜇H inductors, two 250nF

capacitors, two 8𝜇𝐹 capacitors, two 5Ω resistors, and two 50Ω resistors.


13

Figure 2.2 LISN Topology

This topology operates where the inductors appear shorted while the

capacitors are open to allow power to pass through them to the SMPS. When EMI

frequency level noise appears is the system, the inductors will appear open while

the capacitors are shorted causing the noise to only see the 50Ω resistors of the

LISN. Sense the DM noise travels from the power line, it will then flow through

the two series 50Ω resistors creating a 100Ω load for the DM noise. The CM noise

flows to ground resulting in a load of two 50Ω resistors in parallel with a total

resistance of 25Ω.

2.5 Efficiency

Efficiency is a large concern for designing SMPS. Efficiency is the ratio of

useful output power to total input power of a system and is directly proportional to

power dissipation in the system. If high losses appear in the system, the temperature of

the system will increase causing the need for a thermal management component will

arise. The main locations for power dissipation in DC/DC converters are the inductor

and MOSFET conduction loss, MOSFET switching loss, and rectifying diode loss.

Losses appear in both the on and off state of the converter. Figure 2.3 shows the losses

for on and off switching modes of the boost converter.


14

Figure 2.3 On and Off Losses of the Boost Switching Converter

For typical converters, the largest power loss risk element is the diode. The

power dissipation is calculated as the forward voltage drop multiplied by the current

passing through it. The reverse recovery of the diode can also effect the loss in the

system. Schottky diodes are selected for the purpose of power loss management.


15

CHAPTER II

SMPS DESIGN

For analysis of variables effect on boost DC/DC converter operation EMI

results, a standard detailed method will be introduced. This method was constructed to

design at the most detailed level. The method will use the process of having initial

user defined inputs, then proceed to use equations to determine remaining initial

parameters, and finish with calculating each aspect of all components used in the boost

DC/DC converter. The goal of using equations to determine remaining initial design

variables is to constrain these variables in ranges that will have the strongest EMI and

efficiency results. This proposed design method will be analyzed for four switching

frequencies, 200kHz, 800kHz, 1.4MHz, and 2MHz. After the design method has been

analyzed at the highest detail, changed will be made to allow for a design operable in a

larger application range.

3.1 Design process

The design process of the introduced method is one that varies from other

methods by the use of narrowing the allowable user defined inputs. The user is able to

enter in basic parameters for the converter. Once the basic parameters are inputted, the

next step in the design process is to calculate the remaining parameters that will yield

the most desirable efficiency and EMI level. Common with other design processes,

equations for minimum inductor and capacitor values are used. The minimum

component values are effected by the switching frequency, duty cycle, and load

resistance of the converter. After the design process is completed, the results are then

simulated to determine the effect of the various design variables of switching

frequency, duty cycle, and load resistance on the EMI level in the system.

3.1.1 Initial parameters

The boost converter design method that will be evaluated offers the user a

range of values for selecting capacitor size, inductor size, duty cycle, and switching


16

methods. For this method the user must first define the desired output voltage (𝑉𝑜𝑢𝑡),

the desired switching frequency (𝑓𝑠), output power (𝑃𝑜), and the desired voltage ripple

percent (𝑉𝑟𝑖𝑝). Using these initial parameters and the following steps outlining the

proposed method for designing a SMPS helps user’s better design high efficient and

lower EMI results of SMPS. For this evaluation, the table below shows the first list of

input parameters to be evaluated.

Table 3.1 User Defined Input and Output Parameters

𝑉𝑜𝑢𝑡 24 V

𝑉𝑟𝑖𝑝 .48V (2%)

𝑓𝑠 200kHz

800kHz

1.4MHz

2MHz

𝑃𝑜𝑢𝑡 24 W

3.1.2 Calculated parameters

The first step in this new method is to determine maximum and minimum

values for output current (𝐼𝑜), load resistor (𝑅𝐿) , and output power. The minimum

output current is assumed to be 5% of the maximum output current. The maximum

and minimum load resistors are determined by applying Ohms law. The power

maximums and minimums are calculated with max values for typical power equations.

The set of equations to calculate these values and their resulting values are shown in

the table below.

Table 3.2 Initial Parameter Calculations

Variable Equation Calculation

𝐼𝑜(max) 𝑃𝑜𝑢𝑡

𝑉𝑜𝑢𝑡

24

24= 1 𝐴

𝐼0(min) . 05 × 𝐼𝑚𝑎𝑥 . 05 × 1 = .05 𝐴

𝑅𝐿(min) 𝑉𝑜𝑢𝑡

𝐼𝑜𝑢𝑡_𝑚𝑎𝑥

24

1= 24Ω

𝑅𝐿(max) 𝑉𝑜𝑢𝑡

𝐼𝑜𝑢𝑡_𝑚𝑖𝑛

24

. 05= 430

𝑃𝑜(min) 𝑉𝑜𝑢𝑡 × 𝐼𝑜_𝑚𝑖𝑛 24 × .05 = 1.2


17

𝑃𝑜(max) 𝑉𝑜𝑢𝑡 × 𝐼𝑜_𝑚𝑎𝑥 24 × 1 = 24

The next step for this method determines the input voltage range and duty cycle

range for the system. This design method aid in designing parameters that will lead to

a lower EMI level design. It is recommended for systems to be at least above 80%

duty cycle to yield the highest desired EMI results. Duty cycle is the ratio of input

voltage over output voltage as shown in equation 3.1 for CCM operation.

𝐷𝐶𝐶𝑀 = 1 −𝑉𝑖𝑛(max)

𝑉𝑜𝑢𝑡 (3.1)

A second determining factor to keep in mind when designing a SMPS is the efficiency

of the system. Efficiency (𝜂) in SMPS designs is generally the ratio of output power to

dissipated power. Efficiency plays a key role in determining duty cycle as well. For

calculating duty cycle in respect to efficacy (𝐷𝑒𝑓𝑓), the following equation is used.

𝐷𝑒𝑓𝑓 = 1 −𝑉𝑖𝑛(max)×𝜂𝐷

𝑉𝑜𝑢𝑡 (3.2)

The efficiently used in this equation (𝜂𝐷) is not assumed to be equal to the efficiency

of the resulting system. Taking efficiency into account at the duty cycle stage helps

better create a higher efficiency design in early stages. In respect to the above

equation, as the efficiency (𝜂𝐷) increases, the duty cycle decreases. The newly

suggested method aims to determine values that meet a compromise in efficiency

versus duty cycle. To accomplish this, the allowable duty cycle efficiency is in the

range of 40% to 100%. The minimum duty cycle for this method as stated above is

80%. It can then be stated that the system is at the highest allowable duty cycle

efficiency (100%) at the minimum allowable duty cycle (80%). Rearranging equation

3.2, the highest allowable input voltage can be calculated as shown below.

𝑉𝑖𝑛_𝑚𝑎𝑥 =𝑉𝑜𝑢𝑡−𝐷𝑒𝑓𝑓_𝑚𝑖𝑛×𝑉𝑜𝑢𝑡

𝜂=

24−.8×24

1= 4.8 𝑉 (3.3)

The maximum duty cycle is determined by the maximum allowable input voltage and

minimum allowable duty cycle efficiency (40%). The minimum input voltage is

determined by the maximum allowable duty cycle and output voltage. Efficiency was

used to calculate the maximum duty cycle and therefore is not needed to calculate the


18

minimum input voltage. These equations are determined and calculated as shown

below.

𝐷𝑚𝑎𝑥 = 1 −𝑉𝑖𝑛(max)×𝜂𝐷

𝑉𝑜𝑢𝑡= 1 −

4.8×.4

24= .92 (3.4)

𝑉𝑖𝑛(min) = 𝑉𝑜𝑢𝑡 − 𝐷𝑚𝑎𝑥 × 𝑉𝑜𝑢𝑡 = 24 − .92 × 24 = 1.92 𝑉 (3.5)

The initial set of parameters defined by the designer allows the designer to

determine the second set of parameters with ranging values. Values at their maximum

and minimum are interchanged and allow for various tradeoffs in the performance of

the SMPS. These tradeoff are evaluated in later on in this section of this research. The

resulting full set of parameters are applicable to all evaluated frequencies in this

testing and are summed up in Table 3.3 below.

Table 3.3 Initial and Calculated Design Parameters

Initial Parameters

𝑉𝑜𝑢𝑡 24 V

𝑉𝑟𝑖𝑝 .48V (2%)

𝑓𝑠 200kHz

800kHz

1.4MHz

2MHz

𝑃𝑜𝑢𝑡 24 W

Calculated Parameters

𝐼𝑜 .05 A – 1 A

𝑅𝐿 24Ω – 430Ω

𝑃𝑜 1.2W – 24W

𝑉𝑖𝑛 1.92 V – 4.8 V

𝐷 .8 – .92

𝜂𝐷 40% - 100%

3.1.3 Component calculation

The next step in the design method is to determine the time parameters of the

system. The time parameters are dependent on the switching frequency of the system.

For the purpose of all testing conducting in this thesis, the following set of DC/DC

boost converter operation variables are analyzed.


19

Table 3.4 Converts for Testing

Converter A

𝑓𝑠 200kHz

Duty Cycle 80%

Converter B

𝑓𝑠 200kHz

Duty Cycle 92%

Converter C

𝑓𝑠 800kHz

Duty Cycle 80%

Converter D

𝑓𝑠 800kHz

Duty Cycle 92%

Converter E

𝑓𝑠 1.4MHz

Duty Cycle 80%

Converter F

𝑓𝑠 1.4MHz

Duty Cycle 92%

Converter G

𝑓𝑠 2MHz

Duty Cycle 80%

Converter H

𝑓𝑠 2MHz

Duty Cycle 92%

The variable 𝑇𝑠 represents the period of the switching frequency and is

calculated with equation; 𝑇𝑠 =1

𝑓𝑠. The on and off period (𝑇𝑜𝑛/𝑜𝑓𝑓) of the switch in the

SMPS is determined by the duty cycle of the system and the switching period. The

resulting switching periods and on and off periods are calculated for each frequency

and shown below.

Table 3.5 Calculated Switching Periods

Switching Period Equations

Switching Period 𝑇𝑠 =

1

𝑓𝑠

On Period of Switch 𝑇𝑜𝑛 = 𝐷 × 𝑇𝑠

Off Period of Switch 𝑇𝑜𝑓𝑓 = (1 − 𝐷) × 𝑇𝑠


20

Switching Period Calculations Switching Frequency 200kHz 800kHz 1.4MHz 2MHz

Duty Cycle 80% 92% 80% 92% 80% 92% 80% 92%

𝑇𝑠 5µs 1.25µs .714µs .5µs

𝑇𝑜𝑛 4µs 4.6µs 1µs 1.15µs .571µs .657µs .4µs .46µs

𝑇𝑜𝑓𝑓 1µs .4µs .25µs .1µs .143µs .54µs .1µs .04µs

There are many proposed methods for calculating the required inductance for a

boost DC/DC SMPS. All methods have their own tradeoffs that are dependent on

factors such as load percent or efficiency needed. For testing in this thesis, the

minimum inductor values will be calculated with equation 3.6.

𝐿𝑚𝑖𝑛 =(1−𝐷)2×𝐷×𝑅𝐿

2×𝑓𝑠 (3.6)

When examining the inductor equation, it is concluded that as the 𝑅𝐿 increases, the

minimum inductor size will also increase. The effect of the inductance value size will

be examined in this chapter as well as in Chapter IV.

The peak to peak ripple current will determine which MOSFET, inductor, and

capacitor peak current values are acceptable for use in the calculated duty cycle, input

voltage, and minimum inductor ranges. The peak to peak ripple current (∆𝐼𝐿) is

calculated with equation 3.7.

∆𝐼𝐿 =𝑉𝑖𝑛×𝐷

𝑓𝑠×𝐿 (3.7)

The peak to peak ripple current calculated, will now allow for the inductor RMS

current to be calculated. When selecting an inductor, the inductor maximum RMS

current is crucial. The inductor maximum RMS current is dependent on the duty cycle

of the system, input voltage, and peak to peak ripple current as shown in equation 3.8.

𝐼𝐿,𝑅𝑀𝑆 = √(𝑃𝑜

𝑉𝑖𝑛)

2

+∆𝐼𝐿

2

12 (3.8)


21

The next component to be calculated and characterized is the MOSFET for

switching purpose in the system. The inductor leads into the junction for the

MOSFET, therefore the key current equation for selecting the MOSFET is the

maximum inductor peak to peak ripple current (∆𝐼𝐿(max)). This equation allows the

inductor switching peak ripple current (𝐼𝑠𝑤(𝑝𝑘)) to be calculated from equation X.

These equations help determine the needed resistance from drain to source in the on

state (𝑅𝐷𝑆(𝑜𝑛)) of the MOSFET.

𝐼𝑠𝑤(𝑝2𝑘) = √𝐷 (𝑃𝑜

𝑉𝑖𝑛)

2

+∆𝐼𝐿

2

12 (3.9)

The switching peak current is critical. The inductor, MOSFET, and diode must

be able to withstand this current. Once the switching peak to peak current has been

determined, the desired 𝑅𝐷𝑆(𝑜𝑛) of the MOSFET can be calculated. Equation X is used

to calculate 𝑅𝐷𝑆(𝑜𝑛). When determining the 𝑅𝐷𝑆(𝑂𝑁) value of the MOSFET, the

designer should chose a value that causes the conduction power dissipation to be 1%

of the total output power of the system. This ensures that the maximum MOSFET

drain current that is acceptable is highly greater than the drain current that will occur

in reality. For the purpose of this simulation, arbitrary conduction losses are assumed

to be 1%.

𝑅𝐷𝑆(𝑜𝑛) =𝑃𝑜𝑢𝑡×.01

𝐼𝐿,𝑅𝑀𝑆 (3.10)

After the inductor and MOSFET junction, the current in the system must pass

through a diode. The needed diode RMS current is critical for selecting the diode. The

diode RMS current is calculated in equation 3.11.

𝐼𝑑,𝑅𝑀𝑆 = √(1 − 𝐷) (𝑃𝑜

𝑉𝑖𝑛)

2

+∆𝐼𝐿

2

12 (3.11)

For selecting the capacitor, the capacitance value and the ESR value must be

determined. Equation 3.12 calculates the minimum capacitance value which is


22

dependent on the duty cycle and the voltage ripple of the system (𝑉𝑟). The voltage

ripple has previously been defined by the designer to be .48V.

𝐶𝑚𝑖𝑛 =𝐷

𝑅𝐿×𝑓𝑠×𝑉𝑟=

𝐷

𝑅𝐿×𝑓𝑠×.48 (3.12)

Once the capacitor minimum value is determined, the needed ESR value and

RMS current for the capacitors are calculated. The ESR of the capacitor is determined

by the switch peak to peak ripple current and ripple voltage in the system. The RMS

current of the capacitor is dependent on the output current and the diode RMS current.

These equations are shown below.

𝐸𝑆𝑅 =𝑉𝑟

𝐼𝑠𝑤(𝑝𝑘) (3.13)

𝐶𝑅𝑀𝑆 = √𝐼𝑑,𝑅𝑀𝑆2 − 𝐼𝑜(max)

2 (3.14)


23

CHAPTER IV

ANALYSIS I OF SMPS DESIGN

The first test will analyze the recommended inductor and output capacitor at

the minimum recommended values and the output capacitor ESR at the maximum

recommended value. For each switching frequency, the duty cycles will be tested at

80% and 92%. This will allow comparison of the effect of duty cycle and switching

frequency on component selections and their result EMI effect.

4.1 Design Values

The four switching frequencies are selected in the range of 200kHz to 2MHz

with 600kHz step between each switching frequency. This resulted in switching

frequencies of 200kHz, 800MHz, 1.4MHz, and 2MHz. Each switching frequency will

be evaluated at the maximum and minimum duty cycles of 80% and 92%. The

selected duty cycle will affect the input voltage in the system. For operation at 80%

duty cycle, the input voltage will be 4.8V with the output voltage remaining at 24V.

When the duty cycle in increased to 92%, the input voltage will decrease to 1.92V in

order for the output voltage to remain 24V. Increasing the duty cycle also effects the

component minimum values in the system.

4.2 Output response

The output voltage is to remain a constant of 24V. In order for the output

voltage to be 24V, the output power divided by the output current must always equal

24V. The equation for output power is broken down to; 𝑃𝑜𝑢𝑡 = 𝑉𝑜𝑢𝑡 × 𝐼𝑜𝑢𝑡 = (𝑅𝐿 ×

𝐼𝑜𝑢𝑡) × 𝐼𝑜𝑢𝑡. Therefore, the output power and output current will change as the load

resistance changes. The output power, current, and load are not dependent on

switching frequency or duty cycle. This allows the effect of load resistance on the

output current and power to be constant over all switching frequencies and duty cycle.


24

Table 4.1 sums up the resulting effect of load resistance on output current and power

for all switching frequencies and duty cycles.

Table 4.1 Effect of Load Resistance on Converter Output

𝑹𝑳(𝛀) 𝑰𝒐𝒖𝒕(𝑨) 𝑷𝒐𝒖𝒕(𝑾)

24 1 24

50 .48 11.52

75 .32 7.68

100 .24 5.76

125 .192 4.6

150 .16 3.84

175 .137 3.29

200 .12 2.88

225 .1 2.56

250 .096 2.3

275 .087 2.09

300 .08 1.92

325 .07 1.77

350 .068 1.64

375 .064 1.53

400 .06 1.44

430 .055 1.34

4.3 Component Values

For a selected duty cycle, the load resistance will affect the minimum

component values and current values occurring in the system. The first components to

be selected are the MOSFET and diode. It is the goal to select these components to be

able to operate for all testing of the changing switching frequency, duty cycle, and

load resistance. This allows for more appropriate real world application where the

DC/DC Converter will be operational in a large application rage. Selection of the

MOSFET and diode is dependent on the ∆𝐼𝐿, 𝑅𝐷𝑆(𝑜𝑛), 𝐼𝑠𝑤(𝑝2𝑝), and 𝐼𝑑,𝑅𝑀𝑆 of the

system operating under the various operation variables of the system. Table 4.2 sums

up these values for each switching frequency, duty cycle, and load resistance.


25

Table 4.2 Switch and MOSFET Operating Values

200kHz Switching Frequency

80% Duty Cycle 92% Duty Cycle

𝑹𝑳(𝛀) ∆𝑰𝑳(A) 𝑰𝒔𝒘(𝒑𝟐𝒑)(𝑨) 𝑹𝑫𝑺(𝒐𝒏)(𝛀) 𝑰𝒅,𝑹𝑴𝑺(𝑨) ∆𝑰𝑳(A) 𝑰𝒔𝒘(𝒑𝟐𝒑)(𝑨) 𝑹𝑫𝑺(𝒐𝒏)(𝛀) 𝑰𝒅,𝑹𝑴𝑺(𝑨)

24 10 5.32 41.57 3.65 14.43 13.4 18 8.04

50 4.8 2.55 86.6 1.75 6.92 6.71 34.64 3.85

75 3.2 1.7 129.9 1.16 4.61 4.47 51.96 2.57

100 1.38 1.27 173.2 .87 3.46 3.35 69.28 1.92

125 1.1 1.02 216.5 .7 2.77 2.68 86.6 1.54

150 .92 .85 259.8 .58 2.3 2.23 103 1.28

175 .79 .72 303 .5 1.97 1.91 121.2 1.1

200 .69 .63 346 .43 1.73 1.67 138.6 .96

225 .61 .56 389 .38 1.54 1.49 155.9 .857

250 .55 .51 433 .35 1.38 1.34 173.2 .77

275 .5 .46 476 .31 1.25 1.22 190.5 .7

300 .46 .42 519 .29 1.15 1.12 207 .64

325 .426 .39 562.9 .26 1.06 1.03 225 .59

350 .39 .36 606 .25 .98 .95 242 .55

375 .36 .34 649 .23 .92 .89 259 .51

400 .34 .31 692 .21 .866 .84 277 .48

430 .32 .29 744 .2 .8 .78 297 .44




24 5.77 5.3 41.57 3.65 14.4 13.9 18 8.03

50 2.77 2.55 86.6 1.75 6.9 6.7 34.64 3.85

75 1.84 1.7 129.9 1.16 4.6 4.47 51.96 2.57

100 1.38 1.27 173 .87 3.46 3.35 69.28 1.92

125 1.1 1.02 216.5 .7 2.77 2.68 86.6 1.54

150 .92 .85 259 .58 2.3 2.23 103 1.28

175 .79 .72 303 .5 1.97 1.91 121 1.1

200 .69 .63 346 .43 1.73 1.67 138 .96

225 .61 .56 389 .38 1.54 1.49 155 .857

250 .55 .51 433 .35 1.38 1.34 173 .77

275 .5 .46 476 .31 1.25 1.22 190 .7

300 .46 .42 519 .29 1.15 1.12 207 .64

325 .42 .39 562 .26 1.06 1.03 225 .59

350 .39 .36 606 .25 .98 .95 242 .55

375 .37 .34 649 .233 .92 .89 259 .51

400 .34 .31 692 .21 .866 .83 277 .48

430 .32 .29 744 .2 .8 .78 297 .44


26

1.4MHz Switching Frequency



24 5.77 5.3 41.57 3.6 14.4 13.9 18 8.0

50 2.77 2.55 86.6 1.75 6.9 6.7 34.6 3.8

75 1.85 1.7 129.9 1.16 4.6 4.47 51.9 2.57

100 1.38 1.27 173.2 .87 3.46 3.35 69.3 1.92

125 1.1 1.0 216.5 .7 2.77 2.68 86.6 1.54

150 .92 .85 259.8 .58 2.3 2.23 103.9 1.28

175 .79 .72 303.1 .5 1.97 1.91 121.2 1.1

200 .69 .63 346 .43 1.73 1.67 138.6 .96

225 .61 .56 389 .38 1.5 1.49 155.9 .85

250 .55 .51 433 .35 1.38 1.34 173.2 .77

275 .5 .46 476 .31 1.25 1.22 190.5 .7

300 .46 .42 519 .29 1.15 1.2 207 .64

325 .42 .39 562 .26 1.06 1.03 225 .59

350 .39 .36 606 .25 .98 .95 242 .55

375 .36 .34 649.5 .23 .92 .89 259 .51

400 .34 .31 692 .21 .86 .83 277 .48

430 .32 .29 744 .2 .8 .78 297 .44

2MHz Switching Frequency



24 5.77 5.32 41.57 3.65 14.43 13.9 16.63 8.03

50 2.77 2.55 86.6 1.75 6.9 6.7 34.64 3.85

75 1.85 1.7 129.9 1.17 4.6 4.47 51.96 2.57

100 1.38 1.27 173.2 .87 3.46 3.35 69.3 1.93

125 1.1 1.0 216.5 .7 2.77 2.68 86.6 1.54

150 .92 .85 259 .58 2.3 2.23 103.9 1.28

175 .79 .72 303 .5 1.97 1.9 121.2 1.1

200 .69 .63 346 .43 1.7 1.67 138.6 .96

225 .61 .56 389 .38 1.53 1.49 155.9 .85

250 .55 .51 433 .35 1.38 1.34 173.2 .77

275 .5 .46 476 .31 1.26 1.22 190.5 .7

300 .46 .42 519 .29 1.15 1.12 207 .64

325 .42 .39 562 .26 1 1 225 .59

350 .39 .36 606 .25 .98 .95 242 .55

375 .36 .34 649 .23 .92 .89 259 .51

400 .34 .31 692 .21 .86 .83 277 .48

430 .32 .29 744 .2 .8 .78 297 .44

For each switching frequency and duty cycle in the above table, the highest

value for the ∆𝐼𝐿, 𝑅𝐷𝑆(𝑜𝑛), 𝐼𝑠𝑤(𝑝2𝑝), and 𝐼𝑑,𝑅𝑀𝑆 are highlighted in turquoise. For all

switching frequencies and duty cycles, the maximum ∆𝐼𝐿, 𝐼𝑠𝑤(𝑝2𝑝), and 𝐼𝑑,𝑅𝑀𝑆 occur at


27

the minimum 𝑅𝐿of 24Ω while the maximum 𝑅𝐷𝑆(𝑜𝑛) occurs at the maximum 𝑅𝐿of

430Ω. For each switching frequency with 80% duty cycle, the maximum 𝑅𝐷𝑆(𝑜𝑛) is

744Ω. When the duty cycle is 92%, all switching frequencies maximum 𝑅𝐷𝑆(𝑜𝑛) is

297Ω. The values occurring before these common 𝑅𝐷𝑆(𝑜𝑛) are not equal for all

switching frequencies operating in the same duty cycle. This pattern occurs again for

minimum 𝑅𝐷𝑆(𝑜𝑛). For all switching frequencies with a duty cycle of 80%, the

minimum 𝑅𝐷𝑆(𝑜𝑛) is 41.57 for a load resistance of 24Ω. When the duty cycle increased

to 92%, the minimum 𝑅𝐷𝑆(𝑜𝑛) is 18 for a load resistance of 24Ω. This tells us that for

all switching frequency and duty cycle cases, when the load is at the minimum or

maximum, the 𝑅𝐷𝑆(𝑜𝑛) will become equal for all switching frequencies across a

common duty cycle with the used designer inputs.

When selecting a MOSFET, the designer must take into account the

breakdown voltage, power dissipation, and 𝑅𝐷𝑆(𝑜𝑛) of the component and if it will be

the best values for the converter. A desirable breakdown voltage should be 1.5 times

the level of output voltage. In operation mode, it must be verified that the spikes from

the voltage drain are below the MOSFET breakdown voltage. For MOSFET

capacitance, the lower the capacitance value then the lower amount of switching loss

that will occur. The best method for selecting a MOSFET is to select one where during

maximum load, the switching losses will be approximately equal to the conduction

losses. When selecting a single MOSFET for use in all applications, the 𝑅𝐷𝑆(𝑜𝑛) must

be less than the minimum 𝑅𝐷𝑆(𝑜𝑛) that will occur in the system. For this testing, the

minimum 𝑅𝐷𝑆(𝑜𝑛) for an 80% duty cycle will be 41.57, while the minimum 𝑅𝐷𝑆(𝑜𝑛) for

a 92% duty cycle will be 18. The 𝑅𝐷𝑆(𝑜𝑛) of a MOSFET is controlled by the gate

voltage. This allows the user to select a MOSFET suitable for all applications and

dependent on the gate voltage. For this testing, the Si4416DY MOSFET is selected.

The Si4416DY MOSFET is an N-Channel 30-V (D-S) MOSFET. Table 4.3 sums up

the key 𝑅𝐷𝑆(𝑜𝑛) characteristics of the selected MOSFET.


28

Table 4.3 Si4416DY MOSFET Data

𝑽𝑫𝑺(𝑽) 𝑹𝑫𝑺(𝒐𝒏)(Ω) 𝑰𝑫(𝑨)

30V 18m @ 𝑉𝐺𝑆 = 10𝑉 9

28m @ 𝑉𝐺𝑆 = 4.5𝑉 7.3

The diodes selected for SMPS used in this study are Schottky diodes with low

output voltage and capacitance. The selected diode must be able to withstand the peak

input current of the capacitor and be able to dissipate its voltage drop multiplied by the

load current. When deciding on the voltage breakdown of the diode, a value must be

selected that is greater than the output voltage. EMI is minimized in CCM operation

with diodes with soft recovery characteristics. The forward current of the diode must

be greater than the output current appearing in the system. The maximum output

current to occur in the system is 1A. The breakdown voltage must be greater than the

output voltage of the system. Therefore, the diode must have a breakdown voltage

greater than 24V and a forward current greater than 1A. The selected diode for all

applications is the B530C Schottky diode. This diode is from Diodes Inc. and has an

average forward current of 5A and a breakdown voltage of 30V.

The inductor, capacitor, and ESR values are determined using the equations in

Chapter III. For initial testing, the inductor, capacitor, and ESR values will be selected

as the minimum values for a certain switching frequency, duty cycle, and load

resistance. For quick calculations, Excel was used to determine each minimum value

for the set determinants. The resulting minimum values is summed up in Table 4.4.

Table 4.4 Component Calculations



𝑹𝑳(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 24 1.92 3.5 .09 .35 4 .034

50 4 1.67 .18 .74 1.9 .07

75 6 1.2 .28 1.2 1.28 .1

100 8 .83 .375 1.5 .96 .14

125 10 .67 .46 1.9 .77 .18

150 12 .56 .56 2.3 .7 .22


29

175 14 .48 .657 2.6 .55 .25

200 16 .42 .75 3 .48 .28

225 18 .37 .84 3.4 .43 .3

250 20 .34 .93 3.7 .38 .38

275 22 .31 1 4.05 .35 .43

300 24 .28 1.12 4.5 .32 .5

325 26 .26 1.2 5 .28 .52

350 28 .24 1.3 5.2 .26 .55

375 30 .23 1.4 5.5 .25 .56

400 32 .21 1.5 5.9 .21 .58

430 34.4 .2 1.6 6.4 .22 .6

800kHz Switching Frequency 80% Duty Cycle 92% Duty Cycle

𝑹𝑳(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 24 .48 .9 .09 .089 1 .034

50 1 .42 .18 .184 .48 .07

75 1.5 .28 .28 .28 .32 .1

100 2 .21 .375 .37 .24 .14

125 2.5 .17 .46 .46 .2 .18

150 3 .14 .56 .56 .16 .22

175 3.5 .12 .657 .65 .14 .25

200 4 .11 .75 .74 .12 .28

225 4.5 .1 .84 .83 .11 .3

250 5 .09 .93 .92 .096 .38

275 5.5 .08 1 1 .09 .43

300 6 .06 1.12 1.2 .08 .5

325 6.5 .055 1.2 1.25 .075 .52

350 7 .054 1.3 1.3 .07 .55

375 7.5 .052 1.4 1.4 .065 .56

400 8 .05 1.5 1.5 .06 .58

430 8.6 .049 1.6 1.6 .057 .6

1.4MHz Switching Frequency 80% Duty Cycle 92% Duty Cycle

𝑹𝑳(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 24 0.28 0.5 .09 0.05 0.57 .034

50 0.58 0.24 .18 0.11 0.28 .07

75 0.86 0.16 .28 0.16 0.185 .1

100 1.15 0.12 .375 0.21 0.13 .14

125 1.5 0.096 .46 0.27 0.11 .18

150 1.72 0.08 .56 0.32 0.095 .22

175 2 0.07 .657 0.37 0.08 .25

200 2.3 0.06 .75 0.43 0.07 .28

225 2.6 0.055 .84 0.48 0.065 .3

250 2.86 0.05 .93 0.53 0.055 .38

275 3.15 0.045 1 0.58 0.05 .43

300 3.45 0.04 1.12 0.64 0.046 .5

325 3.8 0.39 1.2 0.7 0.042 .52


30

350 4 0.035 1.3 0.74 0.04 .55

375 4.4 0.032 1.4 0.8 0.038 .56

400 4.6 0.03 1.5 0.85 0.034 .58

430 4.92 0.028 1.6 0.91 0.032 .6

2MHz Switching Frequency 80% Duty Cycle 92% Duty Cycle

𝑹𝑳(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 24 0.195 0.35 .09 0.035 0.4 .034

50 0.4 0.17 .18 0.075 0.195 .07

75 0.6 0.12 .28 0.12 0.13 .1

100 0.8 0.085 .375 0.15 0.097 .14

125 1 0.07 .46 0.185 0.08 .18

150 1.2 0.06 .56 0.23 0.065 .22

175 1.4 0.05 .657 0.26 0.055 .25

200 1.6 0.045 .75 0.3 0.05 .28

225 1.8 0.04 .84 0.35 0.045 .3

250 2 0.035 .93 0.37 0.04 .38

275 2.2 0.03 1 0.41 0.036 .43

300 2.4 0.028 1.12 0.45 0.033 .5

325 2.6 0.026 1.2 0.5 0.032 .52

350 2.8 0.025 1.3 0.52 0.03 .55

375 3 0.022 1.4 0.58 0.028 .56

400 3.2 0.021 1.5 0.6 0.025 .58

430 3.5 0.019 1.6 0.65 0.023 .6

For the table above, the maximum values for each switching frequency and

duty cycle minimum inductor, capacitor, and maximum capacitor ESR values are

highlighted in turquoise. When examining these recommended values, there are

several conclusions that can be determined. For the particular design under test, the

ESR values will remain constant for all switching frequencies with the same duty

cycle. The highest minimum inductor and maximum capacitor ESR values will occur

at maximum load of 430Ω. The highest minimum capacitor value will occur at the

minimum load of 24Ω. Table 4.5 shows statistical analysis of each switching

frequency and duty cycle inductor, capacitor, and capacitor ESR values.


31

Table 4.5 Statistical Component Variables



𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) Average 18.01882 0.692353 0.837765 3.367059 0.784706 0.319412 Median 18 0.37 0.84 3.4 0.43 0.31

Standard

Deviation 9.844438 0.799901 0.458407 1.819052 0.913076 0.179328



𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) 𝑳(𝝁𝑯) 𝑪(𝝁𝑭) 𝑪𝑬𝑺𝑹(𝛀) Average 4.504706 0.174118 0.837765 0.843118 0.197824 0.319412 Median 4.5 0.1 0.84 0.83 0.11 0.31

Standard

Deviation 2.46111 0.204818 0.458407 0.464364 0.227794 0.179328




Standard

Deviation 1.417169 0.131564 0.458407 0.261184 0.13025 0.179328




Standard

Deviation 0.990113 0.080075 0.458407 0.186165 0.091045 0.179328

It is concluded form the tables 4.4 and 4.5 that there are common appearing

patters among the statistical analysis of the minimum inductor, capacitor, and

maximum capacitor ESR for each switching frequency and duty cycle. As the

switching frequency is increased, the highest minimum inductor value will decrease.

Along with this conclusion, the average, median, and standard deviation of all

minimum inductor values will decrease as the switching frequency decreased. When

viewing across common switching frequencies, it is apparent that as the duty cycle

increases, the average, median, and standard deviation of the inductor will decrease.


32

When examining the patterns with the minimum capacitor values, it is noticeable that

as the switching frequency increases, the average, median, and standard deviation of

the capacitor values will decrease. As the duty cycle across a single switching

frequency is increased, the average, median, and standard deviation capacitor values

will increase. For all switching frequencies operating with an equal duty cycle, the

average, median, and standard deviation capacitor ESR maximum values will be

equal.

4.4 Results

After reviewing the pattern for recommended minimum inductor and capacitor

values and maximum capacitor ESR values, it is time to test each switching frequency

and duty cycle recommended minimum design values. Each case for switching

frequency and duty cycle was examined to see the EMI effect on the input to the

DC/DC boost converter. The results of these cases are summed up in Table 4.7.

Table 4.7 EMI Result of Simulated Converter

200kHz Switching Frequency Duty Cycle 80% 92%

𝑹𝑳(𝛀) Emission Level(dB)

24 9.2 -2.6

50 9.6 -1.98

75 9.65 0.87

100 9.56 1.13

125 9.45 1.58

150 9.59 1.64

175 9.68 1.79

200 9.86 1.84

225 9.65 1.89

250 9.54 1.9

275 9.53 2

300 9.5 2.002

325 9.42 2.006

350 9.35 2.01

375 9.33 1.99

400 9.29 1.98

430 9.28 1.97


Duty Cycle 80% 92%


24 9.1 -3.4


33

50 9.5 -1.93

75 9.6 -0.46

100 9.63 0.77

125 9.6 -0.24

150 9.55 -1.25

175 9.5 1.42

200 9.45 -0.2

225 9.38 -1.82

250 9.29 1.69

275 9.2 1.72

300 9.13 1.75

325 9 1.8

350 8.95 1.84

375 8.8 1.86

400 8.76 1.89

430 8.64 1.91


Duty Cycle 80% 92%


24 6.74 -5.97

50 7.1 -1.47

75 7.15 -1.53

100 7.18 -1.66

125 7.2 -1.01

150 7.14 -0.36

175 7.2 -1

200 9 -1.62

225 9.5 -2.24

250 9.6 -0.758

275 9.2 -1.718

300 9.3 -2.678

325 9.35 -3.638

350 9.4 -0.6

375 9.35 -0.58

400 9.3 -0.56

430 9 -0.54


Duty Cycle 80% 92%


24 8.5 -5.16

50 8.99 -4.5

75 9.12 -2.9

100 9.2 -0.33

125 9.17 -0.65

150 9.16 0.25

175 9.14 0.528

200 9.12 0.62


34

225 9.07 0.76

250 9.02 0.894

275 8.99 0.96

300 8.9 1.06

325 8.8 1.1

350 8.77 1.145

375 8.7 1.2

400 8.6 1.24

430 8.48 1.26

When viewing the effect of each load increase in the emission level, it is seen

that the emission level will increase until a pivot load point, at which the emission

level will start to decrease for each load change. For 200kHz and 800kHz switching

frequencies operating at an 80% duty cycle, the pivot point will occur for a load of

200Ω which is a 43% load. For switching frequencies of 1.4MHz and 2MHz operating

with a duty cycle of 80%, the pivot point will occur at a 250Ω load which is a 55%

load. When the duty cycle is increased to 92%, the pivot point for 200kHz, 800kHz,

and 1.4MHz will occur when the load is 350Ω or 80% load. When the switching

frequency is 2MHz and the duty cycle is 92%, no pivot point occurs in the changing

load. Statistical methods are now used to better analyze the resulted EMI level for the

evaluated duty cycle and switching frequency cases. Table 4.8 shows the statistical

results of the changing switching frequencies, duty cycle, and load resistance.

Table 4.8 Statistical Results of EMI Levels


Duty Cycle 80% 92%

Emission Level(dB)

Average 9.49 1.29

Median 9.53 1.89

Standard Deviation .16 1.35


Duty Cycle 80% 92%

Emission Level(dB)

Average 9.24 .43

Median 9.29 1.42



Duty Cycle 80% 92%

Emission Level(dB)


35

Average 8.39 -1.37

Median 9 -1.01

Standard Deviation 1.09 1.75


Duty Cycle 80% 92%

Emission Level(dB)

Average 8.92 -.15

Median 8.99 .76


When inspecting the results of Table 4.8, several conclusions can be made. The

average emission level and median emission level for megahertz switching

frequencies is less than those for kilohertz switching frequencies. Increasing the duty

cycle of the system will further decrease the EMI average and median value for all

switching frequencies. Of the cases studied, the best result for EMC regulation was

when the switching frequency was 1.4MHz and the duty cycle was 92%. This shows

that there is a set range with maximum and minimum switching frequency values that

will result in the strongest EMC compliance of the system.

The goal of the test conducted in this chapter was to evaluate DC/DC boost

converter EMI results at the most detailed level. Application for converters that will

only operate for a certain load, switching frequency, and duty cycle is not common in

todays engineering practice. It is desired for any system to be operable with a range of

conditions. This helps further increase the confidence of a system to meet EMC

standards when placed in interference with other system. Now that the detailed effect

of changing operation variables will effect a system, the next step is to design a system

that will operate as desired with changing variables.


36

CHAPTER V

MODIFYED DESIGN OF SMPS

The second analysis of the Chapter III design method will focus on making a

broader application SMPS circuit. The new SMPS circuits will have the same

inductor, capacitor, and capacitor ESR value for all switching frequencies, duty cycles,

and load resistance. It is higher desired for a SMPS to be designed for more than one

load resistance, duty cycle, and switching frequency application. To achieve common

component values, the component calculation equations from Chapter III will be

changed.

5.1 Component calculation and selection

In order to determine the best component value for use in all switching

frequencies and duty cycles, common equations have to determined that will yield an

equal value for all cases. When observing the results of Chapter IV analysis, it is seen

that the switching frequency has a large effect on the EMI results of a converter. Due

to this observation, a set of equations was created to create a common variable among

all switching frequencies. This set of equations are summed up in Table 5.1.

Table 5.1 Modified Component Calculation Equations

Initial Calculations

𝑝𝑘 𝑓𝑠

1𝑘

𝐿min (𝑅𝐿max) (1 − 𝐷𝑚𝑖𝑛)2 × 𝐷𝑚𝑖𝑛 × 𝑅𝐿(max)

2 × 𝑓𝑠

∆𝐼𝐿𝑚𝑎𝑥 𝑉𝑖𝑛(max) × 𝐷𝑚𝑎𝑥

𝑓𝑠 × 𝐿min (𝑅𝐿max)

𝐼𝑠𝑤(𝑝2𝑘)𝑚𝑎𝑥

𝐼𝑠𝑤(𝑝2𝑘) = √𝐷𝑚𝑖𝑛 (𝑃𝑜

𝑉𝑖𝑛(max))

2

+∆𝐼𝐿𝑚𝑎𝑥

2

12

𝐶min (𝑅𝐿min) 𝐷𝑚𝑎𝑥

𝑅𝐿(min) × 𝑓𝑠 × .48

Components Calculations

Inductor 𝐿min (𝑅𝐿max)

100× 𝑝𝑘


37

Capacitor 𝐶min (𝑅𝐿min) × 𝑓𝑠 × 100

𝐶𝐸𝑆𝑅 𝑉𝑟𝑖𝑝

𝐼𝑠𝑤(𝑝2𝑘)𝑚𝑎𝑥

The common variable for switching frequencies was set at 1 kHz because that

is the lowest prefix multiplier of all used switching frequencies. The variable, 𝑝𝑘

represents the ratio of the switching frequency being used to the 1 kHz base frequency.

The maximum inductor peak to peak current (∆𝐼𝐿𝑚𝑎𝑥) is the maximum ∆𝐼𝐿 that will

appear in the system for all duty cycles of a single switching frequency. This values is

constant for changing duty cycles and load resistance in a single switching frequency

and will change value only if the switching frequency is changed. The maximum

switching current (𝐼𝑠𝑤(𝑝2𝑘)𝑚𝑎𝑥) is the highest switching current that will appear in a

converter for a constant switching frequency. The maximum switching current will

only change when the switching frequency is changed and will not depend on any

other variables of the converter. The inductor component value is calculated using the

maximum 𝐿𝑚𝑖𝑛 to be required in the system, which occurs at the load resistance of

430Ω. The inductor switching frequency is then related to the common switching

variable by use of the calculated variable, 𝑝𝑘. It was noticed in past experiments that

as the inductor increases, the EMI level will decrease. The inductor is therefore

multiplied by a factor to further minimize the EMI appearing in the system. The factor

of 100 was selected because it is the approximate ratio between the minimum

inductance at a duty cycle of 50% and the minimum inductance at duty cycles of 80%-

92%. The capacitor for the modified DC/DC Converter is calculated by using the

minimum required capacitance for all load resistance application. The capacitor is then

multiplied by 100 to equate to the inductor value increasing by a multiplication of 100.

The capacitor ESR value is calculated to be the minimum maximum ESR value

allowed. The minimum ESR max occurs when the load resistance is at its minimum of

24Ω. Using the maximum switching current (𝐼𝑠𝑤(𝑝2𝑘)𝑚𝑎𝑥) that will appear in the

system. By using the process of equations from Table 5.1, the effect of duty cycle and

load resistance on component values is depleted. Component values are then only


38

depended on switching frequency and then made common across all switching

frequencies by use of a common variable. This is proven in Table 5.2.

Table 5.2 Applied Modified Calculations

200kHz Switching Frequency Duty Cycle 80% 92%

𝑝𝑘 200𝑘

1𝑘= 200

200𝑘

1𝑘= 200

𝐿min(𝑅𝐿max)(𝐴) (1 − .8)2 × .8 × 430

2 × 200𝑘= 34.4

(1 − .8)2 × .8 × 𝑅𝐿(max)

2 × 200𝑘= 34.4

∆𝐼𝐿𝑚𝑎𝑥(𝐴) 4.8 × .92

200𝑘 × 34.4= .64

4.8 × .92

200𝑘 × 34.4= .64

𝐼𝑠𝑤(𝑝2𝑘)𝑚𝑎𝑥(𝐴)

√. 8 (24

4.8)

2

+. 642

12= 4.475 √. 8 (

24

4.8)

2

+. 642

12= 4.475

𝐶min(𝑅𝐿min)(µ𝐹) . 92

24 × 200𝑘 × .48= 4

. 92

24 × 200𝑘 × .48= .399

Inductor(𝝁𝑯) 34.4

100× 200 = 68.8

34.4

100× 200 = 68.8

Capacitor(𝝁𝑭) 4µ × 200𝑘 × 100 = 79.8 . 399µ × 2𝑘 × 100 = 79.8

𝑪𝑬𝑺𝑹(𝛀) . 48

4.475= .1

. 48

4.475= .1


Duty Cycle 80% 92%

𝑝𝑘 800𝑘

1𝑘= 800

800𝑘

1𝑘= 800

𝐿min(𝑅𝐿max)(𝐴) (1 − .8)2 × .8 × 430

2 × 800𝑘= 8.6

(1 − .8)2 × .8 × 430

2 × 800𝑘= 8.6

∆𝐼𝐿𝑚𝑎𝑥(𝐴) 4.8 × .92

800𝑘 × 8.6= .64

4.8 × .92

800𝑘 × 8.6= .64


√. 8 (24

4.8)

2

+. 642

12= 4.475 √. 8 (

24

4.8)

2

+. 642

12= 4.475


24 × 800𝑘 × .48= 1

. 92

24 × 800𝑘 × .48= 1


100× 800 = 68.8

8.6

100× 800 = 68.8

Capacitor(𝝁𝑭) 1µ × 800𝑘 × 100 = 79.8 1µ × 800𝑘 × 100 = 79.8

𝑪𝑬𝑺𝑹(𝛀) . 48

4.475= .1

. 48

4.475= .1


39

1.4MHz Switching Frequency Duty Cycle 80% 92%

𝑝𝑘 1.4𝑀

1𝑘= 1.4𝑘

1.4𝑀

1𝑘= 1.4𝑘

𝐿min(𝑅𝐿max)(𝐴) (1 − .8)2 × .8 × 430

2 × 1.4𝑀= 4.914

(1 − .8)2 × .8 × 430

2 × 1.4𝑀= 4.914

∆𝐼𝐿𝑚𝑎𝑥(𝐴) 4.8 × .92

1.4𝑀 × 4.914= .64

4.8 × .92

1.4𝑀 × 4.914= .64


√. 8 (24

4.8)

2

+. 642

12= 4.475 √. 8 (

24

4.8)

2

+. 642

12= 4.475


24 × 1.4𝑀 × .48= .6

. 92

24 × 1.4𝑀 × .48= .6


100× 1.4𝑘 = 68.8

4.914

100× 1.4𝑘 = 68.8

Capacitor(𝝁𝑭) . 6µ × 1.4𝑀 × 100 = 79.8 . 6µ × 1.4𝑀 × 100 = 79.8 𝑪𝑬𝑺𝑹(𝛀) . 48

4.475= .1

. 48

4.475= .1

2MHz Switching Frequency Duty Cycle 80% 92%

𝑝𝑘 2𝑀

1𝑘= 2𝑘

2𝑀

1𝑘= 2𝑘

𝐿min(𝑅𝐿max)(𝐴) (1 − .8)2 × .8 × 430

2 × 2𝑀= 3.44

(1 − .8)2 × .8 × 430

2 × 2𝑀= 3.44

∆𝐼𝐿𝑚𝑎𝑥(𝐴) 4.8 × .92

2𝑀 × 3.44= .64

4.8 × .92

2𝑀 × 3.44= .64


√. 8 (24

4.8)

2

+. 642

12= 4.475 √. 8 (

24

4.8)

2

+. 642

12= 4.475


24 × 2𝑀 × .48= .4

. 92

24 × 2𝑀 × .48= .4


100× 2𝑘 = 68.8

3.44

100× 2𝑘 = 68.8

Capacitor(𝝁𝑭) . 4µ × 2𝑀 × 100 = 79.8 . 4µ × 2𝑀 × 100 = 79.8 𝑪𝑬𝑺𝑹(𝛀) . 48

4.475= .1

. 48

4.475= .1

By observing the above table, it is apparent that the key to having equal

component values for all switching frequencies and duty cycles is to have equal

∆𝐼𝐿𝑚𝑎𝑥 and 𝐼𝑠𝑤(𝑝2𝑘)𝑚𝑎𝑥 vales. These values for application with the original design

parameters are constant .64 and 4.47 respectively.


40

5.2 Results

The result of the design method for this chapter is a DC/DC converter with a

constant 68.8µH inductor, 79.86µF capacitor, and a .1Ω capacitor ESR. The goal of

designing a DC/DC Converter in the manor shown in this chapter is to increase the

application range for the DC/DC Converter by having a constant components for a

converter with alternate inputs and loads. The result of this method is shown in

Figures 5.1 – 5.8.

Figure 5.1 Simulation Results of Converter A before Filter


41

Figure 5.2 Simulation Results of Converter B before Filter

Figure 5.3 Simulation Results of Converter C before Filter

Figure 5.4 Simulation Results of Converter D before Filter


42

Figure 5.5 Simulation Results of Converter E before Filter

Figure 5.6 Simulation Results of Converter F before Filter


43

Figure 5.7 Simulation Results of Converter G before Filter

Figure 5.8 Simulation Results of Converter H before Filter

The magnified results of Figures 5.1 – 5.8 around the switching frequency is

found in Appendix A. Table 5.3 shows the range of EMI levels around the used

switching frequency for each simulation


44

Table 5.3 EMI Results Before Filter

Switching

Frequency

200kHz 800kHz 1.4MHz 2MHz

Duty Cycle 80% 92% 80% 92% 80% 92% 80% 92% Max EMI(dB) 4.4 -4.4 -1.8 -11 -8.3 -17 -9.5 -20 Min EMI(dB) 3.35 -5.25 -2.85 -14 -9.8 -23 -10.6 -23.1

Concluding from the table above, the modified converter design method yields

a positive EMI result. It can be observed that as the duty cycle increased, the range

between the maximum EMI level and the minimum EMI level will increase as well.

This can affect the design of a system operating with multiple load resistance by the

inability to confidently know the EMI result from between maximum and minimum

load values. The EMI results are well improved but do not meet the standards for

CISPR22. In order to pass the CISPR22 requirements, an input filter must be applied

to the circuit.


45

CHAPTER VI

FILTER APLLICATION FOR MODIFIED SMPS DESIGN

There are many types of input filters for SMPS. Each input filter design has its

own set of tradeoffs. These tradeoffs can be evaluated to determine which type of

input filter will be most beneficial for various applications. The basic filter topologies

are pi, T, and L.

When deciding the filter layout, the designer must consider the power and

signal flow of the system. The best filter designs are typically balanced by making the

filter thin and long to reduce the coupling capacitance and increase the impedance

occurring between input and output. The attenuation ability of the system decreases

when the SMPS is operating are the self-resonant frequency of the components. When

designing EMI filters, it is common not to focus on the line and load impedance of the

system being the same as the impedances for the designed filter, creating an

unmatched setup. These various basic principles for designing a SMPS input filter are

evaluated throughout this chapter.

6.1 Input filter topologies

The common input filters for use in DM suppression are the pi, T, and L filters.

The input filter is placed between the LISN and SMPS. Pi filters offer the advantage

of coupling with the LISN and increasing the order of the filter and are commonly

used in designs where there is a large bus cap connected to the output of the filter. The

T filter features an inductive input and output which benefits the input overshoot

voltage protection ability. Without the input capacitor, like the one used in a pi filter,

there is not a time delay in the charging which allows the voltage of the T filter to rise

faster. T filters are best used in situations where there are difficult lines present. The

key disadvantage of the T filter is the output connection to the SMPS. The capacitor

facing the SMPS in this topology can block some of the current and voltage flowing to

the SMPS when not properly designed. The L filter is a good compromise between the

pi and T filters. In typical L filter application, a double L may be needed. The


46

disadvantage of the L filter is the fact that it only has two elements which only allows

it to offer 12dB loss per octave. The design of these three filters are shown in Figures

6.1 through 6.3.

Figure 6.1 Pi Filter Schematic

Figure 6.2 L Filter Schematic

Figure 6.3 T Filter Schematic

6.2 Design process

There are many recommended methods for calculating the components for

input filter topologies. The common denominator for all filter design methods is to

determine the required level of attenuation needed for the system. This is

accomplished by first determining the initial level of EMI present in the system before

a filter is added. The method for determining the needed level of attenuation will vary

from method to method. After the common principle of first determining required

attenuation is completed, the remaining steps for the input filter design will change

from method to method. The used design process for this study is based off an

approach by Alfred Hesener in his research paper titled “Electromagnetic Interference

(EMI) in Power Supplies.” This design method uses the approach of adding multiple


47

filter stages until the design is at or below the required attenuation. For the purpose of

this research, only one filter stage will be used for evaluation. Heseners design method

will also simultaneously design a pi, T, and L filter.

The steps for design are summed up below.

1. Determine the parameters summed up in Table 6.1

Table 6.1 Filter Parameters

Minimum input voltage 𝑉𝑚𝑖𝑛 = 1.92𝑉

Max output current 𝐼𝑜𝑢𝑡(max) = 1𝐴

Switching frequency 𝑓𝑠𝑤

2. Calculate the design impedance (𝑍𝑑)

𝑍𝑑 =𝑉𝑖𝑛𝑚𝑖𝑛

∆𝐼𝐿𝑚𝑎𝑥=

1.92

1= 1.92 (6.1)

3. Select cut off frequency (𝑓𝑐𝑢𝑡) in the range of 𝑓𝑠(.01 𝑡𝑜 .1)

4. Calculate the capacitor and inductor vales using the equations below

𝐿𝑓 =𝑍𝑑

2𝜋𝑓𝑐𝑢𝑡 (6.2)

𝐶𝑓 =1

2𝜋𝑓𝑐𝑢𝑡𝑍𝑑 (6.3)

5. Use the table below to calculate the inductor and capacitor values for each input filter

topology

Table 6.2 Filter Component Equations

Pi Filter

Inductor 𝐿𝑓

Capacitors 𝐶𝑓1 = 𝐶𝑓2 =

𝐶𝑓

2

T Filter

Inductors 𝐿𝑓1 = 𝐿𝑓2 =

𝐿𝑓

2

Capacitor 𝐶𝑓

L Filter

Inductor 𝐿𝑓

Capacitor 𝐶𝑓

6. Apply calculated components to the appropriate input filter design and test results to

determine if another stage needs to be added.


48

6.2.1 Applied filter process

Components need to be large enough to be able to handle the peak currents

occurring in the system and provide sufficient damping. However, the components

should not be so large that it would lower the self-resonant frequency, which is

dependent on the parasitic capacitance and inductance. This must be taken into

consideration when viewing the resulting component recommended values. The steps

stated in the section above are now to be applied to the various switching frequency

and duty cycle designs as shown below.

Table 6.3 Filter Component Calculations

Minimum input voltage 𝑉𝑚𝑖𝑛 = 1.92𝑉

Max output current 𝐼𝑜𝑢𝑡(max) = 1𝐴

Switching frequency 𝑓𝑠𝑤

𝑍𝑑 𝑉𝑖𝑛𝑚𝑖𝑛

∆𝐼𝐿𝑚𝑎𝑥=

1.92

1= 1.92


𝑓𝑐𝑢𝑡 200𝑘(. 05) = 10𝑘

𝐿𝑓 𝐿𝑓 =

1.92

2𝜋10𝑘= 30.5𝜇𝐻

𝐿𝑓1, 𝐿𝑓2 𝐿𝑓1 = 𝐿𝑓2 =

30.5𝜇𝐻

2= 15.25𝜇𝐻

𝐶𝑓 𝐶𝑓 =

1

2𝜋10𝑘(1.92)= 8.29𝜇𝐹

𝐶𝑓1, 𝐶𝑓2 𝐶𝑓1 = 𝐶𝑓2 =

8.29𝜇

2= 4.14𝜇𝐹


𝑓𝑐𝑢𝑡 800𝑘(. 05) = 40𝑘

𝐿𝑓 𝐿𝑓 =

1.92

2𝜋40𝑘= 7.6𝜇𝐻


7.6𝜇𝐻

2= 3.8𝜇𝐻

𝐶𝑓 𝐶𝑓 =

1

2𝜋40𝑘(1.92)= 2.07𝜇𝐹


2.07𝜇

2= 1.03𝜇𝐹


𝑓𝑐𝑢𝑡 1.4𝑀(. 05) = 70𝑘

𝐿𝑓 𝐿𝑓 =

1.92

2𝜋70𝑘= 4.36𝜇𝐻


49


4.36𝜇𝐻

2= 2.18𝜇𝐻

𝐶𝑓 𝐶𝑓 =

1

2𝜋70𝑘(1.92)= 1.18𝜇𝐹


1.18𝜇

2= .59𝜇𝐹


𝑓𝑐𝑢𝑡 2𝑀(. 05) = 100𝑘

𝐿𝑓 𝐿𝑓 =

1.92

2𝜋100𝑘= 3.05𝜇𝐻


3.05𝜇𝐻

2= 1.52𝜇𝐻

𝐶𝑓 𝐶𝑓 =

1

2𝜋100𝑘(1.92)= .83𝜇𝐹


. 83𝜇

2= .41𝜇𝐹

6.3 Results

Out of the past two tests, the best results occurred when the common

component values were applied to the various switching frequency and duty cycle

converters. The Pi, T, and L filters are now applied to those circuits to further improve

the EMI level and help determine which filter is best for various switching frequency

and duty cycles converters designed with the method presented in this thesis. The

simulation results of the filters application to each converter design tested is shown in

the figures below.


50

Figure 6.4 Simulation Results of Converter A with Pi Filter

Figure 6.5 Simulation Results of Converter A with L Filter


51

Figure 6.6 Simulation Results of Converter A with T Filter

Figure 6.7 Simulation Results of Converter B with Pi Filter


52

Figure 6.8 Simulation Results of Converter B with L Filter

Figure 6.9 Simulation Results of Converter B with T Filter


53

Figure 6.10 Simulation Results of Converter C with Pi Filter

Figure 6.11 Simulation Results of Converter C with L Filter


54

Figure 6.12 Simulation Results of Converter C with T Filter

Figure 6.13 Simulation Results of Converter D with Pi Filter


55

Figure 6.14 Simulation Results of Converter D with L Filter

Figure 6.15 Simulation Results of Converter D with T Filter


56

Figure 6.16 Simulation Results of Converter E with Pi Filter

Figure 6.17 Simulation Results of Converter E with L Filter


57

Figure 6.18 Simulation Results of Converter E with T Filter

Figure 6.19 Simulation Results of Converter F with Pi Filter


58

Figure 6.20 Simulation Results of Converter F with L Filter

Figure 6.21 Simulation Results of Converter F with T Filter


59

Figure 6.22 Simulation Results of Converter G with Pi Filter

Figure 2.23 Simulation Results of Converter G with L Filter


60

Figure 6.24 Simulation Results of Converter G with T Filter

Figure 6.25 Simulation Results of Converter H with Pi Filter


61

Figure 6.26 Simulation Results of Converter H with L Filter

Figure 6.27 Simulation Results of Converter H with T Filter

When comparing all three filter applications for 200kHz and 80% duty cycle

simulation, it is determined that the Pi and L filter will yield a passing EMI level while

the T filter will not pass CISPR22s standards. When the duty cycle was increased to

92%, all three filter designs passed standards with the best result being when the Pi

filter was used. For an 800kHz switching frequency and 80% duty cycle, all three

filters passed standards but a higher margarine then the 200kHz switching frequency


62

application. The Best result for the 800kHz and 80% duty cycle was when the Pi filter

was used. As the duty cycle of the 800kHz simulation increased to 92%, the EMI

levels further decreased and the Pi filter had the best results. The switching frequency

was then further increased to 1.4MHz with an 80% duty cycle. This simulation

resulted only the Pi and L filters to pass the standards for all frequency ranges. The Pi

filter started showing a spike around the 200kHz frequency but was below standards

requirement. The T filter pass standards for 600kHz and above, but failed standards

around the 200kHz frequency. The duty cycle was then increased to 92% which

resulted in the passing of all filters by standards requirements. The strongest result was

with the Pi filter. For 2MHz switching frequency, all duty cycles and filters passed

CISPR22 standards. The best results was when the duty cycle was at 92%. This

concluded in a lower amount of spikes along the frequency range. The magnified

switching frequency results for the simulations above are found in Appendix B. Table

6.4 shows the resulting EMI range for all switching frequencies, duty cycles, and filter

applications simulated in this chapter.

Table 6.4 Resulting EMI Range for Filter Application


Duty Cycle 80% 92%

EMI Range (dB)

Pi Filter -89…-92 -99.2…-102.4

L Filter -51…-53 -61.5…-63.5

T Filter -11…-14 -61.8…-65


Duty Cycle 80% 92%

EMI Range (dB)

Pi Filter -109.6…-111.2 -122…-130

L Filter -70.5…-72 -89.6…-90.7

T Filter -70.4…-71.5 -88…-93.5


Duty Cycle 80% 92%

EMI Range (dB)

Pi Filter -109…-110 -111…-114

L Filter -69.7…-71 -71.3…-72.7

T Filter -69…-70.5 -71…-76.7



63

Duty Cycle 80% 92%

EMI Range (dB)

Pi Filter -110…-112 -135.7…-138

L Filter -70.5…-72 -113.5…-117

T Filter -70.9…-72.5 -100…-112.5


64

CHAPTER VII

RESULTS

The research conducted in this thesis started with analysis of a proposed

method for designing DC/DC boost converters with components values influenced by

multiple variables. This analysis was conducted in Chapter IV and concluded with a

stronger understanding of how design and output variables can affect the selection of a

converters components values and how it will affect the EMI resulting from the

converter. It was observed that when increasing the duty cycle of a converter, the EMI

in the system will decrease, and increasing the switching frequency will further

decrease the EMI in the system up to a certain point. This test was the first time that

this patter appear and it remained a reoccurring pattern for all tests conducted in this

research.

The first design method from Chapter IV, focused on allowing load resistance,

duty cycle, and switching frequency to effect the component values. The second

design method found in Chapter V, used maximum and minimum values for duty

cycles and load resistance to determine component values and then used a common

variable to relate all switching frequencies to one another and calculated component

values. The goal of this was to decrease the amount of variables that affect the

component value in the system to only the variables defined by the user at initial

design. As a result, a constant set of component values were recommended for all 8

converters under test. This yielded a positive effect on all tested converters from the

previous study.

Chapter V showed an improved method for designing DC/DC boost

converters. This method was then further improved in Chapter VI when filters were

applied. Three filter types were analyzed for each converter. These filter types were

the Pi, L, and T filter. The effect that each filter made on the 8 converter types varied

from converter to converter. This resulted in the ability to determine the assignment of

filter types to converter types. The analysis and assignment of components and filters

for each converter type is conducted below.


65

7.1 Comparison of converter A and B test results

To recall, the converter A had a switching frequency of 200kHz and a duty

cycle of 80% while the converter B had the same switching frequency but operated

with a 92% duty cycle. For all three test methods conducted, this pair constantly had

the highest resulting level of EMI out of all other converter pairs. The converter A

continually had a higher EMI level than the second, making this converter the least

desired converter for applications requiring EMC CISPR22 standards to be meet. The

required maximum EMI level for this switching frequency to meet CISPR22 standards

is -40 dB.

7.1.1 Converter A

When the method for converter design in Chapter IV was applied to converter

1, the EMI level was in the range of 9.2 dB - 9.86 dB. This range improved when the

modified method from Chapter V was applied. The resulting range decreased to 4.4

dB - 3.35 dB. With a required maximum allowable EMI level of -40, converter A from

the Chapter V test method was 44.4 dB - 43.35dB above the standard line. Chapter VI

then applied a Pi filter to the modified converter A. This resulted in an EMI range of -

92 dB to -89 dB. The Pi filter was then removed and an L filter was applied to the

converter. As a result, the EMI range values were increased to -53 dB to -51 dB. This

was still a passing result yet had a lower desired EMI level then with the Pi filter. The

final filter applied to converter A was the T filter. This further increased the values for

the EMI range to a level that would not pass CISPR22 standards. This resulting EMI

range was -11 dB to -14dB. It is noticed that all filters when applied to converter A

resulted in a 3 dB range interval. The strongest application for converter A is when

method two is used for component selection and a Pi input filter designed in Chapter

VI is used.


66

7.1.2Converter B

For Chapter IV analysis of converter 2, the EMI range was shown to be -2.6

dB to 2.01 dB. This range is an improvement from the initial range resulting from

converter 1. When the modified method from Chapter V was applied to converter 1,

the EMI range resulted in -5.25 dB to -4.4 dB. The interval for this range was slightly

increased then the previous converter 2 range. In order to comply with EMC

standards, the EMI level must decrease by at least 35.6 dB. This requirement was meet

by use of any of the three tested input filters. When use of a Pi filter applied to the

modified converter 1, the EMI level decreases to a range of -99.2 to -102.4. This range

is well within the CISPR22 requirements. The L and T filter resulted in EMI ranges of

-61.5 dB to -63.5 dB and -61.8 dB to -65 dB respectively. This is a slightly unexpected

result when comparing to the results of the L and T filter with converter 1. The change

between the L and T filter range in converter 1 was much larger than what is observed

when the L and T filter are applied to converter 2. For applications with converter 2,

there is not a strong case for picking the L filter as opposed to the T filter because their

resulting range values are within 3 dB of one another. The Pi filter far surpassed the

results of the L and T filter for converter 2. Making the Pi filter the most

recommended filter for the modified converter 2 design, yet the L and T filters are

appropriate substitutes for the Pi filter.

7.2 Comparison of converter C and D test results

Converters C and D both operate with a switching frequency of 800kHz.

Converter C uses a duty cycle of 80% and converter D uses a duty cycle of 92%. Both

of these converter had lower EMI results when comparing to its equivalent duty cycle

converter A or B. The CISPR22 maximum allowable EMI level for 800kHz is -65 dB.

Both converter C and D were able to meet this requirement.

7.2.1 Converter C

Converter C did not pass the EMC requirements until an input filter was

applied to the converter. For initial testing in Chapter IV, converter C had and EMI


67

range of 8.64 dB to 9.63 dB. When the modified approach for determining component

values was used, the EMI level ranged from -1.8 dB to -2.85 dB. This required the

input filter to attenuate the EMI level down by at least 63.2 dB. When the Pi input

filter was used on the modified converter, the EMI level meet the requirement and

resulted in a maximum EMI level of -109.6 dB. For L filter application, the EMI

level was in the range of -70.5 dB to -72 dB. Lastly, when the T filter was inputted on

the converter, the EMI level was in the range of

-70.4 dB to -71.5 dB.

7.2.2 Converter D

For application with converter D, the design must feature one of the input

filters with the modified converter in order to pass CISRP22 standards. For initial

testing, the maximum level of EMI appearing is the system was 1.91 dB. After

modified testing, the EMI level decreased to a maximum value of -11 dB. When the

Pi, T and L input filters were applied to converter D, the maximum EMI levels were -

122 dB, -89.6 dB, and -88 dB respectively.

7.3 Comparison of converter E and F test results

Converters E and F were the converters assigned to operate with a 1.4MHz

switching frequency. Converter E operated with an 80% duty cycle and converter F

operated with a 92% duty cycle. The maximum allowable EMI level for these two

converter at 1.4MHz was -65 dB.

7.3.1 Converter E

Converter E had a maximum 9.6 dB EMI level when operating in the initial

test method of Chapter IV and had a resistive load of 250 Ω. When designed with the

modified method of Chapter V, the resulting EMI level was in the range of -8.3 dB to -

9.8 dB. When using a Pi input filter, the EMI ranged from -109 dB to -110 dB. The

EMI range increased when use of a L or T filter was applied. The ranges for the L and

T filter were close with the L filter having a range of -69.7 dB to -71 dB and the T

filter having a range of -69 dB to


68

-70.5 dB. All tested filters are appropriate for applications requiring converter E.

7.3.2 Converter F

The average EMI level of converter F test conducted in Chapter IV was -1.37

dB. This was a strong EMI level when compared to the other converters in this initial

testing. After reanalyzing converter F with the modified method from Chapter V, the

EMI level ranged from -17 dB to -23 dB. This EMI range is so far the lowest out of all

other compared converters for this stage of design. Using the Pi filter with the

modified converter F, the EMI level was in the range of -122 dB to -130 dB. This

range is the lowest determined for all tested converters and all tested filters with each

converter. When the L and T filter are placed at the input of converter F, the resulting

maximum EMI level was

-89.6 dB for the L filter and -88 dB for the T filter.

7.4 Comparison of converter G and H test results

Converter G and H operated at the highest switching frequency tested in this

thesis of 2MHz. Converter G operated with a 80% duty cycle and converter H

operated with a 92% duty cycle. The maximum allowable EMI level at 2MHz is -65

dB.

7.4.1 Converter G

Initial analysis of converter G resulted in a maximum EMI level of 9.2 dB and

a minimum level of 8.48 dB. When the modified converter was used, the EMI level

ranged from -9.5 dB to -10.6 dB. With application of the Pi, L, and T filter, the

maximum EMI levels resulted in -110 dB, -70.2 dB, and -70.9 dB respectively. With

the use of the Pi filter, a spike around 200kHz appeared with an EMI level of -70 dB.

The spike was low enough to not be an issue for use of this converter with the Pi filter

but this effect should be taken into consideration for applications requiring converter

G with a Pi filter.


69

7.4.2 Converter H

Chapter IV analysis of converter H resulted in an EMI range from -5.16 dB to

1.26 dB. After the modified design was applied, the EMI level decreased to a range of

-20 dB to -23.1 dB. When filters were applied to the modified converter G, the EMI

results of frequencies outside the switching frequency had a different result than any

other converter with filter applications. Figure 6.26 shows the simulation result for

converter G across all frequencies. The spikes at all locations are attenuated at a much

higher level than seen in any other Pi filter test. The maximum EMI level at the 2MHz

switching frequency was

-111 dB and the minimum level was -114 dB. The L filter resulted in a maximum EMI

level of -71.3 dB and a minimum level of -72.7 dB. This result is shown in Figures

6.27 and C.23. For T filter application, the EMI level ranged from -100 dB to -112.5

dB. When looking at the results of this filter in Figure 6.28, it is noticed that there is a

dipping spike accruing around 300kHz.

7.5 Conclusion

The initial method for designing SMPS is introduced in Chapter IV. In this

initial approach, all initial variables of switching frequency, duty cycle, and load

resistance were taken into account when selecting the components for each SMPS

under test. The result of this initial step was an insight on how the variables of the

system effect the recommended component values. This also showed how selecting

components based on a single duty cycle will result with higher duty cycles having

components with higher EMI suppression. This same pattern occurred when

increasing the switching frequency. The modified method allowed only the converters

initial operating values summed up in Table 3.3 to determine component values. This

proved to be beneficial for all converters under test. The EMI was now at a level that

is in a range to allow suppression to EMC standards to be accomplished with a single

input filter. This theory was proven in Chapter VI where the Pi, T, and L filters were

calculated and applied to each converter. All results except converter A with a T filter

passed standards set by CISRP22.


70

In conclusion, the results of the testing conducted on the SMPS showed

improvement in EMI results with each modification of the initial method. By focusing

on the initial design conditions of various SMPS, a converter can be designed that will

meet CISRP22 standards for multiple operating variables.


71

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73

APPENDIX A

MAGNIFIED SIMULATION RESULTS OF CONVERTERS

BEFORE FILTER

Figure A.1 Magnified Simulation Results of Converter A before Filter

Figure A.2 Magnified Simulation Results of Converter B before Filter


74

Figure A.3 Magnified Simulation Results of Converter C before Filter

Figure A.4 Magnified Simulation Results of Converter D before Filter


75

Figure A.5 Magnified Simulation Results of Converter E before Filter

Figure A.6 Magnified Simulation Results of Converter F before Filter


76

Figure A.7 Magnified Simulation Results of Converter G before Filter

Figure A.8 Magnified Simulation Results of Converter H before Filter


77

APPENDIX B

MAGNIFIED SIMULATION RESULTS OF CONVERTERS WITH

FILTERS

Figure B.1 Magnified Simulation Results of Converter A with Pi Filter


78

Figure B.2 Magnified Simulation Results of Converter A with L Filter

Figure B.3 Magnified Simulation Results of Converter A with T Filter


79

Figure B.4 Magnified Simulation Results of Converter B with Pi Filter

Figure B.5 Magnified Simulation Results of Converter B with L Filter


80

Figure B.6 Magnified Simulation Results of Converter B with T Filter

Figure B.7 Magnified Simulation Results of Converter C with Pi Filter


81

Figure B.8 Magnified Simulation Results of Converter C with L Filter

Figure B.9 Magnified Simulation Results of Converter C with T Filter


82

Figure B.10 Magnified Simulation Results of Converter D with Pi Filter

Figure B.11 Magnified Simulation Results of Converter D with L Filter


83

Figure B.12 Magnified Simulation Results of Converter D with T Filter

Figure B.13 Magnified Simulation Results of Converter E with Pi Filter


84

Figure B.14 Magnified Simulation Results of Converter E with L Filter

Figure B.15 Magnified Simulation Results of Converter E with T Filter


85

Figure B.16 Magnified Simulation Results of Converter F with Pi Filter

Figure B.17 Magnified Simulation Results of Converter F with L Filter


86

Figure B.18 Magnified Simulation Results of Converter F with T Filter

Figure B.19 Magnified Simulation Results of Converter G with Pi Filter


87

Figure B.20 Magnified Simulation Results of Converter G with L Filter

Figure B.21 Magnified Simulation Results of Converter G with T Filter


88

Figure B.22 Magnified Simulation Results of Converter H with Pi Filter

Figure B.23 Magnified Simulation Results of Converter H with L Filter


89

Figure B.24 Magnified Simulation Results of Converter H with T Filter

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