Embed Size (px)
Citation preview
ANALYSIS AND DESIGN OF N-CHANNEL MOSTRANSISTORS FOR CRYOGENIC SWITCHING APPLICATIONS
Item Type text; Thesis-Reproduction (electronic)
Authors Alwardi, Milad, 1958-
Publisher The University of Arizona.
Rights Copyright © is held by the author. Digital access to this materialis made possible by the University Libraries, University of Arizona.Further transmission, reproduction or presentation (such aspublic display or performance) of protected items is prohibitedexcept with permission of the author.
Download date 10/08/2021 13:44:00
Link to Item http://hdl.handle.net/10150/291980
INFORMATION TO USERS
This reproduction was made from a copy of a document sent to us for microfilming. While the most advanced technology has been used to photograph and reproduce this document, the quality of the reproduction is heavily dependent upon the quality of the material submitted.
The following explanation of techniques is provided to help clarify markings or notations which may appear on this reproduction.
1.The sign or "target" for pages apparently lacking from the document photographed is "Missing Page(s)". If it was possible to obtain the missing page(s) or section, they are spliced into the film along with adjacent pages. This may have necessitated cutting through an image and duplicating adjacent pages to assure complete continuity.
2. When an image on the film is obliterated with a round black mark, it is an indication of either blurred copy because of movement during exposure, duplicate copy, or copyrighted materials that should not have been filmed. For blurred pages, a good image of the page can be found in the adjacent frame. If copyrighted materials were deleted, a target note will appear listing the pages in the adjacent frame.
3. When a map, drawing or chart, etc., is part of the material being photographed, a definite method of "sectioning" the material has been followed. It is customary to begin filming at the upper left hand corner of a large sheet and to continue from left to right in equal sections with small overlaps. If necessary, sectioning is continued again—beginning below the first row and continuing on until complete.
4. For illustrations that cannot be satisfactorily reproduced by xerographic means, photographic prints can be purchased at additional cost and inserted into your xerographic copy. These prints are available upon request from the Dissertations Customer Services Department.
5. Some pages in any document may have indistinct print. In all cases the best available copy has been filmed.
University Microfilms
International 300 N. Zeeb Road Ann Arbor, Ml 48106
1327860
Alwardi, Milad
ANALYSIS AND DESIGN OF N-CHANNEL MOS TRANSISTORS FOR CRYOGENIC SWITCHING APPLICATIONS
The University of Arizona M.S. 1986
University Microfilms
International 300 N. Zeeb Road, Ann Arbor, Ml 48106
PLEASE NOTE:
In all cases this material has been filmed in the best possible way from the available copy. Problems encountered with this document have been identified here with a check mark V .
1. Glossy photographs or pages
2. Colored illustrations, paper or print
3. Photographs with dark background
4. Illustrations are poor copy
5. Pages with black marks, not original copy
6. Print shows through as there is text on both sides of page/
7. Indistinct, broken or small print on several pages
8. Print exceeds margin requirements
9. Tightly bound copy with print lost in spine
10. Computer printout pages with indistinct print
11. Page(s) lacking when material received, and not available from school or author.
12. Page(s) seem to be missing in numbering only as text follows.
13. Two pages numbered . Text follows.
14. Curling and wrinkled pages
15. Dissertation contains pages with print at a slant, filmed as received
16. Other
University Microfilms
International
ANALYSIS AND DESIGN OF N-CHANNEL MOS TRANSISTORS
FOR CRYOGENIC SWITCHING APPLICATIONS
by
Milad Alwardi
A Thesis Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
In partial Fulfillment of the Requirements For the Degree of
MASTER OF SCIENCE WITH A MAJOR IN ELECTRICAL ENGINEERING
In the Graduate College
THE UNIVERSITY OF ARIZONA
1 9 8 6
STATEMENT BY AUTHOR
This thesis has been submitted in partial fulfillment of requirements for an advanced degree at The University of Arizona and is deposited in the University Library to be made available to borrowers under rules of the Library.
Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgment of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in his or her judgment the proposed use of the material is in the interests of scholarship. In all other instances, however, permission must be obtained from the author.
SIGNED:
APPROVAL BY THESIS DIRECTOR
This thesis has been approved on the date shown below:
I °> T)FT. 85 WALTER J. \FAHEY X Date
Professor of Electrical Engineering
DEDICATED TO
Chandra and Manju Goradia
iii
ACKNOWLEDGMENTS
The author wishes to express his appreciation to Dr. James N.
Fordeiiiwalt for his invaluable assistance in the design of a polysilicon
gate process, his guidance and stimulating discussions. Thanks are
also extended to Dr. Frank J. Low and Dr. Eric T. Young of the Steward
Observatory for their recommendations in carrying out the cryogenic
temperature measurements.
iv
TABLE OF CONTENTS
Page
LIST OF ILLUSTRATIONS viii
LIST OF TABLES xi
ABSTRACT xii
CHAPTER
1 INTRODUCTION . 1
2 LOW TEMPERATURE BEHAVIOR OF MOSFET DEVICES 4
2.1 Introduction 4 2.2 Electron and Hole Statistics in Semiconductors ... 4
2.2.1 Thermal Equilibrium Free Carrier Concentration 4
2.2.2 Intrinsic Semiconductor 10 2.2.3 Extrinsic Semiconductor (Non-Degenerate) . . 11 2.2.4 Degenerate Semiconductor ..... 18
2.3 MOSFET Device Static Characteristics 20
2.3.1 Formulation of MOSFET Device Static Characteristics 20
2.3.2 Carrier Freeze-Out and Apparent Drain Voltage 28
2.3.3 Schottky Barrier Effect 33 2.3.4 Gate Voltage Effect on Schottky Barrier ... 40 2.3.5 Modeling of the MOSFET I-V Characteristics
with Schottky Effect 44
2.4 Temperature Dependence of MOSFET Device Parameters 49
2.4.1 Temperature Dependence of Eg 49 2.4.2 Temperature Dependence of n 50 2.4.3 Temperature Dependence of 50 2.4.4 Temperature Dependence of <J>ms 52 2.4.5 Temperature Dependence of yeff 54 2.4.6 Temperature Dependence of V . 58
v
vi
TABLE OF CONTENTS—Continued
Page
2.4.7 Temperature Dependence of Ij) 61 2.4.8 Temperature Dependence of Jg 61
3 MOSFET STATIC CHARACTERISTICS PROGRAM SIMULATION FOR LOW TEMPERATURE APPLICATIONS 65
3.1 Introduction 65 3.2 Program Description 65
3.2.1 Program Specifications and Limitations ... 65 3.2.2 Input Parameters and Output Generated Plots . 68 3.2.3 Description of <|>j?(T) Output Plot 69 3.2.4 Description of Vt(T) Output Plot 69 3.2.5 Description of dV (dT) Output Plot 69 3.2.6 Description of the MOSFET Saturated Transfer
Characteristic IqsaT 3.2.7 Description of the MOSFET Device 1-V
Characteristic Plot 73 3.2.8 Description of MOSFET I-V Characteristic
Plot Including the Schottky Barrier Effect . 78
3.3 LTMOSFET Generated Output 78
4 DESIGN AND FABRICATION OF CRYOGENIC TEMPERATURE TEMPERATURE MOSFET DEVICES 82
4.1 Introduction 82 4.2 Design Considerations 82 4.3 Description of MOSFET Test Vehicle 83 4.4 Discussion of MOSFET Test Device Fabricaton .... 84
5 EXPERIMENTAL RESULTS 91
5.1 Introduction 91 5.2 Device Parameters Measurements 93
5.2.1 Threshold Voltage Measurement 93 5.2.2 Inversion Layer Electron Mobility
Measurement 97 5.2.3 I-V Characteristic Measurement 98 5.2.4 P-N Junction Leakage Current Measurement . . 106
vii
TABLE OF CONTENTS—Cont inued
Page
6 CONCLUSIONS 109
6.1 Summary 109 6.2 Recommendations for Future Work 110
APPENDIX A: LTMOSFET PROGRAM LISTING 112
APPENDIX B: STANDARD WAFER CLEANING PROCEDURE 133
APPENDIX C: FABRICATION PROCEDURE 135
APPENDIX D: LIST OF SYMBOLS 140
SELECTED BIBLIOGRAPHY 143
LIST OF ILLUSTRATIONS
Figure Page
2.1 Fermi-Dirac Integral as a Function of Fermi Energy . . 7
2.2 Derivative of the Fermi-Dirac Distribution Function ... 9
2.3 The Temperature Dependence of the Fermi Level in an Acceptor Doped Semiconductor 16
2.4 Electron Desnity as a Function of Temperature for a Silicon Sample with Donor Impurity Concentration of
10 -*cm-3 17
2.5 Density-of-States Distribution Functions n(E) versus E . 21
2.6 Charge Carrier Concentration in Silicon Samples Containing Arsenic as a Function of 1/T 22
2.8 Energy-Band Diagram of an Ideal MOS System in Strong Inversion 24
2.9 Relative Hole Concentration in the Bulk P/Na versus Temperature with the Acceptor Concentration Na as a Parametet 30
2.10 Energy-Band Diagram of a MOSFET with Gate-Source and Gate-Drain Overlap at 0 K 31
2.11 Conduction Band Diagram along the Channel for MOSFET Showing Potential Hills Resulting from Lack of Gate-Source and Gate-Drain Overlap 32
2.12 Energy-Band Diagram of a Metal-Semiconductor Contact with > 4»s 35
2.13 Parabolic Depletion Layer Type of Potential Energy Barrier for n-Type Semiconductor 37
2.14 Effect of Image Force on the Shape of the Potential., Barrier at a Metal-Semiconductor Interface 38
2.15 Ratio of Tunneling Current Component to the Thermionic Current Component of a Gold-Silicon Barrier 39
viii
ix
LIST OF ILLUSTRATIONS—Continued
Figure Page
2.16 Normalized Current-Voltage Characteristics Predicted by Eq. (2.53) 42
2.17 Schematic Illustration of the Current Voltage Relationship for a Schottky Barrier Contact 43
2.18 Experimental Values of the Drain Apparent Threshold Voltage as a Function of Applied Gate Voltage Vq at 77 K and 4.2 K 45
2.19 Field Fringing Effect Due to the Applied Gate Voltage . . 46
2.20 Simple Model of MOSFET Device Including Schottky Barrier at the Source and Drain Contacts 48
2.21 Energy Band Gap of Silicon as a Function of Temperature . 51
2.22 Variation of the Fermi Potential as a Function of Temperature with Bulk Doping Concentration of 10^5(cm~3) .... 53
2.23 Energy-Band Diagram of a Polysilicon - Si02~Si Structure. 55
2.24 Electron Inversion Layer Mobility as a Function of Temperature for Silicon 56
2.25 Electron Inversion Layer Mobility as a Function of Temperature for the High Field Case 57
2.26 Variation of the Threshold Voltage with Temperature for Substrate Doping Concentration of 10 - cm- 62
2.27 MOSFET Saturation Region Transfer Characteristics with Temperature as a Parameter 63
3.1 Basic Integrating JFET Circuit with n-channel Enhancement Mode MOSFET Reset Switch and a Photoconductor 66
3.2 LTMOSFET Generated Plot of the Fermi Potential as a Function of Temperature 70
3.3 LTMOSFET Generated Plot of the Threshold Voltage Variation with Temperature 71
LIST OF ILLUSTRATIONS—Continued
x
Figure Page
3.4 LTMOSFET Generated Plot of the Variation of the Threshold Voltage with Temperature as a Function of Temperature 72
3.5 LTMOSFET Generated Plot of /IDSat versus Vgg at 300 K, 77 K and 4.2 K 74
3.6 LTMOSFET Generated Plot of IDg versus Vpg with Vgg as a Parameter 75
3.7 LTMOSFET Generated Output Plot of Ijjg versus V g with Vgg as a Parameter Showing the Schottky Effect 79
4.1 Layout of Low Temperature MOSFET Test Vehicle 85
4.2 MOSFET Fabrication Sequence 88
5 . 1 Circuit Schematic for Ij) versus Vq Measurement 92
5.2 Experimental Saturation Region Transfer Characteristic for Device M6 95
5.3 Experimental I-V Characteristics for Device M 6 100
5.4 Simulated I-V Characteristics for Device M 6 103
5.5 Circuit Schematic for p-n Junction Leakage Current Measurement at 300 K and 77 K 107
LIST OF TABLES
Table Page
3.1 Input Parameters to LTMOSFET Simulating Device M 6 . . . 81
4.1 Mask Level Dimensions of Test MOSFET Transistors .... 86
5.1 Measured and Calculated Values of Vp for Transistor M 6 . 96
5.2 Measured and Calculated Values of Threshold Voltage Shift from its Room Temperature Value 96
5.3 Measured and Calculated Values of Threshold Voltage Shift from LN2 Temperature Value 96
5.4 Measured and Calculated Values of High Field Electron Inversion Layer Mobility 98
xi
ABSTRACT
Carrier statistics in semiconductors in the low temperature
range are reviewed in order to analyze the static characteristics of
MOSFET devices at cryogenic temperatures. A first order computer
simulation program has been developed to predict the device behavior
and to aid in the design of MOSFET devices suitable for operation at
such temperatures.
A polysilicon gate process has been used to fabricate n-channel
enhancement mode MOSFET test devices. The FET parameters have been
studied both theoretically and experimentally at three different
temperatures: 300 K, 77 K, and 4.2 K. Excellent agreement was found
between the experimental dc characteristics and those predicted by the
first order model at room temperature and liquid nitrogen temperature.
However, a large increase in the threshold voltage variation with
temperature over its theoretical value was observed at liquid helium
temperature. The non-ohmic behavior at low temperature due to non-
degenerate surface concentration of the source and drain regions is
also discussed.
Finally, improvements in device characteristics of n-channel
enhancement mode MOSFET's are observed at both liquid nitrogen and
liquid helium temperatures.
xii
CHAPTER 1
INTRODUCTION
Much interest in the feasibility of using a MOSFET device as a
cryogenic functional-reset switch in conjunction with infrared detectors
for astronomy has been expressed in the literature in recent years. A
simple integrating amplifier based on commercially available JFET's.
cooled to 77 K, has been already used at the Steward Observatory at
The University of Arizona to measure photocurrents from detectors with
—18 noise levels as low as 1.6 x 10 A/(root Hz), (10 electrons/sec x
Hz ). If an electronics reset switch has to be used as part of the
readout circuit, such a switch must also operate at low temperature in
close proximity to the detector to minimize the noise and leakage
current. Also, it must have high off-resistance, low on-resistance,
very small coupling capacitance, and must not add appreciable noise.
Silicon MOSFET devices hold great promise as chopper switches
for this application since they can be easily designed to meet all the
above requirements. However, low temperature operation of MOS transis
tors results in improved performance over that at room temperature.
The purpose of this work is to investigate the performance of
n-channel enhancement mode MOSFET devices at cryogenic temperatures,
namely, 77 K and 4.2 K. The specific objectives are as follows:
1. To investigate carrier statistics in extrinsic semiconductors
at low temperatures and analyze the MOSFET device static
1
2
characteristics, incorporating into the analysis all functional
dependence upon temperature.
2. Develop a first order computer simulation program to predict
MOSFET device static characteristics at low temperatures.
3. Use an existing self-aligned polysilicon gate process to design
and fabricate an n-channel enhancement mode MOSFET test device
in order to demonstrate some of the improved characteristics
that occur at low temperature.
4. Evaluate the device electrical characteristics as a function
of temperature and check the validity of the theoretical predic
tions by comparing them to the experimental results.
MOSFET device behavior at cryogenic temperature is well under
stood theoretically. The experimental results obtained showed strong
agreement with theoretical predictions, at least in the temperature
range of 300 K - 77 K. Significant improvements in device operation
were observed at lower temperatures. These include an increase in
inversion layer mobility (with a corresponding increase in transcon-
ductance), and a dramatic decrease in p-n junction leakage current.
However, at 4.2 K, the results were not in good agreement with the
calculated values as a result of second order effects.
A brief outline of this thesis proceeds as follows. In Chapter
2, carrier statistics are investigated in extrinsic semiconductor and
the dc characteristics behavior of MOSFET devices with temperature is
discussed, taking into account the drain apparent threshold voltage.
3
Chapter 3 concerns the development of a first order computer
simulation program using the equations analyzed in Chapter 2.
The self-aligned polysilicon process used in the fabrication
of test devices is described in Chapter 4. Design considerations are
also presented.
The experimental results with methods of measurements are given
in Chapter 5 along with the corresponding calculated values for compar
ison and discussion.
A summary of this work is outlined in Chapter 6 along with some
recommendations for future work in this area.
CHAPTER 2
LOW TEMPERATURE BEHAVIOR OF MOSFET DEVICES
2.1 Introduction
It has been demonstrated that devices which rely on bulk
conduction do not operate at very low temperatures as a result of
carrier freeze-out. However, devices which rely on induced surface
conduction can show satisfactory dc characteristics. In this chapter
expressions for electrons and holes concentration in the substrate and
heavily doped source and drain regions are derived. Also, a criterion
for a degenerate state of doping level which allows the design for low
temperature operation is given. The MOSFET device static character
istics are reviewed for room temperature operations taking into account
the low temperature effect.
2.2 Electron and Hole Statistics in Semiconductors
2.2.1 Thermal Equilibrium Free Carrier Concentration
In order to determine the electrical behavior of MOSFET devices
at low temperatures, it is necessary to know the number of electrons
and holes available for current conduction and their dependence upon
temperature.
To find the number of available conduction electrons, it is
sufficient to find the density of the state function, N(E), and the
4
distribution function, f(E). The density of electrons is given by
E
n = {
top
f (E)N(E)dE
(E-E ) c
E (2.1) c
The density of available states, N(E), is proportional to
h
3/2 % N(E) = 4tt I —I (E-E )
h / C (2.2)
The distribution function, f(E), is the Fermi-Dirac distribu
tion function and is given by the following expression
f(E) =
.») \ kT /
1 + exp( (2.3)
Since f(E) falls off rapidly with increasing energy, and the
contribution of electrons occupying upper energy states to the electron
concentration is negligible, we may write
* "3/2
n -
/ 2 m* V
M I E-E V
- 4tt I -f- J (E-Ec)
6
The value of the integral is given by
2 N n =
A * (2.5)
where is the effective density of states in the conduction band
and is given by
( 2it m* kT \3/2
( 2 . 6 )
and (£) is the Fermi-Dirac integral of the order 1/2 which has the 'S
form
M5> • \ h
exp (x-£) + 1 dx
(2.7)
Here x and ? are equal to (E-Ec)/kT and (E -E /kT, respective
ly. Figure 2.1 shows the Fermi-Dirac integral as a function of C. The
electron concentration depends on temperature and the Fermi-Dirac
integral can be approximated for three different ranges of the argu
ment:
V5) = '
exp(5) /ir 2
/iT 1 2 0.25 + exp(-5)
2/3 53/2
for -«o < 5 < -1
for -1 < 5 < 5
for 5 < 5 < *° (2.8)
Fermi-Dirac Integral (<pt ) -5
: !
tTT~=n
! ••! - —r __ . . . . . _u ,
1 . i ' 1
! i
11—1, 1 . —
i : -r- ' | r
- 1.-,
—i-
i •
-M-
+-
— 1 t
i : ! i 1 :T i
' ! i ; j . . : : : 1 j
i j
• —
j i i j h : 1 ! 1 ! >
J/1 :
r ! 1
• ->-i i • • ' ' i '
| 1 j :
Mi
• i ; ;
: • i
—
— -f—r —Uj>
• " j
\ y i 1 i :
&——U-: i • !
-I-; 1—
M : : i •
i—.. i_ i i
• i ,
; i i i » 1 i :
i _i —
-1
• i • •
/ ' ' : ! : : : i i i M i :
1 :—1—I-1" — i — j I . 1. |
• , ' i ! , • i ; i
• I 1 j 1 • • ]
J f
i i : 1 1 i '
—H—
r • • • •
i
' '
i
2 : I ! 1
: ; I !
' ' 1 '
1 . i ; ; •
; j i i ;
' i M T*1 ! • ' !
—f-
i
— ... / H i -i— — H - -
M T"
; 1 I ' l l
— 1-1 u. — — .
i I ji . j . . t .
• r
i M i 1
-! |-1 i-1 i , i
~ r r • i i i
• : ; r f
V l • ;
• : :
s. _
1 1 ' . J J j i l l 1 1 ' '
1 ' • ; : :
i i
i • ! H Hi ! i i i
l i i i -6 -4 -2 0 2 4 6
(E - E,)/kT c r
Fig. 2.1 Fermi-Dirac Integral <J>. as a Function of Fermi Energy [Sze, 1969]
8
The first approximation corresponds to the Boltzmann statistics
and, for this case, the semiconductor is said to be non-degenerate.
The third approximation corresponds to a completely degenerate semi
conductor where the approximation
has been made. This approximation is illustrated in Fig. 2.2. Notice
that this assumption holds better at lower temperatures. The second
approximation is valid for the intermediate state which is the transi
tion from non-degenerate to completely degenerate semiconductor.
-lf?5(E- V
Substituting values for <t>u (5) in Eq. (2.5), we get
for E--E < -kT f c
N n = < c
for -kT < E,-E < 5 kT f c
0.23 + exp
for E,-E > 5 kT f c
(2.9)
Similarly, the hole concentration is given by
9
A 3£(E) 3E
3000 K
300 K
30 K
Fig, 2.2 Derivative of the Fermi-Dirac Distribution Function [Fistul, 1969]
( Ef"E" )
p -•<
0.25 + exp( j- )
(?)
kT
v3/2 8TT
3 (E -E-)
v f
for E..-E > kT f v
for - kT < Er-E < 5 kT f v
for E£-E > kT f v
(2.10)
where is the effective density of states in the valence band and
is given by
/ 2ir m* kT \3'2
•H-H
Notice that for a completely degenerate semiconductor, the
electron concentration is independent of temperature. This is a very
important property in the design of MOSFET devices suitable for opera
tion at cryogenic temperatures.
2.2.2 Intrinsic Semiconductor
For a pure semiconductor (N& = = 0) in thermal equilibrium,
conduction electrons are created solely by thermal excitations of
valence electrons. Thus, for every electron in the conduction band
there must be a hole in the valence band. The electron concentration
is given by
11
and
n = p = n±
n = NcNv exp (-E /kT)
or
3/2
vu'eV A (2.11) n± - 2 (m*m*)3/4 T3/2 exp(-E„/2 kT)
The expression for n In empirical form is given by
n. = 3.87 x 1016 T3/2 exp(-E /2 kT) i go
where Eis the energy band gap at 0 K.
2.2.3 Extrinsic Semiconductor (Non-Degenerate)
When impurities such as boron or phosphorus are added to semi
conductor material, impurity energy levels are introduced with the
forbidden energy band and are very close to the energy band edge E
or E for phosphorus or boron impurities, respectively. Let and N&
denote the donor and acceptor impurity concentration, respectively. A
donor is ionized if a level is not occupied, and an acceptor is
ionized if a level Ea is occupied. Therefore
< - fl-f(Ed)| H, (2a2)
and
N = f (E ) N a a a
(2.13)
where f(E, ) is the distribution function for impurity states and is CI 9 3
given by
f(Ed) =
2 exP (¥0 + 1 and
f (E ) = a
2 exp (W +1 Hence, Eq. (2.12) and Eq. (2.13) become
•I-N,
2 exp (¥») + 1 (2.14)
N N = a / E -Ef \
2eXP\-fe-J+ 1 (2.15)
Now consider two doping levels applicable to MOSFET device
structures:
Case 1: One Type of Impurity in a Semiconductor
This is the case of substrate doping where only one type of
impurity is present. Assuming an n-type semiconductor, that is N = 0, a
the electric neutrality equation has the form
13
n = p + N"t (2.16)
At room temperature we assume all Impurity atoms are ionized
and p « Nj. Hence
n = Nd
Similarly, for a p-type semiconductor
p = N r a
and the Fermi level is given by
Ef - Ec - kT to (»c/lid) (2-17)
At low temperature, however, the impurity concentration plays the lead
ing part since the ionization energy for impurity atoms is much smaller
than the energy gap. In this case, the electric neutrality equation is
simply
n = N j a
or
« ( Ec*Ef ) N
c ***[-—]= Nd
VEf 2 eXp ~kT— + 1
Solving for E , we get
14
Er = AE, + kT Hn -r-f d 4
(2.18)
where AE, = E - E,. d c d
But, at sufficiently low temperature, the inequality
8N -jj— exp (AE /kT) » 1
may hold. Therefore, we obtain
N. + kT/2 Zn —
(2.19)
and
(2.20)
Similarly, for a p-type semiconductor
E, = AE - kT £n a
1 4
(2.21)
15
and at sufficiently low temperature, the hole concentration is given by
, /"vV exp (-AE /2 kT) a (2 .22 )
and the Fermi level takes the form
E + E m E, = — - kT/2 In — * 2 2Nv (2.23)
However, at relatively high temperature, Eq. (2.21) becomes
Ef = Ev - kT In (2>24)
and the acceptor concentration, p, is given by
P = Na (2.25)
The validity of Equations (2.20) and (2.22) in this temperature
range is conditional upon the concentration or Na« For our applica
tions, the MOSFET device will be operated at temperature lower or
equal to liquid nitrogen temperature (77 K). Therefore, for n-channel
MOSFET where N = lO cm- , Equations (2.22) and (2.23) are applicable.
Figure 2.3 shows the temperature dependence of Fermi level for differ
ent doping levels, and Fig. 2.4 illustrates the variation of electron
15 -3 density with respect to temperature for N =10 cm .
3
I I I I I I 0 100 200 300 400 500 600
Temperature (K)
1 - N al
2 - N a2
3 - N a3
(\l < \l « V
Fig. 2.3 The Temperature Dependence of the Fermi Level in an Acceptor Doped Semiconductor [Kireev, 1978]
Intrinsic Range Slope = Eq.
s y W C
Saturation Range
4J •H
CO Freeze-out Range
a <u a a o u y ai »H W
13
0 4 8 12 16 20
1000/T (K"1)
Fig. 2.4 Electron Density as a Function of Temperature for a Silicon Sample with Donor Impurity Concentration
of 1015cm~3 [Sze, 1969]
Case 2: A Semiconductor with Both Types of Impurities
This is the case of source and drain region of MOSFET device
where » Na> It can be shown [Kireev, 1978] that in this case
the semiconductor behaves as doped with only the highest impurity
type.
2.2.4 Degenerate Semiconductor
It was shown earlier in Section 2.2.1 that in a degenerate
semiconductor, the carrier concentration is independent of temperature.
The degeneracy may be attained only through heavy doping and is
discussed next.
For an extrinsic semiconductor the Fermi level approaches the
corresponding energy band edge as the temperature decreases. The
position of the extremum of E is also a function of doping concen
tration. From Eq. (2.19), the change of E with respect to tempera
ture is given by
dEf/dT ~ kT/2 n 2NC ~ ( 2 dT ) (2.26)
The extremum of E is found by equating Eq. (2.26) to zero.
Hence
N
2NC " exp (3/2) (2.27)
The temperature T at which the Fermi level reaches its max
maximum (for an n-type semiconductor) is found from Eq. (2.27)
19
by the condition
N (T ) = c max 2 e3/2 (2>28)
and its empirical form is given by
N, \2/3 & T = 24.71 max \ 10io j (2.29)
Equation (2.29) shows that Tmax increases with increasing
doping level. The concentration N c for which = E£ is termed
critical. To calculate N, , T is substituted in Eq. (2.10) dc max
with the result
E + E, , / Nj \2/3
E = E = _£ i + ie.l x 10~A f ) fmax c 2 \l018/ (2.30)
where E and E, are in eV. Solving for N, c d dc
"dc - 1"» 1 1(,Z1'5 t4Ed (eV)'3/2 (2.31)
For phosphorus, AE = 0.044 eV in silicon; therefore, the
19 -3 critical donor concentration is 2.9 x 10 cm . With the help of the
critical concentration it is possible to assess the impurity concentra
tion at which degeneracy of the semiconductor sets in. However, for
E = Ec, the semiconductor is not yet completely degenerate in the
sense that the charge carrier concentration within some temperature
range becomes independent of temperature. For a complete degeneracy,
higher concentration than N c is needed.
The charge carrier concentration can be determined from the
charge neutrality equation as follows
3/ii \ kT / a \ kT / (2.32)
But there is little sense in Eq. (2.32) since for such high
concentration as is needed to achieve degeneracy, the impurity level
turns into a band which merges with the conduction band as seen in
Fig. 2.5. The degeneracy does not vanish even at very low temperature
because the impurity band mechanism remains active. Also, impurity
ionization energy decreases with the increase in impurity concentra
tion.
Therefore, in the analysis of the MOSFET device, it is assumed
that charge concentration in the source and drain region is equal to
the impurity concentration. Figure 2.6 illustrates the temperature
effect on carrier concentration for different doping levels.
2.3 MOSFET Device Static Characteristics
2.3.1 Formulation of MOSFET Device Static Characteristics
The temperature dependence of the charge carrier concentration
at low temperature was discussed above. A full understanding of the
Conduction Band
Donor State (Delta Function)
E, g
n(E)
Valence Band
(a) Non-Degenerate Semiconductor
.Donor Band
Intrinsic Conduction Band
Degenerate Conduction Band
Band Edge Tailing
E g
n(E)
Valence Band
(b) Degenerate Semiconductor
Fig. 2.5 Density-of-States Distribution Functions n(E) versus E [Sze, 1969]
22
in I S u
a o
CO U 4J c <u o e o u c o u 4-1 o 0) r-H W
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
10 11
10 10
T(K) o o o o CO r-t
o o m
o m <n CM
0.01 0.02
1/T (K-1)
2.7 x 10 19
2.2 x 10 18
1.3 x 10 17
0.03 0.04
0 Measured
— Computed
Fig. 2.6 Charge Carrier Concentration in Silicon Samples Containing Arsenic as a Function of 1/T [Morin and Malta, 1954]
temperature effect on doping concentration was necessary for designing
MOSFET devices that operate satisfactory at cryogenic temperatures. In
this section an investigation of the temperature dependence of MOSFET
device static characteristics is carried out. This is done, first, by
formulating briefly the device static characteristics at room tempera
ture, then by incorporating into them the necessary changes in order to
take into account the low temperature effect for the case of non-
degenerate source and drain.
Consider an ideal metal-oxide-semiconductor system as shown in
Fig. 2.7 for a p-type semiconductor. In this case, <(>m = <J>S» provided
that gate and substrate are equally doped, and
G <t = d> = Y + + ib m ys s 2q yF
where <j>m and <pg represent the work functions of the metal and the
semiconductor, respectively, and xg is the electron affinity.
To ensure strong inversion, a voltage V, must be applied at
the gate of the system as shown in Fig. 2.8. It can be shown that
is given by
VTl"2*F + C^ (2.33)
where the assumption of a one-sided step junction has been made.
Because of work function difference between metal or poly-
silicon, the interface charge density Q present at the SiO--Si inter-ss z
face and the distributed ionic charge in the SiOj, the energy band
diagram of the system is non-ideal. To bring the energy band to the
24
Vacuum Level
q<f>. m
q<l>
1 qx
t E /2
q'l'r
E. X
Metal Oxide Semiconductor
Fig. 2.7 Energy-Band Diagram of an Ideal MOS System
"fm
T > vG > 0
qifrx
/ — fs
Fig. 2.8 Energy-Band Diagram of an Ideal MOS System in Strong Inversion
25
ideal condition (flat-band condition), we must apply at the gate a
voltage VFB equal to
qQss
qQeff vfb - *ms - - -ir-
ox ox (2.34)
The total threshold voltage VT is the sum of Eq. (2.33) and Eq. (2.34)
eff 1 U VT - *ms - nr*" —+ 2*F + — 0 _ ox ox ox (2.35)
where <b is the work function difference, C is the gate oxide capaci-ms ox
tance per unit area, and Q ££ is the lumped equivalent of the distributed
ionic charges. The expression defining VT does not include the effect
of the substrate bias. Indeed, for our application the MOSFET device
will be used as a shunt-chopper with the substrate and source tied to
ground. Also, the effect of a short channel is neglected since, for the
case of our design, the channel length is equal or greater than 10 pm.
The drain current in the triode region is given by
L. = »/L p ,, C J D eff ox (vTnr2*» " lf)VD " 2/3
/2e qN s a
cox
[(VD + 2 )3/2 - (2*f)3/2| . !]
(2.36)
26
where all voltages are taken with respect to the source (ground).
Since at pinch-off the drain current reaches a maximum at a voltage
V (drain to source saturation voltage) and stays constant for UbAl
VJJ DSAT* two re8*ons operation are considered: the triode region
and saturation region. To a first order approximation, Eq. (2.36)
becomes
TDS = (W/L) Weff Cox t(VG " VT>VD ~ <2'37>
for VD < VDSAT (or triode region), and
W * WL) <>Vf f Cox/2> <VG " V12 (2.38)
for VD > (or saturation region).
The saturation voltage at which pinch-off occurs (1 =
is given by
e qN - V„ - v_,0- 2tl> + 3 a
DSAT G FB F fn 2. v>ox )
\ (, , 2Cox2 <VG- W^f
\ EsqNa J (2.39)
The gate leakage current, for good quality oxide, is extremely
small and can be neglected. However, the p-n junction leakage current
(drain-substrate or source-substrate) is relatively high and plays a
27
major role in chopper application, especially in conjunction with infra
red detectors. Hence, the necessity of cooling the MOSFET device
arises. The p-n junction leakage current density is mainly composed of
2 two components: the drift component Jj which is proportional to n and
can be neglected at low temperature, and the generation component
which dominates at low temperature since it is proportional to n . The
generation leakage current density is given by
J = (qn./2x )W (2.40) g i o
where W is the depletion width, tq is the effective minority carrier
lifetime in the depletion region. Assuming a step junction, as the
case of a MOSFET device, W is given by
2es(,"o + V W = - 8 0 R
qNa
where V is the reverse bias voltage and i/i is given by R O
N N, i|) = kT/q £n -§ ° n*(T)
Another important parameter in chopper applications is the
device transconductance g . The MOSFET device transconductance is in
defined as
!h 5m * 3V,
VD = constant
28
In the saturation region of operation, g becomes m
" WL) "ef^ax (VG " V (2.41)
and in the triode region
= (M/L) »efIC»»VD (2.42)
Finally, the last important parameter for chopper applications
to be discussed is the gate-to-drain capacitance, Cgj* conjunction
with the infrared detectors, the MOSFET device is operated in the
triode region as a shunt-chopper with small drain to source voltage
(50 - 100 mV). Therefore, the gate to source capacitance is mainly
equal to half of the gate capacitance, C [Gray and Meyer, 1984]. 6
C . = 1/2 C W/L ,0 gd ox (2.43)
To complete the analysis of the MOSFET devices static charac
teristics, it is necessary to investigate the effect of carrier freeze-
out on the I-V characteristics of the device at low temperature.
2.3.2 Carrier Freeze-Out and Apparent Drain Voltage
The major limiting effect on semiconductor device operation at
cryogenic temperature is carrier freeze-out. As the temperature
decreases, the Fermi level approaches the valence band for a p-type
substrate, and the mobile carrier concentration decreases rapidly.
This decrease of carrier concentration is predicted by Eq. (2.22)
for very low temperatures, and is repeated here
/NvNa 1
P = 'V-y2' exp (-AEa/2kT)
and by Eq. (2.25) for higher temperatures.
The normalized mobile hole concentration as a function of
temperature, with N as a parameter, is shown in Fig. 2.9. However, d
the situation in the channel under the gate is completely different.
Because of the energy band bending in the channel that results from
built-in and applied potential, the acceptors in the surface depletion
region remain ionized even at low temperature [Gaensslen et al., 1977].
This means that the charge concentration in the channel is approxi
mately equal to the impurity acceptor density, N .
The energy band diagrams along the channel are shown in Figures
2.10(a) and 2.10(b) for VD = 0 and VQ > 0. From these diagrams it may
be concluded that the current will flow in the channel for any applied
drain voltage once the gate voltage has exceeded the threshold voltage,
V ,, which reduces the conduction band edge in the channel to the quasi-
Fermi level in the degenerate source region.
The above results will apply to the case where the gate over
laps the source and drain region. However, in the case where the gate
underlaps the source and drain, potential hills exist at the edges of
the channel. This situation is shown in Fig. 2.11(a) for symmetrical
30
1.0
1 x 10
0 .1
0.01 40 80 120 160 200 240 280
T (K)
Fig. 2.9 Relative Hole Concentration in the Bulk P/N versus Temperature with the Acceptor a
Concentration N as a Parameter [Gaensslen, et al., 1977] a
31
Inversion Layer
( ((((<({/( {(((( i(///////y
n'
~Y Source Drain
(a) Along the channel with VD = 0
Conducting Channel
Drain
(b) Along the channel, > 0
Fig. 2.10 Energy-Band Diagram of a MOSFET with Gate-Source and Gate-Drain Overlap at 0 K [Wu and Anderson, 1974]
32
r, i r -type Substrate Source 1
<"> VG * VT* V0 " 0
Drain
Conducting Channel
/ Z VdtX-ST
p-type Substrate
(b) vG > vT, td - »DSI
D
0 v, VDST vdst
(c) Shows th£ actual drain-source threshold voltage VDST
Fig. 2.11 Conduction Band Diagram along the Channel for MOSFET Showing Potential Hills Resulting from Lack of Gate-Source and Gate-Drain Overlap [Wu and Anderson, 1974]
geometry and for a gate voltage V_ > V that brings the conduction band U 1
edge to an energy level below the quasi-Fermi level in the source.
Even for V > V , electrons cannot enter the channel because of poten-U 1
tial barriers unless a drain-to-source voltage higher than a threshold
voltage V 0 is applied to initiate conduction. This situation is DoT
depicted in Figures 2.11(b) and 2.11(c) [Wu and Anderson, 1974],
Therefore, Equations (2.37) and (2.38) should be modified by replacing
VD by VD " ?DST' and VDSAT by VDSAT + ?DST' I_V CUrV6 in thiS
situation is shifted to the right by
2.3.3 Schottky Barrier Effect
When the source and drain are completely degenerate, free
carrier concentration does not experience freeze-out to any serious
degree as we mentioned earlier in Section 2.2.1. Therefore, for a
well-designed MOSFET device with a degenerate source and drain, it is
assumed that the metal contact to the source and drain is ohmic.
However, if the source and drain doping level is not completely
degenerate, the contact ceases to be ohmic at low temperature and a
Schottky barrier appears at the source and drain contacts with nearly
symmetrical I-V characteristics due to tunneling. In this case also
the MOSFET I-V characteristic exhibits a drain to source offset voltage
VDTH" For an aPPlied drain voltage VD < (assuming VG > VT), the
drain current 1 is essentially constant and equal to the leakage
current. When the drain voltage reaches 1 starts to increase
and its value is controlled by the reverse Schottky diode current for
small drain voltage. Since in a self-aligned silicon gate, there is
always a small overlap of the gate to the source and drain, the latter
situation describes best the I-V characteristic when it displays an
apparent threshold voltage. V JJ is temperature dependent through
mobile carrier concentration and will increase with decreasing tempera
ture.
To understand the MOSFET I-V characteristic at low temperatures,
consider a metal-semiconductor contact, specifically an aluminum con
tact to an n-type semiconductor shown in Fig. 2.12. To a first approxi
mation, the barrier height, < > is constant and depends on the contact
material. Depending on the doping level in the semiconductor, three
different types of conduction take place: (1) Thermionic Emission or
Diffusion, (2) Thermionic-Field Emission, and (3) Field Emission.
These three are explained below.
(1) Thermionic Emission or Diffusion
This is the dominant mode of current transport at low doping
level which gives the Schottky barrier rectification property. The
thermionic or diffusion current is given by [Sze, 1969]:
J = Jr [exp(qV/kT)-l] (2.44)
where Jr is the reverse current and is given by
= C exp(-q /kT) (2.45)
where C is a constant that depends on the dominant mode of conduction.
35
Vacuum Level
0 qx.
T" 5+,
r± Jf s
Metal Semiconductor
(a) Before contact
q*o~"T
•- E fs
Metal
mm-Semiconductor
(b) After contact and at thermal equilibrium
Fig. 2.12 Energy-Band Diagram of a Metal-Semiconductor Contact with <|> > d>
m s
36
In reality, the shape of the potential barrier is not parabolic
as shown in Fig. 2.13. Because of the induced mirror-image charge in
the metal, the energy distribution becomes [Rideout, 1975]
q<J>(x) = q2 N x2 q2
2k e 16ir e,e (W-x) (2.46) so a o
where is the relative dynamic (high frequency) dielectric constant
of the semiconductor. Therefore, the lowering of the barrier is given
by
qA<J> = q3 *0 N
a 2 u 22 8ir k e,e s d o (2.47)
From Eq. (2.44) the image force lowering equals the band bend
ing i|>o when
1 9 2 2 - 3 N.j , * 1.8 x 10 k e (qiji ) cm ideal s d o (2.48)
where qiJ>o is in units of eV. From Eq. (2.48) it can be seen the
importance of high doping level to achieve ohmic-contact. Figure 2.14
illustrates the effect of image force on the shape of the potential
barrier. However, as the donor concentration for an n-type semicon-
-h ductor is increased, depletion width narrowing (W a N ) proceeds more
jjj rapidly than barrier lowering (A $ a N ) and, consequently, conduction
becomes dominated by quantum-mechanical tunneling through a narrowed
Thermionic emission or diffusion
Thermionic field emission
Field emission
Ot t — • i
(Image force rounding of the barrier shape is neglected.)
Fig. 2.13 Parabolic Depletion Layer Type of Potential Energy Barrier for n-type Semiconductor [Rideout, 1975]
1.0
ideal
0 . 8
- 2
0.6
-2
0.4
-1
<-1
0.8 0.6 0.4 0.2
Fig. 2.14 Effect of Image Force on the Shape of the Potential Barrier at a Metal-Semiconductor Interface [Rideout, 1975]
barrier rather than by thermionic emission over the barrier or
diffusion
(2) Thermionic-Field Emission
The built-in potential is given by
$ = 4, _<(, - V = q2 N W2/2k e o m s so (2.49)
As the ionized donor concentration N is increased, the depletion region
width W must decrease. Therefore, the top of the barrier becomes thin
enough for thermally excited electrons to tunnel through. This tempera
ture dependent mode of current transport is referred to as thermionic-
field emission.
component dominates the current flow, and the transmission coefficient
has the form [Sze, 1969].
For high doping and low temperatures, however, the tunneling
T « exp(-q<|> /E ) D OO (2.50)
where
E = (<lh/2) (N,/e mV 00 a s e (2.51)
and the tunneling current has a similar expression
Jr « exp(-q*b/Eoo) (2.52)
Equation (2.52) indicates that the tunneling current increases
h exponentially with . The ratio of the tunneling current to the
thermionic current for a gold-silicon (Au-Si) barrier as a function of
temperature is shown in Fig. 2.15. Notice that for higher dopings and
lower temperatures the tunneling component is dominant.
An expression for the diode current density that expresses both
thermionic and thermionic-field emission is given by [Rideout, 1975]
J = Jr exp(qV/n kT)-exp([l/n - 1] qV/n kT) (2.53)
where n is an ideality factor whose value is very close to unity at low
doping and high temperatures. However, it can depart substantially from
unity at high doping or lowered temperatures. The normalized current-
voltage characteristic predicted by Eq. (2.53) is shown in Fig. 2.16.
(3) Field Emission
When the ionized doping carrier concentration becomes very high,
the barrier width becomes thin enough for carriers to tunnel through at
the base of the barrier. Figure 2.17 illustrates the current-voltage
characteristic for a Schottky barrier contact for different doping
levels.
2.3-.4 Gate Voltage Effect on Schottky Barrier
At low temperatures with non-degenerate source and drain doping
levels, the MOSFET's I-V characteristic exhibits a Schottky barrier
effect due to the freeze-out of carriers. As the gate voltage is
increased, however, the apparent drain voltage, is decreased.
41
-5
-10
,-15 10 200 300 100
T(K)
[The tunneling current will dominate > 1)
at higher dopings and lower temperatures.]
Fig. 2.15 Ratio of Tunneling Current Component to the Thermionic Current Component of a Gold-Silicon Barrier
42
+25
n=1.5 / n=2 n=l
+20
+15
n=5 +10
+5
-2 -8 -6 -10
+8 +10 +6 +4 +2 n=l
-5
n=l. 5
-10
-15
-20
n=2 4-25
Fig. 2.16 Normalized Current-Voltage Characteristics Predicted by Eq. (2.53) [Rideout, 1975]
43
/
a Thermionic emission dominates
b Thermionic-field tunneling dominates
c Field-emission tunneling dominates
Fig. 2.17 Schematic Illustration of the Current Voltage Relationship for a Schottky Barrier Contact [Rideout, 1975]
(Vtvtu considered here to be the drain voltage necessary to raise the DTH
drain current I g to 10 yA for a given gate voltage.) This fact has
been observed experimentally and the data collected from the measure
ment on three different devices (different W/L ratio) are shown in Fig.
2.18. This effect can be explained with the aid of Fig. 2.19. As the
gate voltage is increased, the gate field fringing effect increases.
Therefore, electrons are injected into the source and drain regions
near the silicon-silicon dioxide interface, and the carrier concentra
tion in these regions are enhanced. This increase of carrier concentra
tion has the effect of increasing the tunneling component of the
Schottky barrier diode current and lowering the barrier.
2.3.5 Modeling of the MOSFET I-V Characteristics with Schottky Effect
In this model it is assumed that the doping level is in the
transition range of non-degenerate and completely degenerate source and
drain. This assumption is based on the fact that at room temperature
the MOSFET I-V characteristic exhibits normal behavior, but when it is
cooled to 77 K and below, a Schottky effect starts to appear at the
source and drain contacts. In fact, some of the carriers start to
freeze out, reducing the ionized doping level as predicted by Eq. (2.9)
repeated here
N c
0.25 + exp (2.54)
45
2 . 0
1.6 (4.2 K)
1.2
(77 K)
0 . 8
0.4
0
8 6 4 2 0
VG(v)
Fig. 2.18 Experimental Values of the Drain Apparent Threshold Voltage as a Function of Applied Gate Voltage VG at 77 K and 4.2 K
46
m Z—r-r-m-7-r-r
2 /, I ' ' ! ' / f
Gate // n+ Source 1 n+ Drain
J I
(a) Self-aligned poly-silicon gate structure
Z/////W///////A (b) Fringing effect of the applied gate field
Fig. 2.19 Field Fringing Effect Due to the Applied Gate Voltage
47
Assuming that the Fermi level is very close to the conduction band
level, Eq. (2.54) can have the form
n « N
3/2
(2.55)
where is proportional to T
Therefore, the MOSFET device can be modeled by the simple cir
cuit shown in Fig. 2.20. The apparent drain voltage is the sum of the
voltage drop at the forward and reverse Schottky diode when the device
is conducting 10 pA. As the drain voltage increases, the current is
first controlled by the reverse-biased diode, then by the MOSFET
device channel action. To simplify the analysis it is assumed that the
MOSFET drain current is zero for Vn. < V_„„ and then the current lib Uirl
increases as if an effective drain voltage, has been applied.
The value of V_„__ is given by Dfti1 r
VW'1 -exp
DEFF
(V, DTH
(T/300)
vii\ 0)W J)
o
for VDS 1 VDTH
foT VDS < VDTH
(2.56)
where a and m are to be determined experimentally. The experimental
values of V--,. at 77 K and 4.2 R as a function of V„ are shown in Din vjo
Fig. 2.18, and follow approximately a linear dependence upon the gate
voltage. These are given by
48
G
J A
Fig. 2.20 Simple Model of MOSFET Device Including Schottky Barrier at the Source and Drain Contacts
49
VDTH = 1.2 - 0.12 VGS @ 77 K (2.57)
VQTH = 2.25 - 0.162 VGg @ 4.2 K (2.58)
for values of V g < 8 V.
The justification of Eq. (2.56) is derived from the fact that
a) The tunneling probability is proportional to exp(-l/E),
where E is the applied electric field at the barrier. The
factor V__m is a correction factor for the field strength GS>
since the tunneling probability increases with increasing
VGS' 4 b) The tunneling current increases exponentially with .
From Eq. (2.55), the carrier concentration is proportional
3/2 to T . Hence
N « (T/300)3/4 (2.59) a
The right side of Eq. (2.59) appears in the exponent of Eq. (2.56) to
show that the reverse biased diode has a sharper breakdown voltage at
lower temperature (or lower doping) so that for > vDTIj» the MOSFET
I-V characteristic is very similar to that at room temperature except
for a shift to the right by
2.4 Temperature Dependence of MOSFET Device Parameters
2.4.1 Temperature Dependence of E
Experimental results have shown that for most pure semiconductor
materials, the energy gap decreases with increasing temperature. For
high purity silicon, E (300 K) = 1.12 eV, and E (0 K) = 1.16 eV. There-S S
fore, Eg(T) *-s a rather weak function of temperature and is given by the
empirical form
2
Eg(T) = Ego ~ (tVb) (2.60)
where E = 1.16 eV, a = 7.02 x 10~\ and B = 1108. Figure 2.21 shows
the variation of the band gap energy with temperature in silicon.
However, the situation is completely different for degenerate
semiconductor where E (T) decreases due to band-edge tailing. Since g
the band gap energy is a weak function of temperature, its contribution
to the threshold variation with temperature is negligible.
2.4.2 Temperature Dependence of n
The intrinsic carrier concentration is a strong function of
temperature. From Section 2.2.2, the empirical relation for n is
given by
n± - 3.87 x 1016 T3/2 exp(-EgQ/2 kT) (2.61)
2.4.3 Temperature Dependence of
The Fermi level in a p-type semiconductor was derived earlier
for two ranges of temperatures. At very low temperatures the Fermi
level is given by Eq. (2.23), and repeated here
51
1.5
1.4
1.3
0.9
0 . 8
200 0 400 600 800
T(K)
Fig. 2.21 Energy Band Gap of Silicon as a Function of Temperature [Sze, 1969]
52
E + E
Ef = - kT/2 Jin
N a
2N ( 2 . 6 2 )
However, at relatively high temperatures, the Fermi potential
is given by Eq. (2.24), and shown here in a different form
N a
<|»p - kT/q Zn ( T ) ( 2 6 3 )
By examining Equations (2.62) and (2.63), it can be seen that
the Fermi potential varies more strongly at higher temperatures than at
lower temperatures. Therefore, a smaller variation of the threshold
voltage is expected at sufficiently low temperature.
A plot of the bulk Fermi potential as a function of temperature,
15 -3 with the bulk concentration N =10 cm , is shown in Fig. 2.22. The
a
strong variation of Fermi potential with temperature plays the major
role in shifting the threshold voltage.
2.4.4 Temperature Dependence of $
For a metal-oxide-semiconductor system as shown in Fig. 2.8,
the work function difference between metal and semiconductor is given
by
I E <T) - •» " A * + "V + *FCI) (2.64)
for a p-type semiconductor. However, if n-type polysilicon was used
53
0 . 6
0.5
-3-
3 <>•* u p. <u JJ 0 01
0.3
0 .2
0 .1
300 250 100 150 200 50
T(K)
Fig. 2.22 Variation of the Fermi Potential as a Function of Temperature with Bulk Doping Concentration of
1015(cm-3)
instead, as in the case of our design, the diagram of the
semiconductor-oxide-semiconductor band is shown in Fig. 2.23. In
this case
E (T)
•as h (2.65)
for an n+ doped polysilicon. Here again, the dependence of (|> upon
temperature is almost entirely embodied in the variation of (T).
2.4.5 Temperature Dependence of
The temperature dependence of the electron inversion layer
-3/2 mobility has been shown to be proportional to T in the high
temperature range (T > 250 K) as illustrated in Fig. 2.24. However,
as temperature is decreased below 250 K, the electron effective
mobility in the channel does not follow the same strong dependence
on temperature. In the low temperature range (T < 250 K), it has been
reported [Gaensslen et al., 1977] that the electron inversion layer
mobility increases slowly and follows a linear dependence on tempera
ture, for the high field case. However, the extrapolated value of
at 4.2 K gives a value of 1757 cm /vsec, which is not unrealistic
if the roll-off of the effective surface mobility that occurs at very
low temperature due to impurity scattering is ruled out. In fact,
3/2 the bulk mobility at very low temperature increases as T . Although
the linear approximation may give a higher value of Ue££ at 4.2 K,
nevertheless it is used in the simulation program. From Fig. 2.25
Weff(T) is given by
55
Vacuum Level
T <p - tp m . Tsn
r p
a E /2 g J Tms J Tms
1 _ i*' + ...
J Tms
n+ Silicon Gate Oxide Silicon
Fig. 2.23 Energy-Band Diagram of a Polysilicon - SiCL-Si Structure
56
4 10
-1.5
3 10
2 10
3 2 10
T(K)
Fig. 2.24 Electron Inversion Layer Mobility as a Function of Temperature for Silicon [Leistiko, Grove, and Sah, 1965]
57
2 . 0
1.5
1.0
u 0.5
100 150 200 250 300
Fig. 2.25 Electron Inversion Layer Mobility as a Function of Temperature for the High Field Case [Gaenssler, et al., 1977]
58
P -- - 1775 - 4.25 T cm2/vsec (2.66) err
which is a good approximation for the temperature range 300 K - 77 k.
2.4.6 Temperature Dependence of V,j,
The MOSFET threshold voltage, VT, was given in Eq. (2.35) and
repeated here after substituting for <f>mg in the case of polysilicon
gate
E (T) qQ . !
VT * " -V * -C + + M ox ox (2.67)
where distributed ionic charges Qg££ are included in the interface
charge density Q ss
Assuming Q does not depend on temperature and neglecting the SS
band gap variation with temperature, the variation of the threshold
voltage with temperature can be computed for relatively high tempera
ture range as follows [Vadasz and Grove, 1966]
dVT d«p x d ,
dT " dT + C dT s'VM ox
+ ( 4qEsNa = dT 2Cox dT V *p j
^ (i + /qgsNa'\ ' dT \ Cox 7 )
59
where the Fermi potential was given earlier in Eq. (2.63) by
N ij>F(T) = kT/q In n = kT/q [to Ka - fcn n T)]
Therefore
dF
dT
N = k/q £n + kT/q
1 dn (T)
n£(T) dT
But
1 eo dn. (T)/dT = 3/2 ± n (T) + 5- n. (T) 1 T 1 2kT 1
Hence
d ^F _ F kT — •**" "t* dT T q
- 3/2 i T 2kT
"i( VT> - - -g
Since E » 3kT/2q for most temperatures of practical interest go
dK 1 — - - IMT> - E/2ci] dT T . F 8°
and, finally
v
60
dVT 1 f 1 I qesNa ' \ sr' t [VT> - V2'1 ( 1 + -J -f~ )
\ V F / (2.68)
Equation (2.68) is valid at relatively high temperatures. How
ever, at sufficiently low temperature, the Fermi potential is given by
E~ AEm l.rr lb = + — Jin (N /2N ) F „ - a v
2q 2q 2q
and
1 / AE 3kT Eeo \ d /dT = - ( ip + — ] F T \ F 2q 4q 2q /
Therefore
dvT/di-i(»F+^a-^2)(i + ±JJ3T) T V 2q 2q / \ Cox y i|>p / (2.69)
where 3 kT/4 has been neglected. To ensure the continuity of
Equations (2.68)and (2.69) for numerical computations, a general form
that approximates both equations in the temperature range 300 K - 4.2 K
is given by
+ y* - T/3°°> -^)(1 + ~r~~\l —^) dT T\ F 2q 2q / \ Cox
61
A plot of dV ,(T)/dT as a function of temperature is shown in
15 -3 Fig. 2.26, for a substrate doping of 10 cm . From this graph one
can see that the slope of with respect to temperature is about -1.4
mV/K in the neighborhood of 300 K, and decreases to about -0.5 mV/K in
the neighborhood of liquid helium temperature. In the neighborhood of
room temperature, the change is almost a factor of two less than that
for metal gate, reported in some of the literature where <|> has been
taken as a constant.
2.4.7 Temperature Dependence of Ip
The MOSFET device channel current ID is temperature dependent
as can be seen from Equations (2.37) and (2.38) for the triode and
saturation region, respectively. In both regions of operation, the
channel current is linearly dependent on the inversion layer mobility,
eff* However, it was shown that l*e££ increases with decreasing temper
ature. Hence, IQ increases as the temperature decreases (the decrease
in V - V is very small and overpowered by the increase in p f.). G T £
Figure 2.27 is a plot of I_ as a function of V , with the temperature D u
as a parameter. The effect of threshold shift with temperature can be
seen clearly since conduction cannot take place until is greater
than Vt(T). Here the subthreshold conduction is neglected.
2.4.8 Temperature Dependence of Jg
Mainly two components contribute to the p-n junction leakage
current density under reverse bias. These are the diffusion component
and the generation component. The generation component dominates under
62
2 . 0
1.5
1.0
H > "O
0.5
50 0 100 150 250 200 300
T(K)
Fig. 2.26 Variation of the Threshold Voltage with Temperature for Substrate Doping Concentration of 10l5Cmr3
50 r
77 K
300 K
a M
6 4 5 2 3 0 1
VG(v)
Fig, 2.27 MOSFET Saturation Region Transfer Characteristics with Temperature as a Parameter
OJ
64
reverse bias at low temperature (T < 300 K) since it varies proportional-
2 ly to n compared to n for the diffusion component. For a typical
p-n junction, the leakage current density at room temperature for small
-7 2 reverse bias voltage, V , is of the order of 10 A/cm , assuming
K —fi IS 20
t = 1 0 s , N = 1 0 c m , a n d N , = 1 0 c m , w h e r e t i s t h e e f f e c t i v e o a d o
minority carrier lifetime. As temperature drops to 250 K, the leakage
—10 2 current density decreases dramatically to about 10 A/cm , a three
order of magnitude difference for fifty degrees change in temperature.
However, in a practical situation, junction curvature (local defects
such as fast interface charges) greatly increases the leakage current
over its ideal value. But for all temperatures of cryogenic operations,
the p-n junction leakage current is extremely small and can be neglected.
CHAPTER 3
MOSFET STATIC CHARACTERISTICS PROGRAM SIMULATION
FOR LOW TEMPERATURE APPLICATIONS
3.1 Introduction
MOSFET device static characteristics behavior at low tempera
ture showing the temperature variation of the device parameters was
discussed in Chapter 1. To complete this theoretical study it is very
helpful to be able to predict the d.c characteristics of MOSFET devices
at any given temperature in the range 4 K - 300 K. For this reason
a FORTRAN computer program was developed to model the device behavior.
However, due to the specific type of applications we are interested in,
the program has a limited functional capabilities.
3.2 Program Description
3.2.1 Program Specifications and Limitations
The following are the main features of the Low Temperature
MOSFET device modeling program (LTMOSFET):
1. For our applications the MOS transistor is used as a shunt-
chopper with the source and substrate tied to ground as shown
in Fig. 3.1. In this structure the threshold voltage sensi
tivity with substrate bias is ignored. Therefore, the
variation in threshold voltage will be due only to tempera
ture.
65
+3v
I.R.D
*1J230 J230
GND
Out
GND Bias Reset
-3v
Fig. 3.1 Basic Integrating JFET Circuit with n-channel Enhancement Mode MOSFET Reset Switch and a Photoconductor
2. Although the output conductance becomes significant for long
channel devices operated at very low temperature, this effect
is neglected in this model.
3. The drain-characteristic breakdown voltage (drain avalanche
and gate-suppressed drain avalanche) is also ignored for
the same reason given in #1.
4. Uniform impurity distributions are assumed for the substrate
and the source and drain regions.
5. High-field electron inversion layer effective mobility is
used throughout. The values of are calculated from
Eq. (2.66).
6. The model neglects the subthreshold conduction. Therefore,
ID = 0 for VG < VT.
7. For a self-aligned process, the gate overlaps both the source
and drain; therefore, the drain offset voltage is due to
non-ohmic contact to the source and drain regions. This
offset voltage is determined experimentally and fed to the
program.
8. Only the n-channel enhancement mode MOSFET devices are modeled
9. The temperature range of validity of the formulations used in
this program is limited to 4 K - 300 K.
10. Channel length modulation effect is neglected.
As mentioned previously, all voltage polarities are taken with
respect to ground. In the following sections the input parameters to
LTMOSFET (Low Temperature MOSFET) modeling program and the outputs
68
generated by this program are discussed. Also, a sample program output
is shown.
3.2.2 Input Parameters and Output Generated Plots
This modeling program is a special program for plotting speci
fied electrical characteristics of the n-channel MOSFET device in the
temperature range 4.2 K - 300 K. However, the program could be modified
to include second order effects and optional plots. The interest for
the development of this program is to predict within an acceptable limit
the MOSFET device electrical behaviors at low temperatures.
The input parameters to LTMOSFET are:
_3 1. Substrate impurity concentration XNA (cm )
2. Gate oxide thickness TOX (cm)
_2 3. Si-SiO„ interface charge density Q (cm )
4 ss
4. Threshold adjust implant QIMP (cm~^)
5. Channel width W (in ym)
6. Channel length XL (in vim)
7. Parameter a (no units)
8. Parameter m (no units)
The outputs generated by this program are:
1. Plot of the Fermi potential as a function of temperature
2. Plot of the threshold voltage VT as a funtion of temperature
3. Plot of the variation of VT with temperature as a function of
temperature
4. Plot of versus Vgg at 300 K, 77 K and 4.2 K
5. Plot of Ipg versus V g with V g as a parameter at 300 K,
77 K and 4.2 K neglecting the Schottky barrier.
6. Plot of I _ versus V with V as a parameter at 77K and Do Ob Ob
4.2 K taking into account the Schottky barrier effect.
3.2.3 Description of <J>j,(T) Output Plot
The Fermi potential is computed using Eq. (2.21) which is
valid in the temperature range of our interest. The main program
LTMOSFET calls a subroutine, THRVOL, to calculate the values of p(T).
The plot of the Fermi potential as a function of temperature is done
by calling the subroutine MULPLT. The output produced by this sub
routine is shown in Fig. 3.2.
3.2.4 Description of V^,(T) Output Plot
The threshold voltage is computed by using Eq. (2.67) and
this is done by calling the subroutine THRVOL. The user specifies a
theoretical or an experimental value for Q . Again, the generated s s
output plot is done by calling the subroutine MULPLT. The output
produced by this subroutine is shown in Fig. 3.3.
3.2.5 Description of dV ,/dT Output Plot
This plot is generated by computing the variation of the
threshold voltage given in Eq. (2.70) at different temperature points,
and then call MULPLT. The subroutine THRVOL computes the values of
dV^,/dT at the specified temperature points. The output produced by
this subroutine is shown in Fig. 3.4.
70
0.3194E*00 I~I—I-
300- .
run of nc femu-potential as a fjctiqh of tbtemtuk. FIMI-fOTEVTIM. (V)
I J j t <».»W«*00 ^ (0.556«*C0
200
<D M
3 I00 S-4 (U a. 5 <u H
-«IIS SCNi ! II.OOK/DIV. -MIS SCALE i 0.237SE-01/BIV.
-I—I—I- -I—I—I—«—I—I—I 1—I 1—I-I
Fig. 3.2 LTMOSFET Generated Plot of the Fermi Potential as a Function of Temperature
nor of nc mitnm r the tmkmli mm aim lEirewrus versus top. 71
-o.iwe«0! I-I—I-
300 ,* •
200
100
-»—I—I--C.IM1E»0I -I—I—I-
<V7H/dT («V> -o.iiwwo -o.sks»oo -4.smtw -•—I—I—I—»—I—I—I—I—I--I
•I—I—! 1—I—I--*I1S SCALE : 10.MK/DIV. -MIS SCALE I O.UWOO/I1V.
-I—I—I- -I 1—I—I—I—I—I—I—I—I-I-!
Fig. 3.3 LTMOSFET Generated Plot of the Threshold Voltage Variation with Temperature
/lot tf nc tmksnou vutac us * function of memm 72
0.I832E«01 I-l—«--
(0.IWt«8j VTH (V)
0.1T77E01 I.20S0M1 «.2123EIOI 0.219SE+01 -•—I—I—I—I—I 1—I—»—I—I—I—I—I-I
300
200
m
£ 100 § H
-I- -I 1 1 1- -I 1 » 1 1 1- -I 1 1 1 1 1 1--I
WIIIS SCALE : IO.MK/IIV. -MIS SCALE I O.M3W-01/HV.
Fig. 3.4 LTMOSFET Generated Plot of the Variation of the Threshold Voltage with Temperature as a Function of Temperature
3.2.6 Description of the MOSFET Saturated Transfer Characteristic
The values of are computed at 50 points by varying
Vgg from 0 to 5 in step of 0.1V. *dsaT *S comPute<* by calculating
VDSAT rom Ecl* (2.39), and then using that value in Eq. (2.36) to
calulate the Ipg^x* ^SAT *S comPutet* calling the subroutine SC,
assigning the value VDS T to Vp, and calling the subroutine TC to
compute The program generates plots of I g * versus V g at
300 K, 77 K and 4.2 K. The output produced by this subroutine is
shown in Fig. 3.5.
3.2.7 Description of the MOSFET Device I-V Characteristic Plot
A family of I versus V curves with V as a parameter is D D G
plotted at three different temperatures 300 K, 77 K and 4.2 K. The
values of V are generated by the program and vary from 2V to 8V by U
a step of 2V. The program neglects the p-n junction leakage current
and subthreshold conduction. Therefore, for V < V , the drain 0 i
current is assumed to be zero. Also, the channel length modulation
is neglected.
The drain current 1 is computed as follows. At a given
temperature, the threshold voltage V , is computed using Eq. (2.67);
then its values is compared to V . The current is set to zero when (7
V < V . For each value of V , V is computed and compared to O in (7 UbAl
Vp which varies from 0V to 10V by steps of 0.2V. The current is com
puted using Eq. (2.36) and by replacing VD by whenever exceeds
VDSAT" outPuts Pr°duced by this subroutine are shown in Fig. 3.6.
PLOT OF SMT. IMT VS. VSS AT 30W.77K MO IN
Ilttl/2 II 2.06-4 *511/2] It. 20. SO. 40. SO. fO. 70. N. f -I—I—I—I—1—I—I—I—I—I—I—I—I—I—I—I—
1
•I . * I . • I.
< I • . I • . I • . I • . I • . I t. I •. I • I • I • I 4.2 K
.• »
77 K 1 , . • I . • l . • I . • l . • I . • l
• I
300 K '• \ f
-AIIS SCALE: .IV/tlV.
Fig. 3.5 LTMOSFET Generated Plot of AdSAT versus at 300 K, 77 K and 4.2 k
PLOT OF ItS VENUS VIS IT T«3t0.0 K
0. I-•I t II ,»l I .• I I -• I I . * 1 1 . t i l
10. -I-
20. -J- -I-
40. -I-
N. --I-
IIS (( 2.E-2 *AI 10. 70. N. W
-I 1 1 1 1 1 1 1
. • . • - • . • , • . • , t • • . • . • . * . • - • >
. M" , • . • " . • , - •
; :> , • , 4 • • . • , 4 , 4 , 4 - 4 , 4 , 4 , 4 , 4 - 4 a 4 , 4 . 4 , 4 - 4 , 4 , 4 , 4 . • - 4 I—
I « I I t • I I I t I
o
> vO
W o
•I-
> 00
CO o
-I—I—I- -I—I—I
IHUIS SCMit .2V/IIV.
(a) T = 300 K
3.6 LTMOSFET Generated Plot of I c versus V VGg as a Parameter DS
n.or OF us tosus ns IT T« 77.0 *
IK (I 2.E-Z *M t. 10. 20. 30. 40. SO. to. 70. N. fO. I—|—j—|—j—|—j—|—J—|—|—|—j—|—1—|—J—|—1-•I I * I I • I I
I I I I I I I I t I
* I
I I I I I I I I I I
I
>
II W o
I
> vO
C/3 o
> 00
II CO O
WIIS SCALE: .2V/DIV.
(b) T = 77 K
Fig. 3.6 (Continued)
HOT OF IIS VERSUS WS IT T« 1.2 *
IIS II 2.E-2 •») 0. 10. 20. 30. (0. SI. M. 70. N. I—|—j—|—i—| ]—|—J—|—|—t—]—,—j—|—J—|-• I I • I # • I I • t I
I I I I I I « I I I I • I I
> <r
cn o >
I—|—j—|—i—
HI 15 SUUI .2V/DIV.
> vO
W o
-I—,—I-
> 00
w CJ3
-I 1 1-
(c) T = 4.2 K
Fig. 3.6 (Continued)
3.2.8 Description of MOSFET I-V Characteristic Plot Including the Schottky Barrier Effect
These families of plots are generated by the same manner
described in Section 3.2.7 with the following exception. The value
of the drain apparent threshold voltage is calculated from
Eq. (2.57) or Eq. (2.58). For VQ less than Vj^, the drain current is
considered to be zero. However, for V_. greater than V__n, an effective D Din
drain voltage, *-s computed using Eq. (2.56). The is used
instead of to calculate the drain current as described previously.
The I-V characteristics with Schottky effect generated by the program
are shown in Fig. 3.7.
3.3 LTMOSFET Generated Output
The output generated by the computer program LTMOSFET, simulat
ing MOSFET device behavior (Device M6) at low temperature is shown
below. Although this program was developed to simulate only enhance
ment mode n-channel MOSFET devices, it could easily be modified to
simulate the four types of FETs and produce each plot at the user's
choice. The input parameters are shown in Table 3.1.
It PLOT OF IK VS. VIS IICLUSIK THE MOTTKY NMIER EFFECT »T T» 77.0K It
IN (I Z.E-2 •«) 0. 10. 20. SO. 40. SO. t 40. 70. ( 80. W. 100
I t i +1 I - I I • I I • I I • I I • I I • I I
I I I * I t I I I *
I « I t I t t t 1 >
I
>
Cfl o
> vO
II CO Cfl >
00
II C/3 O
| 1 J 1 J 1 1 1 J 1 J 1 J 1 J 1- 1 1 1 1 1
HIIS SULEt .2V/IIV.
(a) T = 77 K
Fig. 3.7 LTMOSFET Generated Output Plot of IDg versus V, with VGg as a Parameter Showing the Schottky Effect
tl PLOT ff IK VS. «N 1KLUBIM THE MOTTXY MtftlER EFFECT «T T« 4.2f It IIS (I 2.E-2 •«)
0. It. 2t. It. 40. St. M. 70. N. I—|—i—|—J—|—J—|—|—|—i—|—|—|—I—|—I—|-I 0 0 I -I I 0 tl I • t t • I I • t I • I 0 • t 0
> <3-
Cfl o
> vO
C/3 o
mi IS SOLE) .2V/IIV. •I—1-
w o
-I—I—I—I-
(b) T = 4.2 K
Fig. 3.7 (Continued)
81
Table 3.1 Input Parameters to LTMOSFET Simulating Device M 6
Simulation of n-Channel Enhancement Mode MOSFET Device at Cryogenic Temperatures
Device Parameters:
Bulk Concentration NA 0.10E + 16
Gate Oxide Thickness T 0.11E - 04 ox
Surface Charges Qgg 0.50E + 11
Threshold Adjust Implant -0.37E + 12
Channel Width W 50.0
Channel Length L 30.0
R.T. Electron Inv. Lay. Mob. Uo 500.0
Parameter Alpha .0500
Parameter m 1.0
CHAPTER 4
DESIGN AND FABRICATION OF CRYOGENIC
TEMPERATURE MOSFET DEVICES
4.1 Introduction
To demonstrate the improvements in device characteristics of
MOSFETs that occur at cryogenic temperature and predicted by the
theoretical model discussed in Chapter 2, the LTMOSFET program was used
to design an n-channel, self-aligned polysilicon gate MOSFET test
device suitable for operation at low temperature. The main interests
in this design are to study the threshold voltage shift, the change in
the surface inversion layer mobility, the Schottky effect for non-
degenerate source and drain doping levels, and the drastic decrease in
p-n junction leakage current.
4.2 Design Considerations
The starting substrate was a boron doped silicon wafer with a
15fi-cm resistivity (i.e., lO^cm impurity concentration), and a ^-00^
orientation. The wafers used were available at The University of
Arizona Microelectronics Laboratory. To ensure an enhancement mode of
operation, the threshold voltage has been raised by utilizing the
threshold tailoring property of ion implantation. This method has the
advantages not only of adjusting the device threshold voltage to a
given value, but also to raise the field inversion threshold voltage
and prevent channeling.
82
83
Due to the lack in MOSFET process characterization parameters,
11 12 -2 such as Q , different implant doses ranging from 10 to 10 cm have
SS
been used. This range of dose was carefully chosen so that the thresh
old voltage falls in the range of 1 to 2V for a theoretical value of
Qgs equal to 5 x lO^cm and a gate oxide thickness of lOOoA. The
energy at which ion implantation was done was chosen such that the
Gaussian profile has its peak of distribution at the Si-Si02 interface
in order to facilitate the calculation of the number of ions that
reached the silicon. Also, we assume a relatively uniform profile
underneath the gate so that the assumption of uniform doping level in
the channel stays valid.
A first order calculation of the channel depletion layer width
at threshold shows that most of the implanted dose in the silicon lies
inside the depletion region. Although lower oxide thickness results
in higher device gain [See Equations (2.41) and (2.42)], we chose to
O use a gate oxide thickness of at least 1000A to prevent reliability
problems such as pin holes and to decrease the gate capacitance. To
minimize the gate overlap capacitance to the source and drain, a self-
aligned polysilicon gate process with ion implanted source and drain
region was used.
4.3 Description of MOSFET Test Vechicle
In order to verify the general quality and reliability of the
process and to check the spreads in transistor parameters, it is
necessary to include some basic test structures. These include several
MOSFET of varying aspect ratio W/L, an M0S capacitor (gate oxide),
four-point probe (n+ diffusion), and two resistors (polysilicon and n+
diffusion). Figure 4.1 illustrates the layout of a test chip used in
this work. The circuit contains eleven transistors, M 1 through M 11,
where each device may be probed separately. The width and length
dimensions of the transistors are listed in Table 4.1 with the mask
level dimensions.
4.4 Discussion of MOSFET Test Device Fabrication
The devices were fabricated using the following method. First,
a field oxide of 2500A thickness was thermally grown in wet oxygen on
boron doped, ^-00^ oriented silicon substrate of 150-cm resistivity.
Then a boron implant was used to raise both gate and field inversion
11 12 -2 threshold voltages. The dose used ranges from 10 to 10 cm . See
Appendix C for the complete procedure.
Next, the device area was delineated, and a 1000A clean gate
oxide was grown by thermal oxidation with 3% HC1 (anhydrous hydrogen
chloride). This process produces an electrically stable oxide with
minimum ionic contaminants such as sodium and potassium. This oxide
also has an increased dielectric breakdown strength, reduced interface
trap density, and a reduction in oxidation-induced stacking faults.
A 4000A, LPCVD polysilicon layer was then deposited over the wafer,
and was delineated using an anisotrop plasma etching technique. The
source and drain regions were implanted using phosphorus as the dopant
15 -2 species. The implant dose and energy were 10 cm and 90 keV,
respectively. This was to ensure a Gaussian profile with a peak
85
Resistor (diff.)
MOS Capacitor
Four-Point Probe
M2
Resistor (Poly-Si)
M3 M4 M5 M6 M7 M8
M9 M10 Mil
Fig. 4.1 Layout of Low Temperature MOSFET Test Vehicle
86
Table 4.1 Mask Level Dimensions of Test MOSFET Transistors
Device W (vim) L (ym)
M 1 100 50
M 2 100 30
M 3 100 20
M 4 100 10
M 5 100 5
M 6 50 30.
M 7 50 20
M 8 50 10
M 9 20 10
M 10 10 10
M 11 10 5
concentration at the Si-SiO interface of approximately 5 x 10 cm .
Although the dose may seem high, after drive-in the surface concentra-
19 -3 tion drops below 2 x 10 cm , and higher implant doses could have been
used. But, because of equipment problems with using a low current ion
implanter, it was necessary to stay with this value.
The implant was followed by a drive-in of 140 minutes at 1050°C
in a nitrogen atmosphere. The drive-in time and temperature produced a
junction depth of 1.5 ym. Approximately 8000A of phosphorus-doped
silicon dioxide was deposited by low temperature chemical vapor deposi
tion (CVD). Contact windows to the source, gate, drain, and substrate
were opened, and aluminum was deposited by e-beam. The aluminum metalli
zation pattern was delineated using a wet chemical etch, and then
sintered on a strip heater at 450°C for three minutes in Forming gas.
The fabrication sequence is illustrated in Fig. 4.2, and uses
a total of four photomasks. The masking steps were all performed with
KTI 747 negative photoresist. Appendix B gives the standard cleaning
process used and Appendix C gives the fabrication procedure.
88
(a) Initial Oxide Growth
SiO„
p-Substrate
Boron Implant
I I 4 4 I I i 14 4
(b) Threshold Tailoring Implant
wmmmmmmmnnh
(c) Mask if 1: Device Area Delineation
2ZZZZL y/M
(d) Gate Oxidation
Gate Oxide
777m /. mm
Fig. 4.2 MOSFET Fabrication Sequence
89
r Polysilicon TTTttX-i'.': V. • .v •: v/*-#77777I /fif hi> iui>>> > >) ftmtt JW/////A
(e) Polysilicon Deposition
(f) Mask //2: Polysilicon Etch
/////Vrrr-r I 7/) tint Y////J
Phosphorus Implant
* 1 1 4 1 1 1 1 1
Ull A-ttt-7 i h'i i'?';;vA) >))) (7777/
(g) Source and Drain Implant
(h) LTCVD Si02 Deposition
h t Y i i i
Fig. 4.2 (Continued)
(i) Mask #3: Contact Window Opening
m * 0 * « • «• a »». I t *•
zzzzzz
Aluminum
(j) Aluminum Deposition
7i
(k) Mask #4: Metal Delineation |
m
Fig. 4.2 (Continued)
CHAPTER 5
EXPERIMENTAL RESULTS
5.1 Introduction
The temperatures of primary interest for conducting electrical
measurements on test devices are room temperature, liquid nitrogen (L )
temperature at 77.3 K and liquid helium (LHe) temperature at 4.2 K. All
of the measurements were made at the Steward Observatory Laboratory. A
single device, Transistor M 6, was selected for detailed low temperature
characterizations. The device was diced and mounted on a gold-plated
header using non-conductive epoxy. A 12 mil thickness sapphire sub
strate was placed between the silicon and the header surface to reduce
stress problems that might occur at such low temperatures. Aluminum
wires of 0.7 mil diameter were ultrasonically bonded to the pads. The
chip was then mounted in an evacuated research dewar. All wiring
connections inside the dewar were done using a 3 mil diameter constantan
wire of very low heat conductivity. Also, the device was shielded to
minimize the heating effect due to radiation. A Tektronix Type 575
transistor curve tracer was used to monitor the I-V characteristics of
the test device at all temperatures. The circuit used to measure I g
versus V is shown in Fig. 5.1. Ud
o The gate oxide thickness was measured to be approximately 1100A.
Standard groove and stain measurement showed a source and drain junction
depth of about 1.65 pm. The effective Si-SiC>2 interface charge density
91
DVM
DVM
Fig. 5.1 Circuit Schematic for I versus V Measurement D Cj
VO to
10 -2 value used In the simulation program is 5 x 10 cm . The effective
temperature.
LTMOSFET was used to simulate the behavior of the Test Device
M 6 at 300 K, 77 K, and 4.2 K using the above listed values for input
data. The output generated by the program for this device was fully
shown in Chapter 3 as a sample program.
5.2 Device Parameters Measurements
5.2.1 Threshold Voltage Measurement
There are many acceptable ways for measuring the MOSFET device
threshold voltage. Here, we chose to use a simple method known as the
I Js versus V method. The circuit of Fig. 5.1 was used for this pur-Db Go
pose. The drain voltage was held constant at 4V to ensure operation in
the saturated region. In this region of operation the drain current
is given by
11 implant dose used in tailoring the threshold voltage was 3.75 x 10
_2 cm . The inversion layer electron mobility simulated by the program
2 is given by Eq. (2.66) which yields a value of 500 cm /vsec at room
2 2L ef f
or
I h - / JL „ Y5 (V - V DS \ 2L eff o x J \ GS l )
94
Values of are plotted as a function of V g. The inter
cept of the linear region of the curve with the V axis gives the Go
experimental value of the threshold voltage. Graphical interpolation
is necessary because of the weak inversion current at V < V . Plots UO 1
of 1-.J* versus V at 300 K, 77 K, and 4.2 K are shown in Fig. 5.2. Db V70
Values of V g are kept low enough to eliminate nonlinearity of the plot
due to roll-off of inversion layer mobility at higher vertical field.
Table 5.1 shows the theoretical threshold values calculated
using the LTMOSFET simulation program, the experimental values found
from Fig. 5.2, and the percentage error at 300 K, 77 K, and 4.2 K. In
Table 5.2 we list the change in threshold voltage AV,j, from its room
temperature value at 77 K and 4.2 K along with the percentage error.
In Table 5.3 the measured and calculated values of the threshold
voltage shift from temperature value of 4.2 K are shown.
The experimental value of the threshold voltage is within 8%
of the calculated value at 300 K and temperature, and 26% at LHe
temperature. This large increase of threshold voltage at 4.2 K may
be due to an increase in interface state trapping effect and a decrease
in Qgg [Rogers, 1968]. The contribution of Qgg to the threshold
voltage is much less than the observed deviation; hence, a more convinc
ing explanation is given by postulating the existence of two sets of
symmetrical states at the Si-Si02 interface, one acceptor type in the
vicinity of the conduction band edge and the other donor type near
the band edge [Harvey, et al., 1968]. As the temperature decreases,
25
20
Jt" 15 <
to * o
H w 10 a
>
V = 4v DS
(a) T = 300 K
(b) T = 77 K
(c) T = 4.2 K
VGS(v)
Fig. 5.2 Experimental Saturation Region Transfer Characteristic for Device M6
96
Table 5.1 Measured and Calculated Values of V , for Transistor M 6
Temperature V,j, (calculated) V,j, (measured) % Error
300 K 1.83 V 1.98 V 8.1
77 K 2.15 V 2.33 V 8.4
4.2 K 2.195 V 2.76 V 25.7
Table 5.2 Measured and Calculated Values of Threshold Voltage Shift from its Room Temperature Value
Temperature AV (calculated) AV , (measured) % Error
77 K 0.318 V 0.350 V 10.1
4.2 K 0.363 V 0.78 V 115
Table 5.3 Measured and Calculated Values of Threshold Voltage Shift from Temperature Value
Temperature V (calculated) V , (measured) % Error
4.2 K 0.045 V 0.43 V 955
more acceptor type surface states are filled, which results in an
increase in V . The change in threshold voltage at 77 K from its value
at room temperature Is about 350 mV or 1.5 mV/K. This is a good agree
ment with the theoretical results for polysilicon gate. However, the
theoretical simulation does not hold below temperature as explained
above.
Overall, the experimental results agree well with the calcu
lated values at room and temperatures, and deviate widely only at
extremely low temperature.
5.2.2 Inversion Layer Electron Mobility Measurement
Measurement of high field inversion layer electron mobility is
straightforward from the I-,, versus Vn(, plot. Indeed, the slope of Db (lb
the curve is approximately equal to
C f f -
Hence,
0 ueff ~ W/L • C
ox
Table 5.4 shows the theoretical and experimental values of
along with the percentage error at the three test temperatures. The
theoretical inversion layer mobility values below 77 K is steadily
increasing with decreasing temperature which is in disagreement with
the experimental results as a result of ionized impurity scattering.
L
98
Table 5.4 Measured and Calculated Values of High Field Electron Inversion Layer Mobility
Temperature yeff (theoretical) y
eff (experiment) % Error
300 K 500 cm2/Vs . 478 cm2/Vs 4.3
77 K 1447 cm2/Vs 1875 cm2/Vs 26
4.2 K 1756 cm2/Vs 1570 cm2/Vs 10.3
Nevertheless, the experimental results are within 10% of the calcu
lated values at 300 K and 4.2 K, and within 26% at 77K.
To show one important benefit of operating the MOSFET device at
low temperature we calculate the device transconductance, g , above m
the pinch-off regime
5s
" 8VGS VDS - const
* ».ff • Co* W/L - V
Therefore, any increase in the effective surface mobility
results in a proportional increase in the device transconductance.
5.2.3 I-V Characteristic Measurement
This measurement was done using the Tektronix Type 575 curve
tracer with external dc gate bias to allow displaying each curve
separately at a given gate voltage. Figure 5.3 illustrates the
measured characteristics at the three specified temperatures along with
several of the calculated points for purposes of comparison.
The simulated I-V characteristics are shown in Fig. 5.4.
These curves were produced at gate voltage values of 2, 4, 6, and 8
volts. Since the experimental I-V characteristics display a strong
Schottky effect at 77 K and 4.2 K, the LTMOSFET simulation program was
used with the option of showing that effect. Values of the parameters
m and a are estimated from the experimental results to be equal to 1.0
and 0.05, respectively. Clearly, both measured and calculated charac
teristics have an apparent drain threshold voltage, which is a
function of the applied gate voltage. The sheet resistance of the
implanted source and drain regions is measured to be approximately
65fi/Q .
From Irvin's curves, the surface impurity concentration at the
19 -3 source and drain is found to be approximately 3 x 10 cm . Apparently,
the source and drain regions are not sufficiently degenerate which is
in agreement with the theoretical criterion of degeneracy developed in
Chapter 2. Hence, higher surface concentration is needed for complete
degeneracy at temperatures as low as 4.2 K.
The room temperature I-V curves show a strong agreement between
the experimental results and the simulation model. This is consistent
with the good agreement between calculated and measured values of V
and Ue£f at this temperature. Notice the high output resistance due to
negligible channel modulation effect in long channel devices (L = 30 um).
100
Ver: 0.2 mA/Div
Hor: lv/Div
— Measured
0 Simulated
—n 1 i i t
VGS = 8v
VGS = 6v
> = 4v >— —i r
(a) T = 300 K
Fig. 5.3 Experimental I-V Characteristics for Device M 6
101
Ver: 0.2 mA/Div
Hor: lv/Div
— Measured
° Simulated
VGS ~ 8v
/ /, < I 0
/ : VGS = 6v
<
/ f y » ( » c
1 / / psj.
4v < » c
(b) T = 77 K
Fig. 5.3 (Continued)
Ver: 0.2 mA/Div
Hor: lv/Div
— Measured
0 Simulated
102
(c) T = 4.2 K
Fig. 5.3 (Continued)
nor of ids vosiis vgs it t«mo.o it
0. 10. Oi—«—i-•i * it .•i» .• i«
!-• « l . • I I . • l •
20. -I—
JO. IIS II 7.1-1 *A>
«. St. M. 70. M. W. -I—t—j—|—i—|—I—| 1—I—l-
M o
, •
2:: . • i . • i . • i
3-.: ' . • . • . • . •
4 : : :**£
5-.: M . • co . • O . •> A ' * O - • . • . • , • , •
7-•
.!! , • , • 9-.:
. • . • . • 10-t I—I-
t l l l t I
> vO
co o
-I-K-AIIS SCALE: .2V/DIV.
> CO
CO o
—,—I- -I—I—I—I—I-
(a) T - 300 K
Fig. 5.4 Simulated I-V Characteristics for Device M6
II HOT OF IK VS. VDS IICLU8IH6 THE SMOTTKT WWIE3 EFFECT *T T» 77.0K It IK (I 2.E-2 aA)
#1_ J0- 30. t «0. t »• f W. It' t 10. f tO. t H
« I I • , •» •
1 - 1 t • I I . • I I * 1 1 • I I • I I
I I I I I I I I I I I I I I I I
I I
> I > I > <r i vo | co
•
I—
II cn o
CO O
II w o
-I—I—I—I—I—I—I—I—I—I—I—I—I—I—I—•—I—«—
I-MIS SCALE: .2V/IIV.
(b) T = 77 K
Fig. 5.4 (Continued)
ii fior of ik vs. ve mciudjh tic swttxy iwriex effect at t* 4.x it ids (i 2.e-2 •«)
o. 10. ». 30- «. so. *0. . ro. 10. 01—I—I—I—1—i—I—I—l—I—I—I—I—I—I—l—I—I-
» I I
V . •I • • I I . • I • • I I • I I • I t
I « I I
10
I
> sr
to o
> vO
CO o
I 1 £ l CO I
CO o >
I—I—I—I—I—I—I—I—I—I—t—I—I-
I-MIS SOLE: .2V/0IV.
-I—I—I—I-
(c) T = 4.2 K
Fig. 5.4 (Continued)
106
However, at LN and LHe temperatures, there Is a discrepancy between
simulated and experimental I-V characteristics. The failure of the
model to correctly predict the device drain current at low temperatures
may be due in part to the lack of a correct model describing the
behavior of the inversion layer mobility in that regime. In addition,
the device experimental threshold voltage deviates largely from the
calculated value due to second order effects.
5.2.4 P-N Junction Leakage Current Measurement
Since n+ - p junctions are an integral part of n-channel MOSFET
devices, junction leakage current becomes one of the most important
parameters related to the operation of MOSFET devices as a chopper in
conjunction with infrared detectors. Such leakage current at room
temperature is too high for successful application.
However, at the temperature the leakage current undergoes a
dramatic reduction such that an indirect method of measurement must be
used to determine the relative leakage current change.
The circuit used for the leakage current measurement is similar
to that of Fig. 5.1, and is shown in Fig. 5.5. The capacitor C has a
value of 560 pF, and the input signal to the gate of the JFET integrator
has the value of 200 mV dc. After the relay is open, the output differ
ential signal decays to its initial level (zero level) within 200 ms at
room temperature. Neglecting the JFET gate capacitance (SJ10 pF), the
leakage current is given approximately by
+3v
Relay
in
Oscilloscope
1 Mfi
-3v
Fig. 5.5 Circuit Schematic for p-n Junction Leakage Current Measurement at 300 K and 77 K
o ""-4
108
AQ 112 x 10"12 . „ ,„-10 . 1 = T~ = = 5.6 x 10 A At 200 x 10-3
For the LN measurement the capacitor was removed, and the same
experiment was repeated. It was found that the differential signal
changed by 6 mV in 100 sec. Assuming a 10 pF gate capacitance, the
manufacturer specification, the leakage current is given approximately
by
= M = C » AV AL At
-11 -3 = 10 1 • 6 x 10 J
100
= 6 x 10"16 A
The reduction in leakage current for this device is almost six
orders of magnitude in going from room temperature to 77 K. Although
this change is not comparable to the theoretical prediction of approxi
mately 30 orders of magnitude decrease, it is large enough for the
M0SFET switch to be useful.
The huge difference between experimental and theoretical results
is mainly a result of junction curvature, local defects, and other
effects.
CHAPTER 6
CONCLUSIONS
6.1 Summary
This work has demonstrated the qualitative and quantitative
agreement between the first order theoretical simulations developed in
Chapters 2 and 3, and the experimental results presented in Chapter 5.
The strong deviation of the experimental results, namely, V , and Ve£f»
from the theoretical values at the LHe temperature is attributed to
other effects that are not included in the first order model, these
effects include the Si-SiO. interface charge, Q , an increase in 2 ss
trapping effect, and a decrease in inversion layer mobility as a result
of impurity scattering.
The use of a polysilicon gate process resulted in a factor of
two decrease in the magnitude of the variation of the threshold voltage
with temperature in the neighborhood of 300 K reported in the literature
for a metal gate process. This result was in agreement with the theoret
ical analysis presented earlier. We also demonstrated that the critical
doping concentration, N , for degeneracy is in good quantitative agree
ment with experimental results, and a higher surface concentration than
N, is needed to eliminate non-ohmic contact behavior of the source and dc
drain contact regions.
Improvements in MOSFET device characteristics at the cryogenic
temperature were attainable. Relative to room temperature and at liquid
nitrogen temperature, desirable improvements in device performance
109
110
includes higher transconductance and much lower junction leakage
current in addition to other improvements such as higher threshold
voltage, steeper device turn-on, and lower aluminum line resistance.
A computer simulation program LTMOSFET was developed to model
the dc behavior of MOSFET device characteristics which include thresh
old voltage variation, and temperatures in the range of 300 K - 4.2 K.
The program assumes uniform impurity distributions in both the sub
strate and the source and drain regions, and neglects short channel
effects, substrate sensitivity, subthreshold conduction, and voltage
breakdown. Apart from the discrepancy between calculated and measured
values of at 77 K, the experimental results were within 10% of
the values generated by the LTMOSFET simulation program. Better agree
ment would be achieved by using the values of an inversion layer
mobility measured at each temperature of interest.
6.2 Recommendations for Future Work
When future work in this area is done, the following sugges
tions might be of great interest:
1. Increase of the source and drain implant dose to reach a
20 -3 surface concentration of about 10 cm ; for example, a dose
16 2 of approximately 10 cm . Also a junction depth of about 1 um
is preferable. To avoid a spiking effect, a metal other than
aluminum could be used.
2. Characterization of the channel mobility for the process used
as a function of temperature. The experimental values of
can be used in the simulation program.
Ill
3. Characterization of the Si-SiC interface charge density.
4. The simulation program can be improved to include the follow
ing second order effects:
a) Finite output impedance for short channel or low tempera
ture effect;
b) Non-uniformity of the implanted dose in the channel; and
c) Threshold voltage variation in the temperature range
300 K - 4.2 K.
APPENDIX A
LTMOSFET PROGRAM LISTING
112
113
PAEE 1 LIST VER 081282 4 10/ 7/84 12:18:44 SVS:0010..LTHOSFET.SA
C
C
C t THIS IS THE MAIN PROBRAM. IT CALLS SUBROUTINES •
C * TO CALCULATE AND PLOT THE FERHI-POTENTIAL,THE <
C » TIE THRESHOLD VOLTABE AND THE THRESHOLD VOLTAGE «
C > . ' _ . .. NITH TEMPERATURE AS A FUNCTION OF TEM-«
C < PERATURE. IT ALSO COMPUTES AND PLOTS THE SBUARE «
C » ROOT OF THE DRAIN CURRENT IN SATURATION AS A t
C • FUNCTION OF THE GATE VOLTABE AT 300K.77JC AND «
C < 4.2K. FINALLY, IT COMPUTES AND PLOT THE I-V »
C » CHARACTERISTICS,NITH V6 AS A PARAMETER AT 300K, •
C i 77K AND 4.2K.TAKIN6 INTO ACCOUNT THE SCHOTTKY- •
C i EFFECT *
C ti< DEFINE ARRAYS AND SET COMMON BLOCKS.
DIMENSION TEMPI3),XID(4,51),SRID(51,3),ASIF<2,31I,AVTH(2,31I
DIMENSION ASSIDI3,! . ,311
CMH0N/SETI/T,0SS,(1INP
COMMON/SET2/CO!,VTH,VFt,Slf,INA
C0W10N/SET3/H,IL,UEFF t VB,VDSAT
C0MMM/SET4/I1DS,VD
COMMON/SETS/DVTH
C •« I WITT DATA DIRECTLY TO TERMINAL.
NRlTE(f,9M)
900 FORMAT!' ENTER NA IN CM««-3'I
READ(9,90ll INA
901 FORMAT(EB.I)
NRITE(9,902)
902 FORHATC ENTER TOI IN CH'I
READ 19,901) TOI
NR1TE(9,903)
903 FORHATC ENTER OSS.... IN CHH-2')
REA0(9,901) BSS
NRITE(9,904I
904 FORMAT(' ENTER OIHP... IN CHH-2 ! B1HP>0 FOR B'l
REftD (9,901) OIHP
HRITE(9,90S)
905 FORHAT(' ENTER M NO UNITS'!
READ/9,909)N
909 FORHAT(F5.I)
KfiITE(9.90oI
906 FORHAT 1' ENTER L NO UNITS')
READ(9,909)XL
HRITE (9,930)
930 FORHAT<' ENTER UO CHM2/V.S')
READ(9,909)U0
NRITE(9,931)
931 FORHAT(' ENTER ALPHA....NO UNITS <•* IF ALPHA'O.O'/
•51,'SCHOTTKV BARRIER EFFECT IS NOT SIHULATED «M'I
AEAQ <9,932 > ALPHA
932 FORHAT(F7.41
NRITE(9,935)
935 FOMMT (' ENTER PARAHETER • F5.1...' I
REM(f,93i)IH
115
PA6E 2 LIST VER 081202 4 10/ 7/84 12:18:44 SYS:0010..LTH05FET.SA
934 FORMAT(F5.1)
C MITE NOSFET DEVICE PARAItETERS.
HRITE(&>9O7)XNA,T0X,aSS,eilfP,H>IL,U0tALPHA,Ilt
907 FORHATMH1 /////20t,'SIIHJLATION OF M-CHANNEL ENHANCEMENT NODE
• HOSFET DEVICE AT CRV06ENIC TENPEftflTURES.'/20*,'
• '//25I,'DEVICE PARAMETERS:'/25t,'
+'/2SX,'BULK CONCENTRATION NA »',E11.2/25«,'6AT
•E 01 IDE THICKNESS TOI >',E11.2
•/25I,'SURFACE CHARGES CSS -',E11.2
+/251,'THRESHOLD ADJUST IMPLANT BINP =',Ell.2/251,
•'CHANNEL MIOTH N »',FB. 1/251,'CHANNEL LEN
•6TH L »',FB.t
•/251,'R.T. ELECTRON INV. LAV. NOB. UO =',F8.1/
•251,'PARAMETER ALPHA »',F7.4
+/25I,'PARAMETER
•/20I,'
t 'i
C <t< CALCULATE 01IDE CAPACITANCE/UNIT AREA
C0t-(3.9«e.8SE-14)/TOX
C HI PRINT INI. AND DEP. VARIABLES FOR TABLE 1
NR1TEI6.2)
2 F0RMAT(1H1,///10I,'TABLE 1.'
+/10I,'
•7101,'I TEHPERATUREIKI I FERHI-POT.(V) I THR.VOLT.(V) 1
• dVTH/dT(iV/K) 1'/
+101,'———————I—————J
• •)
c
c
c
DO 1000 1=1,31
11=1
T=310.-10.«*I
IFIT-O.OIlOOl,1001,1002
1001 TM.2
1002 CALL THRVOL
ASIF(1,I)*SIF
ASIF(2,11=SIF
AVTHI1,I)»VTH
AVTHIZ,II-WTH
ADVTH(1,1I«DVTH
A0VTH(2,I)»DVTH
1000 NRITE(6,3)T,SIF,VTH,IIVTH
3 FOfilWT(10I,'I',6I,F5.1,6I,'I',3I,F7.4,5I,*I',4I,F6.3,'
• !',4I,Fi.2,' l'l
«mi6,920l
920 FOMMTI101,'
«• CALL SUB. THRVOL TO CALCULATE FERHI-POT,THR. VOL.
•h AND dVTH/dT AS A FUNCTION OF TEMP.THESE VALUES ARE
<M THEN STORED IN ARRAY FORM.
PABE 3 LIST VER 061282 4 10/ 7/84 12:18:44 SVS:0010..LTHOSFET.SA
C CALL SUBROUTINE HULPLT TD PLOT FERNI-POTEIITIM. VS. T.
NRITEU,921)
921 F0RHAT(IHI//40«,'PL0T OF THE PERM-POTENTIAL AS A FUNCTION
• OF TEMPERATURE.'//70I,'FERNI-POTENTIAL (V)')
CALL HULPLT(ASIF,2,31,1,2,10,10.0)
C •«« CALL SUBROUTINE HULPLT TO PLOT THE THRESHOLD VS. T.
NR1TE<6,922)
922 FORHAT(1H1//40I,'PLOT OF THE THRESHOLD VOLTAGE AS A FUNCTION
• OF TEMPERATURE'//80J,'VTH IV)')
CALL HULPLTIAVTH,2,31,1,2,10,10.0)
C CALL SUBROUTINE HULPLT TO PLOT THE VARIATION OF THE
C Mt THRESHOLD V0LTA6E AS A FUNCTION OF TEMPERATURE
NRITE(6,923)
923 F0RHAT(IH1//20I,'PL0T OF THE VARIATION OF THE THRESHOLD
• VOLTAGE KITH TEMPERATURE VERSUS TEHP.'//75I,'dVTH/dT
• LIVIM
CALL HULPLT(ADVTH,2,31,1,2,10,10.0)
C ««• ASSI6N VALUES TO THE ARRAY TEMP.
DATA (TEMP(I),I>1,31/300.0,77.0,4.2/
C «»• START A LOOP TO CALCULATE THE SORT OF THE HOSFET DEVICE
C IM SATURATED CURRENT ItSAT AT THREE DIFF. TEMPERATURES.
DO 2040 1*1,3
T«TEI*>(II
CALL THRVOL
UEFF*U0«(3M./T)ti0.3>
II«I*l
MITE <4,4)11,T
4 ~ , isle ',12,/
•18K,'i •
+'/18X,'« TEHPERATURE='F5.I,'K •'/
•*/18*,*«' ,81,
«'t/6<»l',7l,'l',2l,'SKT. IB(A«I/2I «'/lfil,'f
• 1 .-)
DO 3000 N«1,S1
AN-N-1.0
V6»0.1<AN
IF (V6-VTH) 10,10,11
11 CALL SC
VD'VDSAT
CALL TC
SRID<N, I)'SORT(IIDS)
60 TO 3040
10 SRI0(N,I>«0.0
3000 MITE(i,S)V6,SRID(N,I)
3 F0RHAT(t8Il'i'|il|FS.2,9I,'I',4I,E10.3liI,'t')
- 119
PAGE 4 LIST VER 081282 4 10/ 7/84 12:18:44 5VS:0010..LTHOSFET.SA
NRITE(i,19f)
19? F«MTna*,'« «'l
2000 CONTINUE
DO 2001 1*1,3
DO 2002 JM,5l
ASRID(I,J)-SRID(J,1)
2001 CONTINUE
200? CONTINUE
C «#« CALL SOB. NULPLT TO PLOT THE SORT OF HOSFET DEVICE
C Hi SATURATION CURRENT AS A FUNCTION OF SATE VOLTAGE.
M)ITE(6,200)
200 F0RHATI1H1,301,'PLOT OF SORT. IDSAT VS. VGS AT 300K
+,77K AND 10K'//A0I,'IDt<l/2 (I 2.0E-4 A«l/2)'l
CALL NULPLT(ASRID,3,51,2,1,5000.0,0.1)
C "» HOSFET DRAIN CURRENT IS CALCULATED AT 50 VALUES OF
C H< THE DRAIN VOLTAGE.
DO 4000 1*1,3
T'TEVIII
IIIMM
UEFF*1775-(4.25#T)
CALL THRVOL
KRITEI6,6)111, T
6 FOfihAT(1H1,BI,'TABLE ',12,/
• TEflP. •
•',F5.1,'K 1 DRAIN CURRENT NITH V65 AS A PARAHETER
• I>/8I,'l VDS(V)',BI
<>[ V6S«2V I VBS'4V 1 V6S«4V I V6S'8U
• I'l
N 5440 J-1,51
AJ*J-1.0
VD«0.20*flJ
>0 6000 K-1,4
AK«FLOATIK)
V6«2.0«AK
CALL SC
IF(VD-VDSAT)20,21,21
20 CALL TC
IID(K,J)<IIDS
BD TO 6000
21 VD'VOSAT
CALL TC
I1D(K,J)'IIDS
V>0.20«AJ
6000 CONTINUE
5000 CONTINUE
10 7000 L-1,51
AL«L-1.0
PA6E S LIST VER 081282 4 10/ 7/84 12:18:44 S¥S:0010..LTMSFET.SA
VD-0.2<AL
WITE(i,7)VD,<HD(K,L),K'l,4)
7 FORMAT(8K,'I ',F5.2t9I,* I'14(2*,E10.3,2I1'I*H
7000 CONTINUE
MITE(i,22)
22 FORMAT(81,'
• >1
NRITE<&,8)T
8 FORHAT(iHl,J5I,'PLOT OF IOS VERSUS VDS AT T>',
•F5.1,' K'///80I,'IDS (I 2.E-2 •AH
CALL IHJLPLT<XID,4,Slf2,1,S.0E4,0.2)
4000 CONTINUE
C t«t PLOT OF THE HOSFET I-V CHARACTERISTIC INCLUDIN6
C «»» THE SCHOTTKV BARRIER EFFECT.
C ttt CHECK TO SEE IF ALPHA'O.O. IF SO THIS PART OF THE
C fM PR06RAH NILL NOT BE EIECUTED
IFIAIPHA-0.0I9998, 9998,9999
9999 H 1100 1-2,3
T-TEHP(I)
UEFF«1775-(4.25«TI
CALL THRVOL
DO 8200 >1,51
AJ'M.O
VDS»0.2«AJ
DO 8300 K«I,4
AK*FL0AT(K)
V6»2.0«AK
AF'V6«*IH
IF(1-2)8350,8350,83&0
8350 VDTH*1.2-(0.12iU6)
SO TO 8400
8360 VDTH»2.25-(0.147tV6)
8400 HV0*VDTH-VD5
TEFF=iT/300)«0.75
ARB«ALPHA«DVD»AF/TEFF
IFIDVD-0.018420,8410,8410
8410 IIDIK.JI'O.O
EO TO 8300
8420 AR2«4.0
1FIAR6+AR218700,8700,8800
8700 VDEFF*VD5-V0TH
VD=VKFF
EO TO 8990
8800 VDEFF-(VDS-WDTH)«11.0-EIP (AM) I
VD-VDEFF
8990 CALL SC
IF(VO-VDSAT)8330,8440,8440
8330 CALL TC
IIIIK.JI'IIDS
PA6E b LIST VER 081282 4 10/ 7/84 12:18:44 S*S:0010..LTN05FET.SA
BO TO 8300
8440 VD>VBSAT
CAU. TC
I1D(K,J)*IIDS
VD»VD£FF
8300 CONTINUE
8204 CONTINUE
HRITE <6,0500)T
8500 F0RHAT(1H1,20I,'« PLOT OF IDS VS. VDS INCLUDINfi THE
• SHOTTKV BARRIER EFFECT AT T»',F5.1,*K «#'//
•80*,'IDS (I 2.E-2 iA)'l
CALL HULPLT(«IO,4,51,2,1,5.0E4,0.2I
8100 CONTINUE
9998 STOP
END
124
PAGE 1 LIST VER 081282 4 10/ 7/84 12:25:24 SVS.-0010..THRVOL.SA
C t THIS SUBROUTINE HILL CALCULATE THE THRSHOLD VOLTAGE, <
C > THE FERHI-POTENTIAL AND THE VARIATION OF THE THRESHOLD •
C • VOLTAGE NITH TEMPERATURE •
SUBROUTINE THRVOL
DOUBLE PRECISION A22,SR,DS
C0fflt0N/SEU/T,0SS,01HP
C0WI0N/SET2/C0J,VTH,VFB, SIF,INA
C0HH0N/5ETS/DVTH
C •» CALCULATE THE BAND GAP ENERGY EG AS A FUNCTION OF TEHP.
E6«1.14-II7.02E-4«T»TI/(1108.0»T))
C »»» NORIMLIZE INA
13*INA/1.0E10
C <M CALCULATE THE THRESHOLD VOLTAGE
lNV>1.02Elf<((T/300.0lM|.S)
AllaINA/INV
A22-DEXP((0.045*300.0)/(TtO.02581)
SR»0.25«IDS#RTII.O»(8.0«A1HA22))-1.0I
DS'DLOGISRI
EF=0.045-(0.0256«T/300.0I*SS
SlF«(ES/2.0)-EF
BS»fBS5«t .6E-19) /COX
8I»(flIKPil.i£-l9l/C0l
VIH»(-EG/2.4)•SIF-flS-tl
• «(SMT(4.<11.7<e.8SE-14«l.iE-9i!3<5IF))/C0l
VFB*(-E6/2.0)-SIF-flS-0I
C «» CALCULATE THE VARIATION OF VTH KITH RESPECT TO TEHP.
51-SBRT ((1.4E-9»I3M1.7»6.854E-14)/SIF)
52-1.0+(1.0/C0X>«S1
C <« SLAD IS USEO TO 6IVE C0NTIU1TY OF THE SLOPE
SLAD»0.0225«I300.0-TI/300.0
S3«S1F-0.5B»SLAD
C DVTH IS MULTIPLIED BY 1000 TO 6ET THE RESULT IN IV.
DVTH*(1,0/T)<S3iS2<1040.0
RETURN
END
"" — 126
PAGE I LIST VER 081282 4 10/ 7/84 l2:2i:SS SVS:0010..SC.SA
c , 1
C < THIS SUBROUTINE HILL CALCULATE THE SATURATION t
C * VOLTAGE VDSAT «
SUBROUTINE SC
C Hi SET COIWION BLOCKS
CIMHDN/SETl/T,BSS,giNP
CMU1ON/SET2/C0I,VTH,VF8,S1F,ENA
COHHON/SET3/HtIL,UEFFtV6(VDSAT
C <*t NORHALIZE COX
COil'COI/I.OE-5
C NORMAL]?E INA
Vl'INA/l.OElO
C «H CALCULATE VDSAT
A*(11.7«1.4E-9»YH6.B5E-04W(COIHCOI1I
V2«1*I2.0»(IVS-VFB)/A))
VDSAT*V6-VFB-(2.0tSIF)+A-(Af(SDRT(V2)ll
RETURN
END
PAGE 1 LIST VER 081202 4 10/ 7/84 12:28:06 SYS:0010..TC.SA
c
C < THIS SUIROliTINE HILL CALCULATE THE HOSFET DEVICE •
C < MUIN CURRENT •
SUBROUTINE TC
c <•< SET COMON BLOCKS
C0KMN/SET2/C0I, VTH,VFB,SIF,INA
C0HH0N/SET3/N,IL,UEFF,V6,V0SAT
CEMD0N/SET4/IIDS,VD
C NORMALIZE INA AND COI
Z1«INA/1.0E10
C0l2«COI/1.0E-5
C ««» CALCULATE THE DRAIH CURRENT XIDS
CHN/ILUUEFFiCOI
C2-V6-VFB-(2.0«SIF)-(O.S«VD)
C3»(2.0«11.7«0.85E-4«1.4E-9»Z11/(COI2»COI21
C4»(V#+(2.(HSIF))«»!.5
C5*(SIF«2.0)«»1.5
IIDS'CKI (C2<VD) -((2.0/3.4) *SBRT (C3) < (C4-CS)))
RETURN
END
128
PAGE 1 LIST V£R 08I2S2 4 10/ 7/84 12:29:17 SYS:0010..KULPIT.SA
< THIS IS A GENERAL USER SUBROUTINE FOR PLOTING FUNCTIONS «
< KITH OR HITHOUT A PARAMETER DEPENDENCY. TWO OPTIONS ARE •
» AVAILABLE. IF I0PT1«1,THE PROGRAM TAKES THE Y-AIIS AS THE #
» RANGE OF THE FUNCTION. THIS IS A 6ENERAL NAV FOR PLOTTING <
« FUNCTIONS. IF 10PTI IS DIFFERENT THAN 1,THE Y-AIIS IS •
t SCALED FROH 0 TO 10,AND THE FUNCTION IS NORMALIZED TO •
i FIT THAT RANGE. IF I0PT2«1,EACH CURVE,UP TO 5,IS PLOTTED •
« NITH DIFFERENT CHARACTERS. OTHERNISE.THE SANE CHARACTER <
< IS USED «
C tH DEFINE SUBROUTINE NAME AND ARGUMENTS.
SUBROUTINE NtlLPLT(Y,NI,N2,10PT1,I0PT2,FACT,UNCI
DIMENSION YAUS(4) 16RAPH(107),Y<N1 ,N2),SYHB(S)
DATA SPACE,POINT,PLUS,AST,NUMB,DOLLAR/IK ,lH.,lH*,lHi,IHt,lH«/
DATA SYHB11),SYHB(2),SYHB13),SYNBI4), _
+,1H«/
DATA XAXIS,IHARK.E1/1HI,1H-,IK!/
IFII0PTI-II45O,100,450
100 VMIHI.lEft
YMIHUE3S
DO 210 I'1,N2
DO 204 J*I,N1
YNEN>Y(J,I)
IF imi-mmto, no, 120
110 YMI'YNEN
120 IF(VNEH-VRIH)ISO,130,200
130 VHIWNEN
200 CONTINUE
210 CONTINUE
YINT'YNAI-YNIN
DY«YINT/10.0
00 220 1-1,5
I1»I-1
miS(I)*VHIN«(II<DY<2.0)
220 CONTINUE
¥AXISt6>»¥HflX
NRITE(i,230) (MMISU),!*!,!)
230 FORHAT(BI,i(Ell.4,911/101
•'I—I «—I « 1 « 1 • 1 «—
•—, 1 , 1 < 1 1 1 1 1—i'
00 370 I«l,N2
00 241 N»2,106
6R#PH(N)«SPACE
241 CONTINUE
6RM>H(1I'I«IIS
(MPH(107)*IAIIS
IN1'I-1
II-1H1/5
PAGE 2 LIST VER 081282 4 10/ 7/84 12:29:17 SVS:0010..HULPLT.SA
12-11*5
IF(I2-1H1)2S1,250,251
250 6RAPH(1I*1HARK
6RAPH(107)»MARK
251 BO 340 J'l.Nl
ll'Y(J,ll-VNIN
12'U/VINT
I3*I2»100.
K«4.»I3
6RAPH<KI*P0INT
IF(IQPT2-1)340,341,340
341 IF(J-i)342,340,340
342 8RAPH<KI»SVHB(J)
340 CONTINUE
NR1TE<4,340M6RAPH<III,I<»1,I07>
340 FORMAT(101,107A11
370- CONTINUE
NRlTE(4,3il)IlNC,DV
361 FORMAT (101)' I—I « 1 • 1 « 1 « 1 •
• 1 « J , 1 ( 1 1 J 1 1 — I ' / /
+101,'I-AXIS SCALE :',FA.2,'K/OIV.'/10X,'V-AXIS SCALE :',E11.4
V/liv.'i
to TO 550
450 MlTE(i,400)
400 FORMAT(101,'0.',71,'10.',71,'20.',
•71, *30.' ,71, *40. * ,711, *50.' ,71, 'AO. * ,71, *70. * ,71, '80. * ,71, '90.'
•,6«,' 100.'/10I,' I • 1 1 1 1 1 « 1
DO 530 I-1.N2
1FII-II530,530)501
501 00 502 11*1,107
HWH(N)«SPACE
502 CONTINUE
HMPHUOII'IAIIS
11*1-1
12=11/5
13=12*5
IF(13-11)503,504,503
504 WFLPHU)=I(MFLK
6f;WH(10l)=l)WRK
60 TO 505
503 GRAPH! URIAHS
505 00 520 J>1,N1
YP»*(J,IHFACT
K«1.+VP
6RAPH(K)«P0INT
IF(10PT2-1)525,506,525
504 IF(J-4)521,525,525
521 6RAPH(K)'SVHt(J)
525 IF <K-1)540,540,520
540 1F<I3-11> 520,542,520
542 GOAPHIKI'SMftK
520 CONTINUE
PAGE 3 LIST VER 081282 4 10/ 7/84 12:29:17 SYS:0010..KIIPLT.SA 132
IR1TE(&|5I8)(GRAPH(N>,H*1,101)
SIB FORIMTdOI, 101A1I
S30 CONTINUE
WITE(T,S19)IINC
519 FOffllATUOI.lOI'I » M.'IV/IOI.'I-AIIS SCALE:',F5.1,
•'V/DIV.')
550 RETURN
END
APPENDIX B
STANDARD WAFER CLEANING PROCEDURE
Prior to each high temperature processing step the wafers
are given a standard cleaning procedure in order to minimize wafer
contamination which is harmful to the device performance. The wafer
cleaning steps are listed below.
1. Load wafers into teflon carrier.
2. Immerse carrier into 3:1 I SO rl C (the hydrogen peroxide is
30%).
Temperature: 100°C
Time: 6 minutes
3. Rinse wafers in deionized (DI) water.
Time: 5 minutes
4. Immerse carrier into 10:1 1 0 :HF.
Time: 20 seconds
5. Repeat Step it3.
6. Immerse carrier into concentrated HNO .
Temperature: 90°C
Time: 6 minutes
7. Repeat Step #3.
8. Immerse carrier in 20:1 1 0:HF.
Time: 10 seconds
133
134
9. Repeat Step #3.
10. Spin dry.
The first cleaning procedure follows a five minute ultrasonic
cleaning in acetone. Following the spin dry cycle, the wafers are
loaded directly into the furnace to avoid contamination from airborne
particles.
APPENDIX C
FABRICATION PROCEDURE
The polysilicon gate process used in the fabrication of
n-channel enhancement mode MOS field effect transistors is as follows.
Initial Oxidation:
Furnace: Field Oxide
Temperature: 1150°C
1. Purge furnace with O for 15 minutes.
2. Steam oxidation: 18 minutes.
0 bypass at 50 ss (ss - stainless steel float)
0 bubbler at 30 ss
3. Dry oxidation: 10 minutes
0 bypass at 50 ss
Oxide thickness is about 2800X
Field and Threshold Implant:
Species: boron
11 -2 Implant dose: 7.5 x 10 cm
Energy: 90 keV
Device Area Delineation:
Photolithography procedure with Kodak Type 747
Microresist (negative)
1. Wafer dehydration for 20 minutes at 130°C.
2. Spin on HMDS at 4000 rpm for 20 seconds.
135
136
3. Spin on photoresist at 400 rpm for 20 seconds.
4. Prebake at 85°C for 15 minutes.
5. Exposure for 6 seconds.
6. Develop in xylene with the following procedure:
Xylene bath it 1: 20 seconds
Spray with xylene: 10 seconds
Xylene bath #2: 20 seconds
Spray with xylene: 10 seconds
Spray with n-butylacetate: 10 seconds
Blow dry.
7. Post bake at 135°C for 20 minutes.
8. Etch oxide in buffered HF (etch rate is about 650 A/min)
9. Remove photoresist in 10:1 H2S0 :H202
Temperature: 100°C
Time: 10 - 15 minutes
Gate Oxide:
Furnace: Gate Oxide
Temperature: 1000 ° C
1. Purge tube with 3% HC1 for at least 1 hour.
at 85 ss
HC1 at 35 ss
2. Purge tube with nitrogen for 1 hour.
at 85 ss
3. Load wafers.
N£ at 105 ss
C>2 at 20 ss
Time: 2 minutes
4. HC1 dry oxidation for 75 minutes.
0 at 93 ss
HC1 at 34 ss
5. Dry oxidation for 3 minutes.
O2 at 20 ss
at 105 ss
Oxide thickness is about 1100&.
Polysilicon Deposition:
Furnace temperature: 650°C
Time: 45 minutes
Foreline presssure: 400 mTorr
Chamber pressure: 200 mTorr
SiH. at 60 ss 4
as a carrier (Adjust the flow rate to get 400 mTorr
pressure in the chamber.)
Polysilicon Delineation:
1. The photoresist procedure is repeated here, using Mask #2.
2. Plasma etch for 15-18 minutes.
Gas: CF. 4
_2 Pressure: 1.5 x 10 Torr
Source and Drain Implant:
Species: Phosphorus
15 -2 Dose: 10 cm
Energy: 80 keV
Source and Drain Drive-in:
Furnace: Field Oxide
Temperature: 1050°C
Time: 140 minutes
Ambient: nitrogen
Field Oxide Deposition (CVD):
Equipment: Rotox 60
Temperature: 420 ° C
Time: 8 minutes
at 70 ss
SiH. at 40 ss 4
PH at 1.3 ss
O2 at 90 ss
Contact Windows Opening:
1. The photolithography procedure is repeated using the third
mask with the only exception that the exposure time is
reduced to 2 seconds because of an under-exposure problem.
2. Etch oxide in buffered HF (etch rate is about A/sec.)
3. Strip photoresist in 3:1 H2S0 :H202 for 10-15 minutes.
Metallization:
1. Standard cleaning procedure except the last HF dip is done
for 20 seconds.
139
2. Aluminum deposition using the e-beam deposition method.
Thickness: 70001
Metal Delineation:
1. The photolithography procedure is repeated using Mask #4.
2. Aluminum Etch.
Etchant: 80 ml H_P0. 3 4
18 ml H20
4 ml HN03
Temperature: 50 °C
3. Strip photoresist using J-100 Microstrip at 90°C for 10-15
minutes.
4. Alunimum sinter using a strip heater at 450°C for 3 minutes
in a Forming gas ambient (90% N , 10% I ).
APPENDIX D
LIST OF SYMBOLS
Cqx Oxide capacitance per unit area
E Electric field
E . Acceptor (donor) impurity energy level in silicon
E Conduction band edge energy level c
E Bulk Fermi energy level
E Band gap energy 8
Ego Band gap energy at 0 K
E Intrinsic Fermi energy level
E Valence band edge energy level
g MOSFET device transconductance m
h Plank's constant
I MOSFET drain current Do
•SsAT MOSFET drain saturation current
J p-n junction generation leakage current density 8
k Boltzmann's constant
kg Relative permittivity of silicon
L Channel length
<f( m Electron effective mass e
m* Hole effective mass P
n Electron concentration
N Impurity concentration
140
141
N,+ Ionized impurity donor concentration d
N , Acceptor (donor) impurity concentration a,d
N Effective density of states in the conduction (valence) band c,v
n Intrinsic carrier concentration
p Hole concentration
q Magnitude of electron charge
Lumped equivalent of the distributed ionic charges in the
silicon dioxide
Q Interface charge density ss
T Temperature
V Voltage
Vp Drain to source voltage
tvcat Drain saturation voltage UUAL
Vpsi Drain source threshold voltage when the gate does not over
lap the source and drain region
V-.-,, Drain source threshold voltage in the case of a Schottky DTrl
barrier
V__ Flatband voltage FB
V„ Gate to source voltage G
VT MOSFET device threshold voltage
VT Threshold voltage required for strong inversion
V Reverse bias voltage R
eQ Permittivity of free space
e. Relative dynamic (high frequency) dielectric constant of d
silicon
142
e Permittivity of silicon dioxide ox
eg Permittivity of silicon
t Effective minority lifetime in the depletion region o
y Electron inversion layer mobility err
d>, Barrier height D
m
'ms
Metal work function
Metal semiconductor work function difference
d> Semiconductor work function Ts
Xg Semiconductor electron affinity
iBuilt-in potential
i() Bulk Fermi potential
SELECTED BIBLIOGRAPHY
Fistul, V. I. Heavily Doped Semiconductors, Plenum Press, New York, 1969.
Gaensslen, F. H., V. L. Rideout, E. J. Walker, and J. J. Walker. "Very Small MOSFET's for Low-Temperature Operation," IEEE Transaction on Electron Devices, Vol. ED-24, No. 3, 1977.
Kireev, P. S. Semiconductor Physics, Mir Publishers, Moscow, 1978.
Leistiko, 0., A. S. Grove, and C. T. Sah. "Electron and Hole Mobilities in Inversion Layers on Thermally Oxidized Silicon Surfaces," IEEE Transactions on Electron Devices, Vol. ED-12, No. 5, May 1965.
Low, F. J. "Integrating Amplifiers Using Cooled JFETs," Applied Optics, Vol. 23, No. 9, May 1984.
Maddox, R. L. "p-MOSFET Parameters at Cryogenic Temperatures," IEEE Transaction on Electron Devices, Vol. ED-23, Jan. 1976.
Morin, F. J., and J. P. Maita. "Electrical Properties of Silicon Containing Arsenic and Boron," Phys. Rev., Vo. 96, No. 1, 1954.
Nathanson, H. C., C. Jund, and J. Grosvalet. "Temperature Dependence of Apparent Threshold Voltage of Silicon MOS Transistors at Cryogenic Temperatures," IEEE Transaction on Electron Devices, Vol. ED-15, No. 6, June 1986.
Ongj, D. G. Modern MOS Technology, McGraw-Hill, Inc., New York, 1984.
Richman, P. MOS Field-Effect Transistors and Integrated Circuits, A Wiley-Interscience Publication, John Wiley and Sons, Inc., New York, 1973.
Rideout, V. L. "A Review of the Theory and Technology for Ohmic Contacts to Group III-V Compound Semiconductors," Solid State Electronics, Vol. 18, pp. 541-550, 1975.
Rogers, C. G. "MOST's at Cryogenic Temperatures," Solid State Electronics, Vol. 11, p. 1079, 1968.
143
144
Sze, S. M. Physics of Semiconductor Devices, John Wiley and Sons, Inc., New York, 1969.
Vadasz, L., and A. S. Grove. "Temperature Dependence of MOS Transistor Characteristics Below Saturation," IEEE Trans. Electron Devices, Vol. ED-13, No. 12, December 1966.
Wu, S. H., and R. L. Anderson. "MOSFET's in the 0 K Approximation," Solid State Electronics, Vol. 17, pp. 1125-1137, 1974.
