Analysis and Design of a single stage parallel AC to DC Converter

8/13/2019 Analysis and Design of a single stage parallel AC to DC Converter

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 12, DECEMBER 2009 2989

Analysis and Design of a Single-Stage ParallelAC-to-DC Converter

Heng-Yi Li, Hung-Chi Chen , Member, IEEE , and Lon-Kou Chang , Member, IEEE

Abstract In this paper, a single-stage ( S 2 ) parallel ac-to-dc con-verter based on single-switchtwo-output boostyback converter ispresented. Theconverter contains twosemistages. Oneis theboostyback semistage, which transfers partial input power transferredto load directly through one power ow path and has excellentself-power factor correction property when operating in discontin-uous conduction mode even though the boost output is close to thepeak value of the line voltage. The other one is the yback dc-to-dc(dc/dc) semistage that provides the output regulation on anotherparallel power ow path. With this design, the power conversionefciency is improved and the current stress of control switch is re-duced. Furthermore, the calculation process of power distributionand bulkcapacitor voltage, design equations,and design procedurefor key parameters are also presented. By following the procedure,an 80 W prototype converter has been built and tested. The exper-imental results show that the measured line harmonic current atthe worst condition complies with the IEC61000-3-2 class D limits,the maximum bulk capacitor voltage is about 415.4 V, and themax-imum efciency is about 85.8%. Hence, the proposed S 2 converteris suitable for universal input usage.

Index Terms AC/DC power conversion, y back converter,power factor correction, single-stage, single-switch.

I. INTRODUCTION

THE POWER factor correction (PFC) has been widely em-ployed for improving the power quality of the power con-

verters. In conventional converters design, a two-stage structurewas usually employed for performing PFC and output regu-lation simultaneously, where the bulk capacitor C B is in thepower transfer path between the PFC stage and dc-to-dc (dc/dc)stage. This structure can give high power factor and high regu-lation simultaneously by using two independent controllers andpower stages, but the cost of switching devices and the controlcircuitry is not easy to cut down especially in low-power appli-cation. Although unity power factor is the ideal objective, it isno longer an essential requirement. According to the regulationIEC61000-3-2 [1], the power supplies of low-power products

Manuscript received October 27, 2008; revised March 20, 2009. Current ver-sion published December 28,2009. This paper waspresented in part at theIEEEPower Electronics Specialists Conference (PESC), Jeju,Korea, June18th22nd,2006. Recommended for publication by Associate Editor P.-T. Cheng.

H.-Y. Li is with the Department of Electrical and Control Engineering (ECE),National Chiao Tung University (NCTU), Hsinchu 300, Taiwan. He is alsowith the Institute of Nuclear Energy Research, Taoyuan 325, Taiwan (e-mail:[email protected]).

H.-C. Chen is with the Department of Electrical and Control Engineering(ECE), National Chiao Tung University (NCTU), Hsinchu 300, Taiwan (e-mail:[email protected]).

L.-K. Chang is with Macroblock, Inc., Hsinchu 300, Taiwan (e-mail:[email protected]).

Color versions of one or more of the gures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identier 10.1109/TPEL.2009.2023550

such as computers, PC monitors, and television sets have tocomply with class D limits. This fact promotes the developmentof the S2 ac-to-dc converter, such as boost integrated/yback rectier/energy storage/dc-to-dc converter (BIFRED) [2] andboost input current shaper (ICS) [3][8], which comply withthe regulations without achieving unity power factor. In thosedesigns, two power stages were integrated into one stage byusing only one controller and sharing the control switch so thatthe component count and cost could be reduced. However, theseconverters have the problems of high bulk capacitor voltage athigh line and light load when PFC semistage is operated indiscontinuous conduction mode (DCM) and dc/dc semistagein continuous conduction mode (CCM). Some alternative de-signs [5][8] using additional coupled feedback windings couldreduce the bulk capacitor voltage, but they also result in deadangle in the input current so that the input current distortion isincreasing. Furthermore, it can be seen that part of the poweris repeatedly processed or recycled in both the conventionaltwo-stage and S 2 ac-to-dc converters.

To improve the powerprocessing, the concept of parallel PFC(PPFC) has been proposed in [9] and [10]. In those schemes, twoparallel power ow paths are used and part of the input poweris processed only once. Therefore, the converters could transfer

powerwith higherefciency. Since each path only transmitspartof the whole conversion power, the components can be replacedwith smaller ones. However, the PPFC design has complex cir-cuit with special control scheme as mentioned in [11]. Anotherscheme of parallel power processing approach was presentedon the base of two-output preregulator cascaded with two-inputpostregulator [12]. Although the output capacitor is smaller andthepowerconversion efciency is high, some extra implementa-tion pricesexist, such as multiple switching devices and oatingMOSFET driver. In addition, the output range of the postreg-ulator is limited so as not suitable for universal input, and itis a two-stage structure by nature. The universal boost/forwardconverterpresented in [14], [15] makes useof an auxiliary trans-former to reduce link voltage stress without inducing the deadangle of the line current. Hence, it inspires the parallel idea forthe universal S2 converter in this paper.

For an ideal PFC converter, the input power ( pin ) is a sinesquare function biased by constant output power ( P ou t ). Asmentioned in [9] and [10], there is 68% of line average in-put power that can be transferred to output directly through PFCstage, which is called the direct power (DP). Only the remaining32% of line average input power needs to be stored in the bulk capacitor temporarily through PFC stage and taken off from thebulk capacitor through dc/dc stage. Since the processed powersare not directly transferred from ac input to dc output, they are

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2990 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 12, DECEMBER 2009

TABLE IRECENTLY PUBLISHED S2 APPROACHES

called indirect powers (IDPs). Hence, based on the aforemen-tioned concept, a new family of S2 ac-to-dc (ac/dc) converter isproposed in this article to increase the DP content percentageon the input power. In the circuits, the front semistage is of single-switch two-output (SSTO) boostyback congurationthat works as a power factor corrector. Part of input power isprocessed with the front yback cell, and the remainder of inputpower is processed through the path along boost cell- C B -dc/dcsemistage.

To illustrate the circuit and control of the proposed con-verter, several recently published low-power S 2 approaches aretabulated in Table I. Only the proposed converter and thosein [20], [21] are implemented with single-switch andsingle-loopcontroller. However, the efciency of [20] is signicantly lowerthan the proposed one and the component count of [21] is morethan the proposed one. From Table I, the circuits in [20], [21],

and [13] have relatively small capacitor voltages. However, the

circuit of [20] has the shortcoming of low efciency. The circuitof [21] employs two bulk capacitors and multiwinding trans-former to get low voltage. The circuit in [13] puts bulk capacitoron the secondary side of yback transformer, which results inthe low capacitor voltage. However, it also has the shortcomingsof extra control switch and that the efciency would decreasewhen universal voltage is applied. Though the bulk capacitorvoltage in proposed converter is higher than those in [13], [20],and [21], it is not higher than 450 V, the voltage limitation of commercial capacitors. Additionally, the use of single switchwith small current stress, two parallel power streams with smallcomponents, and single-loop controller is a competitive advan-tage in the low-power universal applications.

Besides the S2 parallel topologies, the detailed operationprin-ciple and design procedure for universal application is alsopresented in this article. With the procedure, an 80 W proto-

type is constructed, which is a specic demonstration case used



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LI et al. : ANALYSIS AND DESIGN OF A SINGLE-STAGE PARALLEL AC-TO-DC CONVERTER 2991

Fig. 1. Proposed S2 PPFC scheme.

for clear demonstration. Its experimental results have shownthat input current has no dead angle and its harmonics satisesIEC61000 class D at low line with full load and the maximumbulk capacitor voltage is under 450 V at high line with light

load. It is suggested that the proposed S 2 converter could beused for 50150 W with universal input voltage range and upto 200 W with European voltage range. Therefore, the potentialapplications could be PC monitors, ac/dc adapters, and smalltelevision sets.

II. OPERATION PRINCIPLES

A. S 2 Parallel BoostFlyback Converter

The new design power ow scheme of a S 2 PPFC is shownin Fig. 1. In Fig. 1, the line power pin is fed to SSTO boostyback semistage and split to two power ow streams p1 and

p2 . The power ow stream p1 is processed only by yback celland transferred to output directly, and hence it is DP. Since theinstantaneous pin is always different from output power P ou t ,the remaining input power, p2 , is buffered to bulk capacitor C Bthrough the boost function of boost cell to regulate power ow.To fulll a better output power regulation, a dc/dc semistage isemployed to transfer the power, denoted by p3 , from C B to theoutput when pin is low, especially smaller than P ou t . The powerseries p2 and p3 are processed twice from ac input to dc output,and hence they are IDPs. Furthermore, to obtain high powerfactor, the boost and yback cells both had to better operate inDCM, whereas the dc/dc semistage can be implemented withforward or yback conguration and operate either in CCM orDCM. A S2 implemented circuit of Fig. 1 is shown in Fig. 2(a).The circuit has been simplied so as to use only one com-mon power control switch for SSTO boostyback and dc/dcsemistages as shown in Fig. 2(b). In Fig. 2(b), PFC and out-put regulation are performed with one feedback controller asshown in Fig. 2(c). More topologies variations had been shownin [15]. The practical realization circuit in Fig. 2(b) is com-posed of a SSTO boostyback semistage, which is constructedby LB , D B , T 1 , D O 1 , D I 1 , S, D b, and a bulk capacitor C B , anda dc/dc semistage, which is implemented by a yback circuitand constructed by T 2 , D O 2 , D I 2 , S , and D b. In Fig. 2(a) and(b), the two transformers T 1 and T 2 share the load current, so

their size could be small. Furthermore, the boost inductor LBFig. 2. S2 Implementationcircuit of parallel boostybackybackconverter.

(a) Two-switch circuit. (b) Single-switch circuit. (c) Feedback controller circuit.



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Fig. 3. SSTO boostyback converter. (a) Circuit. (b) Main waveforms.

and transformers T 1 distribute the input power together when

switch S is ON, so the size of LB could be of smaller one. There-fore, the sizes of LB , T 1 , and T 2 can be chosen as smaller onesin this design.

B. SSTO BoostFlyback Circuit

In order to clearly build the primary operation concepts andtheories of the proposed S 2 parallel ac-to-dc converter depictedin Figs.1 and2, theoperation ofa SSTO boostybackconverterdepicted in Fig. 3(a) will be introduced in advance. In SSTOboostyback converter, T 1 DO 1 D I 1 C O RO S isthe yback cell and LB DB C B RB S is the boostcell. This converter has PFC function that will be demonstrated

later. In the converter, the boost inductance LB and the yback transformer T 1 both operate in DCM. When control switch S isturned on, T 1 and LB are charged serially. When S is turned off,T 1 and LB are discharged to RO C O and RB C B , respec-tively. Themain current waveforms of SSTO boostybackcon-verter operating in one switching period are shown in Fig. 3(b).To demonstrate theoperation theoryof theconverter, themovingaverage notation x (t) of a waveform x (t) over a switchingperiod T S is employed and dened as follows [16]:

x (t) x (t) T S = 1T S

t+ T S

tx ( ) d . (1)

To focus on theprimary analyses, some assumptions aremadeas follows.

1) All components are ideal.2) Since switching frequency f S is far greater than line

frequency f L = 1/ T L , where T L is line period. The in-put voltage vin (t), regarded as the rectied line voltageV inpk |sin(L t )| , is approximated to a constant over oneswitching period, where V inpk is the ac voltage amplitudeand L = 2 / T L .

3) Since bulk capacitor C B and output capacitor C O aresufciently large, yback output voltage V O and boostoutput voltage V C B are regarded as constants within one

half line cycle.

From Fig. 3(a), it can be seen that the average input cur-rent i in (t) is equal to the sum of average yback inputdiode current iD I 1 (t) and average boost output diode cur-rent iD B (t) . Therefore, by summing the current waveformsof iD I 1 (t) and iD B (t) shown in Fig. 3(b), i in (t) can beobtained as

i in (t) = iD I 1 (t) + iD B (t) = ipk 1 (d + d2)2 (2a)

where d is the duty ratio of S, d2 is the boost cell diode con-duction time ratio, and the current peak value can be obtainedfrom

ipk 1 = d vin (t)

f S (LB + LM 1) =

d2 (V C B vin (t))f SLB

= d1 n1 V O

f SLM 1(2b)

where LM 1 is the primary magnetizing inductance of T 1 , n 1 isthe primary turns ratio of T 1 , and d1 is the yback cell outputdiode conduction time ratio. From (2b), d2 can be obtained as

d2 = d vin (t)(V C B vin (t)) LB

LB + LM 1 . (2c)

With substituting (2b) and (2c) into (2a), i in (t) can be foundas

i in (t) = d2vin (t)

2f S (LB + LM 1)

1 + vin (t)

(V C B vin (t)) LB

LB + LM 1. (2d)

Since the average current of C O over a half line cycle is zeroat steady state, the half line average current of iD O 1 is equal tothe average output current. Thus

2T L

L

0iD O 1 (t) dt =

V ORO

. (3a)

From Fig. 3(b), average current over one switching periodiD O 1 (t) in (3a) can be obtained as follows:

iD O 1 (t) = n1 ipk 1 d1

2 (3b)

where the magnetism discharging time ratio of T 1 transformer,d1 , can be found from (2b) as

d1 = d vin (t)

n 1 V O LM 1

LB + LM 1. (3c)

With substituting (2b) and (3c) into (3b), iD O 1 (t) can beobtained as

iD O 1 (t) = LM 1d2v2in (t)

2f S (LB + LM 1)2 V O. (3d)

Substituting (3d) into (3a), the voltage gain of yback cellM O can be obtained as

M O = V OV inpk

= d LM 1 RO4f S (LB + LM 1)2 (3e)where RO is the load resistance of yback cell.



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TABLE IIVARIOUS OPERATION MODES IN THE PROPOSED CIRCUIT

Similarly, since C B has zero average current over a half linecycle in steadystate, theaverage current relation canbe obtainedas

2T L

L

0iD B (t) dt =

V C BRB

(4a)

where iD B (t) can be obtained from Fig. 3(b) as

iD B (t) = ipk 1 d2

2 =

LB d2v2in (t)

2f S (LB + LM 1)2 (V C B vin (t)).

(4b)The voltage gain of boost cell M C B is dened and obtained

with substituting (4b) into (4a) as

M C B = V C BV inpk

= d2 RB LB

2 f S (LB + LM 1)2

0

sin2 M C B | sin |

d

(4c)where RB is the load resistance of boost semistage.

It can be seen from (2d) that while d and f S are regarded asconstants, the arrangement of smaller ratio of LB /( LB + LM 1)can result in higher linear relation between i in (t) and vin (t),in other words, lower input harmonic distortion. Furthermore,(3e) and (4c) show that voltage gain rises as load resistanceincreases. In particular, V C B in (4c) can bevery highat light loadand high line. Therefore, the method to keep it under commonlyaccepted limit would be presented in Section III.

C. S 4 Parallel BoostFlybackFlyback Converter

The proposed S 2 boostybackyback PPFC that has twosemistages is shown in Figs. 1 and 2. The boostyback semistage has PFC function and simultaneously gives twoenergy-processing paths. Being the remaining semistage, theyback dc/dc converter circuit has fast output regulation ability.The proposed circuit has three magnetic elements, and each el-ement has two operation modes (i.e., CCM and DCM). Hence,there are eight modes that may happen in the circuit as shownTable II. In order to obtain good power factor, the boost andyback cells are designed to operate in DCM, whereas the y-back dc/dc semistage operates in either CCM or DCM in aline cycle. Thus, the converter has two operating modes. Theoperation mode while the yback dc/dc semistage operates inCCM is dened asthe M 1 mode. Contrarily, the operation modewhile the yback dc/dc semistage operates in DCM is denedas the M 2 mode. As mentioned latter in Section III-C, it is noteasy to make LB operate in DCM throughout universal range,and CCM offers higher efciency and lower current stress than

DCM. M 3 and M 4 modesare allowedunderharmonic limitation

Fig. 4. Main waveforms of yback dc/dc semistage in a switching period.(a) M 1 mode. (b) M 2 mode.

of IEC61000-3-2 class D and not discussed in this paper. Withproperly selected n1 , it iseasy to control T 1 in DCM,so M 5M 8modes would not happen. The main current waveforms of theboostyback semistage in a switching period are the same asFig. 3(b), and the waveforms of yback dc/dc semistage in both

modes are shown in Fig. 4. The circuit operations of the single-switch implemented circuit shown in Fig. 2(b) are demonstratedas follows:

In t0 t t1control switch S is switched on, yback inputdiode D I 1 conducts, and D B , D O 1 ,and DO 2 arecutoff. Becausethe boost inductor LB and the yback transformer primary in-ductance LM 1 both are connected in series, they are chargedby the input power at the same time. The current iLB , which isequal to iD I 1 and also the magnetizing current of T 1 , iLM 1, in-creases linearly from zero. Meanwhile, the currents iD I 2 , whichis equal to the magnetizing current of T 2 , iLM 2 , also increaseslinearly from its initial value while in M 1 mode and from zerowhile in M 2 mode. At the moment t1 , S is turned off. The cur-rents iLB , iD I 1 , and iLM 1 reach the same peak value ipk 1 andthe currents iD I 2 and iLM 2 reach another peak value ipk 2 .

In t1 t t3 , the main switch S is OFF , the diode D I 1 andD I 2 are OFF, and DB , D O 1 and DO 2 are ON. The magneticenergy of inductor LB is transferred to C B and the magneticenergies of the transformers T 1 and T 2 are transferred to thesame output load RL simultaneously. Consequently, the energydischarging in T 1 produces the result that iLM 1 and iD O 1 (=n 1 iLM 1 ) both decrease linearly to zero at t2a and keep zerountil t3 , and iLB and iD B decrease linearly to zero at t2b. Theenergy discharging in T 2 gives the result that both iLM 2 andiD O 2 (= n2 iLM 2 ) decrease linearly to nonzero nal values at

t3 for M 1 mode and to zero at t2c for M 2 mode.



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TABLE IIIVARIOUS CASES IN THE PROPOSED CIRCUIT

Since M 1 and M 2 modes are to be discussed, three kinds of thecombination of operationmodesmaybe yielded withina half line cycle as shown in Table III. The major current waveformsand the corresponding duty ratio waveforms are depicted andshown in Fig. 5. Case I normally happens in low input voltageand high output power condition, whereas case III normallyhappens at high input voltage and low output power.

For transient current balance of C O , the transient load currentcan be expressed as

iO (t) = iD O 1 (t) + iD O 2 (t) iC O (t) (5a)

where iD O 1 (t), iD O 2 (t), and iC O (t) represent the transientcurrent of DO 1 , D O 2 , and C O . By an ideal output voltagefeedback control, the duty-cycle of control switch is variedin order to set output voltage on reference value. As shownin Figs. 3(b) and 4, the input current ( iD O 1 (t) + iD O 2 (t))of C O is regulated to balance with output current ( iO ) in T S so that iO (t) = I O , iC O (t) = 0 , vO (t) = V O ,and(5a)canbe expressed as

I O = V ORL

= P ou t

V O= iD O 1 (t) + iD O 2 (t) (5b)

where V O is the average output voltage, RL is the load resis-tance, iD O 1(t) represents the averaging current of DO 1 asexpressed in (3d), and iD O 2(t) represents the averaging cur-rent of DO 2 . Although the input voltage varies in a half linecycle, the output power will be kept constant through the outputfeedback control. To make (5b) come true, the ideal output volt-age feedback controller should have superior transient responseand robust stability. The structure of controller is implementedwith current-mode controller with optically isolated feedback as shown in Fig. 2(c). In the circuit of Fig. 2(c), output voltagesignal V O is transferred to UC3844 via TL431 and optcoupler,the switch current iS is sensed and fed back to comparator, andthen the duty ratio d of control switch S is well controlled.

For the M 1 mode, consider thebulk capacitance is a large one.Then the duty ratio d in M 1 mode will be kept nearly constantD m 1 and yield a high regulation output, which is given by

V O = V C B dn2 (1 d) d= D m 1

(6)

where n2 is the turns ratio of T 2 . From (6), Dm 1 can be foundas

d = Dm 1 = n2V O

n 2V O + V C B. (7)

From (5b), iD O 2(t) can be obtained as

iD O 2 (t) = I O iD O 1 (t) |d= D m 1 . (8)

Fig. 5. Main waveforms of parallel boostybackyback converter in a linecycle. (a) Case I (M 1 mode only). (b) Case II (both M 1 and M 2 modes).(c) Case III (M 2 mode only).



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TABLE IVTHE CORRESPONDING PARAMETERS OF CASES IIII ILLUSTRATION EXAMPLE

While in M 2 mode, T 2 operates in DCM. From Fig. 4(b) byfollowing the similar deriving procedure of (3d), iD O 2(t) canbe obtained as

iD O 2 (t) = n2 ipk 2 d3

2 =

d2 V 2C B2f S LM 2V O d= dm 2

(9)

where dm 2 is the instant duty ratio in M 2 mode. Substituting(3d) and (9) into (5b), it can be obtained as

d = dm 2 () =

2f SP ou t

L M 1 V 2i n p k s in 2 (L B + L M 1 )2

+ V 2C BL M 2

(10)

where = L t is the phase of sinusoidal line voltage, andP ou t is the output power. In order to generate the complex dutydm 2 , the compensator in the current-mode control had been op-timized to possess superior transient responses such as smallrising time, low overshoot, and zero steady-state error. Addi-tionally, the compensator also can generate the correct duty dm 2with differentoperation modes due to its superior performances.

From (3d) and (5b), iD O 1(t) reaches maximum andiD O 2(t) reaches minimum at L t = /2 . For case I, the

converter operates only in M 1 mode (T 2 operates in CCM), I Omust be greater than the boundary value I D O 1P K + I D O 2B

I O I D O 1P K + I D O 2B (11)

where I D O 1P K is the peak value of iD O 1(t) and I D O 2B isthe boundary value of iD O 2 between CCM and DCM. Theformer can be obtained by replacing d with Dm 1 and vin (t)with V inpk sin (/2) in (3d), and expressed as

I D O 1P K =LM 1D 2m 1V 2inpk

2f S (LB + LM 1)2 V O(12)

and the latter can be obtained by replacing d with Dm 1 in (9)and expressed as

I D O 2B = D2m 1 V 2C B2f SLM 2V O

. (13)

Furthermore, as I O is smaller than the boundary value in (11),M 2 mode shows in the operation of the proposed converter asplotted in Fig. 5(b). From the equality I D O 2 = I D O 2B and (5b),the transition angle T from M 1 to M 2 mode can be expressedas

T = L tT

= sin 1

2f S (LB + LM 1)2 V O

LM 1D2m 1V

2inpk

(I O I D O 2B ) . (14)

As I O gets smaller, the interval of M 2 becomeswider and M 1becomes narrower. It can also be seen from (3d) that iD O 1(t)reaches zero at line voltage phase being 0 and and from (5b)that iD O 2(t) reaches maximum at the same time. Thus, as I Ogets smaller than theboundary valueof (13), theconverter wouldwork in M 2 mode only during a half line cycle. Consequently,for case II operation that the converter works in both M 1 andM 2 modes in a half line cycle, I O will be in the range of

I D O 1B + I D O 2B I O I D O 2B . (15)

Besides, for case III operation that the converter works onlyin M2 mode in a half of a line cycle, I O is smaller than theboundary value

I D O 2B I O . (16)

Based on the earlier discussion, the theoretical currents andvoltage waveforms for the cases IIII examples are illustratedin Fig. 5(a)(c), and the corresponding parameters used areshown in Table IV. For the case I operation, the value of LM 2in (13) intentionally selected a large one so that (11) can besatised and case I operation can present. For the other param-eters, LB , LM 1 , n 1 , and n2 , they are selected according to theequations described in Section III so that cases II and III can beactivated.

From Figs. 2 and 5(a)(c), it can be seen that the average inputcurrent i in (t) is divided into iD I 1(t) and iD B (t) throughthe operation of boostyback semistage. Among these twocurrents, iD O 1(t) is transformed to iD O 1(t) by the yback cell, and then transferred to RL directly. Alternatively, iD B (t)is mainly buffered in C B during vin peak, then transformed toiD O 2(t) by the yback dc/dc semistage, and then transferred

to RL for output regulation. The output current I O is primarilysupplied by iD O 2(t) in low line voltage duration.

The switch current of conventional cascade S4 converter

like [3] mainly composed of inductor current of the boost-ICSsemistage and the transformer primary current of the yback semistage. Both semistages have to handle the whole inputpower. Hence, the peak switch current is doubled and reachespeak value when input power is the maximum and occurs at = /2 . In Fig. 2, the average switch current iS(t) of theproposed converter is the sum of iD I 1(t) and iD I 2(t) andcan be expressed as

iS (t) = iD I 1 (t) + iD I 2 (t) . (17a)

Both iD I 1(t) and iD I 2(t) represent the charged current of the rst semistage from line input and the transformer primary

current of second semistage from bulk capacitor and can be



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Fig. 6. Average switch current for case I.

obtained from Fig. 3(b) as

iD I 1 (t) = iLB (t) iD B (t) (17b)

and

iD I 2 (t) = V OV C B

iD O 2 (t) = V OV C B

(I O iD O 1 (t) ) .(17c)

It can be seen from (17a) and (17c) that if iD O 1(t) in-creases, more output current will be provided by yback cell,and iS (t) will be reduced. Contrarily, if yback cell is absent(i.e., iD O 1(t) = 0 ), the circuit in Fig. 2(b) will be reduced toa conventional S2 converter [3]. Furthermore, from Fig. 3(b),iD I 1(t) can be further obtained as

iD I 1 (t) = ipk 1 d

2 =

d2V inpk sin (L t)2f S (LB + LM 1)

. (17d)

Substituting (3d) into (8) and the result is substituted into(17c), iD I 2(t) for M 1 mode can be further expressed as

iD I 2 (t) = V OV C B

I O LM 1D 2m 1V 2inpk sin

2 (L t)

2f S (LB + LM 1)2 V O.

(17e)Substituting (9) into (17c), iD I 2(t) for M 2 mode can be

further obtained as

iD I 2 (t) = d2 V C B2f S LM 2 d= dm 2

(17f)

where dm 2 can be obtained from (10). It can be seen from(17d)(17f) and Fig. 6 that iD I 1(t) reaches local maximumat = /2 while iD I 2(t) is minimum, and iD I 2(t) reacheslocal maximum at = / 2 or while iD I 1(t) is zero. There-fore, the power processed by yback cell is transferred to loaddirectly and would not be processed by the switch again, the lo-cal maximum current stresses due to DP and IDP do not appearat the same time during half line cycle, so the overall currentstress of main switch was small compared with that of conven-

tional S4

converter.

III. ANALYSIS AND DESIGN

A. Power Distribution and Bulk Capacitor Voltage

In the proposed S2 PPFC scheme shown in Fig. 1, the powerdistribution between the DP ( p1) and IDP ( p2 or p3 ) process-ing paths is one of the important design considerations since itaffects not only the converter efciency but also the power rat-ings required to the components in each processing power path.Besides, in the IDP path, the energy balance between the powerow into ( p2 ) and out ( p3 ) of bulk capacitor determines thebulk capacitor voltage, which can be very high if not properlydesigned. Based on the earlier design considerations, the powerdistribution will be analyzed according to the implementationcircuit shown in Fig. 2(b), and hence the formula related topower distribution and bulk capacitance voltage can be derived.They are formulated as follows.

The input power pin is composed of p1 and p2

pin () = vin (t) iLB (t) = p1 () + p2 () . (18)

The DP processed by yback semistage is given by

p1 () = vin (t) LM 1

LB + LM 1iD I 1 (t) = V O iD O 1 (t) .

(19a)Substitution of iD O 1 (t) given by (3d) into (19a) gives

p1 () = 2 k pP ou t sin2 (19b)

where kP is dened as the DP ratio and can be obtained as

k p P 1,pk (d)

P ou t=

LM 1d2V 2inpk4f S (LB + LM 1)2 P ou t

(20)

and P 1,pk is given by

P 1,pk (d) =LM 1d2V 2inpk

4f S (LB + LM 1)2. (21)

In M 1 mode, k p is a constant and can be found by

k p = k p | d= D m 1 = K P 1. (22)

In M 2 mode, k p is a function of and obtained by

k p = k p | d= dm 2 () = k p2 ()

=LM 1 V 2inpk

2 LM 1V 2inpk sin2 + V

2C B

L M 2 (LB + LM 1)2

. (23)

It can be seen from (23) that k p2 is independent of P ou t . Thevalues of Dm 1 and dm 2 can be obtained from (7) and (10).

The IDP processed by boost semistage from LB to C B isgiven by

p2 () = V C B iD B (t) . (24a)

Substitution of iD B (t) given by (4b) into (24a) gives

p2 () = M C B sin2 M C B | sin |

2k pP ou tK M 1

(24b)

where K M 1 is called inductance ratio and expressed as

K M 1 = LM 1

LB. (25)



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TABLE VK ID P INDIRECT POWER RATIO

The dimensionless variable M C B in (4c) and (24b) can be re-garded as the normalized V C B with respect to V inpk . In practice,the true value of V C B is lower than the theoretical value becauseof presence of the equivalent series resistance (ESR) of induc-tance and capacitor. Thus, in order to avoid the bulk capacitorvoltage V C B fromexceeding the limitation voltage,450V, of thecommercial capacitor, it is suggested that M C B had better been

controlled below or just equal to 1.2 for vac = 265V rm s . Fur-thermore, the IDP processed by yback dc/dc semistage fromC B can be expressed as

p3 () = V O iD O 2 (t) = P ou t p1 ()

= P ou t 1 2k p sin2 . (26a)

Substituting (9) into (26a), p3 for M 2 mode can be expressedas

p3 () = d2 V 2C B2f S LM 2 d= dm 2

= d2 (M C B V inpk )2

2f SLM 2 d= dm 2.

(26b)

Since p1 and p2 (or p3 ) vary with , they would be expressedas

P x, ave |x =1 ,2,3 = 1

0 px () d

x =1 ,2,3. (27)

Therefore, DP ratio K DP is dened as

K DP = P 1,ave

P ou t. (28)

In this equation, high K DP implies high efciency and largeutilization performance of T 1 . Because the average power sentto and out from C B are equal for a half line cycle, the IDP ratioK ID P can be dened as

K ID P = P 2,ave

P ou t=

P 3,aveP ou t

= 1 K DP . (29)

The more detailed IDP ratio expressions dened in (29) forthree cases can be derived as shown in Table V by substituting(24b) and (26a) into (27) and normalizing with P ou t . By usingiterative approaching methodologyfor obtainingaccurate M C B ,the detailed expressions in Table V are calculated repeatedlyuntil (29) is satised, and K DP , K ID P , and M C B can be solvedconsequently. Following the iterative calculation process, thecurves of DP ratio K DP versus output power P ou t for differentline input voltage vac and operation cases are obtained and

shown in Fig. 7, and the curves are obtained by taking the

Fig. 7. K D P versus output power for different vac and cases at the conditionof Table IV-case I.

converter parameters in Table IVcase I as an example. It canbe seen from Fig. 7 that the relation between K DP and case is(K DP)III > (K DP)II > (K DP)I . K DP increases as P ou t is low

or vac is high.The curves of K DP and M C B versus P ou t for differentK M 1 and LM 2 at the assigned conditions of the converter,LM 1 = 150 H, n 2 = 1 .7, V ac = 265 V rm s , and V O = 54 V ,are shown in Fig. 8. Substituting (23) into case III of Table V,M C B obtained from (29) is independent of P ou t . Hence, eachM C B curve in Fig. 8(b) is horizontal when converter operatesin case III. From Fig. 8(a), it can be seen that K DP is greaterat low output power. That is to say, K ID P rises as output powerincreases. This implies that the DP is the main portion provid-ing the load and the IDP is regarded as energy reservoir usedfor regulating the power ow to load. Besides, it can be seenfrom Fig. 8(b) that M C B increases as P ou t decreases and ap-proaches and holds to the maximum value at lighter load. Thisphenomenon shows that high bulk capacitor voltage will be re-sulted at high line and case III. However, from Fig. 8, it alsocan be seen that K DP goes up and M C B slides down as K M 1increases. This is because more input power goes through y-back cell without being buffered by C B . Hence, for the purposeof obtaining high efciency and low V C B it is better to selectK M 1 as large as possible. Furthermore, the decrease of LM 2can lower both K DP and M C B since it can be seen from (9)that low LM 2 will result in large current iDO2 for M 2 modeor equivalently to say that the output power ratio providedby C B will be increased. In other words, more output power

comes from bufferedenergy andless input powerpassesthrough



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Fig. 8. (a) K D P . (b) M C B versusoutput power for different K M 1 and LM 2 ,at LM 1 = 150 H, n2 = 1 .7, V ac = 265 V rm s , V O = 54 V .

yback cell, so this will result in lower efciency. However, it

is good for reducing the maximum value of M C B since morepower is continuously sent out from C B . Therefore, M C B has tobe lower to achieve half line cycle average IDP balance in (29)as can be seen from (24b) and (26b). Besides, decreasing LM 2would cause yback dc/dc semistage closer to DCM but makeworse output voltage regulation. A compromise is suggestedfor selecting proper value of LM 2 in considering of the propervalues of V C B , K DP , and output voltage regulation. It can beseen from Fig. 8 that curves (1) and (2) have high K DP and themaximum values of M C B are below or close to 1.2 among allcurves. Thus, with theconsideration of obtaininghigh efciencyand low V C B , curves (1) and (2) are better choices.

B. Design Equations

Thedesign equationsare going to be derived for theobjectivesof obtaining proper PFC and output voltage regulation. TheDCM operation design of boostyback semistage is essentialfor obtaining good PFC. It can be seen from iLM 1 waveform inFig. 3(b) that to guarantee T 1 operating in DCM, d1 T S shouldbe smaller than (1 d)T S . Thus, n1 should be designed tosatisfy the following equation derived from (3c)

n 1 K M 1

(K M 1 + 1)V inpkV O

dpk(1 dpk )

(30a)

where dpk is the duty ratio occurring at = 2 asshown inFig. 5.From (30a), the minimum turns ratio for T 1 to operate in DCMis obtained as

n 1 n 1,min = K M 1

(K M 1 + 1)V inpk ,min

V Odpk ,ma x

(1 dpk ,ma x ) (30b)

where dpk ,max is the maximum of dpk and occurs at the lowestrectied line input voltage vin (t) = V inpk ,min |sin(/ 2)| and thelargest output power. With conservative design, dpk ,max can bereplaced with the acceptable maximum value.

Similarly, to guarantee LB operating in DCM, d2 T S shouldbe

smaller than (1 d)T S . Thus, LB and LM 1 should be designed

to satisfy the following equation derived from (2c):

(1 dpk ) LB

(LB + LM 1)dpk

(M C B 1) (31a)

where M C B canbe solved from (29) andTableV. From previoussection, it can be known that M C B will slide down and dpkthus rises as output power is increasing. Thus, the worst DCMcondition occurs at the low input voltage and the large outputpower for universal application. From (31a), the minimum timeratio needed for iLB to decay to zero before the end of switchOFF time duration can be obtained as

Ddz = LB

(LB + LM 1)dpk ,ma x

(M C B , min 1) (31b)

where M C B , min = V C B , min / V inpk ,min ,and V C B , min is the min-imum bulk capacitor voltage occurring at the lowest recti-ed line input voltage and the largest output power. However,the converter needs sufcient secondary open voltage of dc/dcsemistage transformer T 2 , V C B / n 2 , to guarantee the output reg-

ulation operation all the time even at vin (t) = 0 . Hence, foryblack dc/dc semistage, the following relation must be satis-ed

V C Bn 2

dzc(1 dzc )

= V O (32a)

where dzc is the duty ratio at vin (t) = 0 as denoted in Fig. 5.It can be seen from (32a) that V O is decreasing as n2 increases.Thus, after rearranging (32a), the turns ratio limitation of T 2 isobtained as

n 2 < V C B , min

V Odzc, max

(1 dz c, ma x ) = n2,ma x (32b)

where dzc, max is the maximum dzc while occurring at the low-est rectied line input voltage and the largest output power,and n 2,ma x is the upper bound of n 2 to satisfy output voltagerequirement shown in (32a).

C. Example and Design Procedure

To verify the proposed boostybackyback converter, aprototype converter with the following specications was de-signed:

1) ac input voltage ( vac ): 85265 V rm s ;2) output voltage ( V O ): 54 V;3) maximum output power ( P ou t ,max ): 80 W;4) switching frequency ( f S ): 100 kHz;5) maximum duty ratio ( D ma x ) at vac = 85 Vrm s : 0.44.As the suggested criterion [17] for universal input voltage S 2

converter, the main design objective is to comply with the linecurrent harmonic standards such as IEC61000-3-2 class D, tokeep bulk capacitor voltage below 450 V, and to lter outputripple as small as possible.

From the previous section, it can be known that LB tends tooperate in CCM as input voltage decreases and load increases,thus at this condition the harmonic current will get large. Fur-thermore, the bulk capacitor voltage will be high and may in-crease over 450 V at high line and light load. While considering

the object of input current, the DCM operation gives a better



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Fig. 9. Ddz and (1 dp k ,m ax ) versus LM 1 for different LB , L M 2 =1.5 mH, at D m ax = 0 .42, vac = 85 V rm s , V O = 54 V, and P ou t = 60 W .

Fig. 10. M C B , m in and n2,m ax versus LM 1 for different LB , L M 2 =1.5 mH, at D m ax = 0 .42, vac = 85 V rm s , VO = 54 V, and P ou t = 60 W .

TABLE VIPARAMETERS OF CRITICAL COMPONENTS

PF in comparing with that given by the CCM operation. How-ever, the CCMoperation offers higher conversion efciency andlower switch current stress than those given by the DCM op-eration. For the regular design, it is not easy to be realized inpractice that LB operates in DCM under the lowest line and thefullest load condition. Hence, it is not necessary for LB to op-erate in DCM during the whole half cycle, and the worst DCMcondition for LB in this example is set at vac = 85 Vrm s , and

P ou t = 60 W. It is permissible that LB operates in CCM during

Fig. 11. Measured line voltage, bulk capacitor voltage, line current, outputvoltage. (a) vac = 85 V rm s , P ou t = 60 W . (b) vac = 265 V rm s , P ou t =60 W . (c) vac = 265 V rm s , P ou t = 20 W .

a small interval within a half line cycle, that is also called semi-continuous conduction mode (SCM) [17] while vac = 85 Vrm sand P ou t > 60 W, as long as the IEC regulation can be satised.With the substitution of the earlier specications to (30b), DCMcondition for T 1 could be reached as long as n1 and K M 1 wereproperly selected. However, LM 1 and LB cannot be determinedby (31b) directly since LM 2 must be assigned in advance, andfurther, M C B , m in and dpk ,max have to be calculated. For the object of low bulk capacitor voltage, M C B had better no more than1.2 at high line and light load condition in order to guaranteeV C B below 450 V by properly selecting K M 1 and LM 2 . Thecritical parameters LB , LM 1 , n1 , LM 2 , and n2 are interrelatedand designed from the following procedure.

1) Assign LM 2 at rst, and calculate M C B , mi n and

dpk ,ma x by following the iterative calculating process in



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Fig. 12. Measured switching waveforms. (a) M 1 mode. (b) M 2 mode atvac = 130 V rm s , R L = 60 .24 .

Section III-A at the preset worst DCM condition of LB ,vac = 85 Vrm s , and P ou t = 60 W.

2) Generate the curves of (1 dpk ,ma x ) and Ddz versusLM 1 for different LB by using equation (31b) with the

calculated M C B , mi n and dpk ,max in step 1.3) Generate the curves of n 2,max versus LM 1 for differentLB with substituting M C B , min and dzc, max in (32b), andset dzc, ma x to 0.42 while P ou t = 60 W to prevent fromover 0.44 when P ou t = 80 W.

4) Select LM 1 and LB from the curves of (1 dpk ,max )and D dz provided from step 2 such that LB can operatein DCM at the preset worst DCM condition, and henceK M 1 = LM 1 / LB is determined.

5) Select n2 with selected LM 1 and LB from n2,max curvesgiven by step 3 such that yback dc/dc semistage cancorrectly fulll output regulation.

6) Select n1 with the selected K M 1 from step 4 substitutedto (30b) such that T 1 can operate in DCM.

7) Calculate M C B at high lineand light loadwith the selectedLB , LM 1 , n1 , LM 2 , and n2 by following the iterativecalculating process in Section III-A.

8) Check M C B whether it is below 1.2 at high line and lightload or not. If not, reduce LM 2 and repeat steps 17 untilM C B is equal to or smaller than 1.2 at high line and lightload.

Following these procedures, the nal curves of (1 dpk ,max )and D dz are shown in Fig. 9, the curves of n 2,max are shownin Fig. 10, and the designed parameters of key components areobtained as LB = 30 H, LM 1 = 150 H, n 1 = 1.6, LM 2 =

1.5 mH, n2 = 1 .7.

Fig. 13. (a) Line voltage and line current measured at worst condition.(b) Harmonic content and class D limits.

IV. EXPERIMENTAL RESULTS

For presenting the performance of the prototype based on theproposed topology, the circuit of Fig. 2(b) and (c) has been builtand tested in the specications described in Section III-C. Theparameters of the critical components are given in Table VI.Because the input current iin = iLB of the proposed converteris pulsating when LB operates in DCM, the electromagneticinterference (EMI) level would be above the limits of standardsuch as Federal Communications Commission (FCC) or In-ternational Special Committee on Radio Interference (CISPR).Hence, an input lter with low input displacement angle be-tween input voltage and current, minimum interaction with theconverter and system stability are designed to attenuate EMI tomeet regulatory specications and get smooth waveform of lineinput current iac in Figs. 11 and 13(a). The detailed design andanalysis about input lter could be referred to [18] and [19].The key waveforms at vac = 85 Vrm s / P ou t = 60 W, vac =265 Vrm s / P ou t = 60 W, and vac = 265 Vrm s / P ou t = 20 W arepresented in Fig. 11, and the switching waveforms for M 1 modeand M2 mode at vac = 130 Vrm s / RL = 60.24 are presentedin Fig. 12. As can be seen, the shapes of line input current iac are

approaching to the average input currents shown in Fig. 5. The



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Fig. 14. Measured bulk capacitor voltage under line and load variations.

Fig. 15. Measured power factor under line and load variations.

Fig. 16. Measured efciency under line and load variations.

measured key waveforms at theworst condition ( vac = 85 V rm sand P ou t = 80 W) are shown in Fig. 13(a). Although the lineinput current is distorted due to the SCM operation of LB , itsharmonic contents still comply with the class D limits as shownin Fig. 13(b). Fig. 14 shows the measured bulk capacitor volt-ageunder line and load variations.Themaximum bulk capacitorvoltage is 415.4 V, which is below the commercial size 450 Vand occurs at vac = 265 V rm s with P ou t = 20 W. Fig. 15 showsmeasured power factor under line and load variations. It can be

seen that the lowest power factor is 0.91 and occurs at the worst

condition. The power factors at most conditions are above 0.95and some even reach 0.99. As described in Sections III-B andIII-C, LB tends to operate in CCM as input voltage decreasesand load increases, andtheworst DCMcondition for LB issetatvac = 85 Vrm s and P ou t = 60 W. Hence, LB begins to operatein SCM when P ou t is greater or equal to 60 W. Consequently,iac is distorted and PF degrades as can be seen vac = 85 Vrm scurve in Fig. 15. Fig. 16 shows efciency under line and loadvariations. The efciency is greater than 80% in most operatingrange, and the maximum value is 85.8% at vac = 130 V rm s withP ou t = 60 W.

V. CONCLUSION

The SSTOboostyback converter andcorresponding S 2 par-allel converter were introduced in this paper. The SSTO boostyback converter has appreciable self-PFC property when op-erates in DCM. By cascading dc/dc semistage to the boost celloutput of boostyback converter, the S 2 parallel converter can

achieve input line current shaping and tight output voltage reg-ulation with single-loop feedback control. Since partial of inputpower is processed only once by yback cell, so the conversionefciency is improved and the switch current stress is smallcompared with the conventional S 2 converter. The proposedcircuit has two parallel power streams so that the componentscould be small. Furthermore, the analysis of the implementedcircuit and the design procedure for universal application arealso presented. With this procedure, an 80 W prototype wasbuilt and tested. The experimental results show that the volt-age across bulk capacitor is kept under 415.4 V for full rangeoperation (85265 V rm s ) and load (2080 W). The maximumpower factor is 0.99 and the measured line current harmoniccontents at the worst condition comply with the IEC61000-3-2class D limits. The maximum efciency is 85.8%. This newcircuit structure also can be extended to more alternative par-allel combinations. Therefore, the proposed parallel converterpresents an overall good performance in the main aspects of universal S 2 PFC converters.

REFERENCES

[1] Electromagnetic Compatibility (EMC), Part 3, International StandardIEC61000-3-2, 2001.

[2] M. J. Willers, M. G. Egan, J. M. D. Murphy, and S. Daly, A BIFREDconverter with a wide load range, in Proc. IEEE IECON 1994 , Bologna,Italy, pp. 226231.

[3] R.Redl,L. Balogh, andN. O. Sokal, A new familyof single-stageisolatedpower-factorcorrectors withfast regulation of theoutput voltage, in Proc.PESC 1994 , pp. 11371144.

[4] L. Huber, J. Zhang, M. M. Jovanovic, and F. C. Lee, Generalized topolo-gies of single-stage input-current-shaping circuits, IEEE Trans. Power Electron. , vol. 16, no. 4, pp. 508513, Jul. 2001.

[5] F. Tsai, P. Markowski, and E. Whitcomb, Off-line yback converter withinput harmonic correction, in Proc. IEEEINTELEC1996 Annu. Meeting ,pp. 120124.

[6] J. Zhang, L. Huber, M. M. Jovanovic, and F. C. Lee, Single-stage input-current-shaping technique with voltage doubler-rectier front end, IEEE Trans. Power Electron. , vol. 16, no. 1, pp. 5563, Jan. 2001.

[7] L. Huber and M. M. Jovanovic, Single-stage, single-switch, isolatedpower supply technique with input-current-shaping and fast output-voltageregulationfor universalinput-voltage-rangeapplications, in Proc.

IEEE APEC 1997 Annu. Meeting , pp. 272280.



14/14


[8] J. Qian, Q. Zhao, and F. C. Lee, Single-stage single-switch powerfactor correction (S 4 -PFC) ac/dc converters with dc bus voltage feed-back, IEEE Trans. Power Electron. , vol. 13, no. 6, pp. 10791088, Nov.1998.

[9] Y. Jiang, F. C. Lee, G. Hua, and W. Tang, A novel single-phasepower factor correction scheme, in Proc. IEEE APEC 1993 , pp. 287292.

[10] Y. Jiang and F. C. Lee, Single-stage single-phase parallel power factorcorrection scheme, in Proc. IEEE PESC 1994 , pp. 11451151.

[11] O. Garcia, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, Single phasepower factor correction: A survey, IEEE Trans. Power Electron. , vol. 18,no. 3, pp. 749755, May 2003.

[12] J. Sebastian, P. J. Villegas, F. Nuno, O. Garcia, and J. Arau, Improvingdynamic response of power-factorpre-regulators by using two-input high-efcient post-regulators, IEEE Trans. Power Electron. , vol. 12, no. 6,pp. 10071016, Nov. 1997.

[13] A. Lazaro, A. Barrado, M. Sanz, V. Salas,and E. Olias,New powerfactorcorrection ac-dc converter with reduced storage capacitor voltage, IEEE Trans. Ind. Electron. , vol. 54, no. 1, pp. 384397, Feb. 2007.

[14] J. Y. Leeand M.J. Youn, Asingle-stagepower-factor-correction converterwith simple link voltage suppressing circuit (LVSC), IEEE Trans. Ind. Electron. , vol. 48, no. 3, pp. 572584, Jun. 2001.

[15] H. Y. Li and L. K. Chang, A single stage single switch parallel ac/dcconverter based on two-output boost-yback converter, in Proc. PESC 2006 , pp. 25012507.

[16] R. W. Erickson, Fundamentals of Power Electronics . New York: Chap-man & Hall, 1997.[17] G. Moschopoulos and P. Jain, Single-phase single-stage power-factor-

corrected converter topologies, IEEE Trans. Ind. Electron. , vol. 52,no. 1, pp. 2335, Feb. 2005.

[18] V. Vlatkovic, D. Borojevic, and F. C. Lee, Input lter design for powerfactor correction circuits, IEEE Trans. Power Electron. , vol. 11, no. 1,pp. 199205, Jan. 1996.

[19] J. Sun, Input impedance analysis of single-phase PFC converters, IEEE Trans. Power Electron. , vol. 20, no. 2, pp. 308314, Mar. 2005.

[20] Q. Zhao, M. Xu, F. C. Lee, and J. Qian, Single-switch parallel powerfactor correction ac-dc converters with inherent load current feed-back, IEEE Trans. Power Electron. , vol. 19, no. 4, pp. 928936, Jul.2004.

[21] S. Luo, W. Qui, W. Wu, andI. Batarseh,Flyboost power factorcorrectioncelland a newfamilyof single-stageac/dc converters, IEEETrans. Power Electron. , vol. 20, no. 1, pp. 2534, Jan. 2005.

[22] D. D.-C. Lu, H. H.-C. Iu, and V. Pjevalica, A single-stage ac/dc converterwith high power factor, regulated bus voltage, and output voltage, IEEE Trans. Power Electron. , vol. 23, no. 1, pp. 218228, Jan. 2008.

[23] R.-T. Chen, Y.-Y. Chen, and Y.-R. Yang, Single-stage asymmetrical half-bridge regulator with ripple reduction technique, IEEE Trans. Power Electron. , vol. 23, no. 3, pp. 13581369, May 2008.

Heng-Yi Li was born in Taipei, Taiwan, in August1963. He received the B.S. degree from the NationalTaiwan Universityof ScienceandTechnology, Taipei,and the M.S. degree from the National Taiwan Uni-versity, Taipei, in 1990, both in mechanical engi-neering. Currently he is working toward the Ph.D.degree at the Institute of Electrical and Control En-gineering, National Chiao Tung University, Hsinchu,Taiwan.

He is currently a Staff Member at the Insti-tute of Nuclear Energy Research, Taoyuan, Taiwan.

His main responsibilities include plasma power development and computer-controlled system design. His recent research interests include ac-to-dc powerfactor correction circuit, high-frequency inverter, and system modeling andcontrol.

Hung-Chi Chen was born in Taichung, Taiwan,in June 1974. He received the B.S. and Ph.D. de-grees fromthe Department of Electrical Engineering,National Tsing-Hua University (NTHU), Hsinchu,Taiwan, in June 1996 and June 2001, respectively.

From October 2001, he was a Researcher at theEnergy and Resources Laboratory (ERL), IndustrialTechnology Research Institute (ITRI), Hsinchu. InAugust 2006, he joined the Department of Electricaland Control (ECE), National Chiao Tung University(NCTU), Hsinchu, where he is currently an Assistant

Professor. His research interests include power electronics, power factor correc-tion, motor and inverter-fed control, DSP/MCU/FPGA-based implementationof digital control.

Lon-Kou Chang (M87) received the B.S. degreefrom the Chung Yuan Christian University, Chung-Li, Taiwan, in 1975, the M.S. degree from the Na-tional Chiao Tung University, Hsinchu, Taiwan, in1977, both in electronics engineering, and the Ph.D.degree in electrical engineering from the Universityof Maryland, College Park, in 1995.

From 1983 to 2008, he wasan AssociateProfessorof electrical and control engineering at the National

Chiao Tung University. During 19821985, he wasa part-time Electrical Supervisor for the Tri-ServiceGeneral Hospital, Taipei, Taiwan. He was also an R&D Consultant of Sun-pentown Int. Co., Taiwan, from 1996 to 1998. He is currently a Consultant atMacroblock Incorporation, Hsinchu.His recent research interests include powerconverter topology design, LED lighting, and ESD and latch up protection de-sign for power ICs.

Documents

Analysis and Design of a single stage parallel AC to DC Converter