A Single-Stage Asymmetrical Half-Bridge Flyback Converter

Article 1

A Single-Stage Asymmetrical Half-Bridge Flyback 2

Converter with Resonant Operation 3

Chung-Yi Ting 2, Yi-Chieh Hsu 2, Jing-Yuan Lin 1,* and Chung-Ping Chen 2 4 1 Department of Electronic and Computer Engineering, National Taiwan University of Science and 5

Technology, Taiwan, ROC; [email protected] (J.L.) 6 2 Graduate Institute of Electronics Engineering, National Taiwan University; [email protected] (C.T.); 7

[email protected] (Y.H.); [email protected] (C.C.) 8 * Correspondence: [email protected] (J.L.); Tel.: x-886-2-27376419 9

10

Abstract: This paper proposes a single-stage asymmetrical half-bridge fly-back (AHBF) converter 11 with resonant mode using dual-mode control. The presented converter has an integrated boost 12 converter and asymmetrical half-bridge fly-back converter and operates in resonant mode. The 13 boost-cell always operates in discontinuous conduction mode (DCM) to achieve high power factor. 14 The presented converter operates simultaneously using a variable-frequency-controller (VFC) and 15 pulse-width-modulation (PWM) controller. Unlike the conventional single-stage design, the 16 intermediate bus voltage of this controller can be regulated depending on the main power switch 17 duty ratio. The asymmetrical half-bridge fly-back converter utilizes a variable switching frequency 18 controller to achieve the output voltage regulation. The asymmetrical half-bridge fly-back 19 converter can achieve zero-voltage-switching (ZVS) operation and significantly reduce the 20 switching losses. Detailed analysis and design of this single-stage asymmetrical half-bridge 21 fly-back converter with resonant mode is described. A wide AC input voltage ranging from 90 to 22 264 Vrms and output 19 V/ 120 W prototype converter was built to verify the theoretical analysis and 23 performance of the presented converter. 24

Keywords: fly-back converter; zero-voltage-switching (ZVS); Variable-frequency-controller (VFC); 25 single-stage 26 27

1. Introduction 28

A conventional power supply was designed with a two-stage scheme that can be divided into 29 two parts. The first stage achieves power-factor-correction (PFC) to reduce the input current 30 harmonics. The second stage is a DC/DC converter that regulates the output voltage. However, the 31 two-stage scheme has several defects, such as high cost and power supply system complexity. In 32 recent years, a single-stage scheme was proposed [1-5] that integrates a boost stage and a DC/DC 33 stage to share a common switch. The boost-cell stage operates in discontinuous conduction mode 34 (DCM) to provide high power factor while the DC/DC stage can be responsible for output voltage 35 regulation. Unfortunately, the single-stage scheme presents major problems in which the 36 intermediate bus voltage cannot be regulated, such as the BIFRED converter, single-stage fly-back 37 converter and single-stage LLC resonant converter [6-10]. When voltage is input for universal 38 applications, the intermediate bus voltage could be as high as 1000 V, causing difficulty in selecting 39 converter components, with voltage stress issues throughout the capacitors and switches. The wide 40 intermediate bus voltage variation will cause output voltage regulation design difficulty and also 41 cause lower conversion efficiency though the DC/DC stage. The single-stage scheme intermediate 42 bus voltage cannot be regulated at light loads and universal input voltage. The 43 zero-voltage-switching (ZVS) fly-back converters have been used widely in industry and are 44

Preprints (www.preprints.org) | NOT PEER-REVIEWED | Posted: 9 May 2018 doi:10.20944/preprints201805.0140.v1

© 2018 by the author(s). Distributed under a Creative Commons CC BY license.

Peer-reviewed version available at Energies 2018, 11, 1721; doi:10.3390/en11071721

http://dx.doi.org/10.20944/preprints201805.0140.v1

http://creativecommons.org/licenses/by/4.0/

http://dx.doi.org/10.3390/en11071721

suitable for low-to-medium power applications, such as LED-driver and desktop computer power 45 supplies. Various kinds of ZVS schemes have been proposed, such as the active-clamp network and 46 asymmetrical half-bridge circuit [11,12]. The active-clamp fly-back converter [13] employs the active 47 clamp network to achieve ZVS operation; however, the voltage stresses on the switches are greater 48 than input voltage which will cause high conduction losses in the power switches. The asymmetrical 49 half-bridge fly-back converter (AHBF) with resonant mode [14-17] was developed to achieve ZVS 50 and reduce the voltage stresses on the switches to less than that of the active-clamp fly-back 51 converter, so the power density and conversion efficiency can be effectively increased. Furthermore, 52 it can operate under changed duty cycles or variable switching frequencies for regulated output 53 voltage. 54

This paper proposes a new single-stage asymmetrical half-bridge fly-back converter with 55 resonant mode. The proposed converter integrates a boost converter and an asymmetrical 56 half-bridge fly-back converter with resonant mode using dual-mode control. The converter 57 intermediate bus voltage can be regulated by the pulse-width-modulation control (PWM). The 58 variable-frequency-controller (VFC) can regulate the converter output voltage. Therefore, this 59 proposed converter can operate in universal input voltage and solves the voltage stress issues 60 throughout the capacitors and switches. The proposed converter utilizes the ZVS technique to 61 decrease the switching losses, resulting in high conversion efficiency. The operational principle for 62 the proposed converter is analyzed, a prototype converter with AC input voltage of 90-264 Vrms and 63 output voltage/current of 19 V/8 A is built to verify the analytical results. 64

2. Circuit Description and Principle Operation of Proposed Converter 65

Figure 1 shows the circuit configuration for the single-stage asymmetrical half-bridge fly-back 66 converter with resonant mode. The primary switches Q1 and Q2 operate at asymmetrical duty ratio. 67 Db1 and Db2 are the anti-paralleled power MOSFETs. The primary side diode Din is a braking diode. 68 The Lboost is a boost-cell inductor. The resonant inductor Lr, resonant capacitor Cr and magnetizing 69 inductor Lm for are the resonant tank for the asymmetrical half-bridge fly-back converter. The 70 secondary diode Dr is a rectifier diode, the Cbus is boost cell output capacitor and CO is the 71 asymmetrical half-bridge fly-back converter output capacitor. 72

Boost AHB LLC

+Vac

–

Cr

Lm CO

+

VO

–

Lboost Din

Q1

Q2

Cbus

n : 1

D1 D2

D3 D4

RO

+Vbus–

Lr Dr

R3

R4VRef

C2 R6

Vbus , feedback

PWM+VFC controller

VO , feedback

R1

R2VRef

C1 R5

QSW

Oscillator

RTCT

Coss2

Db2

Coss1

Db1

73

Figure 1. Schematic of the proposed single-stage asymmetrical half-bridge fly-back converter with resonant 74 mode. 75




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The following assumptions were made to analyze the proposed single-stage asymmetrical 76 half-bridge fly-back converter. 77

− The conduction losses of all switches, diodes and layout traces, and the copper losses of the 78 transformer are neglected. 79

− The turn ratio of the transformer windings is n = N1 / N2. 80

− The resonant inductor Lr is composed of a leakage inductor and external inductor, where 81

Lr = Leakage + Lex. 82

− The conduction times for Q1 are (1-D)Ts and Q2 is DTs, respectively, where D is the duty cycle 83 for Q2, and Ts denotes the switching period. In addition, the dead time is much smaller than 84 that other of conduction times. 85

− In the steady state the bus capacitance Cbus and output capacitance CO are large enough so that 86 the bus voltage Vbus and output voltage VO are a constant value. 87

Both the boost-cell stage and asymmetrical half-bridge fly-back converter stage share the 88 common switches Q1 and Q2, and furthermore there is bus capacitor Cbus between the two stages. The 89 boost-cell stage was presented in [18]. When the switch Q2 is turned on and the switch Q1 is turned 90 off, this results in a positive voltage VLboost = VIN across the inductor Lboost causing a linear increase in 91 the inductor current iLboost. Conversely, when the switch Q1 is turned on and the switch Q2 is turned 92 off, the inductor Lboost is releases energy to the bus capacitor Cbus. Therefore, from the flux-balance of 93 Lboost under the steady-state, Vbus can be determined as 94

2

1 212 2

Lbus

sbus

IN

D RL fV

V

⋅+ ⋅

⋅= +

，

(1) 95

In the DC/DC stage, when the switch Q1 is turned on, the intermediate bus voltage Vbus will 96 charge Cr, Lr and Lm. Conversely, when the switch Q2 is turned on, the secondary diode Dr conducts 97 and Lm is releases energy to the output load. When the asymmetrical half-bridge fly-back converter 98 operates in resonant mode, the voltage transfer ratio can be expressed as 99

( )

( )2

2 2

1 cos1

1 cos11 1 sin

2

rs

O r r

busr

sr

r m s s r ro o s

Df

DnV ZMV D

fDD D DL f f Zn R n R f

ω

ω

ωω

ω ω

− ⋅

− ⋅⋅= =

− ⋅ − − + ⋅ ⋅ + + ⋅

(2) 100

Where 101

1r

r rC Lω =

⋅ (3) 102




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rr

r

LZC

= (4) 103

From equation (2), the voltage transfer ratio of the asymmetrical half-bridge fly-back converter 104 includes relation between the duty ratio D and switching frequency fs simultaneously. Figure 2 105 shows the relation between the duty ratio D, switching frequency fs and voltage transfer ratio. It 106 shows that when the duty-ratio D is decreased from 0.35 to 0.65, to maintain fixed voltage gain, the 107 switching frequency can shift from fc to fa correspondingly. However, Figure 2 also shows that when 108 the switching frequency fs or duty ratio D decreases the voltage gain will be increased. In contrast, 109 when the switching frequency fs or duty ratio D increase, the voltage gain will be decreased. 110

111

Figure 2. Voltage transfer ratio versus normalized switching frequency. 112

From Figure 1, Q2 is the boost-cell stage main switch, therefore the intermediate bus voltage Vbus 113 is regulated by the D to Q2 duty ratio. Unfortunately, changing the D to Q2 duty ratio will affect the 114 asymmetrical half-bridge fly-back converter output voltage. For example, when the D to Q2 duty 115 ratio is increased, the asymmetrical half-bridge fly-back converter output voltage will decrease. 116 Conversely, when the D to Q2 duty ratio is decreased, the asymmetrical half-bridge fly-back 117 converter output voltage will increase. To overcome the change in D to Q2 duty ratio causing 118 unstable asymmetrical half-bridge fly-back converter output voltage, a VFC has been added to the 119 feedback control loop. When the asymmetrical half-bridge fly-back converter output voltage is 120 decreased, the switching frequency fs will decrease to provide larger voltage gain for regulated 121 output voltage. Conversely, when the output voltage is increased, the switching frequency fs will be 122 increased to provide lower voltage gain. According to the above analysis, the intermediate bus 123 voltage Vbus and output voltage VO of the proposed converter can be regulated simultaneously from 124 the PWM control and VFC. 125

Figure 3 depicts the key waveforms of the proposed single-stage asymmetrical half-bridge 126 fly-back converter with resonant mode. Six states are required to complete a switching cycle. The 127 conduction paths for each operating state are illustrated in Figure 4. 128




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Ts

Q2 Q1 Q2 Q1

(1-D) TsD Ts

iLboot

vpri

nVO

DVbus

ir

iLm

iDr

t0 t1 t2t3 t4 t5 t6

vgs

129

Figure 3. Key waveforms of the proposed single-stage asymmetrical half-bridge fly-back converter with 130 resonant mode. 131

State 1: t0<t<t1 132

As shown in Figure 4, Q2 is turned on with the ZVS operating condition. In the meantime the 133 rectifier diode Dr is conducted and the energies stored in the transformer magnetizing inductors are 134 transferred to the output load. The output voltage is reflected to the primary side, therefore, the 135 primary transformer is clamped to –nVO, and iLm decreases linearly. During this period, the resonant 136 inductor Lr and resonant capacitor Cr begin to resonate. On the other hand, the diode Din is 137 conducted and the voltage across the input inductor Lboost is equal to the input voltage VIN so the 138 input inductor current iLboost increases linearly. The input current iLboost can be expressed as 139

( ) ( )0bus

Lboostboost

Vi t t tL

= − (5) 140

The resonant inductor current iLr and the resonant capacitor voltage vCr are given as 141

( ) ( ) ( ) ( ) ( )00 0 0cos sinCr o

Lr Lr r rr

v t nVi t i t t t t t

Zω ω

+ = ⋅ − − ⋅ − (6) 142




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( ) ( ) ( ) ( ) ( )0 0 0 0cos sinCr O Cr O r r Lr rv t nV v t nV t t Z i t t tω ω = + + ⋅ − + ⋅ − (7) 143

The magnetizing current iLm of transformer can be expressed as 144

( ) ( ) ( )00

OLm Lm

m

nV t ti t i t

L−

= − (8) 145

This interval is ended when iLr equals iLm at t1. 146


At time t1 the input inductor current iLboost increases linearly. The resonant inductor current iLr is 148 the same as the magnetizing current iLm therefore, no current is transferred to the secondary side so 149 the rectifier diode Dr is turned off. During this mode, the resonant circuit is composed of Cr, Lr and 150 Lm. Moreover, Lm is equal to series with Lr and Lm is much larger than Lr, so that the resonant cycle is 151 much longer than the previous state. The iLm, iLr and vCr are expressed as 152

( ) ( ) ( ) ( ) ( )1 2 1 2 1 2 1cos sinLr Lr r r r cr ri t i t t t C v t t tω ω ω= ⋅ − − ⋅ − (9) 153

( ) ( ) ( ) ( ) ( )( ) ( )

1 2 1 1 2 2 1

1 2 2 1

cos sin

sinCr Cr r m Lr r r

r Lr r r

v t v t t t L i t t t

L i t t t

ω ω ω

ω ω

= ⋅ − + ⋅ − + ⋅ −

(10) 154

( ) ( )Lm Lri t i t= (11) 155

Where 156

( )21

rr m rC L L

ω =⋅ +

(12) 157

When Q2 is turned off this interval is ended. 158


The mode begins when Q2 is turned off at t = t2. The magnetizing current iLm charges the Q2 160 junction capacitors and discharges the Q1 junction capacitors until the Q2 junction capacitors equal 161 Vbus and the Q1 body diode conducts. Therefore, at time t3, Q1 can be turned on to achieve ZVS. 162 During this period, which is used to allow enough time to achieve ZVS, as well as prevent shoot 163 through in the two switches, the iLr and vCr are expressed as 164

( ) ( ) ( ) ( ) ( )2 1 2 2 1 1 2cos sinLr Lr r r r cr ri t i t t t C v t t tω ω ω= ⋅ − − ⋅ − (13)165

( ) ( ) ( ) ( ) ( )21 2 2 1 2

1sin cosLr

Cr r cr rr r

i tv t t t v t t t

Cω ω

ω= ⋅ − + ⋅ − (14) 166

Where 167




http://dx.doi.org/10.3390/en11071721

( ) ( )11

||r

m r eq rL L C Cω =

+ ⋅, 1 2 1 2;oss oss eq oss ossC C C C C= = = (15) 168

The input current iLboost can be expressed as 169

( ) ( )2IN bus

Lboostboost

V Vi t t tL

−= − − (16) 170


In this state, Q1 is turned on which carries the resonant inductor current iLr and input inductor 172 current iLboost. The voltage across the input inductor Lboost is about (VIN－Vbus) so the input inductor 173 current iLboost linearly decreasing. Referring to Figure 4(d), the rectifier diode Dr is reverse-biased and 174 in the meantime the input energy is stored in the primary magnetizing inductance Lm, while the 175 output capacitors CO provide energy to the output load. The resonant inductor current iLr, 176 magnetizing inductance current iLm and resonant capacitors voltage vCr can be expressed as 177

( ) ( ) ( ) ( )( ) ( )

3 2 3 2 2 3

2 3 2 3

cos sin

sinLr Lr r r r bus r

r r cr r

i t i t t t C v t t

C v t t t

ω ω ω

ω ω

= ⋅ − + ⋅ − − ⋅ −

(17) 178

( ) ( ) ( ) ( ) ( )( ) ( )

3 3 2 3 2 2 3

2 3 2 3

cos sin

sinCr cr Lr r r r bus r

r r cr r

v t v t i t t t C v t t

C v t t t

ω ω ω

ω ω

= + ⋅ − + ⋅ − − ⋅ −

(18) 179

( ) ( )Lm Lri t i t= (19) 180

The input current iLboost are given as 181

( ) ( )3IN bus

Lboostboost

V Vi t t tL

−= − − (20) 182

When input current iLboost reach zero level, this interval is ended. 183


During this stage, Q1 remains turned on so that the direction of iLr is reversed. As with Stage 4 185 the primary magnetizing inductance Lm stores energy and the output capacitors CO continue to 186 provide energy through the output load. The current in Lboost stays at zero (DCM operation) so the 187 PFC feature can be achieved. In the meantime, diode Din is in reverse bias. The resonant inductor 188 current iLr, magnetizing inductance current iLm and the resonant capacitor voltage vCr are given as

189

( ) ( ) ( ) ( )( ) ( )

4 2 4 2 2 4

2 4 2 4

cos sin

sinLr Lr r r r bus r

r r cr r

i t i t t t C v t t

C v t t t

ω ω ω

ω ω

= ⋅ − + ⋅ − − ⋅ −

(21) 190

( ) ( ) ( ) ( ) ( )( ) ( )

4 4 2 4 2 2 4

2 4 2 4

cos sin

sinCr cr Lr r r r bus r

r r cr r

v t v t i t t t C v t t

C v t t t

ω ω ω

ω ω

= + ⋅ − + ⋅ − − ⋅ −

(22) 191




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( ) ( )Lm Lri t i t= (23) 192

where 193

( )21

rr m rC L L

ω =⋅ +

(24) 194

When Q1 turned off, this interval is ended. 195


In this stage, Q1 and Q2 are turned off and the input current iLboost remains at zero, while the 197 output capacitors continue to provide energy through the output load. At this interval, the resonant 198 current iLr charges the Q1 junction capacitors and discharges the Q2 junction capacitors. When Q1 199 equals Vbus and the body diode across Q2 conducts, this interval is ended and the operating state 200 returns to Stage 1 to begin the next switching cycle. The resonant inductor current iLr, magnetizing 201 inductance current iLm and resonant capacitor voltage vCr can be expressed as 202

( ) ( ) ( ) ( ) ( )5 1 5 1 5 1 5cos sinLr Lr r r r Cr ri t i t t t C v t t tω ω ω = ⋅ − + ⋅ − (25) 203

( ) ( ) ( ) ( ) ( )51 5 5 2 5

1sin cosLr

Cr r Cr rr r

I tv t t t v t t t

Cω ω

ω = ⋅ − + ⋅ − (26) 204

( ) ( )Lm Lri t i t= (27) 205

When Stage 6 ends the operating state returns to Stage 1 and the next switching cycle begins. 206


In this stage, Q1 and Q2 are turned off and the input current iLboost remains at zero, while the 208 output capacitors continue to provide energy through the output load. At this interval, the resonant 209 current iLr charges the Q1 junction capacitors and discharges the Q2 junction capacitors. When Q1 210 equals Vbus and the body diode across Q2 conducts, this interval is ended and the operating state 211 returns to Stage 1 to begin the next switching cycle. The resonant inductor current iLr, magnetizing 212 inductance current iLm and resonant capacitor voltage vCr can be expressed as 213

( ) ( ) ( ) ( ) ( )5 1 5 1 5 1 5cos sinLr Lr r r r Cr ri t i t t t C v t t tω ω ω = ⋅ − + ⋅ − (28) 214

( ) ( ) ( ) ( ) ( )51 5 5 2 5

1sin cosLr

Cr r Cr rr r

I tv t t t v t t t

Cω ω

ω = ⋅ − + ⋅ − (29) 215

( ) ( )Lm Lri t i t= (30) 216

When Stage 6 ends the operating state returns to Stage 1 and the next switching cycle begins. 217




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+Vac

–

Cr

Lm CO

+

VO

–

Lboost Din

Q1

Q2

Cbus

n : 1

RO

+Vbus

–LrVIN

iLboost iLr

iLm

iDrip

+VDS2

–

iQ2

Coss2Db2

+ vCr–

iOCoss1Db1 Dr

+

vpri

–

218

(a) 219

+Vac

–

Cr

Lm CO

+

VO

–

Lboost Din

Q1

Q2

Cbus

n : 1

RO

+Vbus

–LrVIN

iLboost iLr

iLm

ip

+VDS2

–

iQ2

Coss2Db2

+ vCr–

iOCoss1Db1 Dr iDr

+

vpri

–

220

(b) 221

+Vac

–

Cr

Lm CO

+

VO

–

Lboost Din

Q1

Q2

Cbus

n : 1

RO

+Vbus

–LrVIN

iLboost iLr

iLm

ip

+VDS2

–

iQ2

Coss2Db2

+ vCr–

iOCoss1Db1

iQ1Dr iDr

+

vpri

–

222

(c) 223

+Vac

–

Cr

Lm

+

VO

–

Lboost Din

Q1

Q2

Cbus

+Vbus

–LrVIN

iLboost iLr

iLm

ip

+VDS2

–

iQ2

Coss2Db2

+ vCr–

iOCoss1Db1

iQ1Dr iDr

CO RO

+

vpri

–

224 (d) 225




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+Vac

–

Cr

Lm

+

VO

–

Lboost Din

Q1

Q2

Cbus

n : 1

+Vbus

–LrVIN

iLboost iLr

iLm

ip

+VDS2

–

iQ2

Coss2Db2

+ vCr–

iOCoss1Db1

iQ1

CO RO

Dr iDr

+

vpri

–

226 (e) 227

+Vac

–

Cr

Lm

Lboost Din

Q1

Q2

Cbus

n : 1

+Vbus

–LrVIN

iLboost iLr

iLm

ip

+VDS2

–

iQ2

Coss2Db2

+ vCr–

Coss1Db1iQ1

+

VO

–

iO

CO RO

Dr iDr

+

vpri

–

228 (f) 229

Figure 4. Operation Modes of the proposed single-stage asymmetrical half-bridge fly-back converter during 230 one switching period: (a) State 1; (b) State 2; (c) State 3; (d) State 4; (e) State 5; (f) State 6. 231

3. Circuit Design for the Proposed Converter 232

Dmax is the maximum duty cycle for the proposed converter. For to achieve high power-factor 233 the input inductor current must be operated in DCM so the input inductor Lboost can be expressed as 234

( )2max max

_ peak _ min( ) 1

2bus s

boosIN s

V TL D Di f

< ⋅ ⋅ −⋅

(31) 235

Where iIN_peak is the maximum peak-current of the input inductor Lboost, and fs_min is the lowest 236 switching frequency for the proposed converter. From equation (28), when Lm is greater than the 237 resonant inductor Lr, the voltage gain can be approximated as 238

( )1 1O busV V Dn

= ⋅ − (32) 239

Therefore, the turn ratio of the transformer primary winding to secondary winding can be equal to 240

( )1bus

O

Vn DV

= ⋅ − (33) 241

At t = t3, to ensure the ZVS operation for Q1, the magnetizing inductance current iLm must discharge 242 the Coss1 until the voltage is equal to zero so the minimum iLm at t3 can be given as 243




http://dx.doi.org/10.3390/en11071721

( )3 min_ min 2O

sLm tm

nVi D TL

= ⋅ (34) 244

According to equation (31), the maximum magnetizing inductance Lm can be expressed as 245

( ) ( )3 min_ max1 22

O deadm t

bus oss oss s

nV tL DV C C f

⋅= ⋅⋅ + ⋅

(35) 246

On the other hand, at t = t6, to ensure ZVS operation for Q2, the magnetizing inductance current 247 iLm must discharge Coss2 until the voltage is equal to zero so the minimum iLm at t6 can be given as 248

( )6 max_ min (1 )2

OLm t

m s

nVi DL f

= ⋅ −⋅ ⋅

(36) 249

According to equation (33), the maximum magnetizing inductance Lm can be expressed as 250

( ) ( )6 max_ max1 2

(1 )2

O deadm t

bus oss oss s

nV tL DV C C f

⋅= ⋅ −⋅ + ⋅

(37) 251

Form Figure 3a, the resonant capacitor Cr and the resonant inductor Lr are resonating from t0 to 252 t1, this time interval is during the Q2 turn-on time, which is about half the resonant period and can be 253 approximately expressed as 254

2max2r

rr

D

CL

ω ⋅ ≤ (38) 255

The output filter capacitance CO can be calculated as 256

( )max1O

OO

O s

P DVC

V f

⋅ −≥

Δ ⋅ (39) 257

Where fs is the switching frequency and △VO is the output voltage ripple. The voltage stresses of Q1 258 and Q2 are equal to Vbus. The voltage stresses of the secondary diode Dr is 259

max busr O

D VD Vn⋅= + (40) 260

The peak secondary diode current is expressed as 261

( ),maxmax2 1Dr OI I

Dπ= ⋅

⋅ − (41) 262

263

264




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4. Experimental Results 265

In order to verify the feasibility of the proposed converter, a 120 W prototype converter is built 266 in the laboratory. Figure 5. shows the proposed converter and the experimental parameters are 267 designed in Table 1. 268

+Vac–

40 nF

450 µH

+

VO

–

F20L60330 µF/420 V

10 : 1

RO

100 µH STPS41L60C

IPP60R99

IPP60R99

200 µH

B20XD60 1200 µF/50 V 269

Figure 5. Implementation of the proposed single-stage asymmetrical half-bridge fly-back converter with 270 resonant mode. 271

Table 1. Experimental parameters of the proposed converter. 272

Parameters Value

Input ac voltage range: 85~264 Vrms

Output voltage: VO = 19 V

Output voltage ripple: △VO = 0.95 V

Intermediate bus voltage: Vbus=420 V

Maximum output current: IO = 6.32 A

Input inductor: Lboost = 200 µH

Magnetizing inductance: Lm = 450 µH

Turns ratio: n = Np/Ns = 3T

Resonant inductor: Lr = 100 µH

Maximum duty cycle: Dmax = 0.75

Resonant capacitors: Cr = 40 nF

Switching frequency: fs = 60~150 kHz

Output capacitor: CO = 1200 µF

A PQ26/20 TDK core is used for the input inductor. The PQ32/30 core is used for the isolation 273 transformer and the transformer turn ratio is calculated from (29). The magnetizing inductance Lm is 274 designed from (32) at approximately 450 µH. The IPP60R99 MOSFET is used producing output 275 capacitance COSS of about 130 pF at a 430 V drain-to-source voltage, including the output 276 capacitances of Q1 and Q2 it is about 260 pF. Therefore, to ensure ZVS operations, 330 ns dead time 277 was inserted between the Q1 and Q2 gate signals. The resonant frequency fr is placed at about 80 kHz 278 so the resonant capacitor Cr and resonant inductor Lr can be calculated from (35). The output voltage 279




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ripple △VO is required to be smaller than 0.95 V. The output capacitor CO is calculated to be greater 280 than 474 µF from equation (36). Therefore, a 1200 µF output capacitor is used. 281

Figure 6 shows the experimental results for vGS1, vGS2, iLboost and iLr at different output currents 282 and at VIn,main. Referring to Figure 3, six operation states can be observed in Figure 6. When Q1 is 283 turned on and Q2 is turned off, the iLboost linearly decreases and iLr linearly increases. When Q1 and Q2 284 are turned off, ZVS operation can be achieved. During the Q1 turned off and Q2 turned on period, the 285 iLboost increases linearly and the resonant inductor Lr and resonant capacitor begin to resonate. On the 286 other hand, Figure 6 also shows that when the output load increases from light load to full load, the 287 duty ratio of Q2 increases from 0.5 to 0.75 for regulated bus voltage Vbus, and the switching frequency 288 decreases from about 125 kHz to 62 kHz for regulated output voltage VO. Figure 7 shows the 289 measured input voltage vac, input current iac and input inductor current iLboost under full load 290 conditions. The input current near sinusoidal waveform and input inductor current are shown 291 operated in DCM so that high power factor can be achieved. 292

293

(a) 294

295

(b) 296




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297

(c) 298

299

(d) 300

Figure 6. Waveforms for vGS1, vGS2, iLboost and iLr at different load current: (a) 1.6 A; (b) 3.2 A; (c) 4.7 A; (d) 6.3 A. 301




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302

Figure 7. Waveforms for vac, iac and iLboost at vac = 230 Vrms . 303

Figure 8 shows the gate-to-source waveforms and drain-to-source voltages for primary 304 switches Q1 and Q2 at the full-load. The waveform shows that VDS1 and VDS2 reach zero levels after Q1 305 and Q2 are turned on. Therefore, ZVS conduction is achieved so that overall conversion efficiency is 306 increased. The transient output voltage VO during a step load current from 1.6 to 6.3 A and 6.3 to 1.6 307 A are shown in Figure 8 when input voltage of 230 Vrms, which shows that VO can still be regulated. 308 Figure 10 depicts the bus voltage variation under 25%, 50%, 75% and 100% load condition and the 309 bus voltage is regulated around 430 V. Figure 11 also depicts the input current power factor. It 310 indicates that the power factor is greater than 0.9 at different load conditions. Figure 12 shows the 311 measured efficiencies of the proposed single stage asymmetrical half-bridge fly-back converter 312 through different outputs. The average efficiency is around 86% above which the rated full load 313 efficiency is about 90%. 314 315

316

Figure 8. Zero-voltage turn-on switching for Q1 and Q2. 317




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318

(a) 319

320

(b) 321

Figure 9. Load transient response under different loads: (a) 20% to 100%; (b) 100% to 20%. 322




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415

420

425

430

435

440

445

450

25% 50% 7 5% 100%

V b us Vo lta ge115 Vrms 230 Vrms

Po 323

Figure 10. Vbus voltage variation curve for 115 Vrms and 230 Vrms. 324

0.8

0.85

0.9

0.95

1

25% 50% 75% 100%

PF115 Vrms 230 Vrms

Po

325

Figure 11. PF curve for 115 Vrms and 230 Vrms. 326 327




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70

75

80

85

90

95

2 5 % 5 0 % 7 5 % 1 0 0 %

Eff ic ie ncy115 Vrms 230 Vrms

328

Figure 12. Efficiency curve for 115 Vrms and 230 Vrms 329

5. Conclusions 330

This paper presented a single stage asymmetrical half-bridge fly-back converter with resonant 331 mode. The switches operate simultaneously in the variable-frequency-controller (VFC) and 332 pulse-width-modulation (PWM) control to regulate the bus voltage and output voltage. The 333 operating modes in a complete switching cycle were analyzed and discussed in detail. The key 334 equations were derived and the design procedures formulated. The experimental results on an AC 335 input voltage 90 to 264 Vrms with output 120 W prototype were recorded to verify the theoretical 336 scheme. The measured results show that the power factor is above 0.9, the average efficiency is 337 around 86% and the highest conversion efficiency is about 90%. The proposed single stage 338 asymmetrical half-bridge fly-back converter is especially suitable for low-to-medium power level 339 applications. 340 Author Contributions: Chung-Yi Ting designed, simulated the work, and wrote the paper; Yi-Chieh Hsu 341 implemented the work and performed the experiment; Jing-Yuan Lin and Chung-ping Chen provided all 342 material for implementing the work, supervised the design, circuit simulation, analysis, experiment, and 343 correct the paper. 344 Acknowledgments: The authors would like to acknowledge the financial support of the Ministry of Science 345 and Technology of Taiwan through grant number MOST 106-2221-E-011-095-MY3. 346 Conflicts of Interest: The authors declare no conflict of interest. 347 348 References 349 1. Qian, J.; Lee, F.C. A high-efficiency single-stage single-switch high-power-factor AC/DC converter with 350

universal input. IEEE Trans. Power Electron. 1998, 13, 699-705. [CrossRef] 351 2. Kang, F.S.; Park, S.J.; Kim, C.U. ZVZCS single-stage PFC AC-to-DC half-bridge converter. IEEE Trans. 352

Industrial Electron. 2002, 49, 206-216. [CrossRef] 353 3. Zhang, J.; Lee, F.C.; Jovanovic, M.M. An improved CCM single-stage PFC converter with a low frequency 354

auxiliary switch. IEEE Trans. Power Electron. 2003, 18, 44-50. [CrossRef] 355




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4. Ogata, M.; Nishi, T. Graph-theoretical approach to 2-switch DC-DC converter. International Journal of 356 Circuit Theory and Applications. 2005, 33, 161-173. [CrossRef] 357

5. O'Sullivan, D. L.; Egan, M.G.; Willers, M. J. A Family of Single-Stage Resonant AC/DC Converters with 358 PFC. IEEE Trans. Power Electron. 2009, 24, 398-408. [CrossRef] 359

6. Willers, M.J.; Egan, M.G.; Daly, S.; Murphy, J.M.D. Analysis and design of a practical 360 discontinuous-conduction-mode BIFRED converter. IEEE Trans. Industrial Electron. 1999, 46, 724-733. 361 [CrossRef] 362

7. Shu, Y.; Lin, B.T. Add active clamping and soft switching to boost flyback single stage isolated power 363 factor corrected power supplies. IEEE Trans. Power Electron. 2011, 26, 3144-3152. [CrossRef] 364

8. Chen, S.Y.; Li, Z.R.; Chen, C. L. Analysis and Design of single stage AC/DC LLC resonant converter. IEEE 365 Trans. Industrial Electron. 2012, 59, 1538-1544. [CrossRef] 366

9. Luo, S.; Wei, H.; Zhu, G.; Batarseh, I. Several schemes of alleviating bus voltage stress in single stage 367 power factor correction converters. In Proceedings Power Electronics and Drive Systems Conference, Hong 368 Kong, 27-29 July 1999; pp. 921-926. 369

10. Wu, X.; Yang, J.; Zhang, J.; Xu, M. Design Considerations of Soft-Switched Buck PFC Converter with 370 Constant On-Time (COT) Control. IEEE Trans. Power Electron. 2011, 26, 3144-3152. [CrossRef] 371

11. Wu, X.; Zhang, J.; Ye X.; Qian, Z. Analysis and Derivations for a Family ZVS Converter Based on a New 372 Active Clamp ZVS Cell. IEEE Trans. Industrial Electron. 2008, 55, 773-781. [CrossRef] 373

12. Choi, B.; Lim, W.; Bang, S.; Choi, S. Small-signal analysis and control design of asymmetrical half-bridge 374 DC-DC converters. IEEE Trans. Industrial Electron. 2006, 53, 511-520. [CrossRef] 375

13. Watson, R.; Hua, G.C.; Lee, F.C. Characterization of an active clamp flyback topology for power factor 376 correction applications. IEEE Trans. Power Electron. 1996, 11, 191-198. [CrossRef] 377

14. Kim, K.T.; Kwon, J.M.; Lee, H.M.; Kwon, B.H. Single-stage high-power factor half-bridge flyback 378 converter with synchronous rectifier. IET Trans. Power Electron. 2014, 7, 1755-4535. [CrossRef] 379

15. Buso, S.; Spiazzi, G.; Sichirollo, F. Study of the asymmetrical half-bridge flyback converter as an effective 380 line fed solid state lamp driver. IEEE Trans. Industrial Electron. 2014, 61, 6730-6738. [CrossRef] 381

16. Song, W.; Zhong, Y.; Zhang, H.; Sun, X.; Zhang, Q.; Wang, W. A Study of Z-Source Dual-Bridge Matrix 382 Converter Immune to Abnormal Input Voltage Disturbance and with High Voltage Transfer Ratio. IEEE 383 Trans. Industrial Informat. 2013, 9, 828-838. [CrossRef] 384

17. Li, H.; Zhou, W.; Zhou, S.; Yi, X. Analysis and design of high frequency asymmetrical half bridge flyback 385 converter. Electrical Machines and Systems International Conference, Wuhan, China, 17-20 October 2008; 386 pp. 1902-1904. 387

18. Tse, C.K.; Chow, M.H.L. New single-stage power-factor-corrected regulators operating in discontinuous 388 capacitor voltage mode. In Proceedings of the 28th IEEE Power Electronics Specialists Conference, Saint 389 Louis, MO, USA, 27-27 June 1997; pp. 371-377. 390




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A Single-Stage Asymmetrical Half-Bridge Flyback Converter