9
860 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012 Asymmetrical Full-bridge Converter With High-Voltage Gain Hyun-Lark Do Abstract—This paper proposes an asymmetrical full-bridge con- verter with high-voltage gain. The control of the proposed con- verter is implemented with the asymmetrical pulsewidth modu- lation technique. The proposed converter achieves zero-voltage switching (ZVS) of all power switches. Zero-current switching (ZCS) of output diodes is also achieved. The proposed converter can provide high-voltage gain and the voltages across the semi- conductor devices are effectively clamped. Steady-state analysis of the proposed converter is presented. A laboratory prototype of the proposed converter is developed, and its experimental results are presented for validation. Index Terms—DC–DC converter, high-voltage gain, soft switching, zero-voltage switching (ZVS), zero-current switching (ZCS). I. INTRODUCTION H IGH-EFFICIENCY dc–dc converters with high-voltage gain have been researched due to increasing demands. They are required as an interface system between the low- voltage sources and the load which requires higher voltage in many applications such as electric vehicles, uninterruptible power supplies, fuel cells, and photovoltaic systems [1]–[7]. A conventional boost converter is often used in step-up applica- tions due to its simple structure and low cost. However, it is not suitable for high step-up applications. This is because the conventional boost converter requires an extreme duty cycle to obtain high-voltage gain and its voltage gain is limited due to its parasitic components [8]. Also, the severe reverse-recovery problem of the output diodes degrades system performance such as efficiency and electromagnetic noises. In order to remedy these problems, high step-up dc–dc con- verters using coupled inductors have been suggested in [9] and [10]. However, they have parasitic oscillations across the switches and diodes due to a resonance between the leakage inductance of a coupled inductor and parasitic capacitances of the semiconductor devices. Also, the galvanic isolation between the input and output stages of the power converters needs to be provided to meet safety standards Manuscript received March 24, 2011; revised May 25, 2011; accepted July 4, 2011. Date of current version January 9, 2012. Recommended for publication by Associate Editor M. Vitelli. The author is with the Department of Electronic and Information Engineering, Seoul National University of Science and Technology, Seoul 139-743, Korea (e-mail: hldo@ snut.ac.kr). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2011.2161777 The current-fed converters are often used in high step-up ap- plications due to their inherent low input current ripple charac- teristic and high-voltage gain [11], [12]. However, in the current- fed converters, the voltage stresses of the switches are serious. In order to clamp the voltages across the switches and provide zero-voltage switching (ZVS) features, active snubbers are often employed. The snubbers require additional switches and cause additional conduction losses. As a result, the system efficiency decreases. On the other hand, the voltage-fed converters such as phase-shift full-bridge (PSFB) converters, which are widely used, show low-voltage stress of the switching devices. PSFB converters feature fixed switching frequency and ZVS of power switches. However, they have some drawbacks including large conduction loss due to circulating current, duty cycle loss, and the voltage spikes across output rectifiers. The large voltage spikes of the output rectifiers are serious problems especially in high-voltage applications. To remedy these problems, many topologies have been proposed in [13]–[18]. In some of them, auxiliary snubber circuits are employed to suppress the voltage spikes at the secondary side. However, the complexity and the overall cost are increased while the system efficiency decreases due to the additional circuits. The asymmetrical pulsewidth modulation (APWM) tech- nique was introduced in [19]. The APWM technique has var- ious advantages such as zero switching loss, no conduction loss penalty, and fixed switching frequency. In [19], full-bridge and half-bridge converters with APWM control were suggested. Their main drawback is that the maximum duty cycle is limited to 0.5 and a large turn ratio of a transformer is required to ob- tain high-voltage gain. Modified APWM control scheme for the asymmetrical full-bridge converter was proposed in [20]. And new asymmetrical full-bridge converter was proposed in [21]. Without considering the transformer turn ratio, the converters in [20] and [21] are buck-type converters. Therefore, they are not suitable for high step-up applications. In order to overcome these problems, an asymmetrical full- bridge converter with high-voltage gain is proposed and shown in Fig. 1. The APWM technique is applied to the proposed converter to eliminate switching losses and maintain low con- duction loss. The limitation of the maximum duty cycle disap- pears in the proposed topology. The proposed converter features high-voltage gain, fixed switching frequency, soft-switching op- erations of all power switches and output diodes, and clamped voltages across power switches and output diodes. The reverse- recovery problem of the output diodes is significantly alleviated due to an additional inductor at the secondary side. Therefore, the proposed converter shows high efficiency and it is suitable for high-voltage applications. 0885-8993/$26.00 © 2011 IEEE

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Page 1: Asymmetrical Full-Bridge Converter

860 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012

Asymmetrical Full-bridge ConverterWith High-Voltage Gain

Hyun-Lark Do

Abstract—This paper proposes an asymmetrical full-bridge con-verter with high-voltage gain. The control of the proposed con-verter is implemented with the asymmetrical pulsewidth modu-lation technique. The proposed converter achieves zero-voltageswitching (ZVS) of all power switches. Zero-current switching(ZCS) of output diodes is also achieved. The proposed convertercan provide high-voltage gain and the voltages across the semi-conductor devices are effectively clamped. Steady-state analysis ofthe proposed converter is presented. A laboratory prototype of theproposed converter is developed, and its experimental results arepresented for validation.

Index Terms—DC–DC converter, high-voltage gain, softswitching, zero-voltage switching (ZVS), zero-current switching(ZCS).

I. INTRODUCTION

H IGH-EFFICIENCY dc–dc converters with high-voltagegain have been researched due to increasing demands.

They are required as an interface system between the low-voltage sources and the load which requires higher voltagein many applications such as electric vehicles, uninterruptiblepower supplies, fuel cells, and photovoltaic systems [1]–[7]. Aconventional boost converter is often used in step-up applica-tions due to its simple structure and low cost. However, it isnot suitable for high step-up applications. This is because theconventional boost converter requires an extreme duty cycle toobtain high-voltage gain and its voltage gain is limited due toits parasitic components [8]. Also, the severe reverse-recoveryproblem of the output diodes degrades system performance suchas efficiency and electromagnetic noises.

In order to remedy these problems, high step-up dc–dc con-verters using coupled inductors have been suggested in [9]and [10]. However, they have parasitic oscillations across theswitches and diodes due to a resonance between the leakageinductance of a coupled inductor and parasitic capacitances ofthe semiconductor devices. Also, the galvanic isolation betweenthe input and output stages of the power converters needs to beprovided to meet safety standards

Manuscript received March 24, 2011; revised May 25, 2011; accepted July 4,2011. Date of current version January 9, 2012. Recommended for publicationby Associate Editor M. Vitelli.

The author is with the Department of Electronic and Information Engineering,Seoul National University of Science and Technology, Seoul 139-743, Korea(e-mail: hldo@ snut.ac.kr).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2011.2161777

The current-fed converters are often used in high step-up ap-plications due to their inherent low input current ripple charac-teristic and high-voltage gain [11], [12]. However, in the current-fed converters, the voltage stresses of the switches are serious.In order to clamp the voltages across the switches and providezero-voltage switching (ZVS) features, active snubbers are oftenemployed. The snubbers require additional switches and causeadditional conduction losses. As a result, the system efficiencydecreases. On the other hand, the voltage-fed converters suchas phase-shift full-bridge (PSFB) converters, which are widelyused, show low-voltage stress of the switching devices. PSFBconverters feature fixed switching frequency and ZVS of powerswitches. However, they have some drawbacks including largeconduction loss due to circulating current, duty cycle loss, andthe voltage spikes across output rectifiers. The large voltagespikes of the output rectifiers are serious problems especiallyin high-voltage applications. To remedy these problems, manytopologies have been proposed in [13]–[18]. In some of them,auxiliary snubber circuits are employed to suppress the voltagespikes at the secondary side. However, the complexity and theoverall cost are increased while the system efficiency decreasesdue to the additional circuits.

The asymmetrical pulsewidth modulation (APWM) tech-nique was introduced in [19]. The APWM technique has var-ious advantages such as zero switching loss, no conductionloss penalty, and fixed switching frequency. In [19], full-bridgeand half-bridge converters with APWM control were suggested.Their main drawback is that the maximum duty cycle is limitedto 0.5 and a large turn ratio of a transformer is required to ob-tain high-voltage gain. Modified APWM control scheme for theasymmetrical full-bridge converter was proposed in [20]. Andnew asymmetrical full-bridge converter was proposed in [21].Without considering the transformer turn ratio, the convertersin [20] and [21] are buck-type converters. Therefore, they arenot suitable for high step-up applications.

In order to overcome these problems, an asymmetrical full-bridge converter with high-voltage gain is proposed and shownin Fig. 1. The APWM technique is applied to the proposedconverter to eliminate switching losses and maintain low con-duction loss. The limitation of the maximum duty cycle disap-pears in the proposed topology. The proposed converter featureshigh-voltage gain, fixed switching frequency, soft-switching op-erations of all power switches and output diodes, and clampedvoltages across power switches and output diodes. The reverse-recovery problem of the output diodes is significantly alleviateddue to an additional inductor at the secondary side. Therefore,the proposed converter shows high efficiency and it is suitablefor high-voltage applications.

0885-8993/$26.00 © 2011 IEEE

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Fig. 1. Circuit diagram of the proposed converter.

Fig. 2. Equivalent circuit of the proposed converter.

II. PRINCIPLE OF OPERATION

A. Circuit Description

Fig. 1 shows the circuit diagram of the proposed converterwith high-voltage gain. The proposed converter has four powerswitches S1 through S4 . There is also the clamping capacitorCc between top side switches S1 and S3 of two switch bridges.The voltages across the switches S1 and S2 in the first bridge areconfined to the input voltage Vin . The clamping capacitor Cc canclamp the voltages across the switches S3 and S4 in the secondbridge. The output stage of the proposed converter has a voltagedoubler structure that consists of the secondary winding N2 ofthe transformer T, the serial inductor Ls , the output capacitorsCo 1 , and Co 2 , and the output diodes Do 1 and Do2 . Accordingto the voltage doubler structure, the voltage gain increases andthe voltage stresses of the output diodes are confined to theoutput voltage Vo without any auxiliary circuits. The equivalentcircuit of the proposed converter is shown in Fig. 2. The diodesD1 through D4 are the intrinsic body diodes of all switches.The capacitors C1 through C4 represent their parasitic outputcapacitances. The transformer T is modeled as the magnetizinginductance Lm and the ideal transformer that has a turn ratioof 1:n (n = N2 /N1). Its leakage inductance is included in the

serial inductor Ls . To simplify the analysis, it is assumed thatthe clamping capacitor Cc has a large value and the voltageacross Cc is constant as Vc under a steady state. Similarly, theoutput capacitor voltages are assumed to be constant as Vo1 andVo2 , respectively. The theoretical waveforms of the proposedconverter are shown in Fig. 3. The switch S1(S4) and the switchS2(S3) are operated asymmetrically and the duty cycle D is basedon the switch S1(S4). A small delay between driving signals forS1(S4) and S2(S3) is a deadtime for the switches. It preventscross conduction and allows ZVS.

B. Modal Analysis

The operation of the proposed converter during a switchingperiod Ts is divided into four modes as shown in Fig. 4. Before t0 ,the switches S2 and S3 , and the output diode Do 1 are conducting.At t0 , the magnetizing current im and the secondary current isarrive at their minimum values Im 2 and −IDo1 , respectively.

Mode 1 [t0 , t1]: At t0 , the switches S2 and S3 are turnedOFF. Then, the energy stored in the magnetic components startsto charge/discharge the parasitic capacitances C1 through C4 .Therefore, the voltages vS 2 and vS 3 start to rise from zero.Similarly, the voltage vS 4 starts to fall from Vin + Vc and the

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862 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012

Fig. 3. Theoretical waveforms.

voltage vS 1 starts to fall from Vin . Since all the parasitic outputcapacitances C1 through C4 are very small, this transition timeinterval is very short and it is ignored in Fig. 3. When the voltagesvS 1 and vS 4 arrive at zero, their body diodes D1 and D4 areturned ON. Then, the gate signals are applied to the switches S1and S4 . Since the currents have already flown through D1 andD4 and the voltages vS 1 and vS 4 are clamped as zero beforethe switches S1 and S4 are turned ON, zero-voltage turn-ONof S1 and S4 is achieved. With the turn-ON of S1 and S4 , theprimary voltage vp across Lm is Vin . Then, the magnetizingcurrent im increases linearly from its minimum value Im 2 asfollows:

im (t) = Im2 +Vin

Lm(t − t0) . (1)

Since the voltage vLs across Ls is nVin+Vo 1 , the secondarycurrent is increases from its minimum value −IDo1 as follows:

is(t) = −IDo1 +nVin + Vo1

Ls(t − t0) . (2)

In this mode, the switch currents iS 1 and iS 4 can be writtenby

iS1(t) = iS4(t) = Im2 − nIDo1

+(

Vin

Lm+

n (nVin + Vo1)Ls

)(t − t0) . (3)

Mode 2 [t1 , t2]: At t1 , the currents is and iDo1 arrive at zeroand the diode Do 1 is turned OFF. Then, the output diode Do2 isturned ON and its current increases linearly. Since the currentchanging rate of Do 1 is controlled by the serial inductor Ls , its

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Fig. 4. Operating Modes.

reverse-recovery problem is significantly alleviated. Since thevoltage vLs is (nVin−Vo 2) in this mode, the current is are givenby

is(t) =nVin − Vo2

Ls(t − t1) . (4)

Since the voltage vp is not changed in this mode, (1) is stilleffective. In this mode, the switch current iS 1 and iS 4 can bewritten by

iS1(t)= iS4(t)= im (t1) +(

Vin

Lm+

n (nVin − Vo2)Ls

)(t − t1) .

(5)At the end of this mode, the currents im and is arrive at theirmaximum values Im 1 and IDo2 , respectively.

Mode 3 [t2 , t3]: Similar to mode 1, the switches S1 and S4 areturned OFF at t2 . The parasitic capacitors C1 and C4 start to be

charged from zero, whereas the parasitic capacitors C2 and C3start to be discharged from Vin and Vin + Vc , respectively. Withthe same assumption as mode 1, this transition time intervalis very short and it is ignored in Fig. 3. After the parasiticcapacitors are fully charged and discharged, the voltages vS 2and vS 3 become zero and the body diodes D2 and D3 are turnedON. Then, the gate signals are applied to the switches S2 andS3 . Since the currents have already flown through D2 and D3and the voltages vS 2 and vS 3 are clamped as zero, zero-voltageturn-ON of S2 and S3 is achieved. With the turn-ON of S2 andS3 , the voltage vp across Lm is −(Vin+Vc ). Then, the currentim decreases linearly from its maximum value Im 1 as follows:

im (t) = Im1 −Vin + Vc

Lm(t − t2) . (6)

Since the voltage vLs across Ls is −(n(Vin + Vc ) +Vo2), thecurrent is decreases from its maximum value IDo2 as follows:

is(t) = IDo2 −n (Vin + Vc) + Vo2

Ls(t − t2) . (7)

In this mode, the switch currents iS 2 and iS 3 can be writtenby

iS2(t) = iS3(t) = −Im1 − nIDo2

+(

(Vin + Vc)Lm

+n (n (Vin + Vc) + Vo2)

Ls

)(t − t2) .

(8)

Mode 4 [t3 , t4]: Similar to mode 2, the currents is and iDo2arrive at zero and the diode Do 2 is turned OFF at t3 . Then, theoutput diode Do1 is turned ON and its current increases linearly.Since the current changing rate of Do2 is controlled by Ls , itsreverse-recovery problem is significantly alleviated. Since thevoltage vLs is −(n(Vin + Vc )−Vo1), the current is is given by

is(t) = −n (Vin + Vc) − Vo1

Ls(t − t3) . (9)

Since the voltage vp is not changed in this mode, (6) is stilleffective. In this mode, the switch currents iS 2 and iS 3 can bewritten by

iS2(t) = iS3(t) = −im (t3)

+(

(Vin + Vc)Lm

+n (n (Vin + Vc) − Vo1)

Ls

)(t − t3) .

(10)

At the end of this mode, the currents im and is arrive at Im 2and −IDo1 , respectively.

III. DESIGN PARAMETERS

A. Clamping Capacitor Voltage Vc

Referring to the voltage waveform vp in Fig. 3, the volt-secondbalance law gives

VinDTs − (Vin + Vc)(1 − D)Ts = 0. (11)

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864 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012

From (11), the clamping capacitor voltage Vc is obtained by

Vc =2D − 11 − D

Vin . (12)

B. Voltage Gain

From (2) and (9), the maximum diode current IDo1 can bewritten as follows:

IDo1 =nVin + Vo1

Lsd1Ts

=n (Vin + Vc) − Vo1

Ls(1 − D − d2) Ts. (13)

From (12) and (13), the voltage Vo 1 is obtained by

Vo1 =D − d1 − (D/1 − D)d2

1 − D + d1 − d2· nVin . (14)

Similarly, from (4) and (7), the maximum diode current IDo2can be written as follows:

IDo2 =nVin − Vo2

Ls(D − d1) Ts =

n (Vin + Vc) + Vo2

Lsd2Ts.

(15)From (12) and (15), Vo 2 can be obtained by

Vo2 =D − d1 − (D/1 − D)d2

D − d1 + d2· nVin . (16)

In Fig. 2, the secondary current is is the sum of the currentflowing through the output capacitors Co 1 and Co 2 . Therefore,the average value of is should be zero. As a result, the averagevalues of the diode currents iDo1 and iDo2 are equal to the outputcurrent Io and the following relation can be obtained by

Io =(1 − D + d1 − d2) IDo1

2=

(D − d1 + d2) IDo2

2. (17)

From (13) through (17), d1 and d2 is obtained by

d1 = kD (18)

d2 = k (1 − D) (19)

k =12

(1 −

√1 − 8LsIo

nDVinTs

). (20)

Using (14), (16), (18), and (19), the voltage gain M of theproposed converter is obtained by

M =Vo

Vin=

n (1 − 2k) D

(D + (1 − 2D)k) (1 − D − (1 − 2D)k). (21)

Fig. 5(a) shows the voltage gain M according to D with k = 0.07and Fig. 5(b) shows M according to k with n = 3.

C. Maximum and Minimum Values of theMagnetizing Current im

From (1), the following relation is obtained by

Im1 − Im2 =Vin

LmDTs. (22)

In modes 3 and 4, the switch current iS 3 is flowing through theclamping capacitor Cc . Since the average capacitor current must

Fig. 5. Voltage gain M: (a) according to D and (b) according to k.

be zero under a steady-state condition, the average value of iS 3is zero. Therefore, the following relation can be obtained fromFig. 3 as follows:

Im1 + Im2

2· (1 − D) Ts

+ n

(IDo2d2Ts

2− IDo1 (1 − D − d2) Ts

2

)= 0. (23)

Using (17) and (21), the (23) can be rewritten as

Im1 + Im2

2− Iin = 0 (24)

where Iin ( = Vo Io /Vin ) is the average input current at unityefficiency. From (22) and (24), the maximum value Im 1 and theminimum value Im 2 are given by

Im1 = Iin +VinDTs

2Lm(25)

Im2 = Iin − VinDTs

2Lm. (26)

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D. ZVS Conditions for the Switches S1 Through S4

From Fig. 3, there is no current cancellation between ip (=nis)and im at t2 . Therefore, for ZVS of S2 and S3 , the total energystored in Lm and Ls should be larger than the energy storedin C1 through C4 . Namely, the following condition should besatisfied:

Lm I2m1

2+

LsI2Do2

2>

(C1 + C2) V 2in

2

+(C3 + C4) (Vin + Vc)

2

2. (27)

Since n, Im 1 , and IDo1 always have positive values and C1through C4 are quite small, it can be easily seen that the in-equality of (27) is satisfied. On the other hand, there is currentcancellation between ip ( = nis) and im at t0 . Therefore, for ZVSof S1 and S4 , the energy difference between the energies storedin Lm and Ls should be larger than the energy stored in C1through C4 as follows:

−Lm I2m2

2+

LsI2Do1

2>

(C1 + C2) V 2in

2

+(C3 + C4) (Vin + Vc)

2

2. (28)

This condition can be used to determine Lm .

E. Voltage Stresses of Power Switches and Output Diodes

Maximum values of vS 1 and vS 2 in the first bridge are con-fined to the input voltage Vin . The voltage stresses of S3 and S4are the sum of the input voltage Vin and the clamping capacitorvoltage Vc . Since the clamping capacitor voltage depends on theduty cycle, the voltage stresses of S3 and S4 can be changed ac-cording to load. Maximum values of vS 3 and vS 4 in the secondbridge is given by

vS3,max = vS4,max = Vin + Vc =DVin

1 − D. (29)

When the duty cycle D is below 0.5, the maximum values ofvS 3 and vS 4 are lower than the input voltage Vin . Due to thevoltage doubler structure, the maximum values of the voltagesacross the output diodes are confined to the output voltage Vo .

IV. DESIGN EXAMPLE

To validate the characteristic of the proposed converter, de-sign procedure is given in this section with the followingspecifications:

1) Input voltage Vin = 48 V.2) Output voltage Vo = 400 V.3) Maximum output power Po,max = 150 W.4) Switching frequency fs = 74 kHz.

A. Selection of k∗, Dmax , and n

As shown in Fig. 5(b), the smaller k is, the higher the voltagegain is. However, to obtain zero-current switching (ZCS) ofoutput diodes, a proper k is needed. Since k is a function of theoutput current Io , k∗ is defined as k under full load condition and

it is selected as 0.06 by considering the diode current changingslopes.

From (29), it can be seen that the voltage stresses of S3 andS4 depend on D. If they need to be kept below 150 V, D shouldbe smaller than 0.75. Therefore, the maximum duty cycle Dmaxis determined as 0.7.

Since the required voltage gain is 8.3, the turn ratio n can becalculated from (21) by using k∗ and Dmax .

B. Selection of Ls

From (20), the serial inductor Ls can be determined asfollows:

Ls =nDmaxVinTs

8Io,max

[1 − (1 − 2k∗)2

]. (30)

By using previously selected k∗ and Dmax , (32) gives Ls =87.5 μH. Then, Ls is selected as 90 μH.

C. Selection of Lm

From (17), IDo1 is calculated as 2.287 A. By assuming theoutput capacitances C1 through C4 of the switches as 500 pF,the inequality of (28) gives Lm < 136 μH. Then, Lm is selectedas 132 μH.

D. Selection of Cc , Co 1 , and Co 2

The switch current iS 3 flows through Cc . From the currentwaveform iS 3 in Fig. 3, the resulting ripple in the voltage acrossCc depends on the area under the current waveform. The voltageripple ΔVc across Cc is approximately given by

ΔVc ≈ (1 − D) Ts

4Cc(Im1 + nIDo2) . (31)

From (31), Cc should be larger than 3.49 μF to keep ΔVc below1 V. The value of Cc is selected as 6.6 μF.

The secondary current is flows through Co 1 and Co 2 equally.The voltage ripple ΔVo 1 across Co 1 is given by

ΔVo1 =(D − d1 + d2) TsIDo2

4Co1. (32)

From (32), Co 1 should be larger than 18.75 μF to keep ΔVo 1below 0.1 V. The value of Co 1 is selected as 47 μF. Similarly,Co1 is selected as 47 μF.

V. EXPERIMENTAL RESULTS

According to the design guideline presented in the previ-ous section, the prototype was implemented. The control circuitwas implemented with a constant-frequency pulsewidth modu-lation controller KA7552 from Fairchild. The PWM output ofKA7552 is fed to MIC4428 which has one inverting plus onenoninverting output. They are then fed to IR2110s which gen-erate gate signals for each bridge. For S1 through S4 , n-channelpower MOSFETs are used. Fig. 6 shows the gate driving cir-cuit. FQP85N06 is used for S1 and S2 and FQP32N20C is usedfor S3 and S4 . For the output diodes Do 1 and Do2 , the ultrafastrecovery diode RF2001T4S from Rohm is used. Fig. 7 showsp-spice simulation results based on the specifications and the

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866 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012

Fig. 6. Gate driving circuit.

Fig. 7. Simulation Results.

circuit parameters of the prototype. It shows the key waveformsof the proposed converter and the soft-switching waveforms ofthe power switches S1 through S4 and the output diodes Do 1 andDo2 . Fig. 8 shows the measured key waveforms of the proposedconverter. It shows the currents is and iT , the clamping capacitorvoltage Vc , and the switch voltage vS 2 . According to (12), the

Fig. 8. Measured key waveforms.

clamping capacitor voltage Vc should be 64 V. It agrees withthe experimental result. The measured maximum voltage stressof S4 is around 110 V, which agrees with the theoretical analy-sis. The measured soft-switching waveforms of all switches anddiodes are shown in Fig. 9. The ZVS operations of the powerswitches are shown in Fig. 9(a)–(d). The voltages across theswitches go to zero before the gate pulses are applied to theswitches. Since the switch voltages are clamped as zero beforethe gate pulses are applied, the ZVS turn-ON of the switchesis achieved. Fig. 9(e) shows ZCS of the output diodes. Afterthe diode currents fall to zero, the voltages across the dioderise to the output voltage Vo . Therefore, the ZCS turn-OFF ofthe output diodes is achieved. It can be seen that the voltagesvDo1 and vDo2 are confined to Vo . Fig. 10 shows the measuredefficiency of the proposed converter. The power consumed inthe control circuit is ignored. The proposed converter exhibitsthe efficiency of 95.3% at full load. Due to its soft-switchingcharacteristic and alleviated reverse-recovery problem, it showsa higher efficiency than the conventional PSFB converter.

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Fig. 9. Measured soft-switching waveforms of (a) S1 , (b) S2 , (c) S3 , (d) S4 , and (e) Do 1 and Do 2 .

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868 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012

Fig. 10. Measured efficiency.

VI. CONCLUSION

In this paper, an asymmetrical full-bridge converter with high-voltage gain has been presented. The ZVS of all power switchesand ZCS of the output diodes are achieved. The proposed con-verter is able to provide a high efficiency and high-voltage gainwith relatively low transformer turn ratio. Also, without any aux-iliary circuits, the voltages across the switches and the outputdiodes are effectively clamped. Therefore, the proposed con-verter is suitable for high-voltage applications. A prototype wasbuilt to verify the performance of the proposed converter. Thevoltage gain is 8.3 with the transformer turn ratio of 3. It providesa high efficiency of 95.3% at full load.

REFERENCES

[1] R. J. Wai, W. H. Wang, and C. Y. Lin, “High-performance stand-alonephotovoltaic generation system,” IEEE Trans. Ind. Electron., vol. 55,no. 1, pp. 240–250, Jan. 2008.

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Hyun-Lark Do received the B.S. degree fromHanyang University, Seoul, Korea, in 1999, and theM.S. and Ph.D. degrees, both in electronic and electri-cal engineering, from the Pohang University of Sci-ence and Technology, Pohang, Korea, in 2002 and2005, respectively.

From 2005 to 2008, he was a Senior Research En-gineer with the PDP Research Laboratory, LG Elec-tronics Inc., Gumi, Korea. Since 2008, he has beenwith the Department of Electronic and InformationEngineering, Seoul National University of Science

and Technology, Seoul, where he is currently a Professor. His research interestsinclude the modeling, design, and control of power converters, soft-switchingpower converters, resonant converters, power factor correction circuits, anddriving circuits for plasma display panels.