ANALOG CIRCUIT DESIGN

Analog Circuit Design Low-Power Low-Voltage,

Integrated Filters and Smart Power

Edited by

RUDY J. V AN DE PLASSCHE Philips Research Laboratories.

Eindhoven University a/Technology. The Netherlands

WILLY M. C. SANSEN K.U. Leuven. Heverlee. Belgium

and

JOHAN H. HUUSING T. U. Delft. Delft. The Netherlands

SPRINGER SCIENCE+BUSINESS MEDIA, LLC

Library of Congress Cataloging-in-Publication Data Analog circuit design: low-power low-voltage. Integrated filters, and

SNart power I edited by Rudy J. van de Plassche, Willy M.C. Sansen, Johan H. HuljSlng.

p. CN. "This book contains the revised contributions of all speakers of

the third AACO Workshop ·held In Eindhoven March 1994"--Pref. Includes bibliographical references.

1. Integrated clrcults--Oeslgn and constructlon--Congresses. 2. Analog-to-dlgltal converters--Oeslgn and constructlon­-Congresses. 3. Electric fllters--Oeslgn and constructlon--Congresses. I. Plassche, Rudy J. van de. II. Sannn, Wll\y M. C. III. HUljslng. Johan H. IV. Workshop of Advances In Analogue Circuit Design (3rd : 1994 : Eindhoven, Netherlands) TK7874.A6484 1995 621.3815--dc20 94-35832

ISBN 978-1-4419-5149-6 ISBN 978-1-4757-2353-3 (eBook) DOI 10.1007/978-1-4757-2353-3

Printed on acid-free paper

All Rights Reserved © 1995 Springer Science+Business Media New York. Fifth printing 2002

Originally published by Kluwer Academic Publishers in 1995 Softcover reprint of the hardcover 1 st edition 1995

No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical,

including photocopying, recording or by any information storage and retrieval system, without written permission from the copyright owner.

This printing is a digital duplication of the original edition.

Contents

Preface

PART I: WW-POWER LOW-VOLTAGE Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Low-Power Low-Voltage Limitations and Prospects in Analog Design Eric A. Vittoz .......................................... 3

Low-Voltage Low-Power Amplifiers Ron Hogervorst, Johan H. Huijsing, Klaas-Jan de Langen, Ruud O.H. Eschauzier 17

Design Considerations for High-Speed Low-Power Low-Voltage CMOS Analog-to-Digital Converters Thomas B. Cho, David W. Cline, Cormac S.O. Conroy and Paul R. Gray ..... 49

Micro-Power Analog-Filter Design Gert Groenewold, Bert Monna and Bram Nauta . . . . . . . . . . . . . . . . . . . . .. 73

Low Power Oversampled AID Converters Evert Dijkstra, Olivier Nys, Enrique Blumenkrantz . . . . . . . . . . . . . . . . . . .. 89

Low Voltage Low Power Design Techniques for Medical Devices David A. Wayne. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 105

PART ll: INTEGRATED FILTERS Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 127

Developments in Integrated Continuous Time Filters Yannis Tsividis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 129

Analog Integrated Polyphase Filters Michiel Steyaert and Jan Crols ................................ 149

Transconductor - C Filters John M. Khoury ...................................... '. .. 167

Recent Advances in Switched-Current Filters John B. Hughes, Kenneth W. Moulding. . . . . . . . . . . . . . . . . . . . . . . . . .. 187

Switched Capacitor Filters Robert C.J. Taylor ....................................... 203

Current-Mode Continuous-Time Filters David J. Allstot and Rajesh H. Zele . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 227

ADVANCES IN ANALOG CIRCUIT DESIGN

Preface

Low-Power Low-Voltage Integrated Filters

Smart Power

This book contains the revised contributions of all speakers of the third AACD Workshop held in Eindhoven March 1994. With this third book in a row it is hoped that a valuable contribution is given to the understanding and enhancement of advanced analog circuit design in Europe and the rest of the world.

This third workshop held in Eindhoven is for the time being the last workshop organized in the Benelux triangle Delft, Leuven, Eindhoven. In 1995 the local organization will move to Villach in Austria. Moving out of the Benelux gives the AACD Workshop a Pan-European character. The organization of the workshop itself will remain unchanged. Every day six tutorials will be presented followed by a panel session consisting of the day speakers and the session organizer.

This third workshop dealt with low-power low-voltage designs, integrated filters and smart power system and circuit design. The choices for these subjects are mainly detennined by the attendees of the workshop and in a certain way represent the hot topics of the analog design community.

The aim of the workshop is to brainstonn on new possibilities and future developments in the area of analog circuit design. To introduce a subject known speakers that are experts in the field are invited. After the introduction a discussion is organized to allow people to ventilate ideas and problems that they encounter during the design of advanced analog circuits.

I sincerely hope that this fonnula can be maintained and will be successful during the coming workshops especially next years meeting in Villach.

Rudy J. van de Plassche Philips Research Laboratories Eindhoven Eindhoven University of Technology

vii

LOW-POWER LOW-VOLTAGE

J.H. Huijsing

Preface

Low-power and low-voltage become highly important design criteria for analog and digital integrated circuits. Firstly the dimensions become smaller and densities higher. This reduces the isolation barriers so that they can only withstand a few volts in the future. Secondly the density becomes so high, that per cell only very little power can be spent to prevent the chip from overheating. Moreover, battery life time is an important specification in portable units like wireless phones and lap top personal computers.

The six following papers cover low-power low-voltage analog circuit design. The first two papers discuss basic limitations and solutions for elementary functions like amplifiers. The third and fourth paper consider the design of low-power low­voltage analog-to-digital converters. The fifth paper covers the topic of micro­power analog filters. Finally, the sixth paper examines the important application field of low-power for medical devices.

R.J. van de Plassche et aI. (eds.), Analog Circuit Design. L e 1995 Kluwer Academic Publishers.

LOW-POWER LOW-VOLTAGE LIMITATIONS AND PROSPECTS IN ANALOG DESIGN

Eric A.VI1TOZ CSEM, Swiss Center for Electronics and Microtechnology,

NeuchAtel, Switzerland.

ABSTRACT The fundamental limits and practical limitations to low­power low-voltage operation of analog circuits are identified. The various levels of analog design, namely devices, circuits and systems are then examined. For each level, specific problems and existing or anticipated solutions are discussed. Prospects on the future role of low­power analog circuits are addressed in the conclusion.

I. INTRODUCTION

The need for low-power circuits has up to now been limited to niche products like watches, hearing aids or pacemakers. For the large majority of VLSI-based products, low-power consumption has been close to last in the list of specifications, the only limit being given by the necessity to evacuate heat generated on-chip. This situation has changed drastically in the last few years, mainly because of the growing need for portability in computer and telecommunication products. Other concomitant reasons are the growing relative cost of power supplies. or even unacceptable network power required by very large systems. Low­voltage may be a requirement imposed by the process or by the system, or it may be an element of the strategy for reducing power of digital circuits. It has little influence on the power consumption of analog circuits, but it complicates their implementation since the corresponding reduction of maximum signal amplitude must be compensated by lowering the noise floor. This paper will first examine the fundamental limits and the practical limitations to low-power in analog circuits. It will then discuss various existing and anticipated solutions for reducing power and voltage.

3 R.J. WlIIM PItu8CI!. el al. (_.J, Analo, Circull/)esign, 3-15. C 1995 Kluwer Aeotkmic Publishen.

4

2. LIMITS TO LOW-POWER IN ANALOG CIRCUITS

Power is needed in analog circuits to keep the signal energy above thermal noise in order to achieve the required signal-to-noise ratio SIN. The power necessary to create, from a voltage source VB, a sinusoidal signal of peak-to-peak amplitude Vpp and frequency f across a capacitor C can be expressed as

P = fVBVppC (1)

whereas the signal to noise ratio is given by

v!/8 SIN = kTIC (2)

Combining (1) and (2) yields

P = 8 VVB kTfSIN (3) pp which is minimum when the peak-to-peak amplitude of signal Vpp equals the supply voltage VB:

Pmin = 8kT fSIN (4) This absolute limit is very steep, since it requires a lO-fold increase of power for every lOdB of SIN. It applies to each pole of any linear filter (continuous or switched capacitors). High-Q poles in the bandpass reduce the maximum amplitude at other frequencies and therefore increase the required power, according to (3). Approximately the same result is found for relaxation oscillators, whereas the minimum power required for a voltage amplifier of gain Av can be shown to be Av-times larger than the limit given by (4). These are basic asymptotic limits, which do not depend on the technology nor on the choice of power supply voltage. However, a number of obstacles or technological limitations are on the way to approach these limits in practical circuits: Capacitors increase the power necessary to achieve a given bandwidth. They are only acceptable if their presence reduces the noise power by the same amount (by reducing the noise bandwidth). Therefore, ill­placed parasitic capacitors very often increase power consumption. The power spent in bias circuitry is wasted and should in principle be minimized. However, inadequate bias schemes may increase the noise and result in a proportional increase in power. For example, a bias current is more noisy if it is obtained by mUltiplying a smaller current. According to (3), power is increased if the signal at any node corresponding to a functional pole (pole within the bandwidth, or state variable) has a peak-to-peak voltage amplitude smaller than VB. Thus,

5

care must be taken to amplify the signal as early as possible to its maximum possible voltage value, and to maintain this level all along the processing path. Current-mode (with limited voltage swing) is therefore not a good approach to reduce power, as long as the energy is supplied by a voltage source. The presence of additional sources of noise implies an increase in power consumption. These include 1/1 noise in the devices, and noise coming from the power supply or generated on chip by other blocks of the circuit. When capacitive loads are imposed (for example by parasitic capacitors), the current I necessary to obtain a given bandwidth is inversely proportional to the transconductance-to-current ratio gmtlof the active device. The small value of gmlI of MOS transistors operated in strong inversion may therefore cause an increase in power consumption. The need for precision usually leads to using larger dimensions for active and passive components, with a resulting increase in parasitic capacitors and power. All switched capacitors must be clocked at a frequency higher than twice the signal frequency. The power consumed by the clock itself may be dominant in some applications. Ways to reduce the effect of these various limitations can be found at all levels of analog design ranging from device to system.

3. DEVICES FOR LPLV

For analog design, the basic static behaviour of a MOS transistor is best characterized by a symmetrical model [1, 2, 3] in which the drain current ID is decomposed into a forward component IF and a reverse component IR:

ID = IF -IR = lsI f(Vs,Va) - f(VD,Va)] (5) where source voltage V s, drain voltage V D and gate voltage Va are all referred to the local substrate. [(V, Va) is a monotonically decreasing function of V which tends to a square law for f» 1 (corresponding component of current in strong inversion) and to an exponential for f« 1 (weak inversion). It can be approximated by

Vp-V [(V,va) = ln2{ 1 + exp 2Ur } (6)

where Ur =kTtq and Vp is called the pinch-off voltage, approximately given by

Vp = Va-Vro (7) n

VTO is the threshold voltage and n<2 is a slope factor which is only weakly dependent on Va (tends to 1 for Va very large).

6

The third and last basic parameter of the transistor is the specific current Is in (5). It is given by

• .2 W 2 Is = 2n/lCoxUTL = 2npUT (8)

and can alternatively be replaced by the usual transfer parameter p. This specific current, which characterizes the level for which the component is in moderate inversion, typically ranges from 10 to 200nA for minimum size devices. The overall mode of operation of the transistor depends on the respective levels of both IF and JR, as illustrated in Fig. I.

log (lpIS)

Vs>Vp ii!liil'og (IR"S)

Fig.1 : Modes of operation of a MOS transistor.

If both IF and IR are in weak inversion (VS and VD<VP), then the whole transistor is said to operate in the weak inversion mode and behaves, in many aspects, similarly to a bipolar transistor without any DC control current. Combining (5) to (7) gives the corresponding drain current

VG-VTO Vs VD JD = Ise nUT {e- UT - e- ui} (9)

Weak inversion provides the minimum possible value of drain to source saturation voltage (VDSsaF 4 to 6UT), which helps keeping peak-to-peak signal amplitudes close to VB. The gate to drain transconductance gm in saturation is obtained by differentiating JD=IF given by (5) to (7). The result is represented in Fig.2 as a function of the inversion coefficient ID lIs. It can be seen that weak inversion provides the maximum value of gmlJD. Thus, if the current is limited, weak inversion provides the maximum value of transconductance gm and of bandwidth gmlC for a given value of capacitive load C, and the minimum value of input noise resistance RN =.1/gm. This maximum value of gmllD also results in a maximum value of the intrinsic voltage gain, which helps to simplify the architecture of amplifiers, and in minimum input offset in a pair.

1 , ,

t inversion nUT 9m coefficient TO

lOllS O~~~~~~~ __ ~~

0.01 100

Fig.2 : Transconductance-to-current ratio; solid line obtained from the model; experimental points for comparison.

Weak inversion is not applicable to very high frequencies, since

gm(ID=ls) YJJ /Tmax,weak = 21r(CG+CD} < (10)

7

cannot exceed a few hundred MHz for L= 1 J.1m. Pushing IT to higher values by operating the transistor in strong inversion (UT replaced by Vp/2 in (10) requires a quadratic increase in drain bias current. Furthermore, all the attractive features of weak: inversion are then lost. Indeed, most of these features can be obtained from high-frequency bipolar transistors; BiCMOS thus appears to be the best technology for low-power high-frequency analog circuits. Other problems with weak inversion are the large relative noise content of the drain current and the degradation of drain current mismatch due to threshold mismatch. Both effects result from the maximum value of gmllD. Thus, using weak inversion to counter the low value of supply voltage VB by maximizing the signal swing results in very inaccurate and noisy currents. The precision of currents at low-voltage can be drastically improved by operating the MOS transistor as a lateral bipolar [4], or by using true bipolar transistors.

4. CIRCIDT LIMITATIONS AND SOLUTIONS

Contrary to the case of digital circuits, reducing the supply voltage VB does usually not help reducing the power consumption of analog circuits. Several problems must be solved when low-voltage is imposed by the system or by the source of energy. Using MOS transistors as analog switches has proved to be very efficient for implementing all kinds of analog functions. If the switch is a n­channel transistor, it is put into conduction by connecting its gate to the positive supply rail. According to (6) and (7) and assuming the substrate is connected at the negative supply rail, a strongly inverted channel is only created if the analog voltage V is smaller than Vmax given by (7):

Vmax = VPn = (VB-VTOn)lnn (11) The rest of the voltage range can be covered by connecting a p-channel transistor in parallel, which only conducts above a minimum value V min

8

of V. Now, if the supply voltage VB is smaller than a minimum value given by

V . - VTOpnn + VTOnnp (12) Bmm - np + nn + npnn

then V max< V min and a gap of non-conduction remains in the middle of the voltage range. In practice, VBmin is typically around 3V for maximum threshold values of the order of O.7V. This very severe limitation to low­voltage operation of analog switches can be circumvented by various solutions: Lower values of VTO may be required from the process, but it would increase the off-current of the switch due to the weak inversion behaviour. The transistors can be put in a separate well connected to V during the on-state and connected to the supply rail in the off-state. This is only possible for one type of transistor, and the analog node must provide the charge necessary to change the well potential. Circuits may be architectured to avoid the need for switches conducting in the whole range. This solution is in opposition to the need for maximum signal swing in order to minimize power, according to (3). Another solution amounts to provide on-chip multiplication of the clock voltage as illustrated by the example of Fig.3 [5].

~---fll-+ft'f"--r ..... -" separate n-well

.h to n-channel switches

Va

voltage

Va __

o --L _____ .L...L....:: 0 (p-substrate)

Ei&J. : On-chip clock voltage multiplication.

The large-amplitude clock ;h is delivered by a CMOS inverter, with the p-channel transistor operating at the high voltage produced by a diode­capacitor multiplier. It is used to drive n-channel switches which then conduct in the whole range 0 to VB. The diode may be implemented by lateral diodes in the polysilicon layer available in some special processes [6], or by diode-connected p-channel transistors located in separate wells.

9

The effect of the charge injected from switches is worse at low supply voltage. since it corresponds to a relatively larger fraction of the signal amplitude for the same on-conductance g of switches (same channel charge q=gV/p.).

Low-voltage operation' prevents the use of any stack of transistors. In particular. cascodes must be implemented to bias the drain voltage of the common source device just at the verge of saturation. A well-known solution is illustrated in Fig.4a [7. 2]. If the three transistors are operated in strong inversion. they can be sized to impose V D 1 = V P 1 independently of the value of current 10. for example by choosing /3]=/32=4/13.

1+ + I + I Tz ~ Tz

~ .. T, ---Iu-~-...a..-substrate -~~-

® ~ : Low-voltage cascode: a: for strong inversion

b: self-cascode for weak inversion. This scheme must be modified to be applicable to weak inversion [2]. An alternative is given by the compact solution illustrated in Fig.4b [8]. From (9). it can be shown that this combination of two transistors with Early voltages VEl and VE2 provides an output conductance

I I + FUr/VEl (13) go = VE2 1 +F

which approaches that of a real cascode if the factor & Vn)J -VT02

F =]Iie nUT (14)

is large. This can be obtained by using channel width W 2 » W l, with W 1 as small as possible. VrOl is then increased by narrow channel effect. which further increases F. The limitations faced in optimizing operational amplifiers for low current and low voltage can be illustrated by the very simple single stage OT A shown in Fig.5. The overall transconductance gm of this amplifier is that of input transistors Tl-Tj multiplied by mirror ratio B. Loaded by CL. the circuit behaves essentially as an integrator with time constant

tu=CIlgm (15) If all other poles are at a much higher frequency. their effect may be approximated by a single equivalent pole with time constant 'rp.

10

Ignoring the finite DC gain, the transfer function of the amplifier may then be expressed by

1 Av = s'ru (J + s'rp) (16)

IAvl (log)

Avo

lL....-...r---~Ir"!-..... CJ)

1/'tu (log)

~ : Single stage OTA and its frequency behaviour.

The OTA always operates in closed loop, with a certain amount of negative voltage feedback {351. The settling time for small perturbations can then be approximated by [9]

Ts = (2'rp +'rul{3)ln(Jle) (17) where e is the relative settling error after time Ts. Settling time Ts also increases with 'rp and settling becomes oscillatory when this term dominates (small phase margin). Using (16), the total output noise v~ in closed loop due to an equivalent input white noise resistance RN can be calculated analytically [2]:

~ _ kTRN -1 kT (18) N - p;r;; - P CL

Surprisingly, this result does not depend on 'rp. Thus, capacitors elswhere than at the output node indirectly increase the power by reducing the speed and degrading stability, but they have no effect on reducing the noise. By definition, r =gmRN is a factor of merit which should be as small as possible. The smallest value is obtained when the noise is limited to that of the input pair, by implementing a large gain in branch Tl(3)-T2(4) (gml(3) I gm2(4) »1, so Tl(3) in weak inversion, and all other transistors deeply in strong inversion). Then:

r= ;min = nB (19) The price to pay is a reduced maximum signal amplitude due to the large saturation voltage Vp of T7 and T8. It also increases 'rp by reducing gm2(4). If these drawbacks are avoided by operating all the transistors in weak inversion, then 'Y is degraded to

r= '}max = n(2B+l+BIC) (20) which is 3 to 4 times rmin if B~ 1 and C= 1.

11

As shown by (18), noise is increased above the theoretical minimum kTICL by a factor r 1/3. It might seem interesting to increase the power efficiency of the amplifier (percentage of supply current delivered to the load C L) by selecting a large value for mirror ratio B. But this would increase r and hence the noise proportionally. Relation (18) also shows that any reduction of the feedback factor /3 below unity (due for example to parasitic capacitors at the input node) increases the noise proportionally. Except for small variations of r. the noise power expressed by (18) is not directly dependent on the bias current. However, reducing the noise by increasing CL requires an increase in current to maintain the small­signal settling time Ts and the slew rate B1oICL. Power efficiency and slew rate can be drastically increased by using class-AB amplifiers, which can provide to the load a current much larger than their standby bias current. A very simple and efficient solution intended for switched capacitor circuits is illustrated in Fig.6 [10].

Ei&& : Low-power class-AB transconductance amplifier.

This circuit operates in two phases : an amplifying phase (position of switches shown in the figure) and a biasing phase (opposite position of switches). During the biasing phase, T3-T2 are configured as a mirror which imposes bias current 10 through diode-connected transistor TJ. At equilibrium, the gate voltage of TJ reaches an internal virtual ground level (no current available from the output node). Switch SJ is grounded, thus capacitor C J is charged to adapt the external virtual ground level to the desired value. In the amplifying phase, TJ and T2 are configured as a CMOS inverter and the two transistors are driven in parallel by any voltage difference between input and ground. This solution is an excellent illustration as to how simplicity can bring high performance when power is limited. In weak inversion, this circuit provides the maximum possible value of transconductance (and thus minimum equivalent input noise resistance RN) for current 10, and a maximum value of small-signal DC gain equal to the intrinsic gain of a single isolated transistor. Gain may be further increased beyond 100dB by cascoding TJ and T2; the maximum peak-to-peak signal amplitude is

12

then only 400 to 600m V below VB. The auto-zeroing properties of the switching scheme [11, 3] result in good low-frequency PSRR and eliminate the Iff noise. The noise figure of merit ris almost as low as that of a single transistor. This circuit provides class AB operation, since a current much larger than bias 10 is supplied to the load CL for large input amplitudes; power efficiency is then excellent, since most of the current absorbed from the power supply is delivered to the load. Last but not least, this amplifier can be transformed into a stray- and offset-insensitive SC-integrator by just adding the integrating capacitor Ci. Capacitor C1 then becomes a SC-resistor which can be duplicated with S1 if several inputs are needed.

5. SYSTEM CONSIDERATIONS FOR LOW-POWER.

Power minimization must already be addressed at the system level. A first aspect is the management of the power delivered to the various blocks of a chip, which will be very important for digital sUb-circuits. For analog blocks, voltage is not critically related to power, and power management can be limited to shutting off some functions when they are not needed, and to possibly mUltiplying (on- or off-chip) the supply voltage if it comes from a very low voltage source. High-frequency operation tends to require a power much above the limits presented in section 2, essentially because of the presence of parasitic capacitors. The architecture of low-power RF receivers should thus be selected to minimize the number of active devices operating at the carrier frequency. An extreme solution would be to directly sample the RF signal at a subharmonic of the usual local oscillator frequency. All the image bands produced by this undersampling process would have to be eliminated by passive SAW filters just after the antenna. Of course, the signal power available after mixing would be reduced by the undersampling factor, so this solution is usually not applicable. Even if undersampling remains an interesting possibility, it must be preceded by RF amplification stages. Certain applications such as paging or the Global Positioning System (GPS) do not require full-time operation of the receiver. Indeed, depending on the protocol, the duty cycle may be drastically reduced, with a proportional reduction in power consumption. Commercially available watch pagers already operate continuously for 30 days on a small battery. For continuous operation, and even when high frequency is not an obstacle, it will never be possible to pass the limit given by equation (4), and at least ten times more power will probably be needed for practical reasons. This means that it will never be possible to realize a I6-bit audio AID converter (SIN=98dB) that consumes less than about 50-IOOJlW, and even more power will be needed for amplifying the analog

13

signal before conversion. On the other hand, a few micro watts per pole will be sufficient to implement the subsequent digital filtering with an advanced process and low-voltage operation. Thus, the necessary analog interfaces will (and do in fact already) consume most of the power in a signal processing chain when a dynamic range larger than 40 to 60dB is required. This is true only if the dynamic range must be assimilated with the maximum signal-to-noise ratio SIN that can be achieved in the whole bandwidth. However, in many applications, the SIN necessary for a certain level of signal is much smaller than the full dynamic of the signal. For example, speech transmission only requires a SIN of 40dB, but the range of signals to be processed can be as large as 100dB. By letting the noise follow the signal level to maintain just the necessary value of SIN, the 60dB difference in this example provides the possibility to reduce power consumption by a factor of 106! A well-known solution along this line is to use automatic gain control (AGe), in which the gain is slowly adapted to maintain constant the RMS or peak level of the signal, without affecting its instantaneous wave form. This solution necessarily causes some distortions, which must be minimized by carefully selecting the time constant(s) of the control loop. Another known approach is the automatic range selection used in instrumentation. This approach can be extended to general analog processing systems by using the architecture shown in Fig.7 [12].

x (in)

example for 2 ranges:

Eig.1 : Analog floating point technique [12].

This approach, called analog floating point technique, amounts to multiply the instantaneous signal x (t) by a factor K which is adapted to maintain the signal x'(t) entering the processor within a range min-max. The scaled signal x' is then processed to produce a signal y' which is divided by the same factor K. Distortions by the processor are avoided if

14

its state vector:. (set of state variables) is multiplied by K+IK each time the factor changes from K to a new value K+. This updating of the state vector must be carried out in a time shorter than half the period of the highest frequency to be processed. It can be done between two sampling instants if the system· is operating in discrete time.

6. CONCLUSION: PROSPECTS IN ANALOG DESIGN.

Digital signal processing consumes much less power than analog solutions when a large value of signal-to-noise ratio is required (typically more than 60dB) [13]. This advantage will be reinforced wjth the trend towards scaled down processes operating at a lower voltage. For example, high-fidelity music can only be efficiently processed, stored or transmitted by using digital solutions. This is a typical example of tasks aiming to the restitution of signals, for which digital solutions are much more efficient. The burden of minimizing the overall power consumption is then put on the unavoidable interface circuits to the analog world. In particular, effort are still needed to bring the power consumption of high-precision AID or D/A converters closer to its theoretical minimum. Scaled-down processes will be a help, provided they do not force a reduction of the analog supply voltage below 1 Volt. Care must be taken in the system definition phase to avoid wasting a lot of power by exaggerating the requirement on signal-to-noise ratio SIN, or by confusing it with the required dynamic range. Each additional lOdB of SIN requires a to-fold increase in power consumption. On the other hand, this very steep dependency of power on SIN for analog circuits makes them much more power efficient than digital circuits if the task can be executed with a small value of SIN. For example, speech recognition can almost certainly be done with a value of SIN smaller than 40dB. This is a typical example of a task aiming at the perception of signals, for which analog solutions are expected to be much more efficient. As is witnessed by even the most simple animals, what is needed for perception (in particular vision, audition and olfaction) is the massively parallel collective processing of a large number of signals that are continuous in time and in amplitude. Precision is not needed, noise might even be helpful and non-linear effects can be exploited. Low-precision analog VLSI can operate in continuous time and can exploit, in an opportunistic manner, all the nice features offered by the transistor [14]. It therefore seems to be best suited for the implementation of low-power perception machines.

15

REFERENCES [1] H.Oguey and S.Cserveny, "MOS modelling at low current density",

Summer course on Process and Device Modelling, KU-Leuven, 1983.

[2] E.Vittoz, "Micropower Techniques", in Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Edit. I. Franca and Y.Tsividis, Prentice Hall, 1993.

[3] C.Enz, High Precision CMOS Micropower Amplifiers, Ph.D.Thesis No 802, EPFL, Lausanne, 1989.

[4] E. Vittoz, "MaS transistors operated in the lateral bipolar mode and their application in CMOS technology", IEEE I.Solid-State Circuits, vol. SC-18, pp.273-279, Iune 1983.

[5] F.Krummenacher et al., "Higher sampling rate in SC circuits by on­chip clock-voltage multiplication", Dig. ESSCIRC '83, pp.240-241, Lausanne 1983.

[6] M.Dutoit and F.Sollberger, "Lateral polysilicon p-n diodes", I. Electrochem. Soc. ,Vol. 125, pp.1648-1651, Oct. 1978.

[7] T.C.Choi et al., "High-frequency CMOS switched-capacitor filters for communications applications", IEEE I.Solid-State Circuits, vol. SC-18, pp.652-664, Dec. 1983.

[8] R.C.Schober et al., "Ultra low power circuit techniques for focal plane electronics applications", JPLTask Plan 80.3295, 1993.

[9] E .Vittoz, "Microwatt switched capacitor circuit design", Electrocomponents Science and Technology, Vol. 9, pp.263-273, 1982.

[10] F.Krummenacher, E.Vittoz and M.Degrauwe, "Class AB CMOS amplifiers for micropower SC filters", Electronics Letters, Vol. 17, pp.433-435, 25th June 1981.

[11] E. Vittoz, "Dynamic analog techniques", in Design of Analog­Digital VLSI Circuits for Telecommunications and Signal Processing, Edit. J.Franca and Y.Tsividis, Prentice Hall, 1993.

[12] E.Blumenkrantz, patent application, 1994. [13] E.Vittoz, "Low power design: ways to approach the limits",

ISSCC'94 Dig. tech. papers, pp.14-18, 1994. [14] E.Vittoz, "Analog VLSI signal processing: why, where and hoW?",

to be published in the Joum. of VLSI Signal Processing, Kluwer, 1994.

LOW-VOLTAGE LOW-POWER AMPLIFIERS

Ron Hogervorst. lohan H. Huijsing. Klaas-Ian de Langen. Ruud G.H. Eschauzier

Delft University of Technology Faculty of Electrical Engineering Laboratory for Electronic Instrumentation Mekelweg4 2628 CD Delft The Netherlands Phone: (+31) 15786518

Abstract- Low-voltage low-power amplifiers are limited in their dynamic range and bandwidth. The maximum dynamic range Is limited by the supply-power and the ther­mal noise in resistors. To obtain the maximum dynamic range several rail-to-rail input and output stages are designed. The bandwidth is limited by the low-power condition. To reach the maximum bandwidth as well as a large DC-gain various frequency compensation techniques, such as Paral­lel, Nested Miller and Multipath Nested Miller Compensa­tion are discussed.

I. Introduction

The continuing down-scaling of dimensions in Ie technology results in a lowering of breakdown voltages. This development in technology pushes the supply voltages to lower values. Further, the smaller dimensions also lead to higher component densities which results in less allowable power

17 R l van tk PlasSCM el al. (eds.), Analog CirculI Design, 17-47. C 1995 Kluwer Academic PublisMrs.

18

per electronic function. The increasing popularity of portable battery-pow­ered electronics pulls supply voltages and power to smaller values. Supply voltages will go from the present 5 V to 3 V. further to 2 V. and ultimately to 1 V.

The lowering of supply voltages and power has an enormous impact on the signal handling capability in analog circuit design. Firstly. the dynamic range decreases because of lower allowable signal voltages and larger noise voltages caused by the lower supply currents. Secondly. the bandwidth of circuits is reduced due to lower supply currents.

This paper discusses the limits of low-voltage low-power amplifiers. In section II it is shown how the maximum dynamic range is determined by the available supply-power and the bandwidth. The dynamic range for sev­eral examples. such as the current-to-voltage converter and the voltage amplifier. has been calculated. To obtain the maximum dynamic range. rail­to-rail input stages and rail-to-rail output stages are designed in section III and IV. respectively. In section V. it is shown how the unity-gain frequency of an amplifier is limited by the supply current. In section VI. several tech­niques to increase the gain of an amplifier are discussed. The gain can be increased by either cascading more stages or by improving each stage. Fur­ther, frequency compensation techniques for amplifiers with one or more stages are discussed in this section. Finally in section VII some conclusions are drawn.

II. Dynamic-Range versus Supply-Power

The dynamic range of an operational amplifier can be defined as the maxi­mum voltage level of a signal divided by the voltage noise. The top value of a single-phase signal is equal to half the supply voltage, as is shown in Fig. I.

~t~ Vsup,lsup

Vsf -'---~-7-VsurJ2 Vgr

time-

Fig. 1. Single rail-to-rail voltage across a class-B driven signal process­ing resistor.

19

If this signal is present across a class-B driven signal processing resistor, Rs, the average power drawn from the supply is given by:

2 _ _ Vsup

P sup - Vsu/ av - 2ltRs (1)

where Psup is the average supply power, Vsup is the supply voltage and Iav is the average current drawn from the power-supply. The thermal noise­voltage across the resistor, vn' is given by:

(2)

where k is Boltzmann's constant, T is the absolute temperature and Be is the equivalent noise bandwidth. Using (1) and (2) the maximum dynamic range, DRmax, can now be calculated as:

(3)

where Vss is the root-mean square value of the signal. Dividing the DRmax by the supply-power the following expression is obtained:

(4)

From (4) it can be concluded that, for a given temperature and bandwidth, the DRmax-to-supply-power ratio is constant.

Exactly the same expressions can be found for the balanced case, as shown in Fig. 2. The top value of the balanced signal is equal to the supply volt­age. To consume the same power supply in the balanced case, the resistor

20

RB should be four times larger than that of the single-phase case. Vsbt ~ Vsup,lsup

v.t ~-V.,./2 ----'-"----......... --V gr

tims-Fig. 2. Balanced rail-to-rail voltage

across a class-B driven signal processing resistor.

If it is assumed that the single-phase driven resistor Rs has a value of IOkO, Vsup is 1 V, Be is 1 MHz, Tis 300 K and Psup is 16 J1w, it can be cal­culated that the DRmax is equal to 89 dB. To consume the same power in the balancing case the resistor Rb should be four times the resistor in the single phase driven case, i.e RB is 40 kO.

In the following paragraphs some examples with respect to the dynamic range (DR) will be discussed. It is assumed that the supply-power is the same for all examples and has a value of 16 J1 W. The equivalent noise band­width, the supply voltage and the temperature have the same values as in the previous paragraph.

An example is a simple single-ended current-to-voltage converter, as shown in Fig. 3 .

...... ----..,.--r-r--~--4 vout

~------~----------~V~1-2

Fig. 3. Single-ended current-to-voltage converter.

At a supply-power of 16 J1w, the DR is 89 dB, which is equal to the maxi­mum achievable dynamic range at this supply power. This maximum can only be obtained if the amplifier has rail-to-rail and class-AB capabilities. If the signal processing resistor is driven in class A, the DR is at least a fac­tor 1t or 5 dB below its maximum value. In many applications, e.g. audio

21

and telecommunications, the signals are often much lower than their maxi­mum value. In those applications the DR can easily be 20 dB below the maximum value of the dynamic range, where it is assumed that the ampli­fier is of a c1ass-A type. If the output voltage swing of the operational amplifier is not rail-to-rail but reduced to one third of the supply-voltage, this happens when a diode-voltage Vbe is lost at a supply voltage of 1 V, the DR is a factor 3 or 5 dB below its maximum value. Note that in this case, the resistor should be one third of the previous case, in order to consume the same supply power. The same results can be found when the balanced version of the current-to-voltage, as shown in Fig. 4, is used.

F\1=20 k.Q

Rb2=20 k.Q

Fig. 4. Balanced current-to-voltage converter.

R1=20 k

+

/I)--------------L--------fJ Vsur/2

Fig. 5. Single-ended inverting voltage amplifier.

Another example is the inverting voltage follower, as shown in Fig. 5. This amplifier needs an additional buffer to drive the resistor Rj • To have a power consumption of 16 J.1 W at a 1-V supply voltage, the signal processing resistors R] and R2 should be equal to 20 kn. The dynamic range loses 3 dB because each resistor has a thermal noise voltage which is two times larger than the original 10 kn. The dynamic range loses another 3 dB because of the additional input buffer. The result is a dynamic range which is 6 dB below its optimum, i.e. 83 dB. If the value of the signal processing resistor R j is changed from 20 kn into 2 kn, an inverting amplifier with a gain of

22

ten is obtained. Again, the dynamic range loses 3 dB because of the input buffer. It loses another 10 dB because the input voltage swing is only one tenth of the supply voltage. The result is a 13 dB reduction of the dynamic range. In other words, the equivalent output noise resistance is twenty times the original 10 kO. The same results can be found for the balancing case, as is shown in Fig. 6.

+

Fig. 6. Balanced inverting voltage amplifier with a gain of 10.

+ Vout

The non-inverting amplifiers are shown in Fig. 7 and Fig. 8. The amplifiers have a gain of 10. The amplifiers lose 10 dB in dynamic range because the maximum input signal is only one tenth of the supply voltage. In other words the equivalent output noise resistance is ten times the original IOkO.The resulting value ofthe DR is 79 dB.

f)-----------'------fJ Vsur/2

Fig. 7. Single-ended non-inverting voltage amplifier.

23

--..lln=O

R2=18 kll

+ + Vln R1=4 kll Vout -

R3=18 kll

Fig. 8. Balanced non-inverting voltage amplifier.

The balanced inverting voltage integrator, as shown in Fig. 9, looses only 3 dB in DR, because of the input buffers. The capacitors do not add to the noise [1]. The resulting dynamic range is 86 dB. It can be calculated that

R1=40 kll C1 >--r--{=J--.---I

Fig. 9. Balanced inverting voltage integrator.

the dynamic range of the balanced inverting voltage integrator is given by:

2 DR = 1tVsupC

4kT (5)

24

where it is assumed that

(6)

A very severe reduction of DR can be found in current mirrors. The DR of a bipolar current mirror. as shown in Fig. 10. is given by:

v P DR = 4 n _T_ sup (n+ 1)2 Vsup 16kTBe

(7)

where VT is the thermal voltage and n is the gain of the current-mirror. The current mirror loses a factor 7t. because it is class-A biased. as well as a fac­tor Vr/Vsuy' because the signal is compressed in a voltage range of V:p which is 25 m V at room temperature. The resulting dynamic range for a

....-------.------4 V sup

V.url2

L...-___ ---' _______ Gr.

Fig. 10. Bipolar current mirror

bipolar current mirror is 68 dB. where it is assumed that n equals one.

The DR of a CMOS current mirror is given by:

3 n (V os - VTH) Psup DR = - --~ --=:--..::...:.:~ -:--::-:-::=-=-

2 (n + I) 2 Vsup 16kTBe (8)

where Vos is the gate-source voltage of a MOS transistor and VTH is the threshold voltage. Assume that n equals one and the gate-source voltage is about 6VT above V771• which is a commonly used value when aMOS tran-

25

sistor is biased in strong inversion. Now, the dynamic range is equal to 77 dB. Note that the DR of a MOS mirror is larger than that of a bipolar one.

So far, the non-idealities of the operational amplifiers have been disre­garded. If these non-idealities are taken into account the dynamic range reduces even more. Important non-idealities are caused by the shot noise in bipolar transistors and thermal-noise and flicker noise in field-effect tran­sistors.

The equivalent input noise voltage resistance for bipolar transistors is given by:

(9)

where Ie is the collector current and re is the small-signal emitter resistance of a bipolar transistor. Suppose Ie is equal to 10 JlA and VT is 25 mV, this results in an Reqv of 1250n for the bipolar case.

The equivalent input noise voltage resistance of field effect transistors is given by:

(10)

where y is a constant depending on the process, Il is the mobility of the charge carriers, Cox is the normalized oxide capacitance, K is the flicker noise coefficient, f is the frequency and ex is a constant close to one. Wand L are the width and length of a transistor, respectively. The first term of (10) represents the thermal noise, the second term represents the flicker noise. Suppose that the field-effect transistor is operatin~ above the flicker noise region, and that y is 2/3, IlCox equals 75 10-6 AN , and ID is 10 JlA. For a Wover L ratio of 25, Re v is equal to 3440 n, which is larger than in the bipolar case. In general, the field-effect transistor will have a larger equiva­lent noise resistance than a bipolar transistor, because the gm of a field effect transistor is always smaller than that of a bipolar one.

26

The dynamic range in the DC situation is given by:

2 _ Vsup

DRmax,DC - --=-2 ~ Voffse'

(11)

where Voffiet is the offset voltage of a balanced input stage. For a bipolar input stage with an offset of 0.3 m V, the DRmax,DC is 70 dB, where it is assumed that the supply voltage is equal to 1 V. For an Field-effect input stage with an offset voltage of 3 m V the DRmax,DC is 50 dB. Again it is assumed that the supply voltage is 1 V. The DRmax,DC can only be increased by using special layout structures or by using chopping techniques.

III. Voltage Efficient Input Stages

To obtain the maximum DR, the input stage should be able to deal with common-mode input voltages from rail-to-rail. A single N-channel or P­channel input stage, as shown in Fig. 11, does not meet these requirements .

.-------~------~~~r7~~~---------~-r------r----,----VDD

.-~------~---~-L---------~~~~~~~---------~------vss

Fig. 11. Common-mode input voltage range of a P-Cha1l1lel or an N-channel input stage.

From Fig. 11, it can be concluded that the common-mode input voltage range of a P-channel input pair, M3-M4, is limited between:

(12)

where V CM is the common-mode input voltage Vgs is the gate-source volt­age, VDsat is the bias voltage across a current-source, VDD and Vss are the positive and the negative supply-rail, respectively. The common-mode

27

input voltage range of an N-channel input pair, MrM2' is given by:

VSS + VGS + VDsat < VCM < VDD (13)

~----------'-----------------r-----~~--r---4VDD

+

.-----------~----------------~----~~------4Vss

Fig. 12. Rail-to-rail CMOS complementary input stage.

If the N-channel and P-channel input pair are placed in parallel, as is shown in Fig. 12, the common-mode input voltage range becomes:

(14)

To obtain a rail-to-rail operation of the complementary input stage the sup­ply-voltage should have a minimum value of:

Vsup,min = 2V GS + 2VDsat (15)

If the supply voltage is below this value a gap occurs in the common-mode input range. Using CMOS technology, the minimum supply voltage for fully rail-to rail operation is approximately 1.8 V. Of course, this voltage depends on the bias-current level and the threshold voltage of the transis­tors. In bipolar technology a minimum supply voltage of 1.6 V can be obtained.

The transistors MJ-MS add the drain-currents of the input transistors. MJ and M7 operate as folded cascodes, while M6 and Ms act like a current mir­ror.

28

A drawback of the complementary input stage is that the transconductance (g"J varies a factor two over the whole common-mode input range, as is shown in Fig. 13. This impedes an optimal frequency compensation of the amplifier [3].

2 P+N pair

Ppair N pair

04-------------~~--------------------------------~--------~~ low intermediate high Voo

Vc;;;--Fi8. 13. gm versus the common-mode input voltage for a

complementary input stage.

In bipolar technology, the gm of a transistor is proportional to the collector current. Therefore, a constant 8m can be obtained by keeping the sum of the tail-currents of the complementary input stages constant. A realization is shown in Fig. 14. Depending on the common-mode input voltage the cur­rent switch, Qs, directs the tail-current, Ibb to either one of the input stages [2,3,4]. The result is a constant 8m over the common-mode input range, as is shown in Fig. 15.

In CMOS technology, the 8m of a transistor is also proportional to the drain-current, providing that the transistor operates in weak-inversion. In this case, the 8m can be kept constant by using the same circuit as in bipolar technology. In strong-inversion however, this scheme leads to a gm which varies approximately 40% over the common-mode input range, as is shown in Fig. 15. The reason is that the gm of a MOS transistor, which operates in strong-inversion, is proportional to the square-root of the drain-current instead of proportional to it.

In Fig. 16 a rail-to-rail input stage is shown, which has a largely constant gm when the input transistors operate in strong inversion. If both input pairs operate, the tail-currents of both input pairs are equal, and have a value of Iref If only one input pair operates, the current-switches, Ms and Ms, and

29

~~~--~------------~----~------VEE

Fig. 14. Rail-to-rail input stage. The one-time current mirror controls the gm·

(b) strong Inversion

\ __ , 40% 2

/ , 1~--~-------w-~'--~~--'~-~----------

(a) bipolar or weak Inversion

O;-----------r---------------------~---------+--

Fig. 15. gm versus common-mode input voltage/or the complementary input stage with one-times cur­rent mirror.

the three-times current mirrors. MoM7 and M9-M10' increase the tail-cur­rent of the active input pair by a factor 4. Thus. the tail-current of the actual active input pair has a value of 4lref The result is an approximately con­stant gm. In the transition regions of the current-switches the gm varies about 15%. as is shown in Fig. 17 [5].

It should be noted that the offset voltage of rail-to-rail input stages changes

30

~----r-----r-----~r------------r-----,--,-~VDD

~--~~----~----~~----------~----~----~V~

Fig. 16. Rail-to-rail input stage. The 3-times current mirrors control the gm'

when the complementary input stage gradually switches from one input pair to the other. This change of the offset voltage degrades the CMMR in the transition regions.

2 -t------ ..a-;'~"

1

o;-------~~--------------~~----~

Fig. 17. gm versus the transconductance for the complemen­tary input stage with three-times current mirror.

Iv. Voltage and Current Emcient Output Stages

Output stages for low-voltage low-power applications should have a rail­to-rail output range and should be class-AB biased. The class-AB biasing should provide a high ratio between the maximum output current and the quiescent current. To avoid high-frequency distortion, it should prevent that

31

either one of the transistors is ever cut off. The desired class-AB character­istic is shown in Fig. 18. In this section some examples of class-AB rail-to­rail output stages will be discussed.

'out neg 0 'out pos 'out--

Fig. 18. Desired class-AB transfer function.

Conventional bipolar output stages. such as in the JlA 741. have output tran­sistors. Qp and QN' connected in a common-collector configuration. as is shown in Fig. 19a. These output transistors are class-AB biased by D] and D2• These diodes keep the sum of the base-emitter voltages of the output transistors constant. the result is that the product of the push and pull cur­rent is constant. and is given by:

(16)

From (16) it can be concluded that neither one of the output transistors is cut off. Similar output stages with output transistors connected in a com­mon-drain configuration can be found in MOS technology.

A drawback of a common-collector output stage is that the maximum out­put voltage swing is limited to:

(17)

where Vbe is the base-emitter voltage of a bipolar transistor. As shown on page 4 this seriously degrades the dynamic range of the output stage. To overcome this problem the output transistors should be connected in a com­mon-emitter configuration. The class-AB biasing of the output transistors. Qp and QN' is schematically shown Fig. 19b. The diodes. DI and D2• together with the floating voltage sources. which have a value of Vsl2. keep the sum of the base-emitter voltages of the output transistors constant. In order to obtain a quiescent current in the output transistors which is inde-

32

Vee

lout -

Fig. 19a. Conventi01UlI Class-AB output stage.

Vin

Vee

V + s "2

Irl V + s "2

VEE

Fig. 19b. Rail-to-rail Class­AB output stage.

pendent of the supply voltage, the voltage Vs should be equal to the supply voltage. A similar discussion can be held for CMOS output stages.

Fig. 20 shows a first example of the principle depicted in Fig. 19b. The out­put transistors, Qp and QN' are biased by the diodes, D] and D2, and the coupling resistors, R] and R2. If the base currents of the output transistors are neglected, it can be concluded that the two in-phase input currents lin] and 1in2 generate equal voltages across R] and R2, respectively. Therefore the sum of the base-emitter voltages of the output transistors is approxi­mately constant. This circuit can operate on supply voltages as low as 0.9 V. Drawbacks of this circuit are the relatively large loss of signal current in the resistors and a quiescent current in the output transistors which is deter­mined by inaccurate resistors.

One problem can be overcome by directing the signal current through cas­codes, Q] and Q2, to the complementary output transistor which results in a higher gain, as is shown in Fig. 21. The inaccurate biasing due to the large resistors, however, remains.

If the resistors are eliminated from the circuit as shown Fig. 21, the circuit of Fig. 22 is obtained. The sum of the base-emitter voltages is kept constant by the two translinear loops [6]. The transistors Q] and Q2 form a loop with a very high resistance, which prevents a loss of signal current. The coupling of the class-AB circuit is so strong that one of the signal current-sources, lin] and lin2' will suffice to drive the output transistors. The only drawback

.--------.....,----..---fJ Vee

R1=20 k °1 )--J.--"-------+--~ Q p

'----------'----'----iD VEE

Fig. 20. Bipolar rail-to-rail output stage with resis­tive class-AB control.

'-----'----'-----'---fJVEE

Fig. 21. Bipolar rail-to-rail output stage with resistor coupledfeedforward class-AB control.

33

is that the circuit needs two stacked diodes which allows the circuit only to operate on supply voltages down to 1.8 V.

Also in CMOS, the circuit with two translinear loops, as is shown in Fig. 23, can be used [7]. The minimum allowable supply-voltage is deter­mined by the sum of the gate-source voltages of the output transistors. This

34

voltage can be between 1.6 V and 2.8 V depending on the process and on the maximum output current.

~-----T-------r------~~Vcc

Fig. 22. Bipolar rail-to-rail output stage with transistor coupled feedforward class-AB control .

.----------,.---------~----~--_fJ Voo

Vout

'-----------'L----------'------'-----9' V ss

Fig. 23. CMOS rail-to-rail output stage with transistor coupled feedforward class-AB control.

If an accurate class-AB control on a lower supply voltage is required, a feedback biased class-AB control should be used [3,8,9]. An example of such an class-AB control is shown in Fig. 24.

The transistors Q33 and Q34 measure the currents through the output tran­sistors QlJ and Q12' respectively. The resistors R34 and R35 convert these

Fig. 24. Bipolar feedback-biased class-AB output stage.

currents into voltages. First suppose that QJl is delivering the output cur­rent. The voltage across R35 is much larger than the voltage across R34• As a result the tail-current of Q34 and Q35 flows completely through Q34. Now the emitter voltage of Q34-Q35 reflects the minimum current. that is the cur­rent through the output transistor which is not delivering the output current. If a difference occurs between this emitter voltage and V R the differential amplifier Q3J and Q32 feeds a correction signal to the output transistors. In this way the minimum current of the output transistors is controlled. Now suppose that the output stage is in rest. The voltages across R35 and R36 are equal and therefore the current. 135. is equally divided over Q34 and Q35. The emitter-voltage of Q35 and Q34 reflects the quiescent current of the out­put transistors. Again. if a difference occurs between this voltage and VR• the differential amplifier feeds a correction signal to the output transistors. In this way. the quiescent current of the output transistors can be controlled. The same principle can be applied in CMOS. as is described in [5].

A modified CMOS feedback biased class-AB output stage. Mr M17• is shown in Fig. 25 [10]. In this AB control the decision pair and the feedback amplifier are combined. Mr M3• The output stage functions the same way as that shown in Fig. 24. The main advantage of this circuit is that the large resistors are replaced by smaller diode-connected transistors. MJl and MH . The minimum allowable supply voltage of this circuit is as low as 1.3 V. depending on process parameters.

36

117~ ~113

1"'1

11/12

Fig. 25. CMOS feedback-biased class-AB output stage. The feedback amplifier and decision pair are combined.

V. Bandwidth versus Power Supply

The bandwidth of a one stage amplifier is given by:

B=~ 21tCL

For a bipolar stage (18) can be written as:

Ie B = :---;-;-~

21tUTCL

Voo

Vo

(18)

(19)

If (19) is divided by the supply-power the following expression is obtained

B 1 1 (20)

It is obvious that the lower the supply voltage the higher the bandwidth-to­supply-power ratio.

For CMOS transistors operating in strong inversion the gm is given by:

(21)

where ).1 is the mobility of the charge carriers, Cox is the normalized oxide

37

capacitance. W is the width of a transistor. L is the length of a transistor and VTH is the threshold voltage. If (21) is substituted in (18). the following equation is obtained.

(22)

Dividing (22) by the supply power results in:

B 1 2 (23)

Comparing (20) and (23). it can be concluded that the bandwidth to supply­power ratio of a bipolar transistor is higher than that of a MOS stage. assuming that the supply voltages are the same. It should be noted that the gate-source voltage of a MOS transistor operating in strong inversion has to be more than 6VT above its threshold voltage.

The bandwidth of a two-stage amplifier is equal to the geometric mean of the bandwidths of the stages [11]. Because the circuit has two dominant poles stability problems are likely to occur in a feedback configuration. To avoid closed-loop instability. the open-loop phase margin should be 60°. The result of this is a loss of a factor two in the bandwidth. Thus. the band­width is given by:

(24)

For the bipolar version two-stage operational amplifier. as shown in Fig. 26. (24) can be written as:

(25)

If it is assumed that CL is the input capacitance of the next stage. the band­width has a broad optimum for:

lEi - = 1 (26) IEE2

38

Substituting (26) in (25) and dividing by the supply power. we obtain:

B _ 1 1 Psup - 41tVTVsup jC2CL

(27)

For CMOS the bandwidth and bandwidth supply-power ratio are:

W J,lCoxL (VGS - VTH) B = ------~==~---

21tjC2CL (28)

B 1 1 Psup = 41t(VGS-VTH)VsupjC2CL

(29)

Again it can be concluded that the bandwidth of a bipolar amplifier is larger than that of a MOS amplifier.

In Fig. 26 and Fig. 27 the splitting of the poles to obtain a 600 phase margin is shown. The poles can be splitted by either inserting a Miller R~M net­work. or a by inserting a parallel RpC p network.

~--------------~---evcc

'11 CURRENT MIRROR

I Cpl C2

_.L_ -T­

I I I I

.J.. R I I 'IEE2 p~J

I ~------~--~--~----VEE

Fig. 26. Two-stage amplifier with parallel compen­sation or Miller compensation.

The advantage of the parallel network has the advantage that the maximum

39

bandwidth, according to (24), can be obtained. The bandwidth can even be larger than that of a one stage amplifier, because the internal capacitor C2 can be much smaller than the load capacitor, C L- However, due to process variations the zero never cancels the pole complete, resulting in a pole-zero doublet. This pole-zero doublet results in slow settling components, which can only be allowed in some applications. If the output transistor is class-AB biased the resistor Rp has to change as function of the current through the output transistors, which is difficult to achieve.

0) • 0) 0) -1 1 2 CO2 (rad/sec) Fig. 27. Bode-plot of the two-stage amplifier with

Miller compensation.

The advantage of the Miller compensation is that no pole-zero doublets occur in the transfer of the amplifier. A drawback is that the bandwidth of the opamp is limited to that of the output stage. In general this bandwidth is much lower than the maximum achievable bandwidth as given by (24).

VI. Gain and Frequency Compensation

The gain of an amplifier can be increased by either cascading more stages or by improving each stage separately. In this section several compensation methods of multi-stage amplifiers are discussed. Further, it is shown how to improve a gain stage. Several solutions for bipolar. CMOS and BiCMOS stage are discussed.

A simple method to compensate a three-stage amplifier is the nested Miller compensation. as is shown in Fig. 28 [3.12]. The amplifier consists of an input stage, Q3rQ32. an intermediate stage, Q2J-Q22' and an output stage. Q/. Each stage has a dominant pole at its output. The magnitude plot is shown in Fig. 29.

The output and intermediate stage can be conceived as a two stage ampli-

40

~--~--------~~----------------~-------4Vcc

r---+---~---------'----T-~~r-~V~

Cm2

I

+ I I I I Gm2 I I I I I I I

~1 I C + J~ C i'i C1 R •• --- 3 VR R : : --- 2 R', _ ... -3 •• -T- 2 •• -T- 1 •• -T-.,. I .,. I .,. I

~----~~~--~-----L----~----~--~~~VEE

Fig. 28. Three-stage amplifier with nested Miller compensation.

t Voltage

gain (dB)

frequency (Hz) -

Fig. 29. The open-loop gain o/the three-stage amplifier with nested Miller compensation.

fier with two dominant poles, /} and h. The capacitor CM} closes the first Miller loop which splits h and h to h' and h', respectively. The pole h' is 3 dB below the unity-gain frequency, as is shown in Fig. 29. Therefore, the intermediate and output stage can now be conceived as one stage with one dominant pole h'. The Miller splitting can now be repeated by inserting CM2• This capacitor splits apart the polesfJ andh', resulting in a dominant pole in h". This nesting of capacitors is relatively simple and can be

41

repeated. A drawback is that each time a Miller capacitor is inserted the unity-gain frequency decreases a factor two.

The factor two loss in unity-gain bandwidth can be precluded by using the ~-T--"'-T--"'--"'--"'--"'--"'--"'-T--"'~--"'--"'--"'--"'--"'~--"'--"'~V~

,~ ,~

I I

Q33 Oal C:M I

I I I I I I + I I I I

Vin I I I I I I I I

Ra~i oJ. IC C 1 I, R' , _.L_ 2 Rl , , 211 -T-.... 'I. I

I I I

VEE

Fig. 30. Three-stage amplifier with multi path nested Miller compensation.

Multipath Nested Miller compensation structure. as is shown in Fig. 30 [13.14.15]. The circuit consists of a three stage Nested Miller opamp and an additional input stage. Q33"Q34' This input stage bypasses the intermedi­ate stage. Q21-Q22' The result is an amplifier which has a three-stage gain path and a two-stage high-frequency path. Fig.31 shows the frequency characteristic of the Multipath Nested Miller compensation. The gain and the high frequency path can be easily matched by making the unity-gain frequencies of both paths equal. Hence:

gm3l gm32 CMl - CM2

(30)

This matching of transconductances and capacitances can be very accu­rately.

Another way of increasing the gain is to improve every single stage. A well-known example is to improve the current gain of a transistor by using the Darlington configuration. as is shown in Fig. 32. The circuit has two disadvantages. Firstly. it consists of two stacked base-emitter voltages

42

t Voltage Gain (dB)

f " ____ .... 2

'".... . / gain path ,..,¥

.... , " .... ,

'"

frequency (Hz) -...

", high-frequency path

.. f I 1

Fig. 31. Frequency response of the three-stage amplifier with mUltipath nested Miller compensation.

which need a minimum supply voltage of 1.8 V. Secondly, the base-emitter capacitor of the output transistor, QIt loads the emitter of Q2' resulting in a second pole. Using the Miller compensation around the whole stage, the second pole causes peaking, as is shown in Fig. 33. This can be suppressed by inserting an additional Miller capacitor CMO [4]. This results in a factor two reduction of the unity-gain frequency.

Fig. 32. Darlington output stage.

The current gain of a bipolar transistors can also be increased by using the Widlar stage, as is shown in Fig. 34 [16]. It consists oftwo meandered Dar­lington transistors and a current booster, Q4-Q6' This stage does not have stacked base-emitter voltages which allows it to operate on supply-voltages down to 0.9 V. A disadvantage is that Miller compensation around the whole stage makes the circuit to oscillate unless the bandwidth is strongly reduced by inserting an additional capacitor C MO'

t I~I (log) i----~'kI_~__t"""'-----

m(log)-

Fig. 33. Frequency response o/the Darlington output stage.

Fig. 34. Widlar output stage.

43

The problems of the Darlington and the Widlar output stage can be over­come by using the Multipath driven output stage, as is shown in Fig. 35. The high-frequency path consists of a direct driven output transistor, Qj. The gain path consists of gain stage, Q2' and a current mirror, Q3-Q4' The Multipath Nested output stage combines the high bandwidth of a single transistor with the current-gain of a two cascaded transistors. The circuit is able to operate on supply voltages down to 0.9 V.

To boost the voltage gain of CMOS transistors, they can be cascoded, as is shown in Fig. 36. The folded cascodes, MjS-Mj8' improve the gain of the circuit. The gain can even be further increased by boosting the cascode transistors [17]. The circuit is able to operate on supply voltages as low as 1.6 V.

44

L-____ L..-_-4 VEE

Fig. 35. Multipath driven output stage with nested Miller com­pensation

v Fig. 36. Cascoded CMOS rail-to-rail output stage with feedback-biased ss

class-AB control.

BiCMOS offers new possibilities for low-voltage low-power design. The large current-gain of MOS transistors can be combined with the large gm of bipolar transistors.

An example is shown in Fig. 37, the CMOS transistor, Mj> tremendously boosts the current gain of the bipolar output transistor, Qj. The high fre­quency behavior of this circuit is even worse as the Darlington stage, as shown Fig. 32. The minimum supply voltage is also larger than the Darling­ton stage.

45

r--------flvpp

r--~---r---r-4Vwt Cm1 C m2 J

I

Fig. 37. BiCMOS Darlington stage

A much better frequency behavior is obtained with the two-stage Multipath configuration as shown in Fig. 38. The circuit combines the large gm' and therefore the large bandwidth, of a direct driven bipolar output transistor, Qb and the large current gain of a MOS transistor, MI' The circuit is able to function on supply voltages down to 0.9 V.

r-----r---__ vpp

~--~-~---~-~--VNN

Fig. 38. BiCMOS multi path driven output stage

VII. Conclusions

The maximum dynamic range of low-voltage low-power amplifiers is squeezed between the low supply-voltages and the larger thennal noise voltages caused by the lower supply currents. To obtain the maximum

46

dynamic range the input and output stages should be able to handle rail-to­rail signal voltages. Bipolar and CMOS rail-to-rail input stages with con­stant-gm have been presented. Further, voltage and current efficient rail-to­rail class-AB output stages have been discussed.

The bandwidth of low-power amplifiers is limited by the low-currents. To obtain the maximum bandwidth several frequency compensation tech­niques, such as the parallel, Nested Miller and Multipath Nested Miller fre­quency compensation, are discussed. It is shown that the Multipath Miller frequency compensation technique is very effective to obtain a stable amplifier with a large bandwidth-to-power ratio.

The gain of amplifiers can be increased by either cascading or by improv­ing each stage. The current gain of a single bipolar stage can be improved by using Darlington or Widlar types of structures. The voltage gain of a MOS stage can be increased by applying cascodes to the circuit. In BiC­MOS technology, the gain can be improved by combining the high current gain of a MOS transistor and the large transconductance of a bipolar tran­sistor.

47

References

[I] G. Groenewold, "Optimal Dynamic Range Integrated Continuous-TIme Filters", Ph.D. Thesis, Delft University of Technology, Delft, The Netherlands, 1992.

[2] I.H. Huijsing and R.I. v.d. Plassche, "Differential Amplifier with Rail-to-Rail Input Capa­bility and Constant Transconductance", U.S. Appl. No. 4,555,673, Nov. 26,1985.

[3] I.H. Huijsing and D. Linebarger, "Low-Voltage Operational Amplifier with Rail-to-Rail Input and Output Ranges", IEEE I. of Solid-State Circuits, Vol SC-20, No.6, Dec. 1985, pp. 1144-1150.

[4] I. Fonderie, M.M. Maris, E.I. Schnitger, I.H. Huijsing, "l-V Operational Amplifier with Rail-to-Rail input and output Ranges"

[5] R. Hogervorst, R.I. Wiegerink, P.A.L. de long, 1. Fonderie, R.F. Wassenaar, I.H. Huijs­ing, "CMOS Low-Voltage Operational Amplifiers with constant-gm Rail-to-Rail input stage", Proc. IEEE International Symposium on Circuits and Systems, San Diego, May 10-13,1992,pp.2876-2879.

[6] W.C.M. Renirie, I.H. Huijsing, "Simplified Class-AB Control Circuits for Bipolar Rail­to-Rail Output Stages of Operational Amplifiers", Proc. European Solid-State Circuits Conference, Sept. 21-23, 1992, pp. 183-186.

[7] D.M. Montecelli, "A quad CMOS single-supply Opamp with rail-to-rail output swing", IEEE I. of Solid-State Circuits, Vol. SC-21, Dec. 1986, pp. 1026-1034.

[8] I.H. Huijsing and F. Tol, "Monolithic Operational Amplifier Design with improved HF behavior", IEEE I. Solid-State Circuits, Vol. SC-ll, No.2, April 1976, pp. 323-328.

[9] E. Seevinck, W. de lager, P. Buitendijk, " A Low-Distortion Output Stage with improved stability for monolithic power amplifiers", IEEE I. Solid-State Circuits, Vol. SC-23, Iune 1988, pp. 794-801.

[10] R.G.H. Eschauzier, R. Hogervorst, I.H. Huijsing, "A Programmable 1.5 V CMOS Class­AB Operational Amplifier with Hybrid Nested Miller Compensation for 120 dB Gain and 6 MHz UGF', in Digest IEEE International Solid-State Circuits Conference, February 16-18,1994,pp.246-247.

[11] E.M. Cherry and D.E. Hooper, "Amplifying Devices and Low-Pass Amplifier Design", Iohn Wiley and Sons Inc., New York, 1988, pp. 690-701.

[12] I.H. Huijsing, "Multi-Stage Amplifier with Capacitive Nesting for Frequency Compensa­tion", U.S. Patent, Appl. No. 4,559,502, Dec. 17,1985.

[13] I. Fonderie and 1.H. Huijsing, "Operational Amplifier with I-V Rail-to-Rail Multipath­Driven Output Stage", IEEE I. of Solid-State Circuits, vol. 26, No. 12, Dec. 1991, pp. 1817-1824.

[14] I.H. Huijsing and M.1. Fonderie, "Multi-stage amplifier with capacitive nesting and multi-path forward feeding for frequency compensation", U.S. Patent, Appl. No. 5,155,447, Oct. 4, 1992.

[15] R.G.H. Eschauzier, L.P.T. Kerklaan and 1.H. Huijsing, "A 100-MHz 100-dB Operational Amplifier with Multipath Nested Miller Compensation Structure", IEEE I. Solid-State Circuits, Vol. 27, No. 12, Dec. 1992, pp. 1709-1717.

[16] R.I. Widlar, "Low voltage techniques", IEEE 1. of Solid-State Circuits, Vol. SC-13, pp. 838-846, Dec. 1978.

[17] K. Bult and G.I.G.M. Geelen, "A Fast-Settling CMOS Opamp with 90-dB DC-Gain and 116 MHz Unity-Gain Frequency", in Digest IEEE International Solid-State Circuits Con­ference, February 1990, pp. 108-109.

[18] I.H. Huijsing, R. Hogervorst, I. Fonderie, KJ. de Langen, B.I. van den Dool and G. Groenewold, "Low-Voltage Analog Signal Processing", Chapter 4 of: Ismail-Fiez: "Ana­log VLSI Signal and Information Processing", McGraw-Hill, 1993.

Design Considerations for High-Speed Low-Power Low-Voltage CMOS Analog-to-Digital Converters

Thomas B. Cho, David W. Cline, Cormac S.G. Conroy, and Paul R. Gray

Department of Electrical Engineering and Computer Sciences,

University of California at Berkeley

Abstract

This paper describes architecture and circuit approaches for

the design of high-speed, low-power, pipelined analog-to-digital

converters in CMOS. The role of pipeline architectures in high-­

speed conversion is first discussed. Then a number of design

issues related to power optimization in pipeline AID converters

are discussed, including power minimization in switched capaci­

tor gain blocks operated on low supply voltages, implementation

of transmission gates on low voltages, and capacitor scaling in

pipelines. The application of these approaches is illustrated using

results from an experimental IO-bit 20-MS/s pipeline AID con­

verter implemented in 1.2-J.l.m CMOS technology that achieves a

power dissipation of 35 mW at full speed operation.

49

RJ. van de Plauche fit al. (ed6.), Analog Circuit Duign, 49-71. o 1995 Khlwer Academic Publishen.

50

1. Introduction

The realization of signal sampling and quantization at high sample rates

with low power dissipation is an important goal in many applications, includ­

ing portable video devices such as camcorders, personal communication

devices such as wireless LAN transceivers, in the read channels of magnetic

storage devices using digital data detection, and many others. This paper

describes architecture and circuit approaches for the design of high-speed,

low-power pipeline analog-to-digital converters in CMOS. Here the term high

speed is taken to imply sampling rates above 1 Mhz. In the first section the dif­

ferent conversion techniques applicable in this range of sample rates is dis­

cussed. Following that the particular problems associated with power

minimization in video-rate pipeline ADCs is discussed. These include optimi­

zation of capacitor sizes, design of low-voltage transmission gates, and opti­

mization of switched capacitor gain blocks and operational amplifiers for

minimum power dissipation. As an example of the application of these tech­

niques, the design of a power-optimized lO-bit pipeline AID converter (ADC)

that achieves =1.67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described.

2. Techniques for CMOS Video-Rate AID Conversion

Analog-to-digital conversion techniques can be categorized in many ways.

One convenient means of comparing techniques is to examine the number of

"analog clock cycles" required to produce one effective output sample of the

signal being quantized. Here an analog clock cycle usually involves analog

operations such as comparison, DI A converter settling, operational amplifier

settling, and so forth. The actual settling time required is of course both tech­

nology dependent and implementation dependent, but the number of cycles

required for an effective conversion is a convenient means of comparison.

In Fig. 1, several of the widely used AID conversion techniques are com-

51

pared qualitatively on this basis. To take one example, at the 12 bit level serial

and integrating conversion techniques require several thousand clock cycles.

Sigma delta oversampling converters require on the order of 64, depending on

the order of the loop, although overs amp ling ratios as low as 16 have been

reported for very high-order cases. Successive approximation requires about

12 clocks, and flash, half-flash, and pipelined ADCs require on the order of

one clock cycle. For sampling rates in the 5Msample/sec range and above,

flash, multi-step flash, and pipelined approaches are required to achieve the

throughput rates needed in technologies readily available today.

14-

Bits 12-of.Resol 10 _ utlon

a-6_

Flash, Pipeline t=1

/

Succs. Approx t=n

2nd order Sigma-delta 1-6it V t=2(O.4n+1)

Clock Cycles per output sample

Fig. 1 Qualitative Comparison of AID Conversion Techniques

S2

From a power dissipation perspective, full flash ADCs are attractive only at

low resolution levels where the number of comparators is small and their off­

set is non-critical, allowing the use of fully dynamic implementations. At res­

olutions in the 8-12 bit range, the only practical options for low power

dissipation are multistep flash and pipeline configurations. Multistep flash

implementations have been used very successfully in low-power applications at the to-bit level [6]. Pipelines are also attractive [1][2][3] and have the

potential advantages of inherent single-path sampling of the signal, giving

good high-frequency effective bit performance, and the capability of using non-critical purely dynamic comparators because of the amplification of the

signal in the pipeline coupled with the use of digital correction. This paper

will concentrate on the design of pipeline ADCs for low-power applications.

3. Design Considerations for Low-Power Pipeline ADCs

A block diagram of a typical pipeline AID converter is shown in Fig. 2. It

Vln

DlA

c VI,... .....

. J, c

Fig. 2 A typical pipeline AID converter Implementation.

53

consists of a cascade of N identical stages in which each stage performs a

coarse quantization (usually 1 to 3 bits), a D/A function on the quantization

result, subtraction, and amplification of the remainder. A sample/hold (S/H)

function in each stage allows all stages to operate concurrently, giving very

high throughput. Fig. 2 illustrates the particular configuration of interest here

in which the DI A, subtraction, amplification, and SIH functions are performed

by a switched capacitor circuit.

In CMOS implementations, the D/A function is most often performed by

an array of equal capacitors. When the input signal is applied, each stage sam­

ples and quantizes the signal to its per-stage resolution of B+ 1 bits, subtracts

the quantized analog voltage from the signal by connecting the bottom plate of

each capacitor to ±Vref or 0, and passes the residue to the next stage with

amplification for finer conversion. One extra bit resolved in the flash AID block allows the comparator offset to be within ±Vref 12B+l as in [1][2]. In

the experimental prototype[3], the per-stage resolution (B+ 1) is chosen to be 2

bits, giving one bit of effective resolution after digital correction. The input

signal to the first stage is sampled simultaneously by the switched capacitor

amplifier and by the dynamic comparators of the flash AID. This is made pos­

sible by the fact that digital correction allows comparator errors up to 114 full

scale without degradation of linearity or SNR. The overall pipeline contains 9

2-bit ft.ash quantizers and 8 interstage amplifiers.

In traditional high-speed flash, multi-step flash, and pipeline ADCs, the

principal power .. dissipating elements have been the comparators (because of

their large number and required low offset and high speed), the interstage gain

blocks, and the resistor string that was typically used as a DAC level genera­

tor. However, dramatic reductions in the power dissipation of conventional

converters can be achieved by making modifications to the traditional imple­

mentation.

Perhaps the most important single factor is that by taking advantage of the

54

error correction capability inherent in pipelines, the effect of comparator

input-referred errors on the quantization result can be greatly reduced. This in

tum allows for the use of purely dynamic circuits to perform the comparator

function, despite the fact that such dynamic latches can have tens or hundreds

of millivolts of offset voltage.

A second key factor is the replacement of the resistive DACllevel generator

function by either a switched capacitor dynamic level shift function as shown

in the example of Fig. 2. This eliminates the quiescent power of the resistors

string but of course introduces the (much smaller) additional dynamic dissi­

pation of capacitive DAC.

Given these power reductions the principal power dissipating element

becomes the interstage gain block, and in particular the dissipation of the

operational amplifiers used to implement the block. This dissipation is tied

directly to the value of the sampling and DAC level generation capacitors that

must be used in each stage of the pipeline, which in tum is dictated by funda­

mental kT/C considerations. The power dissipation required for dynamic

switching of these capacitors during conversion is typically orders of magni­

tude lower than that actually dissipated by the operational amplifiers used. As

a result, optimization of the design of the interstage gain block amplifiers is

critically important for power reduction in the overall implementation. Opti­

mization of the circuit design together with optimum choice of power supply

voltage can achieve large reductions, and this will be discussed in the follow­

ing sections.

Aspects of these design trade-off are discussed in more detail in the fol­

lowing sections. In each case, results from an experimental pipeline ADC [3]

are shown for illustration.

3.1 Operation at Lowered Power Supply Voltage

From a fundamental viewpoint, operation at reduced power supply volt-

55

ages is not advantageous from a power dissipation perspective for analog cir­

cuits whose dynamic range is kT/C limited and whose power dissipation is

dominated by CV2 dynamic power in the capacitors storing analog state vari­

ables. In this case in order to preserve dynamic range capacitor values must be

increased as the inverse square of the power supply voltage, precisely cancel­

ing any advantage that would accrue in dynamic power. For the more typical

case of "class A" operation, where the capacitors storing state variables are

driven by conventional operational amplifiers, the dissipation in the opera­

tional amplifiers tends to dominate and tends to vary linearly with capacitor

size for a given settling time requirement. In this case operation at lower sup­

ply voltage would appear to be strongly disadvantageous, since overall power

tends to increase with decreasing supply voltage.

Balanced against these fundamental considerations is the fact that few

actual ADCs described to date are dominated by the power dissipation associ­

ated with switching or driving of capacitive elements whose kT/C noise limits

dynamic range. Virtually all of the other power dissipation contributors benefit

from reduced supply voltages, and at least in the 8-10 bit resolution range a

net power reduction can be achieved by reducing the supply voltage to 3 volts.

A more important motivation for doing this is the fact that in many systems

the digital portions of large mixed-signal chips, within which the ADC will

reside as a cell, will be driven to 3.3 volts and perhaps eventually to 1.5 volts

by a combination of technology scaling and power minimization in the digital

sections.

Operation at lowered supply voltages introduces two important practical

problems. First, the operation of the gain block depends on realization of a rel­

atively high performance differential operational amplifier. Second, the imple­

mentation using switched capacitor circuitry requires transmission gates with

near rail-to-rail operation, presenting mounting difficulties at lower supply

voltages. These two issues are discussed in the next section.

56

Design of Low-Voltage Switched-Capacitor Gain Blocks

Two typical implementations of switched capacitor gain blocks are shown

in Fig. 3. In a typical pipeline implementation, the capacitor Cs is made up of

capacitive segments and performs the DAC function as well as the sample/­

hold function. Virtually all CMOS pipeline ADCs intended for high speed

applications use an interstage gain of 2 or 4, with 2 being the most common

CF

"'---"1------""". • ...... - (a) AcL = Cs/CF

Vout >-..... -

+ .. -- (b) ACL = 1+Cs/CF

Fig. 3 Two common SC gain stage configurations; Cs and CF are the sampling and feedback capacitances, respectively; AcL is the closed-loop gain. For simplicity, these figures show single-ended implementations.

choice. This relatively low value, corresponding to a net of one bit per stage of

resolution after digital correction, allows the best settling time in a given tech­

nology to be achieved with a relatively simple operational amplifier. The value

of Cs is determined by the value of kT/C noise that can be tolerated without

excessive idle channel noise in the ADC. For a lO-bit ADC operating with a

I-volt peak: input signal, a value of O.5pF gives for example a kT/C equivalent

57

voltage noise of about 90u V per sample, corresponding to about O.l1sb. That

is about the maximum level that can be tolerated in order to maintain a quiet

output code when the input is biased mid-tread.

The design of operational amplifiers for this application differs from the

general-purpose case. For each amplifier in the pipeline, the source capaci­

tance, load capacitance, and feedback capacitances are known for each phase

of the clock. It is also assumed that the desired sampling rate is known. Once

the basic configuration is chosen, optimization can be achieved by choice of

devices sizes, compensation capacitors, and bias currents so as to minimize

power dissipation at a fixed sampling rate. This process is perhaps best illus­

trated by the example of telescopic and folded-cascode operational amplifier,

illustrated in Fig. 4. While these amplifiers do have non-dominant poles con­

tributed by the common-gate devices in the signal path, these poles are often

Folded Cascode Unfolded Cascode (Telescopic)

Fig. 4 Folded Cascode and Telescopic Amplifier Configurations

well beyond the unity-gain frequency and not significant for the closed loop

gains used in pipelines. Also, the series resistance of the transmission gates

used to switch the various capacitances in the circuit complicate the transient

response. However, at least to a first approximation the trade-off between

power dissipation and settling time for this class of amplifier can be ana­

lyzed using the single time constant circuit shown in Fig 5. Here the three

58

capacitances represent the combinations of the capacitors explicitly included

in the circuit plus the parasitics associated with the capacitors and the active

devices.

Fig. 5 Single-time-constant Equivalent Circuit for Folded Cascode, OTA connected in a gain block circuit.

Under these assumptions, the only variables available for optimization are

the device bias current and the device length and width. If speed is fixed and

power is minimized, the result is that the optimum transistor size is the short­

est channel length that can be accommodated given the voltage gain require­

ment, and a device width such that its Cgs is equal to the effective capacitance

connected to it in the circuit (i.e. the source capacitance plus the series combi­

nation of the feedback and load capacitances).

CpCL Cgs = Cs + Cp + CL

The above result is obtained by assuming square law MOS device charac­

teristics and neglecting the output parasitic capacitance of the amplifier. Gen­

erally similar but more complex results are obtained when these assumptions

are not made. With this design choice the relationship between the time con­

stant and the device unity-current-gain frequency roT of the MOS transistor

becomes:

59

where 't is the desired time constant of the circuit, CL is the load capaci­

tance, and CF is the feedback capacitance. The ratio of these two capacitors is

in effect the "charge gain" of the circuit since it represents the charge delivered

to the load per unit of charge inserted into the summing node.

The power dissipation that corresponds to this optimum device size for

the telescopic op amp case is:

It is worth noting that the analysis could be redone with power fixed with

the goal of maximizing the speed. The result from doing the analysis this way

is the same as the result above. Thus, minimizing power for fixed speed is

equivalent to maximizing speed for fixed power.

For an example case of load capacitance of I pF, source capacitance of 2pF,

feedback capacitance of IpF, effective channel length of 0.8 micron, and

power supply voltage of 3 volts, effective channel mobility of about

500cm2N-sec, and optimum time constant of 400ps, the power dissipation of

the optimum gain block is approximately lOmW assuming a telescopic opera­

tional amplifier. A time constant of 400ps would allow a settling time on the

order of 5ns, and a clocking rate of 50 to 100Msamples/sec. As can be seen

from the functional dependence of the above relations on technology and on

source and load capacitances, power dissipation is dramatically reduced by

scaling of the channel length of the CMOS device, which increases the IDr, and by the use of smaller capacitances in the circuit.

Practical degradations such as additional parasitic capacitances, the effect

60

of the neglected non-dominant poles, and other effects will result in somewhat

poorer settling time performance. In the case of single-poly technologies

where the parasitic capacitances are comparable with the source, feedback,

and load capacitances themselves, an additional degradation of about 50% in

speed results. Perhaps the most difficult issue in the actual gain block amplifier design is

insuring adequate voltage gain and signal swing. For lO-bit resolution in a 1

bit/stage pipeline, voltage gains greater than 60 dB are needed in the first stage

operational amplifier. Achieving this in a telescopic op amp requires a gmro for

the individual devices of about 80. That in tum requires either very long chan­

nellengths or very small V gs-VT values to achieve. Both alternatives degrade

the amplifier settling time behavior too much to be practical for high-speed

pipeline applications.

A number of alternatives exist for improving the gain of the amplifier. One

would be to use a two-stage configuration with pole-split compensation, with

one of the two stages cascoded. However, because of the non-dominant pole

resulting from the load capacitance and the necessity of driving a compensa­

tion capacitor, a substantial degradation in achievable bandwidth and settling

time at a given power dissipation results. Optimization of two-stage and

three-stage miller compensated amplifiers is a critically important problem,

because they will be needed at lower supply voltages and also at higher ADC

resolution levels. However, for lObit resolution at 3.3 volts, another viable

alternative is to use the telescopic operational amplifier together with a low-­

gain, wideband buffer amplifier preceding the amplifier to increase the gain by

a factor of two to three. While this does add another stage with its power dissi­

pation, it preserves the very desirable property of the cascode amplifier that

the load capacitance is also the compensation capacitance. The low-gain

preamplifier in effect increases the gm of the transconductance stage, but adds

a non-dominant pole due to the input capacitance of the transconductance

61

stage.

This configuration was utilized in the pipeline prototype ADC we use as an

example in this paper. The circuit diagram of this amplifier is shown in Fig. 6.

Voltage gain is also enhanced by the inclusion of series feedback gain-boost

amplifiers [4] in the PMOS current sources. These amplifiers are capacitively

coupled into the signal path using level shift capacitors C I and C2 which are

initialized by closing switches SWI and SW2. The common-mode feedback is

also capacitive through C3 and C4.

Main

Amplifier

Gain·Boost

A"l'lifier ............

C1

Vout+

Veld = 3 .3V

C2

I Vdd =3.3V

Bias1

Veld =3.3V

I j

Fig. 6 Op amp with gain-boost amplifier.

In the gain-of-2 configuration shown in Fig. 3(b), this amplifier achieved

a simulated 0.1 % settling time of about 17nsec with CS=O.39pF, CF= 0.39pF

and external load of 1.8 pF. Power dissipation of the first stage op amp is

62

4.8mW and from experimental results it can be deduced that the voltage gain

is greater than 6OdB.

Implementation of full-swing transmission gates at low voltages

At 3.3 volt supplies the implementation of transmission gates of reason­

able performance is problematical. The inclusion of an extra zero-threshold

transistor in the process is an attractive alternative but adds process complex­

ity. Another alternative is to simply use a dynamic circuit to boost the clock

drive of NMOS transistors to provide the rail-to-rail transmission gate func­

tion. This approach will become progressively more difficult at lower and

lower supply voltages, but at 3.3 volts using a 5-volt-capable technology it is a

relatively straightforward solution. The particular implementation of the

charge pump used in this instance is illustrated in fig. 7(a) [5].

Fig. 7 (a) A charge pump circuit and. (b) high voltage generator for the well of M1.

63

By applying a square wave input signal of 3.3 V, C 1 and C2 are self-­

charged to 3.3 V, and an inverted square wave output of =5 V is generated.

Because this gate voltage overdrive is much higher than the signal cornmon-­mode voltage (=Vddl2), sampling switches are implemented with NMOS

switches only, and the parasitic capacitance from PMOS is eliminated. Fig. 7(b) shows the bias voltage generator for the n-well of M 1 to prevent latch up.

An important aspect of the design is the avoidance of crosstalk through

gate clock lines. During the clock phase when the clock lines are in the high

state, they are driven from a source capacitance that is simply the boost capac­

itor itself, a high impedance. If two transmission gates share the same clock

line, then in this state crosstalk can occur through the two gate capacitances

because of the high common impedance. For this reason a separate driver is used for each transmission gate.

3.2 Optimum Capacitor Sizing in Pipeline ADCs

A fundamental noise source present in AID converters is thermal noise, and

the magnitude of this noise is a function of the sampling capacitor size

(a2thermal- kT/C). In order to reduce the power dissipation, the sampling

capacitor must be reduced, since it becomes the load capacitance of the previ­ous stage and the size of the amplifier is proportional to that of the capacitor.

Noting that the stage requirements on the speed and accuracy become less

stringent as the stage resolution decreases down the pipeline, stages in the

later part of the pipeline can be scaled down. Near the front end, the sizes of

sampling capacitors and op amps are determined by the noise floor, and

toward the end of the pipeline, parasitic capacitances begin to dominate, and

so settling time requirements determine the size of each stage.

The optimization of capacitor sizes through the pipeline is a complex opti­

mization task, since the later stages contribute to both power dissipation and

noise depending on their capacitor sizes. Such an optimization was carried out

64

for the example pipeline discussed here. The result is summarized in Fig. 8,

where normalized op amp bias currents of each stage are shown. Through this

optimization process, the static power dissipation can be reduced by about

50% relative to the dissipation if all stages are identical.

Iblas;'lblas

-+.:o-~-o------------------

-~c__.- -.- - .- ----- ----- ---

Ith stage

Fig. 8 Normalized bias current of each stage.

3.3 Self-Calibration of Power-Optimized Pipeline ADCs

One important implication of the use of small capacitors in the first three

stages is that the 0.1 % capacitor matching required in the 01 A capacitors

required for 10 bit INL will not be achieved in the as-fabricated state. Fortu­

nately, a number of techniques have evolved for calibrating the linearity of

pipeline AID converters. These include analog-based techniques [2] and digi­

tal-based techniques [7]. In the experimental prototype AOC, calibration cir­

cuitry has been incorporated into the first three stages to remove OAC

mismatch errors.

65

3.4 Dynamic Comparators

In most traditional high resolution AID converters, precision comparators

consume dc power since low-offset pre-amp stages are required. However, a

pipelined configuration using digital correction (Le., overrange detection or

redundancy) offers major advantages in achieving lower power dissipation

since the error from a large comparator offset in the flash AID section can be

easily compensated. Thus, simple dynamic latches can be used to implement

the comparators in the low-resolution flash AID converter thereby eliminating

dc power dissipation.

The use of purely dynamic comparators introduces the additional problem

of generating the levels for comparison in a power-efficient way. The tradi­

tional approach to this, using resistive dividers, consumes high power. A sec­

ond approach would be to use capacitive voltage dividers, but that also

consumes significant dynamic power.

In the 1 bit/stage pipeline implementation, a 1.5 bit (Le. two levels) ADC is

required at each stage. Two relatively noncritical comparator levels must be

generated; comparator offsets up to ±250 m V can be tolerated for a reference

voltage of 1 V. An attractive alternative, made possible by this large error tol­

erance on the decision levels, is to use triode-region devices to offset the

threshold of the dynamic comparators by the requisite amount, as shown in

Fig. 9. In this comparator, transistors MI-M4 operate as variable resistors, and

the comparator decision threshold occurs when the effective on resistance of

M 1 in parallel with M2 matches the effective on resistance of M3 in parallel

with M4. Thus the comparator threshold is set by simply applying the desired

differential voltage to M 1 and M4. In the experimental prototype this

approach to comparator implementation was taken.

66

latch I reset

Vout-

Vref-

Fig. 9 Dynamic comparator with integral threshold setting

67

3.5 Experimental Results from Prototype ADC

The experimental prototype was fabricated in a 1.2-llm, double-poly, dou­

ble-metal CMOS technology. Chip area not including the pad ring is 3.2 mm

x 3.3 mm. A die photo is shown in Fig. 10.

Fig. 10 Die photo.

68

All measurements were made at room temperature and with a 3.3 volt sup­

ply. In Fig. 11, measured SNDR is plotted for 100kHz and 10 MHz input fre­

quencies at 20-MS/s conversion rate. The peak SNDR is 59.1 dB for 100 kHz

input sine wave, which is higher than that of a 0.8-J.1m AID converter

described in [6].

SNOR(dB)

!

60

ss so

I ~~/ , i ~/j ,- ---! P' i ideal-',. . 1100kHZ --

30 ..&1.'/' 10 MHz .......

2S ,./~ 1 -----r-' " ".' 20 '" ;

45

40

35

-40 ·30 -20 -10 o Inpu,le.el (dB)

Fig. 11 SNDR versus input signal level.

In Fig. 12, measured differential nonlinearity (DNL) and integral nonlin­

earity (INL) vs. input code are plotted. The magnitude of the maximum DNL

and INL are 0.5 LSB and 0.6 LSB, respectively.

(LSB)

1.0

O,S

0.0

-0.5

-1.0 0

(LSB) (I)

1.0

o.s 0.0

·O.s · 1.0

0

Fig. 12 (a) DNL and (b) INL.

30

20

15

10

3

Power(mW)

2 10 20

F. (MSI.)

Fig. 13 Power versus sampling frequency.

69

Fig. 13 shows the measured power consumption vs. the sampling fre­

quency on a log-log scale. The op amp bias current is controlled by one master

bias current source, and in this experiment the bias current was varied exter­

nally as a function on sampling rate. At reduced bias current and a sampling

frequency of 1 MS/s, the power consumption was 2.8 mW with SNDR of 58

dB.

Additional performance measurements are summarized in Table 1.

4. Summary and Discussion

Optimization of circuit and architecture of pipeline ADCs can yield major

improvements in power dissipation. It appears likely that further power reduc­

tions are possible through a number of approaches. In the example discussed

here, the internal voltage swings were only 1 volt due to the limited swing of

the operational amplifiers. The use of improved amplifiers with better swing

will allow major improvements in power dissipation. It is unclear however

70

whether the use of multistage pole-split amplifiers, the simplest way of

achieving good output swing, will result in overall improvements in power

because of the relatively poor power efficiency of these amplifiers. Since

power dissipation is still quite far away from the dynamic power required to

charge and discharge the capacitors, the use of class AB configurations offers strong potential if the speed can be maintained. Scaling of technology will

provide power dissipation improvement.

Another open issue is the relative benefit of even lower supply voltages.

Operation at voltages in the 1 volt range will be desirable for compatibility

with low-voltage systems, but are not likely to yield the same benefits in

power dissipation as is the case for digital logic and memory, at least at resolu­

tions of 10 bits and above.

Thble 1: AID Performance: 3.3 V and 15°C.

Technology 1.2-J1m CMOS

Resolution lOb

Conversion Rate 20 MS/s

Active Area 3.2 mm x 3.3 mm

Differential Input Range ±lV

Input Capacitance 1 pF (single-ended)

Power Dissipation 35mW· (2.8mW· at lMS/s)

DNL 0.5 LSB

INL 0.6LSB

SNDR 59.1 dB (Fin = 100 kHz) 55.0 dB (Fin = 10 MHz)

• Output pad driver power consumption not included.

71

REFERENCES

[1] S. H. Lewis, H. S. Fettennan, George F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, "1O-b 20-Msamplels analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 27, pp.351-358, March 1992.

[2] Y.-M. Lin, B. Kim, and P. R. Gray, "A 13-b 2.5MHz self-calibrated pipe­lined AID converter in 3-~m CMOS," IEEE J. Solid-State Circuits, vol. 26, pp. 628-636, Apr. 1991.

[3] T. Cho and P. R. Gray, "A lO-bit, 20MS/s, 35mW Pipeline AID Con­verter", Digest of Technical papers, 1994 Custom Integrated Circuits Conference, May, 1994

[4] K. Bult and G.J.G.M. Geelen, "A fast-settling CMOS opamp with 90-dB DC gain and 116 MHz unity-gain frequency," ISSCC Dig. Tech. Papers, pp. 108-109, Feb. 1990.

[5] Y. Nakagome et al., "Experimental1.5-V 64-Mb DRAM," IEEE J. Sol­id-State Circuits, vol. 26, pp. 465-472, Apr. 1991.

[6] K. Kusumoto, K. Murata, A. Matsuzawa, S. Tada, M. Maruyama, K. Oka, and H. Konishi," A lO-b 20-MHz 30-mW pipelined interpolating CMOS ADC," in ISSCC Dig. Tech. Papers, pp. 62-63, Feb. 1993.

[7] A. N. Karanicolas, H. Lee, K. L. Bacrania, "A 15-b IMS/s digitally self-­calibrated pipeline ADC," ISSCC Dig. Tech. Papers, pp. 60-61 Feb. 1993.

Micro-Power Analog-Filter Design

Gert Groenewold Philips Semiconductors, Sunnyvale, CA, USA

Bert Monna Delft University of Technology, Electronics Research Lab

Delft, The Netherlands

Bram Nauta Philips Research Lab, Eindhoven, The Netherlands

Abstract

There are fundamental minima for the power consumption of filters. We will see how tlieae minima can be found approximately, and also how filters that approach these minima can be designed for supply voltages down to about IV.

1 Introduction

Most applications for low-power or low-voltage filters are battery op­erated. Other applications are high-frequency filters, which by their nature need much power· to operate, so that the power consumption needs to be controlled to reduce chip temperature.

Especially for low-voltage filters, it is advisable to try to use rail­to-rail circuits. We will prove that this is also the case for low-power filters, even if the supply voltage does not impose a direct limit. In fact, we will see that a fundamental minimum for the power dissipation can be directly linked to the dynamic range (which is the ma.xim!ll signal­to-noise ratio), and that there is no first-order link between the supply voltage and either the dynamic range or the power dissipation. Beyond the fundamental limits, there are always practical limits to what can be achieved, and here is the place where clever circuit design comes in.

73

RJ. WIll de Pltusche et al. (ed8.). A/UlID, Cirr:uit Dul,,,, 73-88. o 1995 KJawer Academic PublUhen.

74

au

b1 1/8 cl m O----=--+-~-_9_--=-_O out

Figure 1: A second-order filter network.

a b

Figure 2: A Voltage-mode and a current-mode integrator. Both consist of a transcon­duct or alld a capacitor.

After having seen an illustrative example, we will discuss the funda­mentals of power consumption in filters. This gives us the basics of how to curb it. Then we will see how with this knowledge practical circuits can be designed, and where practical limits are found.

2 An Example

A simple example may illustrate the basics of the filter design. Figure 1 shows a network for a second-order lowpass filter. The

network consists of two integrators with transfer 1/8, and a number of inte~connections. Two suitable integrator configurations are shown in Figure 2. The integrator of Figure 2{a) is a voltage-in voltage-out integrator, the other one is current-in current-out. Both consist of a capacitor and a voltage-to-current converter, also known as a transcon­ductance stage or trans conductor. The number of inputs of the voltage­mode integrator can be extended by adding transconductors and con­necting their outputs to the output of the integrator. Similarly, the number of outputs of the current-mode integrator can be extended by adding transconductors and connecting their inputs to the input of the integrator. If we use either of these two integrator types, one of the two filters of Figure 3 will result.

7S

a b

Figure 3: A voltage-mode and a current-mode filter, based on the signal-flow graph of Figure 1 and the integrators of Figure 2.

A well known dynamic-range optimization step for filter networks like these is a process called scaling. The underlying idea is that if the dynamic range is maximal, all the critical internal signal levels must be equal. Intuitively, it is not difficult to see why. The filters consist of a network of active integrators. The integrators have a maximal signal amplitude at which they work correctly without generating too much distortion by saturation effects. The maximal input or output signal level of the filter is determined by the level at which at least one of the integrators starts to saturate. At this level, all the internal signal levels should be made as large as possible so that a maximal distance to the noise level is maintained. This means that all integrators should begin to saturate at the same (maximal) input signal level, although this does not necessarily need to happen for each integrator at the same frequency. If the output signal of the filter is a voltage, usually the same limit exists for the output signal as for the internal signals. Therefore, the internal signal levels also need to be made equal to the output signal level in this case.

The internal signal levels can be equalized without changing either the overall transfer function or the network topology by modifying the transconductance values. This process is called scaling and has for analog active filters probably been introduced by Martin and Sedra [1]. For digital filters earlier references can be found [2].

A mathematical proof of the fact that optimality requires equal signal levels exists [3J. It is more complicated than the line of thought sketched above, because in the process of scaling the noise sources are modified.

Because the internal signal levels need to be made as large as possible, the signal voltage levels in the two filters of Figure 3 will be equal if

76

the same transconductor type is used. The filter networks are almost identical, and therefore the noise properties of both versions will be almost identical, if the capacitance values are the same. This means that the dynamic-range properties of the voltage-mode filter and the current-mode filter are the same.

This is an important conclusion. It means that in the design of low­power low-voltage filters there is no direct advantage in using current mode. In a sense, there is no such thing as a current-mode filter, because internally there is a continuous interplay between voltage and current; the capacitances convert current to voltage, and the transconductors vice versa. The only difference between a voltage-mode and a current­mode filter is the nature of the input and output signal, which in a properly scaled filter never limit the dynamic range. We will show in the next section that there is no direct link between the dynamic range and the supply voltage of any active filter. The dynamic range can rather be linked to the power dissipation and the chip area.

One exception might be brought up. If there is internal dynamic­range compression in the voltage domain, a current-mode filter can have an advantage [4]. These filters can be used if they don't have to process large and small signal levels at the same time. They may therefore be useful in audio applications, but not in for instance intermediate­frequency filtering. The advantage lies in the fact that the input and output signals of the filter are currents, so that these do not need to be compressed.

3 Power and Noise

As early as in 1971, it was pointed out by Blom and Voorman [5, 6], that there is a fundamental link between the power dissipation and the dynamic range of an active filter. In simple terms, the signal power needs to be a larger than the noise power by a certain amount. Because the filters are active, this signal power is drawn from the power supplies. If the dynamic range is specified, we can determine the minimum power level at which the circuit can operate if we know the noise level.

Along those lines, Blom and Voorman came up with an expression for the power consumption of gyrator-capacitor filters. A simplified

77

derivation is given below. In this derivation, a filter is viewed as a network of integrators, which is more general than the gyrator approach.

It has been proven before [3, 7] that the noise level of a filter is dependent on the total capacitance of the filter, the transfer function, the network configuration, and the noise factor of the active circuits of the filter. The network configuration can be optimized, so that this factor can be removed from the dependency. This can only be done in an analytic way for narrow-band bandpass filters, and even in this case, it is a complex process. It is, however easily possible to make a rough estimate.

Suppose the total integration capacitance in the filter is C. If the order of the filter is n, there generally are either n or 2n capacitances. Let us assume that there are n capacitances Cj (i = 1, 2, ... n), each with value C In. Each capacitance can be associated with a minimal mean-squared noise voltage over the capacitor of

-2-_ kT _ nkT Vnoise - C j - C (1)

where C is the value of the capacitor, k is Boltzmann's constant, and T is the absolute temperature. The excess noise of the active circuits has not yet been taken into consideration. This can be done by multi­plying this expression by the noise factor ~ of these circuits. This noise factor is defined as the ratio of the total noise power associated with the integrator and a fundamental minimum determined by the total of transconductors or resistors that set the time constants of the integra­tor. A noise-free active circuit would give rise to a noise factor of 1. If it is assumed that the noise associated with each capacitance appears without amplification or attenuation at the output (this generally ap­pears to be approximately the case), the total mean-squared output noise voltage is

n 2kT v.2 _c_ noise,out - '" C . (2)

We have assumed a voltage output. If the output signal is carried by a current, an effective transconductance factor needs to be taken into consideration and the derivation works the same way.

Suppose the dynamic range is required to be DR, the mean-squared

78

output signal voltage then needs to be

(3)

If the filter is scaled to optimize dynamic range, all the internal capac­itances carry the same signal voltage, which is the same as the output signal voltage, and the total mean-squared signal current in the capac­itances is

(4)

This current is drawn from the supply voltages. If the supply voltage is Yaup, the power drawn is

(5)

This is a very crude estimate, but it can give valuable insight into the fundamentals of power consumption in filters.

According to (5), the power dissipation is minimal if C is minimal. How small can C be made? Equation (3) links the mean-squared signal voltage at the output of the filter (and at the internal nodes) to the capacitance. If the capacitance is made smaller, the signal voltages have to be enlarged. The capacitances can be made smaller up to the point where the maximal signal voltage has been reached. If we assume that the signal is sinusoidal, its amplitude has to be equal to

(6)

The maximally allowable amplitude is largest if the integrators can han­dle rail-to-rail signals. In that case, the maximal amplitude is half the supply voltage. This gives us with (6) a minimal capacitance value, which, when substituted into (5) yields a power estimate.

(7)

This estimate applies to class-B output stages. If class-A output stages are used, the supply current increases minimally by a factor 1r [3]. As the dynamic range of a bandpass filter is inversely proportional to its quality factor Q [6, 7, 8], which is defined as the ratio of its central

79

frequency to its bandwidth, (7) needs to be multiplied by Q in this case.

This power estimate only includes the power that is necessary to charge and discharge the filter capacitances with an amplitude large enough to satisfy the dynamic-range requirements. In practice, some extra power is necessary to bias stages, as we will see in Section 4.

Some important conclusions can now be drawn. To minimize the power dissipation of active filters, we need to:

• minimize the noise factor of the active circuits,

• use rail-to-rail class-B output stages.

Equation (7) shows that the power consumption is independent of the supply voltage. In fact, it suggests that any dynamic range can be realized at with any supply voltage. In a theoretical sense, this is true. Practically, the capacitance that is needed to maintain the DR increases if the supply voltage is reduced. This imposes a practical limit. Another limit stems from the fact that at low supply voltages it is difficult to realize the active circuits.

4 Circuits

Traditionally, there are two methods available to realize integrators, which are the filter building blocks. One is known as the transconductor­C method, the other as the opamp-R-C method. An example of a transconductor integrator is shown in Figure 4. It consists of a differ­ential pair loaded with a capacitor. This circuit is very non-linear, but several linearization methods can be applied [9, 10, 11]. The main ad­vantages of this stage are its enormous tuning range and its potential for high-frequency operation. It is, however, not extremely suitable for low-power applications, because it can not process rail-to-rail signals. The input and output swing can be maximized by linearizing and by reducing the saturation voltages of the bias current sources. The lat­ter can be done by reducing the emitter resistors of the current-source transistors. Even if these resistors are zero valued, the stage can still not process rail-to-rail signals. Also, if the emitter resistors are reduced

80

Vee

bias!

out-out +

in+

in-

bias2

Figure 4: A bipolar transconductance integrator.

;.-..t.---, -,--L-_---L_-o Vout

Figure 5: An opamp- MOSFET-C filter.

in value, the noise generation by the bias circuits increases, which forces us to dissipate even more power to maintain a dynamic range.

By the knowledge of the authors (based on an extensive investiga­tion [12]), there is only one way to realize rail-to-rail integrators with a low noise factor, viz. the opamp-MOSFET-C (or opamp-R-C) method. This method was initiated by Banu and Tsividis [13, 14] and immedi­ately yielded dynamic ranges of 94 and lOOdB, figures that have since then almost never been equaled. The 94dB figure had been obtained with a 20mW dissipation. With (7), a lower limit for the power con­sumption for class-A output stages is estimated at 44JL W.

Another example of such a filter, designed by Jaap van der Plas [15], is given in Figure 5. It is a fifth-order filter, consisting of a network of five

+ Vin/2

- Vin/2

C/2

Figure 6: An opamp-MOSFET-C integrator .

.-----.-------------~------._------~_o~~

+0--+--11 + VOU!

1------1--0 via

~~----~--~--------~----~------~_o~

Figure 7: The opamp used in the filter of Figure 5.

81

integrators. Each integrator has been realized with a balanced opamp, two capacitors, and a number of MOSFET's that serve as tunable re­sistors. One such integrator is shown in Figure 6. For this integrator to be able to process rail-to-rail signals at its output, the opamp needs to have a rail-to-rail output stage. Figure 7 shows the opamp. As NMOS transistors generate much more 1/ I-noise than PMOS transistors, no NMOS transistors have been used. For that reason, the input differential pair (Pl and P2) has been loaded with resistors (ild) in stead of NMOS transistors, even if this reduces the opamp gain. For common-mode stability as well as for even-order nonlinearity cancellation, an accurate common-mode feedback circuit (P3-P6 and the circuitry around it) has been added. This particular common-mode feedback configuration has been originally proposed by Banu et al. [16]. The output stage gives the opamp and the integrators output rail-to-rail capabilities.

The integrators can have a rail-to-rail input swing if the gate voltages

82

of the MOSFET's are higher than the supply voltage plus the threshold voltage of the MOSFET's. If the MOSFET's are of the enhancement type, this would mean that the gate voltages need to be higher than the supply. Because the gates do not draw current, this is not difficult to accomplish. Several charge pumps have been developed for this purpose (e.g., [17]).

If depletion MOSFET's are available, their gate voltages could be kept below the supply voltage, eliminating the need for a charge pump. It is unfortunate that very few processes allow for the usage of these devices. Many companies develop and use BiCMOS processes for the development of low-power low-voltage circuits. The step from CMOS to BiCMOS that is made, is a lot more involved than a step that would add depletion MOSFET's, while this step simplifies the design of low-voltage filters greatly.

In an initial implementation, this filter had a 98dB dynamic range with a power consumption of 10m W. A minimum power consumption by (7) is 0.13m W for a class-A output stage. In a later study [12] it appeared that with the same power consumption, the dynamic range could be increased to 104.5dB, which would be estimated by (7) to cost minimally O.6m W. Even with this improvement, the actual filter still consumes more than necessary. To get closer to the fundamental minima, bipolar class-AB opamps should be used.

Figure 8 shows a 3V class-AB opamp designed by Anton de Graauw [18]. The use of bipolar transistors at the input was favorable for noise per­formance. The bias current for the input stage has been optimized for noise minimization. The noise factor of the integrators that have been realized with this opamp is as low as 1.18, which corresponds to 0.7dB.

For the output stage a fully differential rail-to-rail class-AB config­uration has been chosen [19, 20]. The main transistors in one output stage are the CE stages Q3 and Q4, resp. Qs and Q6. The common-mode feedback circuit consists of Reb Rs2, Q18, Q17, Q1S, Q16 and U:r• Apart from the mentioned functions of such a circuit to ensure common-mode stability and reducing even-order distortion, it also serves to annihi­late common-mode to differential-mode conversion caused by NPN-PNP asymmetry in the output stage. The circuit consisting of Q7 to Q14 and the surrounding current sources biases the output stages at 1.5JLA each.

in+Q----i

m.o-----+_-~

7SOnA -

Figure 8: A 3V class-AB opamp.

83

1--+--..--....---+---<:1 out·

~+_-L-~-+_-_oom+

84

3V

1---.-----0 out-

1----1-.--+--0 out + in + 0-------'--1

in - 0------+-------'

Figure 9: A class-A opalllp.

With a 3V supply voltage, the opamp can handle a single-ended output swing of 2.8V, which brings the opamp to within O.6dB from rail-to-rail operation.

The opamp was designed for application in a bandpass filter with a central frequency of 100kHz and a bandwidth of 7 kHz. The filter contains 16 integration capacitors of 10pF each. With the above opamp properties, the dynamic range of the filter is 75dB with a total static power consumption of O.94m W. If the filter is processing maximum­level signals, the power consumption increases by about O.2m W. This means that still most of the supply power is used for biasing the active circuits. Especially the current that is necessary to bias the input stage for optimal noise performance contributes to this. The actual power consumption compares reasonably to the estimate of O.25m W that is obtained via (7).

Another 3V opamp is depicted in Figure 9. This opamp has been designed by Marcel Lugthart [21] for application in a 100kHz notch filter with a Q of 33. The input stage is a differential pair, optimized to a noise factor of 1.11 in the same way as in the previous opamp. The output stage is a rail-to-rail CE-stage, biased in class A at 60JLA.

The dynamic range of the second-order notch filter is about 80dB. With corrections for the quality factor and the fact that the output stage

is class A, an estimate for the lower limit of the power consumption according to (7) is 0.34mW. The actual circuit consumes 1.5mW. The difference is largely due to overdimension of the output stage.

A noteworthy detail of this ·opamp is its phase compensation. It can be proven [21] that the effects of the non-idealities of the opamp on the phase shift of the integrator add up to zero at the notch frequency if the dominant pole of the opamp is situated at the same frequency. This has been accomplished by choosing proper values for the common­mode feedback resistors Rsl and Rs2. This method makes it possible to construct high-frequency opamp-R-C filters without placing extreme demands on the bandwidth of the opamps.

If filters have to operate at even lower supply voltages, it becomes increasingly important to maintain a high swing and minimize the noise generation. Below a supply voltage of 1.2V the swing is mainly limited at the input of the opamp. This is because in a practical filter circuit the input bias voltage of the opamp is equal to the output bias voltage. So for an optimal swing, the DC input bias voltage must be half the supply voltage, which means that below 2V it is not very well possible anymore to use a differential pair. The input bias voltage can not be brought closer than one basis-emitter voltage to both supply lines at the same time, and this minimum is attained by using an input CE stage with the emitter grounded, as shown in Figure 10. The common-mode stabilization circuits that have been used in the above opamps can not be used here. Common-mode feedback has been implemented with a resistor bridge. For common-mode stability these resistors can not be made too large, so that the noise factor of this opamp can not be made smaller than 2. The input bias voltage has been reduced by choosing a large input device. A rail-to-rail swing is attainable at a supply voltage of 1.2V. Below this voltage, the swing rapidly decreases, and the circuit works to about 0.8V.

If this opamp were to be used in the eighth-order filter mentioned above, with 16 10pF integration capacitors, a dynamic range of 64dB can be realized with a 1.2V supply voltage. According to (7), corrected for the quality factor and class-A operation, a minimum power consumption of O.llm W is necessary. The static power consumption of the actual filter would be 0.24mW, which compares reasonably.

85

86

.---------.----,-----.------.----,-----.-----o~c

2.51/

loOk

'-------t---'------'----'---'--+-f--'----'-----1------'----t--ognd

+in

4x200k

- + out

Figure 10: A IV opam}>.

-in

5 Conclusions

We have seen that there is a fundamental lower limit to the power con­sumption of a continuous-time active filter. This limit can be directly linked to the dynamic range of the filter, and there is no direct con­nection between the dynamic range and the supply voltage. We came to a very rough approximation of this limit in (7). This limit is set by the power that is necessary to charge and discharge the capacitors in the filter with a certain frequency and amplitude. Practical filters will always dissipate more power, because some power is needed to bias cir­cuits, especially input circuits that need to be biased for optimal noise performance.

In order to approach the fundamental limit as close as possible, rail­to-rail circuits with a low noise factor should be used. The only can­didates that we found were opamp-MOSFET-C filters. These circuits can be configured in a close-to-optimum way down to supply voltages of 1.2V, although they can work less optimally to O.BV.

87

References

[1] Ken Ma.rtin and Adel S. Sedra. Designing leap-frog and SFG filters with optimum dynamic range. Proceedings of the IEEE, 65(8):1210-1211, August 1977.

[2] L.B. Jackson. On the interaction of roundoff noise and dy­namic range in digital filters. The Bell System Technical Journal, 47(2):159-184, February 1970.

[3] Gert Groenewold. Optimal Dynamic Range Integrated Continuous­Time Filters. PhD thesis, Delft University of Technology, 1992.

[4] E. Seevinck. Companding current-mode integrator: A new circuit principle for continuous-time monolithic filters. Electronics Letters, 26(24):2046-2047, November 1990.

[5] D. Blom and J.O. Voorman. Noise and dissipation of electronic gyrators. Philips Research Reports, 26:103-113, 1971.

[6] J.O. Voorman. The Gyrator as a Monolithic Circuit in Electronic Systems. PhD thesis, University of Nijmegen, Nijmegen, 1977.

[7] Gert Groenewold. The design of high dynamic range continuous­time integratable bandpass filters. IEEE Transactions on Circuits and Systems, 38(8):838-852, August 1991.

[8] Haideh Khorramabadi and Paul R. Gray. High-frequency CMOS continuous-time filters. IEEE Journal of Solid State Circuits, SC-19(6):939-948, December 1984.

[9] J.O. Voorman, W.H.A. Briils, and P.J. Barth. Bipolar integration of analog gyrator and laguerre type filters (transconductor-capacitor filters). In Proceedings ECCTD'83, pages 108-110, Stuttgart, September 1983.

[10] Johannes O. Voorman. Transconductance amplifier. U.S. Patent 4,723,110, February 2, 1988.

[11] Hiroshi Tanimoto, Mikio Koyama, and Yoshihiro Yoshida. Realiza­tion of a I-V active filter using a linearization technique employing

88

plurality of emitter-coupled pairs. IEEE Journal of Solid State Circuits, 26{7}:937-945, July 1991.

[12] Gert Groenewold. Optimal dynamic range integrators. IEEE Transactions on Circuits and Systems-I: Fundamental Theory And A~plications, 39{8}:614-627, August 1992.

[13] Mihai Banu and Yannis Tsividis. Fully integrated active RC filters in MOS technology. IEEE Journal of Solid State Circuits, SC-18(6):644-651, December 1983.

[14] Mihai Banu and Yannis Tsividis. An elliptic continuous-time CMOS filter with on-chip automatic tuning. IEEE Journal of Solid State Circuits, SC-20(6):1114-1121, December 1985.

[15] Jaap van der Plas. MOSFET-C filter with low excess noise and accurate automatic tuning. IEEE Journal of Solid State Circuits, 26(7):922-929, July 1991.

[16] Mihai Banu, John M. Khoury, and Yannis Tsividis. Fully differen­tial operational amplifiers with accurate output balancing. IEEE Journal of Solid State Circuits, 23(6):1410-1414, 1988.

[17] J.C. Sandee. Een on-chip automatisch afstemcircuit voor tijdcon­tinue filters met een optimaal dynamisch bereik. Master's thesis, Delft University of Technology, Delft, November 1992.

[18] A.J.M. de Graauw. Een operationele versterker voor MOSFET­C filters. Master's thesis, Delft University of Technology, Delft, December 1992.

[19] Johan H. Huijsing. Private Communication.

[20] Joseph N. Babanezhad. A low-output-impedance fully differential op amp with large output swing and continuous-time common­mode feedback. IEEE Journal of Solid State Circuits, 26(12):1825-1833, December 1991.

[21] M.L. Lugthart. Realisatie van een geintegreerd notchfilter. Master's thesis, Delft University of Technology, Delft, November 1993.

Low Power Oversampled AID Converters

Evert DIJKSTRA, Olivier NYS, Enrique BLUMENKRANTZ

CSEM. Swiss Centre for Electronics and Microtechnology, NeuchAtel, Switzerland

Abstract The fundamental and practical power limits of AID converters are identified. It will be demonstrated that oversampled AID converters are power-efficient for the medium to high resolution range. For this type of converters, some practical low power circuit implementations are discussed. Finally, this paper will introduce the novel "analog floating point" concept for oversampled AID. As will be demonstrated, significant power can be saved on the system level by clearly distinguishing the required SNR and the total dynamic range that has to be respected.

1. Introduction The recent increase in demand for complex portable products has led to a world-wide surge of interest in low power, low voltage design. Many of these portable products follow the general trend towards an increased use of digital signal processing techniques. Besides the classical arguments such as e.g. increased flexibility, better testability, easier design etc., it can be demonstrated [1] that this approach is, for current technologies, also justified from a power consumption point of view for signal to noise ratio's larger than 70-80 dB. With future generations of technology and a significant voltage scaling, the digital circuitry will consume even less power. This implies that in the future, the digital design techniques will be more power efficient than analog alternatives for signal to noise ratio's larger than 40-50 dB [2].

89

Rl van de Plassche et aI. (eds.), Analog Circuit Design, 89-103. C 1995 Kluwer Academic Publishers.

90

The above analysis does not take into account the AID and the DI A conversion. It turns out that the power consumption of the converters is far from negligible in many practical portable systems. Section 2 of this paper will review the fundamental and the practical limits of the AID's power consumption.

In this paper we will mainly focus on oversampled AID converters. Section 3 will discuss why and when to use this type of converters for low power applications and how much they should be oversampled.

The design of the sub-circuits may strongly influence the power consumption. Carefully designed OT A's and comparators are reqllired for the modulator. In addition, as most micropower converters are powered with different voltages, power efficient voltage multipliers and level shifters are required. Section 4 will discuss some of the circuit issues in more detail.

The system requirements can in many applications be reduced by applying the novel "analog floating point" concept This concept clearly distinguishes the required SNR and the total dynamic range that has to be respected. Indeed, it turns out that good system results can be obtained by implementing an automatic range switching before the actual AID converter. This will reduce the required SNR of the converter and therefore the power consumption. Section 5 will discuss how automatic range switching can be implemented in oversampled AID converters. It is expected that this novel concept may reduce the power consumption by orders of magnitude for a number of practical applications.

2. Fundamental & Practical limits As an AID converter quantifies the ratio between the input signal and the reference voltage, the most critical noise sources are located on both nodes. Assuming that the input voltage Yin and the reference voltage Vref are first converted into currents by respectively the input resistance's Rin and Rref, the full scale range Vinmax of the converter is defined as:

U· IT if Rin vmmax= vre ._-Rre!

(1 )

The thermal energy fluctuation in both Rin ~d Rref generates a thermal noise source with a spectral density of 4*k*T*R. Referred to the input the total noise spectral density is given, in [V2IHz], by:

Sn(!)=4.k.T.Rin.(l+ Rin) RTe!

(2)

91

Assuming that other noise sources are negligible with respect to the thennal noise, the SNR can be defined as the ratio between the full scale input signal power and the thermal noise power integrated over the signal bandwidth BW:

Vinmax2

SNR= 2 R' 4· k· T· Rin· BW· (1 +~) Rref

(3)

The minimum power consumption is the power dissipated in the input resistances. For a full scale DC input level, this minimum power consumption is given by :

Pmin= Vinmax2 + Vref2 = Vinmax2 '(1+ Rref ) Rin Rref Rin Rin

(4),

This equation can also be expressed as a function of the signal to noise ratio and the bandwidth :

Pmin=8.k.T.BW.SNR.(I+ Rin ).(1+ Rref ) (5) Rref Rin

The theoretical minimum power consumption is proportional to both the signal bandwidth and the signal-to-noise ratio. Note that the SNR is expressed as a ratio of powers. Hence, the minimum power consumption is increased by a factor 4 for each additional bit of resolution. The minimum power consumption is also depending on the ratio between the full scale input signal and the reference voltage. The optimum is reached when Vinmax equals Vref (or equivalently when Rin equals Rref). Under these conditions Pmin is given by:

Pmin = 32· k· T· BW· SNR (6)

This theoretical limit is neither dependent on the selected conversion algorithm, nor on the supply voltage.

It equally holds for switched capacitor implementations and oversampled converters. The sampling at frequency fs of a signal by means of capacitor C is equivalent to a resistance value R=lI(fs*C). For a given bandwidth, the SNR of an oversampled switched capacitor AID converter can be derived from eq. (3):

92

Vinmax2

SNR=N.Cin. 2 2.k.T.(1+ C~ef)

Cm

(7)

where the oversampling ratio N is defined as the ratio between the sampling frequency and the Nyquist frequency (N=fs/(2*BW)). This SNR is proportional to both the capacitor size and the oversampling ratio. To keep the thermal noise below a certain level requires a minimum conductance. For a given bandwidth, this conductance is proportional to the capacitor size and the oversampling rate.

Figure 1 illustrates the relation between the dynamic range and the minimum required energy per conversion. This energy is defined as the minimum power consumption divided by the Nyquist rate. Different practical realisations of converters have also been depicted.

20 0.01

0.001 0.0001 IE-OS lE-06 lE-07 IE-OS lE-09 lE-lO lE-ll lE-12 lE-13 lE-14

•

dynamic range [dB]

40 60 80 100

th.energy

real energy • • • . -• ... I . • • • ~ .

." r"

./': JI' ~

./" L ~

120 140

• ... N ..

L ./"

." ".

./

l

I 5

Fig. 1: The energy per conversion as a function of dynamic range

Those converters that exceed a dynamic range of 100 dB, are mostly found around a straight line running parallel to the theoretical limit This parallel line lies around 3 to 4 orders of magnitude higher than the line defined by eq(6). The difference between theoretical and real power consumption is due to many practical reasons. In the estimation of the theoretical limit only the power consumption in the ADC's front-end has been considered. Practically, however, the currents through these input resistances or capacitors have also to be processed by amplifiers. As the input thermal noise of the amplifiers itself is added to the thermal noise of the input devices, the latter should be reduced even further in order to satisfy the overall noise performance. The non rail-to rail swing of the amplifiers and the power consumption in the biasing circuitry further reduces the power

93

efficiency. In order to reduce the parasitic capacitors, the transistors of the amplifiers must often be biased in medium or strong inversion, increasing the bias current required to ensure a given transconductance.

For dynamic ranges lower than 100 dB, the power consumption is not anymore determined by the thermal noise criteria. The reason is that the minimum thermal noise criteria is already fulfilled by a too high (unpractical) input impedance. As the total integrated thermal noise of a switched capacitor of 1 pF is only 90 )lVI, it would be optimum for an AID with an LSB of roughly the same size. Optimum power for lower resolutions would require sampling of the input signal and the reference voltage on capacitors much lower than 1 pF. This is, however, not realistic for practical reasons such as charge injection or parasitic coupling. To avoid a poor reproducible behaviour, the signal charge must remain well above the charges that are injected by parasitic effects. For converters requiring a precise matching b~tween components (such as algorithmic or successive approximation converters), capacitors should be much bigger than IpF.

Hence, for dynamic ranges lower than 100 dB, it is more realistic to consider that each elementary operation that is performed during the conversion (such as integration, mUltiplication or comparison) consumes a given energy Ei. For oversampled AID converters the energy consumed by the integrators EO is dominant. The number of integrations performed per conversion is the product of the oversampling rate N and the modulator order m. This results in a power consumption of m*N*EO.

While considering only the quantization noise, the resolution will be dependent on the modulator order m and on the oversampling ratio N. As the resolution generally increases with 6*m or 6*m+3 dB for each doubling of the oversampling ratio [3], high order converters theoretically require less oversampling. Therefore, for medium to high resolutions, the higher order converters are theoretically more power efficient. Figure 2 illustrates this graphically. The obtained graph requires some additional comments for both single loop and multistage modulators [4]. For high order single loop modulators stability criteria require a higher conversion rate than the one that is theoretically required [5,6]. For multistage modulators [7],[8],[9], the size of capacitors and hence the power consumption is generally increased due to the more severe matching requirements. Multistage converters resemble more and more a pipeline algorithmic AID converter. As they are less oversampled, less elementary operations are performed per conversion. However, due to the increased size of capacitors, they require more energy per elementary operation.

1 A sampling noise k.T/C of65~V is associared to a capacitor of IpF. However. 2 sampling actions occur in the SC circuilry of an ADC. One during signal sampling, the other during charge transfer. This accounts for a total uncertainty of 9Ot! v.

94

i c:I

i-1:1

'i .... ~ .....

14

22

20

18

16 • ORDERI.

14 ~~ORDER2'

12 r-----7T~--~~~----~ * ORDER3

10 • ORDER4 I

8 10 100 1000 10000 100000

Energy per conversion (FJEO) Fig. 2: The energy per conversion required tor a given reSOlutiOn

and a given modulator order.

3. Why, when and how much oversampling Until today, all high resolution AID converters are based on oversampling techniques, such as I-A modulation [10]. Some of the well-known advantages are the robustness to parasitic effects and the relatively modest requirements on components matching. In addition, combined with double correlated sampling or chopper techniques oversampling allows to eliminate the lIf noise by modulation at a high frequency and subsequent low pass filtering [11], [12].

At first sight it may seem a paradox to employ oversampled AID for low power applications. However, oversampled AID are not less power efficient as long as the power consumption is constrained by thermal noise considerations. For a switched capacitor implementation the achievable SNR is proportional to both the capacitor size and the oversampling ratio (see eq. 7). This means that an increase of the sampling rate allows a proportional reduction of the capacitor size. The power consumption remains therefore unchanged.

This frequency-capacitor exchange holds only as long as the capacitor size is not imposed by other practical constraints such as charge injection, parasitic coupling or matching. Indeed, using the minimum size for capacitors, a critical overs amp ling ratio is required in order to reach a sufficiently low thermal noise level. Choosing a higher oversampling ratio increases the power consumption, as the capacitors can not be reduced below the minimum value.

0.01 -x- order 1

0.001

0.0001

0.00001

0.000001

-lIC-order2

~'-order3

---<>- order 4

0.00000001 +-+-+-+--I----tt--l--+-+-+ ................. -f-+-+-I

resolution [bits]

Fig. 3: The min required energy per conversion as a function of resolution and converter order

95

Figure 3 illustrates how the order of the converter must be chosen in order to minimise the power consumption. For high resolutions (>15 bits), the power consumption is essentially determined by the thermal noise, which imposes the input resistance of the first stage, and hence its current and power consumption. In such a case, the order should be chosen as small as possible in order to limit the contribution of the next stages to the total power consumption. The order of the converter must however be selected sufficiently high so that the required oversampling ratio will not ask for a capacitor smaller than the minimum capacitor size. In this example, for resolutions between 17 and 22 bits, the converter order must be at least 2, because a fIrst order would require an oversampling ratio much higher than the critical one. For lower resolutions, the critical oversampling ratio is lower. Hence a higher order must be selected in order to obtain an oversampling ratio which is closer to the critical one.

4. Circuit implementation The supply voltage management for the different blocks of an oversampled AID converter is important in order to minimise its overall power consumption. Subsection 4.1 will discuss the various requirements and some of the circuits that are necessary for the voltage conversion. The main sub-blocks of an oversampled AID, i.e. the OTA's and the comparators will be respectively discussed in the subsections 4.2 and 4.3.

4.1.0. Power supply requirements The power consumption of the digital decimation filter can be made of secondary importance if an appropriate architecture is chosen [13,14] and if

96

it is operated at the lowest possible supply voltage. For battery operated applications this usually corresponds to a single cell, i.e. 1.5V.

The theoretical limit of the power consumption is independent from the supply voltage (see eq. (6»; this limit takes, however, only the thermal noise into account. In practice, the analog part needs a minimum supply voltage in order to work properly. In addition, since parameters like transconductance, gain and bandwidth are dependent upon current, these parameters define the minimum current level needed by the analog circuitry. Operation of the circuits as near as possible to these (two) lower bounds warrants minimum power consumption.

A power efficient analog circuit implies that the signal excursion will be as close as possible to the rail-to-rail supply of the analog circuitry. To achieve this in a switched capacitor circuit it is necessary to generate gate voltages for the switches that are at least one Vt plus a few hundred m V above the supply voltage of the analog circuitry.

It follows from the previous reasoning that at least 3 different supply voltages are needed for an optimum operation, i.e. one for the digital, (e.g. 1.5V), one for the analog (e.g. 2V) and one for the switches (e.g. 3V).

4.1.1 Voltage Multiplier The voltage for the analog switches (e.g. 3V) can be created from the battery voltage (e.g. 1.5V) by a voltage doubler. Fig. 4 shows the basic circuit of a high efficiency voltage doubler. Capacitor C I is successively charged to the battery's voltage and then put in series with it. This produces a voltage Vm that is two times the battery voltage. Capacitor C2 is used to store the voltage Vm and hold Vm reasonably constant while Cl is being recharged .

. -~ ... -.... ----....... ------.. -----.. -... -.. --------------... --- .. ---.. l l~

C2

. . .-......... -----_ .......... __ ...... -_ ......... -... -- ............ -_ .......................... -Figure 4: Basic circuit of a voltage doubler

4.1.2 Level Shifters Power efficient level shifters are required for the transfer of the logic voltage levels (e.g. 0 and 1.5V) to the voltage levels required by the analog switches (e.g. 0 and 3V).

97

~~u---~--~--------~--- _ o--t---1~--_-

pi

+---o4>HV +---0 XHV

XLV

Fig. 5 : Level shifter for the main phases Fig.6 Dynamic level shifter

Fig. 5 shows a level shifter that raises the phase signal level. It consists of a latch which is driven by a low voltage phase signal and its inverse. Either nl or n2 can conduct, driving the latch output N2 either up or down. The high voltage phase signal is obtained after the inverter. As current feed­through spikes occur upon each change of state this circuit is only used for the main phases, i.e. those phases defining the time slots in which a very specific operation is performed. Within these time slots, power efficient dynamic level shifters as depicted in fig. 6 can be employed to shift the voltage level of a logic decision to a particular switch. The dynamic level shifter works as follows: When 0HV goes low, node N is precharged to VHDD. Output XHV will then be given by the logic AND between XLV (the low voltage control signal) and 0HV (the enabling or main phase). XHV is restored to zero next time 0HV goes low.

4.2. The Fully Differential OTA Core In an oversampled AID converter, the most important power consumers are the integrators. Since the active part of the integrators consists of OTAs (Operational Transconductance Amplifiers), it is important to optimise their power consumption. In order to maximise signal excursion and to minimise the effects of parasitic coupling, a fully differential approach is recommended.

Fig. 7 shows the core of a low-voltage folded cascode OTA. This circuit has been selected because it combines low supply voltage, a minimum number of branches and a good PSRR and CMRR.

The first integrator should be biased with a current such that the unity gain frequency of the loaded OTA equals a few times the oversampling frequency. If the same level of capacitance is used, the second and following integrators can usually be biased at somewhat smaller currents. However, a more significant power saving can be obtained by using smaller capacitors in the second and following stages. This is possible

98

since the amplification of the first integrator reduces their incidence on thermal noise, matching and charge injection.

VAOD

VB3 MP7

VB2 VOUTPOS

MPI VOUTNEIl

VB, MN2

_1- VCMCONT MN4 _1-

CINTT" VASS """-;;-IHT

VINNEll V'NPOS

Fig. 7: The fully differential OTA core, together with the charge redistribution capacitors CN and CP.It's application in a SC integrator is suggested by capacitors Cint (dashed line)

Designing the OTA's with a minimum bandwidth may lead to a slewing problem during the first part of the integration phase. This slewing may affect the converter performances if the settling in the integrators is signal dependent. To avoid this problem a charge redistribution capacitor can be placed in parallel with the OT A's inputs (CN and CP in fig. 7). This additional capacitor obviously increases the time constant of the integrator, but a non-linear settling is now avoided. The final settling error may be bigger, but an uncompleted (but linear) settling does not notably affect the I.-A performances.

An alternative to the charge redistribution capacitor may be to use adaptive biasing OTAs[15]. The bias current may be either dependent upon the signal. or it may be simply increased during the settling phase. In both cases, the design should guarantee a linear settling.

Fig. 8 shows a possible biasing circuit for fig. 7's OT A. Provided that parasitic signal coupling through the biasing circuit can be avoided, the same bias circuit can be shared between different OTA's.

In general, an optimum design of a low power differential circuit implies that the input and output common mode voltages are different. Ideally, the output common mode is centered around the middle of the analog. supply whereas the input common mode should ensure the correct operation of the differential pair. The biasing circuit of Figure 8 generates also the desired input common mode voltage VINCMD. The output common mode voltage

99

VCMOUTD equals 112* (V ADD-V ASS) and can be generated from the supply vlotage with a voltage divider and a buffer.

VADD r··OTA·C;;····················"···~ J MPS I

I~+-----~----~r-*-=-----~M~-i - -j

PI MP2 i

~+-t--~1:-~ VINNEll YlNCMll i

t .................................................. ;

Fig 8: The biasing generator and its interaction with the OTA core

The common mode output of the fully differential OT A has to be well defined. Since the feedback of capacitors CINT only acts differentially, the common mode output signal needs to be stabilised with an auxiliary feedback loop. VCMCONT (see figure 7, 8 and 9) modifies the output common mode of the OTA. If VCMCONT goes up, the output common mode goes down, and vice versa. Voltage VPOL is generated by the bias circuit (fig 8). VPOL corresponds to the final voltage that node VCMCONT should reach in order to make sure that the output common mode voltage does not change. Fig. 9 shows how the common mode feedback loop is closed [16]. This circuit controls VCMCONT around the optimum equilibrium defined by VPOL in such a way that the output common mode tracks VCMOUTD as close as possible.

VCMCONT YOUTP08 YOUTNEII

VPOL YCMOUTD

Fig. 9: The common mode feedback circuit

100

VINCMD

Fig. 10: Fully differential implementation of a coefficient

Figure 10 shows the fully differential coupling that is employed between the ADC input and its first integrator as well as between the integrators themselves. A slightly more complicated form of this circuit is used for the coupling of the reference. Depending upon the decision of the comparator(s) the reference signal or the inverted reference signal is integrated. Note that the circuit of fig. 10 performs simultaneously a differential sampling and common mode level shifting.

4.3. The Comparators. The comparators used in low power ADCs follow the same guidelines as the OTAs. i.e. a minimum number of branches and operation at the lowest possible voltage. Capacitive level shifters similar to the one depicted in fig. 10 may be necessary to ensure an optimum operation of the input differential pair. Latched comparators are typically chosen because of their maximum equivalent gain for a given power consumption. Since the comparators are used only during very precise parts of the conversion algorithm. their bias currents are switched off when they are not needed. The incidence in power consumption of a comparator is typically less than 114 of an OTA's power consumption.

S. Analog floating point converters The specincations of high resolution systems may often be decomposed in several distinct signal ranges. in each of which a given accuracy has to be maintained. As the accuracy requirements are usually expressed as a relative error in the signal range under consideration. the absolute accuracy requirement can be relaxed in the less sensitive ranges.

However. because of the difficulty to implement an automatic switching between ranges without the creation of signal perturbations. most of today's high resolution systems must be designed to guarantee the most stringent absolute error over the total signal range. As a result. the SNR and therefore the power consumption (see fig. 1) are much higher than theoretically necessary.

101

G

Crnt

C1

J

Fig. 11: Example of a first order L-8 ADC with range switching.

For illustration purposes, a first order L-8 loop is depicted in Fig. 11. The circuit inside the dotted box represents the classical converter. The D/A feedback is represented by the Vref which can be integrated positively or negatively depending on the previous output sample. The converter is embedded in a multi-range system, which can multiply simultaneously by G the analog input signal and divide by G the digital output signal.

The charge on the integrator capacitor Cint represents the quantization error between the input signal Vin and the output code, accumulated with a gain proportional to G. A discrete or continuous change from one range to another requires a certain time before Cint has accumulated enough history to correctly represent the quantization error between the input signal Yin and the output code, accumulated with the new gain.

In order to cancel the noise due to the switching from one range to another, the quantization error accumulated by the integrator has to be updated to the new value of the gain. This is achieved by mUltiplying this value by the ratio of the new gain to the previous one.

Figure 12 shows the solution for the same first order converter. Only a few switches and a capacitor Ccorr identical to Cint have been added. The high simplicity of the updating circuitry has been obtained by constraining the gain to change only by a factor 2 at a time. Upon a change of the gain from

102

Q

'=' C2

~ C1

Vref.

C2

Fig. 12: Example of first I.-A ADC with Analog Floating Point operation.

o to 2*0, the accumulated error, represented by the charge on Cint, must be multiplied by 2. This is performed by successively copying the charge of Cint into Ccorr (by closing S 1 and S4) and dumping the charge on Ccorr onto Cint (by closing S2 and S3). The new charge on Cint then represents the quantization error between input signal and output code, accumulated with gain 2*0.

Upon a change of the gain from 0 to 0/2, the charge on Cint must be halved. This is performed by successively discharging Ccorr (by closing S 1 and S2) and connecting Ccorr in parallel with Cint (by closin~ S3 and S4). The new charge on Cint will correspond to the quantization error accumulated with gain 0/2.

The same principle can obviously be applied to different oversampled architectures. All perturbations due to range switching can be avoided if the technique of fig. 12 is applied to all integration capacitors. Although any gain changes are theoretically possible, it turns out that practical applications are best implemented by factor two gain changes.

In oversampled converters, the implementation of an automatic range switching is relatively straight forward. Indeed, a low resolution estimate of

103

the signal range can be obtained by some elementary low pass filtering on the output stream. Knowing this estimate and some of the signal characteristics it is generally easy to implement an automatic range switching scheme.

It is expected that the "analog floating point" concept will reduce the power consumption for a number of applications by a few orders of magnitude.

6. Conclusions In this paper several aspects of low power oversampled ND converters have been discussed. Despite huge efforts on the architectural and the circuit design level, the power consumption remains several orders of magnitude above the theoretical limit. Although further optimisation is still possible, we can not expect that the gap will be bridged soon. A radical improvement can, however, be expected from the "analog floating point" concept. Many systems can reach a good performance, while consuming orders of magnitude less than "straigtforward" approaches.

References: [1] E. Vittoz, "Future of Analog in the VLSI environment", Proc. ISCAS '90, pp. 1372-1375 [2] E. Vittoz, "Low power design: Ways to approach the limits", plenary session address ISSCC 1994, Feb 16-18, 1994, San Francisco. [3] J.C. Candy, "Decimation for Sigma Delta Modulation", IEEE Transactions on Communcations, Vol COM-34, No I, pp 72-76, January 1986. [4] O. Nys, E. Dijkstra, "Low power oversampled AID converters", ECCTD 1993, Davos, Aug 30 -Sept 3,1993. [5] J. C. Candy, "A Use of Double Integration in Sigma Delta Modulation", IEEE Transactions on Communications, Vol. COM-33, No 3, pp 249-258, March 1985. [6] B. P. Del Signore, D.A Kerth, N. S. Sooch, EJ. Swanson, "A monolithic 20-b Delta-Sigma AID Converter", IEEE Journal of Solid-State Circuits, VOL SC25, No 6 pp 1311-1317, December 1990. (7] Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, T. YoshifOme, "A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping", IEEE Journal of Solid State Circuits, VOL SC-22, No 6, pp 921-929, December 1987. [8] K. Uchimura, T. Hayashi, T. Kimura, A Iwata, "Oversampling A-fO-D and D-to-A converter with multistage Noise Shaping Modulators", IEEE Transactions on Acoustics, Speech and Signal Processing, VOL 36, No 12, pp 1899-1905, December 1988. [9] M. Rebeschini, N.R. van Bavel, P. Rakers, R. Greene, 1. Caldwell, J.R. Haug, "A 16-b 16O-KHz CMOS. AID Converter Using Sigma-Delta Modulation", IEEE Journal of Solid-State Circuits, VOL SC25, No 2, pp 431-440, April 1990. [10] "Oversampling Delta-Sigma Data Converters", edited by J.C. Candy and G.C. Temes, IEEE Press, 1992. (11] O. Nys, E. Dijkstra "On Configurable Oversampled AID Converters", IEEE Journal of Solid-State Circuits, VOL SC28, No 7, pp 736-742, July 1993. [12] 1. Robert, P. Deval, "A Second-Order High-Resolution Incremental AID Converter with Offset and Charge Injection Compensation", IEEE Journal of Solid-State Circuits, VOL SC 23, No 3, pp 736-741, June 1988. [13] E. Dijkstra, O. Nys, C. Piguet, M. Degrauwe, "On The Use of Modulo Arithmetic Comb Filters In Sigma Delta Modulators", Proceedings from ICASSP -Intemation~ Conference on Acoustics, Speech, and Signal Processing, pp 2001-2004, New York, April 11-14, 1988. [14] E. DiJkstra, L. Cardolettl, O. Nys, C. Piguet, M. Degrauwe, "Wave Digital Decimation Filters In Oversampled AID Converters", Proceedings of ISCAS 88 International Symposium on Circuits and Systems, pp 2327-2330, Helsinki, Finland, june 7-9, 1988. [15] M. Degrauwe, J. Rijmenants, E. A. Vittoz and H.I. De Man, "Adaptive Biasing CMOS Amplifiers", IEEE Journal of Solid-State Circuits, VOL SC-17, No 3 pp 522-528, June 1982. [16] R. Castello and P.R. Gray, "A HJgh-Pcrformance Switched-Capacitor Filter", IEEE JSSC, vol SC-20 No 6 pp 1122-1132, Dec. 1985.

LOW VOLTAGE LOW POWER DESIGN TECHNIQUES FOR MEDICAL DEVICES

David A. Wayne

Hearing Innovations, Inc. 5210 E. Williams Circle Tucson, AZ 85711 USA

Abstract Low-power electronics in the medical area include devices

such as implantable cardiac pacemakers, cardiac defibrillators, implantable neurological stimulators (mainly for pain relief), implantable muscle stimulation devices, hearing aids, bone conduction amplifiers, tinnitus blockers and cochlear implants. Of these devices, cardiac pacemakers and hearing aids are the most widely used and historically most mature. They also represent the largest market segments. The worldwide pacemaker market was approximately US$ 2 billion in recent years, and that of the hearing aid about US$ 1.5 billion.

Development of these devices, while admittedly mature, is by no means in decline. In both pacemakers and hearing instruments, improvements in electronic technology will yet give rise to significant performance advances. This paper will discuss the current state of development in these two medical devices, and then provide a glimpse towards the future.

1 Pacemaker Technology 1.1 Introduction

Cardiac pacemakers act to maintain a normal heart rate when there has been damage to the heart's normal timing system. This natural cardiac "conduction" system allows the heart to beat at a rate -­influenced by nerve and hormonal messages -- which allows the necessary amount of oxygen to be delivered to the organs of the body. If muscular exertion or other influences, such as fright, increase the oxygen demand, the heart rate increases as a result. Damage to the conduction system interferes with such a rate increase, and also usually causes a slow resting heart rate. This results in weakness, shortness of breath, and eventual cellular damage. These conduction defects can be "intennittent" and give rise to a highly variable heart rate.

105

RJ. van de Plassche et al. (eds.), Analog Circuit Design, 105-126. C 1995 Kluwer Academic Publishers.

106

A pacemaker delivers an electrical stimulus pulse to the heart which causes it to contract. By adjusting the rate of the stimulus, the heart rate may be likewise adjusted and thereby increased to allow greater oxygen delivery to the body.

The pacemaker was first commercialized (in an external unit) in the early 1930' s and used a clockwork mechanism for timing. In this early unit, the stimulus was delivered to the heart muscle by means of needle electrodes, and thus could only be used temporarily. The first implantable pacemaker was introduced in 1958. This device contained Mercury batteries and a simple discrete transistor circuit in an epoxy case. (Refer to Figure 1.) It operated at a fixed rate and provided stimulation pulses whether or not the heart needed them. The problem with this method of operation is that, should synchrony be lost, a stimulus pulse delivered during an incorrect portion of the cardiac cycle would be very dangerous. This meant that the heart had to be kept in lock with the stimulus pulse train. High pulse energies were needed to ensure "capture" of the heart cycle.

The initial pacemakers were adjustable, but only by means of a needle inserted into a port in the unit to adjust a potentiometer. This obviously wasn't a procedure that one wished to perform often. The drawbacks, then, of first generation pacemakers were lack of ease of adjustability and the asynchronous nature of their operation.

The addition of an amplifier and filter and some simple logic allowed the pacemaker to "monitor" the patient's cardiac cycle and provide stimulus pulses only when the patient's heart did not beat in time. This reduced the risk of asynchronous pacing and reduced the energy needed, since the unit only paced upon "demand." The electrode used to sense the heart's activity was the same as that providing the stimulus pulse. Cardiac signals obtained in this way range between about 0.2 m V and 5 m V in amplitude and have information in the frequency range of 10 Hz to 200 Hz. In early demand pacemakers, the amplifier and filter (referred to together as a "sense amplifier") were fabricated first in hybrid and then in bipolar IC technology. Demand pacemakers first appeared in 1966.

Pacemaker battery technology changed from Mercury to Lithium chemistry in the early 1970's. Lithium batteries give high energy density and no gas generation. This allowed pacemaker manufacturers to use a metal case to hermetically enclose the electronics and battery. This packaging method substantially improved reliability and virtually eliminated the problems of sensitivity to EM!. Smaller physical dimensions also resulted.

Adding low power digital logic and a means for receiving a high­frequency signal allowed the pacemaker to be externally adjustable and provided additional performance enhancements. This advance was made possible by the development of CMOS technology in the mid 1970' s.

107

Not only the pulse rate but also pulse width, pulse amplitude and sensitivity of the input amplifier could be adjusted through this means.

The capability to send data from the pacemaker to external equipment was added shortly thereafter (by 1980). Data such as the contents of internal programming .registers, battery state, and perhaps the actual analog signal from the heart lead (usually transmitted as a simple pulse FM) made up the information transmitted up to the external programming system.

By adding a second entire channel, both the upper and the lower chambers of the heart could be monitored and paced. This "dual chamber" pacemaker has several advantages. If the low heart rate is due to loss of conduction of the signal, and thus pumping synchrony, between the upper and lower chambers of the heart, then a dual chamber pacemaker can restore that synchrony. This gives not only a higher heart rate, but one which responds to the needs of the body when activity level is bigher, because the upper chamber responds to activity by increasing its rate. If the pacemaker senses this rate change, it can increase the rate of the lower chamber -- in physiologically appropriate synchronization. This is significant because the lower chambers of the heart are the powerful pumps and their rate and coordination with the upper chambers is important to give best cardiac pumping efficiency. Dual­chamber pacemakers appeared in the early 1980's.

Modem pacemakers -- both single and dual chamber -- have improved the quantity and accuracy of the data telemetered out, measuring the battery voltage, energy usage, electrode condition, and the analog heart signal. In some units, a short sequence of this internal EKG may be stored digitally for later "playback" as a diagnostic tool. In addition, the latest generation of pacemakers includes sensors and circuitry to actually monitor the patient's level of physical activity (usually by sensing motion or vibration) to allow the unit to speed up or slow down the heart rate according to the activity level of the moment. This capability allows the unit to "mimic" the body's normal responses very closely. A block diagram of a modem dual-chamber pacemaker is illustrated in Figure 2.

In light of all the capability contained in a modem pacemaker, battery life is a key concern. Battery capacity is customarily measured in Ampere-hours, but for low power devices like pacemakers it is useful to convert to a different set of units. One Amp-hr. equals 114 ~A-years, so for a ten-year pacemaker using a 1 A-br battery, the total current drain may be only 10 ~. Since the stimulus pulse might typically be 400 ~s wide at a 1.2 Hz rate (72 beats per minute) at 5 V, the average current needed for stimulation is about 3 ~. Thus, all other circuitry must operate on less than 7 ~A. The situation is even more challenging for a dual-chamber unit, having about twice the circuitry. This challenge is being met by modem pacemakers.

In the following sections, the major stages of a modem pacemaker will be discussed, and some typical circuits described.

\08

1.2 Sense Amplifiers Sense amplifiers are amplifier/filter/comparator circuits which

determine if a heart beat has occurred. The typical approach is to amplify the signal, bandpass fIlter it, and then compare it to a reference voltage. A digital output signal i$ asserted if the magnitude of the signal exceeds a programmed threshold. The threshold levels generally range from about 150 J1V to 10 mV (referred to the input).

Early pacemakers used bipolar integrated circuits with numerous external components for sense amplifiers. The IC contained low power operational amplifiers, a simple bandgap voltage reference, and a voltage comparator. External passive components were used to determine the frequency response and gain of the filters. Control signals from a CMOS timing chip selected preamplifier gain and comparison threshold. The comparator's digital output was then directed back to the CMOS chip to control timing.

To reduce the complexity of pacemaker systems, analog sections were subsequently integrated on the same CMOS chip as the timing and programming blocks. This was accomplished through the use of switched-capacitor filter (SCF) circuits. SCFs allow accurate frequency shaping without precision components. However, they require anti-alias pre-filtering, so that some external passive components were still needed. In addition, instead of amplifiers having bandwidths only high enough to ensure proper analog filter characteristics, wider amplifier bandwidths were needed in order to ensure settling at the SCF clock frequencies (usually 1-2 kHz). A typical switched capacitor filter sense amplifier is shown in Figure 3.

Because' of the shortcomings of SCFs, a return to continuous-time filters is occurring. Continuous-time filters allow smaller numbers of external components, even if some are used in controlling the filter response. More importantly, amplifier bias current may be decreased significantly because of the reduced bandwidth required. Circuitry for clock generation and distribution is eliminated as well. A continuous­time fIlter having a similar response to that of the SCF previously shown is illustrated in Figure 4. In both cases, amplifiers use MOS devices operated in the weak inversion region to obtain high gain and low current.

1.3 Measurement Circuitry The measurement of battery voltage, electrode characteristics, and

other analog quantities requires an ADC. The first systems having this capability made use of a simple capacitive charge redistribution converter,as shown in Figure 5, Oversampled ADCs are used in several modern pacemakers, because of their structural simplicity. Relaxed anti­alias filter requirements also result because of the higher input sampling rate.

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1.4 Output Stimulus Generation Output stimulus pulses are needed with widely adjustable amplitudes

to allow use of the minimum safe pulse energy. The efficiency of the stimulus generation is very important since this block often has the highest current drain in the system. Output amplitudes usually range from 200 mV to 8 V. .

The basic capacitive charge pumping approach to generating an output voltage is shown in Figure 6. This method is used to provide fractions and mUltiples of the battery voltage with high efficiency. (Overhead current drains of 10 - 100 nA are normally observed.) To obtain intermediate levels, linear regulation is often used.

2 Hearing Aid Technology 2.1 Introduction

Hearing loss is the most frequently occurring disability, and it is a condition many of us will face as we age. Loss also may be caused or worsened due to noise exposure. This impairment occurs in a way that is difficult to correct, because it is usually both frequency dependent and involves a diminution of dynamic range. That is, the loss usually occurs by a significant increase in the sound level needed for threshold (how loud sounds must be to be just audible), but not much increase in the loudness levels that are uncomfortably loud. This dynamic range reduction varies with frequency, usually becoming worse at higher frequencies.

A hearing aid, therefore, must be able to modify the signal in both amplitude and frequency in a way which depends on the sound level. The dynamic range must be compressed so that soft sounds are amplified to allow them to be heard, but loud sounds are not amplified very much. Moreover, higher frequencies must be amplified more at low sound levels. Gain or frequency response changes, as they occur, must also not cause unnatural sounds. An additional complication is the effect on frequency response due to the presence of a hearing aid in the ear canal: this "occlusion" effect eliminates a boost at about 2 kHz due to acoustic resonance of the canal. Lack of this boost effect causes an unnatural "hollow" sound.

The power supply for a hearing aid is a small battery which is replaced periodically by the patient. Replacement intervals of about a week are customary, so the size of the unit is generally determined by the amount of output power required. If hearing loss is slight, a very small unit is possible which is placed entirely within the ear canal. If loss is profound, power requirements are such that the unit is large enough to have to be placed behind the ear. Intermediate sizes fit in the ear and are compact to the degree that the battery and circuitry sizes allow. The initial battery voltage is typically 1.35 V, declining to about 1.1 V at

110

depletion. This low supply voltage is a challenge for the circuit designer, severely limiting the number of devices that can be "stacked up" in a circuit. The limitation is even more difficult for MOS circuits using standard processes, since VT ranges usually go as high as 1.0 or 1.1 V. Bipolar devices are useful, because of their higher transconductance and lower and better controlled input voltage characteristics.

A typical modem hearing aid is composed of a microphone preamplifier, filters, variable gain or frequency stages, a control block (to adjust the gain or frequency in response to an input), and an output amplifier to drive the miniature loudspeaker (referred to as a "receiver"). The block diagram of a modern hearing aid circuit is shown in Figure 7. In the following, these blocks will be discussed and examples provided.

2.2 Preamp The microphone preamp increases the level of the microphone signal

by typically 20 dB. Low noise and wide input range are requirements of the preamp. A typical preamp in BiCMOS technology is shown in Figure 8.

2.3 Fllters Filters are needed to correct for frequency-dependent loss as well as

the occlusion effect of the hearing aid in the ear canal. The types of filters used range from simple RC filters, with little or no adjustability, to multiple bandpass filters arranged much like a graphic equalizer. In one product, 13 bandpass filters are used, arranged in roughly one-third octave bands.

Two example filters are shown below. The first is an active continuous-time adjustable high-pass filter used to provide enhanced speech comprehension in noise. The second is a three-band switched capacitor filter used in the same product to adjust for loss and the occlusion effect mentioned above.

The first filter is a fourth-order Sallen-Key highpass made using variable transconductance blocks in place of the resistors (see Figure 9). Two identical second-order blocks are used in cascade. The transconductor was designed for large signal dynamic range and wide transconductance control range. The control of transconductance, and thus the cutoff frequency, comes from a circuit which develops a control voltage in response to the magnitude of the input signal. The circuit also controls the attack and release times of the bandwidth control. Frequency response characteristics of this filter are shown in Figure 10. The variation of frequency response with input levels is shown, with the cutoff frequency rising as input increases.

The second filter is composed of three fourth-order switched capacitor stages whose output is summed through variable resistances. The clock frequency is variable, allowing flexibility in the adjustment of frequency

III

response. Elliptical bighpass and lowpass, and Chebychev bandpass filters are used, as shown in Figures 11 and 12. The frequency responses of the three filters are shown in Figure 13.

Using switched capacitor circuits at 1 volt with a standard CMOS fabrication process required a clock boost circuit as well as a negative power supply rail generator. The clock generation circuits are shown in Figure 14.

2.4 Gain Control/Compression In the circuit discussed above, the control of amplification, as a

function of incoming signal level occurred by means of changes in filter band edge frequencies. Another option is to split the incoming signal into several bands and apply amplitude compression to some or all of them. Modem hearing aids have from 2 to 13 bands with compression.

2.5 Output Amplifier Because of the requirements of low quiescent power and high output,

pulse-width modulation is often used in the output amplifier stage. This type of amplifier is designated "Class D." To obtain the maximum output level, both sides of the receiver are driven with signals out of phase (a "bridge" output). A diagram of this method is shown in Figure 15.

3 Conclusion Modem low-power medical devices may be characterized as digitally­controlled analog systems. That is, the signal path is almost entirely analog, and the digital sections of these devices are used for timing and control. In the future, more digital signal processing will be employed. A programmable digital signal processing approach offers great flexibility. In both the cardiac pacemaker and the hearing aid, this flexibility will allow the electronic system to adapt its performance automatically to the needs of the patient. In pacemakers, the unit will adjust the parameters of stimulation as needed and also will "learn" the electronic cardiac signature of the specific patient. In hearing aids, a digital approach will allow better speech comprehension by suppressing background noise, while giving more natural sound in varying environments. In both types of devices, the application of advanced technology and innovative design techniques will allow a more nearly perfect or "transparent" augmentation of the biological system.

112

References

1. Geddes, L., Historical Highlights in Cardiac Pacing, IEEE Eneineerine in Medicine and Bioloey, pp. 12-18, June 1990.

2. Ryan, T., YLSI Electronics: Microstructure Science (Chapter 7. Cardiac Pacemakers), Vol. 17 ,Academic Press, 1989.

3. Stotts, L., Introduction to Implantable Biomedical IC Design, IEEE Circuits and Devices, pp. 12-18, January 1989.

4. Teel, T. and Wayne, D., A Standard Cell Approach to Analog IC Design Utilizing Subthreshold Building Blocks, IEEE Custom Inteerated Circuits Conference, pp. 484-490, 1985.

5. Preves. D., Understandine Dieitally Proerammable Hearine Aids (Chapter 12), Allyn and Bacon, 1994.

6. Steams, W., Rationale for Multi-Channel Filtering in Hearing Aids, Hearine Instruments, pp. 28-30, 1984.

7. Killion, M., The K-Amp Hearing Aid: An Attempt to Present High Fidelity for Persons with Impaired Hearing, Am. J. of Audioloey, pp. 52-74, 1993.

8. Callias, F. et al, A Set of Four ICs in CMOS Technology for a Programmable Hearing Aid, IEEE J. of Solid-State Circuits, pp. 301-312, 1989.

9. Ong, D., Designing Programmable Hearing Aids Using BiCMOS, IEEE ASIC Conference. 1992.

10. Wayne, D. et al, A Single-Chip Hearing Aid with One Volt Switched­Capacitor Filters, IEEE Custom Integrated Circuits Conference, pp. 7.5.1 - 7.5.4, 1992.

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INTEGRATED FILTERS

R.J. van de Plassche

Preface

The integration of a system on a chip requires in many cases some kind of analog filtering. In discrete time systems mostly filtering is used to avoid aliasing of signals or reject the repeated signal bands due to the sampling operation. In other applications filters are used to detennine the wanted signal frequency spectrum. When such filters are implemented as an external filter than usually cost goes up, a number of extra pins to the integrated circuit are needed and at the same time accuracy problems may be introduced. The integration of the filter function on the chip is thus an important item. System cost is lowered, while at the same time the total function is more accurately fulfilled. However, in an integrated circuit inductors are practically unusable because of the low quality factor (between 3 and 5 for silicon). Therefore all circuits will use resistors and capacitors to obtain the filtering function. In this Session nearly all known techniques to construct integrated filters will be discussed.

The first paper by Y. Tsividis gives an overview of the different techniques that are used to construct an integrated filter today and ideas that are at the experimental stage and will be used in the future. It is an introduction to the upcoming papers that discuss in more detail the implementation of integrated filters.

The second paper by M. Steyaert and 1. Crols describes a polyphase analog filter to construct an accurate band-pass filter for application in a low-IF receiver structure. The polyphase structure allows the implementation of a non­symmetrical filter function with respect to frequency. For example negative signal frequencies can be rejected, while positive frequencies are band-passed. Such systems are very useful in receiver applications.

The third paper by 1M. Khoury discusses theory and practice of fully-integrated continuous-time trans conductor-capacitor filters. These types of filters are widely used in integrated circuits because of the accuracy of implementation, the low­power consumption and the higher frequencies for which they can be applied.

The fourth paper by J. Hughes and K. Moulding discusses the application of current copier cells for high-accuracy wide-band filter applications. Current copier cells can be used to design simple integrated filters. An improved copier

127

R.J. van de Plassche et aL (eds.), Analog Circuit Design. 127-128. C 1995 Kluwer Academic Publishers.

128

structure is described and a demonstration of the technique is given using an 8 MHz low-pass filter structure. Perfonnance of these filters is comparable to switched capacitor filter structures.

The fifth paper by R. Taylor describes practical design problems encountered by the implementation of a filter using a switched capacitor architecture. The limitations include capacitor sizing and matching problems, amplifier speed and switch charge injection and resistance. Different methods to overcome these limitation are examined.

The last paper in this session by D. Allstot and R. Zele describes current-mode continuous-time filter structures to be implemented on silicon. The advantage of a current mode architecture is the low internal voltage swing resulting in filter implementations with supply voltages as low as 3 Volts. A simulation example of a filter implementation using a three-pole lowpass filter with a -3 dB bandwidth of 125 MHz is given.

From these practical examples it has become clear that the design of integrated filters has become an important issue for a system on a chip integration. Designers have to pick the best suitable architecture for their specific problem. However, the design of high-frequency low-power filter functions remains a difficult subject.

DEVELOPMENTS IN INTEGRATED CONTINUOUS TIME FILTERS

Yannis Tsividis

Division of Computer Science National Technical University of Athens

Heroon Polytechniou 9 Zographou 15773 Athens, Greece

ABSTRACT

Developments in integrated continous time filters are reviewed. For completeness, well-established techiques are included in the discussion; however, emphasis is placed on emerging techiques, ideas that are at the experimental stage, and promising ideas that, although not recent, have yet to be adopted on a large scale.

1. INTRODUCTION

Integrated continuous-time (CT) filtering is today a recognized, industry proven signal processing technique, employed in a variety of applications [1]. Most of these applications belong to the niche of high­frequency medium dynamic range signal processing when the signal is already in analog form. In such cases, CT filters avoid problems related to sampling and switching and can offer advantages in terms of power dissipation in comparison to digital filters [2].

A variety of techniques have been proposed for implementing CT filters. The currently dominant transconductor-C technique is discussed

129 RJ. VQ/I de PItusche., al. (eds.). Arralog Circui, Daign. 129-148. C 1995 Kluwt!r AcademIc PubUsht!n.

130

elsewhere in this volume. In addition, several review articles discussing continuous-time filters have recently been published [3-5]. For these reasons, our overview of established techiques in this paper will be kept short, and most space will be devoted to several less well-established and less well-documented techiques. We will include techiques that have proven their capabilities and are awaiting wide adoption, as well as ideas that are currently at the experimental stage; of the latter, some may never "make it", but all are interesting and may help spark other ideas that may prove fertile.

Most CT filter chips reported are based on integrators, and are synthesized using biquads, leap-frog topologies, or gyrators (which can be composed of two integrators in a loop). Synthesis techniques are summarized elsewhere [3,4]. Fig. 1 shows three extensively discussed techniques for making on-chip integrators; these will now be briefly reviewed.

2. Gm-C FILTERS

The Gm-C techique, shown in Fig. 1 a, is by far the most established one [6-15]. It produces an integrator with unity-gain frequency Gm/C. This circuit can otTer high-frequency operation thanks to the fact that no low-impedance output stage is needed. The trans conductor needs to be tunable, in order to make possible corrections for tolerances, temperature variations, aging, etc. Tunability is usually accomplished by voltage or current-controlled transistors, which are linearized using a variety of techniques [6-15, 1, 3-5]. More details on Gm-C integrators, and on filters composed of such integrators, can be found in the chapter by John Khoury elsewhere in this volume [16].

3. Gm-C-OTA FILTERS

The main disadvantage of Gm-C filters is the strong etTect of paracitic capacitances, which contribute to both mismatches and nonlinearities [5]. This problem can be significantly reduced by adding an operational transconductance amplifier (OTA), leading to the Gm-C-OTA integrator of Fig. lb [17-19] (by "OTA" we mean an op amp without a low-impedance output stage, with its input operating at virtual short-circuit; a "transonductor" is instead an element that needs to be

131

able to handle large input signals, and whose transconductance must be accurately controlled). The approximation of a virtual ground at the OT A input helps reduce the effect of parasitics, and makes the design of the trans conductor's output stage easier, in terms of both output impedance and signal swing. The use of a simple OT A is sufficient, since the total integrator dc gain is the product of the dc gains of the OTA and the trans conductor, and is thus sufficiently large to reduce phase lead errors that are caused by finite dc gain.

In a recently presented Gm-C-OTA 8 MHz low-pass filter [19], fixed linear resistors are used in the trans conductors for high linearity, and tunability is achieved using a current multiplier (also used in some Gm-C filters [4])~ HDTV-compatible performance is demonstrated using this approach.

4. MOSFET-C-OP AMP FILTERS

Each of the two active elements in Fig. 1 b draws power and contributes to excess noise. This problem can become more serious when signal addition is needed, since then one needs one transconductor (or, at least, one transconductor input stage) per input signal. One can thus consider replacing transconductors by passive elements, as shown in the MOSFET-C-op amp integrator of Fig. Ic [20-25]. Here the MOSFETs implement tunable resistors, the dominant (even) nonlinearities of which can be shown to cancel out. For additional linearization, and for better immunity to substrate noise and common-mode offsets, one can replace the two MOSFETs in Fig. 1 c by the Czamul-Song circuit of Fig. 2 [26, 27] ; the advantages of this circuit must, however, be weighed against an increase in power dissipation (to drive the extra MOSFETs), and a moderate increase in random noise and mismatch efects. The main disadvantage of the MOSFET -C op amp tecnique is the need for an op amp with a low-impedance output stage, to drive the MOSFET resistors. Techiques to deal with this problem are discussed in the next two sections.

5. MOSFET-C-OTA FILTERS

One way to deal with the resistor-driving requirement in MOSFET-C filters, is to replace the op amp in Fig. 1 c by an OT A, and to boost the

132

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133

OTA's transconductance to very high values [22, 23]. It can then be shown [5] that the circuit behaves as if an op amp were used in it. For high frequency filters, in which impedance levels are low, the OTA's trancsconductance must be so high that a CMOS implementation becomes difficult; however, BiCMOS is a natural for this approach: bipolar transistors (further aided by positive feedback) can be used to provide the high transconductance [22, 23], whereras MOSFETs are still used to provide the tunable resistors. Using this approach, Ref. [23] reports a fifth-order video filter in 1.5 urn BiCMOS, dissipating 13 mW, with a dynamic range of 70 dB (at 1 % 3d-order IMD) and with a chip area of 0.3 mm2. Ref. [22] mentions a 216 MHz oscillator using the same techique. Thus, in BiCMOS technology MOSFET -C circuits become atractive at high frequencies. The flexibility offered by these circuits is significant; as an example, Fig. 3 shows a MOSFET -C biquad [22] which can implement low-pass, high-pass, band-pass, and all-pass responses. The Czarnul-Song circuit of Fig. 2 can of course be used in conjunction with this biquad too.

6. FILTERS USING INTEGRA TORS WITH LOW (BUT PRECISE) DC GAIN

In all techniques discussed, it is usually attempted to make the integrator dc gains sufficiently large, so that the phase lead caused by finite dc gain [3-5] becomes negligible. The achievement of large dc gain is not easy however, (especially in low-voltage circuits), and may involve compromising other performance parameters. An alternate approach has recently been pursued [28, 29]: the dc gain is allowed to be small, but it is made predictable and its effect is taken into account in the design process. Consider, for example [28], a resistive-load differential amplifier using bipolar transistors. The amplifier is biased by a current derived by applying to an on-chip resistor R a voltage which is proportional to absolute temperature. Well-known circuit techniques can be used to generate this current. The transistor transconductance, gm=qIlkT, thus becomes independent of temperature and inversely proportional to R; thus the gain, gmRL, where RL is the load resistance, becomes proportional to RUR, which is well-controlled. In addition, the use of resistive loads makes the output dc level well controlled, without the need for using complicated common-mode feedback circuitry. This technique can be considered for application in a several types of

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continuous-time filters. The analysis in [28, 29] is very helpful for estimating the limits of the approach in the presence of realistic tolerances.

7. TRUE ACTIVE RC FILTERS

Integrated filters using RC intergrators with true resistors (as opposed to MOSFETs) have been presented [30, 31]. Very careful considerations of the possible sources of nonlinearity have produced integrated filters with over 95 dB dynamic range, compatible for 16-bit digital audio. Since the linear resistors used are fixed, element arrays are used for tuning, which is accomplished in discrete steps.

8. R-MOSFET-C FILTERS

Hybrids between true RC and MOSFET -C balanced integrators have been proposed [32-33]. The linear resistors help improve linearity above that obtainable with MOSFET -C filters, whereas the presence of MOSFETS allows continuous tuning. One version of this approach has been demonstrated in a fifth-order audio filter [32].

9. INDIVIDUALLY LINEARIZED TUNABLE RESISTORS

The use of MOSFETS in conjunction with resistors in the techiques just discussed represents attemps to allow for some tunability at the expense of linearity. Attempts to make individually linearized tunable resistors have also been made; several can be found in the references given in [1, p. 49]. Most of these cancel the dominant nonlinearities in the MOSFET characteristics, but do not cancel residual nonlinearities due to the body effect along the channel, and the dependence of mobility on the gate-channel Voltage. A resistor that is, in principle, not affected by these has been proposed in [34]. Both the gate and the body are used as resistors with voltage applied along each. Even in the presence of signals, a fixed voltage is maintained all along the depletion region; thus the body effect is not activated by the signal. Also, a fixed voltage is maintained all along the oxide; thus, the mobility is fixed even in the presence of signals. In this way the channel becomes a linear, voltage-controlled resistor. A variety of higher-order effects, though, and the significant overhead of the peripheral circuitry, have so far limited

the possibilities of this scheme.

10. FILTERS USING PURELY "DIGITAL" FABRICATION PROCESSES

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There are obvious cost advantages in making possible analog filters on chips fabricated with conventional, "no capacitor", digital processes. This challenge has successfully been met by switched-current filters, reviewed in this book in the chapter by John Hughes. In the continuous-time domain things are more difficult. Possibilities here include the use of junction capacitors [35, 4, 22, 23], the use of MOS capacitors in inversion [36] or accumulation [37] in voltage-mode filters, the use of MOS capacitors in inversion in current-mode filters [38, 39], and the use of MOS transistors as distributed RC elements [40]. Of these, current-mode continuous-time filters are discussed in another chapter in this volume by David Allstot and Rajesh Zele [39]. Due to the nonlinearities involved, obtaining large signal swings using any of the above techniques is a challenge.

11. RF FILTERS

Wireless communications have opened up a wide area of application for continuous-time filters. Some of the required filters are difficult or impossible to place on a chip, due to dynamic range limitations, especially in high selectivity applications. There are some points in the transceiver chain, however (e.g., in certain parts of the transmitter exciter), where the signals are of fixed amplitude, and the signal-to-noise requirements are modest. In such cases, integrated CT filters may be suitable. At frequencies around I GHz, inductors with Q values in the range of 3 to 10 can be integrated within a reasonable chip area using conventional technology [41, 42, 43]. These can be used for passive filtering . The Q of a passive filter is limited by the Q of the inductors in it. In cases where higher-Q filters are needed, one can consider enhancing the passive inductor Q by active circuits. One can compensate the losses by using a negative resistance in series with the inductor [44], or in parallel with it [45]. An implementation example of the latter approach is shown in Fig. 4 [46]. Here a transconductor GmI, used with positive feedback, implements the negative conductance; varying Gml through II tunes Q. Gm2 together with the very small resistor R2

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+Vi

-Vi

Fig. 3. A versatile MOSFET-C biquad [22].

Lossy L Inductor

+Vo

-Yo

+ V

LO

Fig. 4. A tunable bandpass RLC filter with active Q enhancement [46].

137

implements a current amplifier which is used for current multiplication; varying Gm2 through 12 tunes the center frequency. Finally, Gm3 drives the entire "tank", and tuning it through 13 adjusts the filter gain. Extensive simulations of this sheme implemented in bipolar technology show promising results oat frequencies around I GHz [46]; however, the above frequency tuning method can significantly add to the power dissipation.

12. LOW VOLTAGE OPERATION

The recent drive towards low-voltage/low-power battery-driven electronics [2] imposes special considerations on the design of CT filters, as it does for most other integrated blocks. In bipolar tecnology there exist several examples where the low voltage challenge has been met successfully [47, 48]. Related techniques can be used with MOSFETs in weak inversion, but the low currents in that regions will limit speed. For high speed work using MOSFETs, one can consider several different posibilities. One is to use Gm-C or Gm-C-OTA filters and to try to modifY existing trasconductor topologies for low-voltage strong-inversion operation, or to attempt to come up with new ones. Another approach is to use the MOSFET -C circuits of Figs. 1 (c) or 2. For the op amps or OTAs used in these circuits, several low-voltage rail-to-rail techniques can be used [49, 50]. To allow rail-to-rail operation of the MOSFET resistors, several options can be considered. One is to use a CMOS technology with a depletion device feature; a compander achieving a large dynamic range with a 1.8 V supply has been demonstrated by Toshiba using this approach [51]. Yet another option is to drive the MOS gates of the above circuits with a voltage higher than the supply voltage used normally for the CMOS devices, provided the technology used does not have a prohibitively low breakdown Voltage. The gate voltage can be obtained from the bipolar part on BiCMOS chips, if that part uses a higher supply voltage [4]. Or, it can be produced by an on-chip charge pump [52], taking advantage of the fact that the gates driven by this higher voltage draw no current. Finally, since the gates in the circuits of Fig. Ic and 2 do not draw current, and since the voltage on them need only vary very slowly (just to compensate for enviromental changes), it may be acceptable in some cases to use a single external battery as a level shifter, for driving the gates of all MOSFET resistors in all filters on a chip. This battery would

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hardly need replacement, and can be viewed as an external component whose cost can be justified if the benefits obtained by the increased signal swing are significant.

13. DYNAMIC RANGE AND POWER DISSIPATION

Decreasing supply voltage values have made it increasingly difficult to achieve adequate dynamic range in CT filters; the decreased signal swings are just not sufficiently larger than random noise or the interference from the digital circuits on the same chip. As is the case with switched-capacitor filters [53], increasing the maximum achievable dynamic range of a continuous-time filter makes necessary an increase in chip area and power dissipation [2, 4, 50, 54, 55, 5], especially for high Q designs. For high frequency operation, there is the additional complication of further increased power consumption. Dynamic range is perhaps the key issue in CT filters today, in the context of low-voltage circuits. A detailed study of techniques for achieving optimum dynamic range for a given power dissipation in the context of micropower CT filters is presented by Groenewold, Monna and Nauta elsewhere in this volume [50].

14. THE USE OF COMPANDING

In an attempt to increase the dynamic range of CT filters, the use of companding (compressing/expanding) has been proposed [56-60]. Both instantaneous [56, 59, 60] and syllabic [57, 58] companding have been considered. The advantages and disadvantages of these methods have not been adequately investigated at the time of this writing.

15. AUTOMATIC TUNING

Precision automatic tuning continues to present a challenge in conjunction with any of the techniques discussed above. The dominant techniques for automatic tuning are shown in Fig. 5. In each, an on-chip reference circuit is monitored and tuned, and the main filter becomes tuned by virtue of matching. These techniques have been extensively discussed elsewhere [6-9, 11-14, 17-19,21,24,25,30-32,35,47,61-67, 1, 3]. While most filters in use employ continuous-time ciruits to monitor sinusoidal steady state responses, techniques employing

EXT. RESISTOR

PHASE ~ CLOCK COMPo

1 M PHASE TEXT. [ , I COMPo SIGNAL

Fig. 5. Common techniques for automatic filter tuning_

139

140

swiched capacitors have been reported [63, 24, 32], as are techniques which tune through monitoring pulse responses [64]. The use of adaptive techniques has been reported in [67].

The true challenge for automatic tuning lies, of course, in very high Q designs (1 /Q less than the achievable matching), in which case indirect tuning as in Fig. 5 is no longer feasible. A possibility here is to use direct tuning [65, 25], in which the very filter that processes the signal is briefly taken off service in order to be tuned automatically. For continuous service one can consider complementary direct tuning which uses two filters, with one being tuned while the other processes the signal; this technique presents the challenge of achieving a "seamless" transition at the output every time the tuned filter is reconnected to the output [65]. Another possiblily is to tune the very filter that processes the signal, while it is processing it [66]. This presents the challenge of finding two paths within the same filter, (one for the signal being processed, and another for the tuning "pilot"signal), in such a way that the two do no interfere with each other. Both approaches are at their infancy, with many issues remaining to be addressed.

16. CONCLUSIONS

Continuous-time filtering is and will be indispensable in many cases. One reason for this is that, no matter what progress is made by digital and other sampled-data filters, antialiasing and smoothing will be needed at analog interfaces, which are found in an ever-expanding variety of aplications. In addition, even in cases where continuous-time filtering is not mandatory, it may offer advantages in terms of high frequency performance and/or low power, especially in medium dynamic range applications. Despite the adoption of continuous-time filtering techniques in several products, work on such techniques continues as vigorously as ever, since new challenges have presented themselves on a large scale. These include low voltage and micropower operation and the use of on-chip inductors. We have briefly discussed these and other challenges, emphasizing techniques under development.

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Analog Integrated Polyphase Filters

Michiel Steyaert and Jan Crols

K.U.Leuven, ESAT-MICAS, Kardinaal Mercierlaan 94, B-3001 Heverlee, Belgium

Abstract

When it comes to integratability, the zero-IF receiver is an alternative for the

heterodyne or IF receiver. In recent years it has been introduced in several

applications, but its performance can not be compared to that of the IF receiver

yet. In this paper the principle of the low-IF receiver is introduced. The low-IF

receiver has a topology which is closely related to the zero-IF receiver. Like the

zero-IF receiver, the implementation of a low-IF receiver can be done with a

high degree of integration. Its performance can however be better. The low-IF

receiver is not sensitive to DC-offsets or LO to RF crosstalk. The principle of

the low-IF receiver is based on the replacement of the LF lowpass filter of a

zero-IF receiver with an analog integrated active polyphase filter. An active

polyphase filter can perform a lowpass filter operation shifted on to a center

frequency. In this paper the realization of a 5th order lowpass Butterworth filter

centered around a low IF of 250 kHz is presented. This polyphase filter is

designed for a low-IF receiver for high quality applications. The filter is implemented with the active-RC technique in a standard 1.2 J.1m CMOS

process.

1. Introduction

In this paper the design of highly integrated and high performant receivers for digital and continuous time telecommunication systems based on phase and frequency modulation is discussed. In the most recent years the use of

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RJ. van tk Pltusche et aI. (eds.), Analog Circuit Design, 149-166. C 1995 Kluwer Academic Publishers.

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digital signal processors (DSP's) has been introduced in this type of receivers. DSP's enable the use of complex demodulation algorithm and this makes an important quality improvement possible. Both for existing communication systems, like the public PM broadcasting at 100 MHz [1], as for new digital systems in which now more complex modulation schemes can be used [2]. However, the use of DSP's is still limited to the final demodulation of the wanted signal at baseband or almost baseband. The downconversion from its carrier frequency and the separation of the wanted signal from its neighbours by means of filtering still have to be done with analog components. Integrating these high frequency, high dynamic range components without the loss of performance is a problem.

The heterodyne or IF receiver is the best known and most frequently used receiver topology. It can be high performant, but integration of its components, especially its filter sections, is in that case not possible. The problem of the mirror signal suppression requires the use of a high quality tuneable HF (high frequency) filter and a high quality IF (intermediate frequency) filter. Both filters can not be realized in an analog integrated way and only the quality of discrete, sensitive and expensive components is acceptable. The IF must be situated relatively high (like on about 1/10 of the carrier frequency) and sometimes several IF stages are required before a suitable AID-conversion can be performed. This makes the IF receiver even more expensive.

In the last few year the zero-IF receiver has been introduced in several digital telecommunication systems [3],[4]. The main advantage of a zero­IF receivers over an IF receiver is the very high integration level that can be achieved. In the zero-IF topology the wanted signal is directly downconverted to the baseband and only a low-Q HF filter and two easy integratable lowpass filters are required. Although full integration is very important for cost reduction, the use of zero-IF receivers, a receiver topology which has already been known for years, was very limited in the past and this is due to its poor performance compared to IF receivers. It is only nowadays that one begins to use zero-IF receivers in systems based on digital communications. In these systems a lower performance can be accepted in exchange for the higher degree of integration and the ease with which a zero-IF receiver can be combined with a DSP for the baseband demodulation of the digital signal.

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In this paper the low-IF receiver is introduced. Its topology is based on the use of an integrated active polyphase filter. The low-IF receiver combines the advantages of both IF and zero-IF receivers and it makes the realization of highly integrated and high performant receivers possible. In the second part of this paper the advantages and disadvantages of IF and zero-IF receivers are discussed. The principle of the low-IF receiver is introduced and it is shown how this topology can combine the advantages of both IF and zero-IF receivers. In the third part of this paper analog polyphase filters are presented. Their properties and behaviour are discussed and the implications of analog implementation of these filters are explained. The fourth part of this text deals with the design and realization of an active integrated 5th order Butterworth polyphase filter for a low-IF receiver. In the fifth and final part of this text the performance of this filter is analysed and the results are discussed.

2. Integrated receivers

A. IF receivers

IF receivers are the most often used type of receivers and their way of operating is very well known [5]. In fig. 1 a schematic representation of the IF receiver topology is given. The antenna signal, i.e. the wanted signal and its neighbours, is downconverted from its carrier to the IF by multiplying it with a single sinusoidal signal. On the IF the wanted signal is filtered out and then it can be either demodulated on this intermediate frequency or it can, when the signal quality is not yet good enough, be further downconverted and filtered.

:F-A~ ~ I • * Demodulator

Fig. 1 : The IF receiver topology

152

The main disadvantage here is that apart from the wanted signal also an unwanted signal, called the mirror frequency, is downconverted to the IF. When the wanted signal is situated on Ie' the mirror frequency is on Ie - 2 Ii' This is illustrated with equation 1. The output of the mixer gives a frequency component on Ii for I" = Ie and I" = Ie -2/i' The antenna signal a(t) is in this case a phase modulated signal and equal to cos(21Cf"t + m(t) + q,).

a(t)xsin(21C(/e - li)t+ qJ)

= cos(21Cf" + m(t) + q,) x sin(21C(/e - I)t + qJ)

= ~[Sin(21C(/" + Ie - li)t+ m(t)+ q, + qJ)

-sin(21C(/" - Ie + li)t + m(t)+ q, - qJ)]

(1)

The downconversion process is illustrated with fig. 2. The signal on the mirror frequency has to be suppressed at high frequencies before it is mixed down to the IF and this is not easy. An HF filter can only be realized if Ii is high enough. Even when the ratio 2· Ie / Ii is chosen as small as 20, the specifications for the HF filter are still very severe. This ratio is equal to the relative distance between the wanted signal and the mirror signal. The required Q-factor of the HF must be proportional to this ratio and is therefore very high (e.g. 40 or more for a ratio of 20). The center frequency of the HF filter must be tuneable and in high quality application the HF filter must also have a high order (uptil6th order for a mirror signal suppression of 60 to 70 dB). A filter with these specifications can not be integrated. These filters are realized with discrete components. They consist of capacitors and inductors which have to be tuned during production. The tuneabilaty of the center frequency is realized by means of a discrete varicap diode. These HF filters are expensive and vulnerable.

1 LO-s/gnal

t 'IF IF :.": t = c\_r1 "_" D_D ..

I ________ ~ __ ~ _______ L_~

~_j _______ ~_J ________ ~ Fig. 2 : Frequency downconversion in an IF receiver

153

Once the signal is downconverted to the IF. it has to be filtered further on in order to extract the wanted signal from its neighbours. The high IF makes that this filter too must have a high Q (e.g. 50) and a high order (8th or 10th order). Integrating these IF filters is also very hard. Although ever more analog integrated IF filters are published, for most applications they are not good enough and instead ceramic resonators are still being used. In [6],[7] and [8] is shown that the performance of integrated active bandpass filter is intrinsically Q-times more worse than the performance of a passive bandpass filter. This means that the discrete passive bandpass filters will always be a lot better if one is concerned with power and area efficiency. The problem is that, compared to integrated filters, these discrete components are very expensive.

B. Zero-IF receivers

L _________ ! _________ j t _________ l _________ ~

Fig. 3 : Downconversion to baseband with an IF receiver

It might seem that direct downconversion to the baseband is the solution to the mirror signal problem. The IF is then zero and the mirror signal is equal to the wanted signal. Choosing the IF to be zero does however not eliminate the problem of the mirror frequency. A sine brings both the wanted signal from the positive and the negative frequencies to the baseband. Fig. 3 shows how these signals, which are each others mirror image, are superimposed in the baseband. The result is that the lower and upper sideband are placed on top of each other in the baseband and become inseparable. It is not always possible to recover m(t) from cos(m(t) - cp + ¢). This problem is solved by doing the downconversion twice. Once with a sine and once with a cosine. This is what is done in a zero-IF receiver. Fig. 4 gives the zero-IF receiver topology. With equations 2 and 3 this downconversion is calculated.

154

Uj(t) = a(t) x cos(27ifct + qJ)

uq (t) = a(t) x sin(27ifct + qJ) (2)

The original signal m(t) can be found as the angle of the vector (uj (t),uq (t»).

( u (t)J m(t) = arctan -q- + qJ - f/J

uj(t) (3)

The demodulation in a DSP can be done be means of an angle measurement algorithm. The CORDIC algorithm is an example of such an algorithm [9].

Fig. 4 : The zero-IF receiver topology

The downconversion can be calculated in an other and more transparent way with the method of the complex signals [10]. Any vector of two independent signals, like the I and Q signal in a zero-IF receiver, is a complex signal. The I-component is the real part, the Q-component is the imaginary part (u(t) = uj(t)+ juq(t». Complex signals can be analyzed as if they would be one signal with a frequency spectrum which can be different for positive and negative frequencies. Equation 4 gives the downconversion calculated with complex signals. In a zero-IF receiver the wanted signal is downconverted with a single positive frequency. Fig. 5 shows that in this way only the negative frequency components of the wanted signal are downconverted.

U(t) = Uj(t)+ juq(t)

= a(t) x cos(a>ct) + j·a(t)xsin(OJct)

= a(t) X (cos(OJct) + j. sin(OJct»)

= a(t) X ejllJ•1

lSS

(4)

The advantages of the zero-IF receiver are obvious [3],[4]. There is no need for a high-Q tuneable bandpass filter. In most designs a broadband HF filter which requires no tuning or adjusting is used to reduce the dynamic range requirements for the downconversion mixer and prevent mixing of the RF signal with harmonic components of the LO signal. The lowpass filters can easily be realized as analog integrated filters.

I~ LQ.slgnal

Wanlad rt signal ,- -, I

~---------!---------~ Fig. 5 : In a zero-IF receiver the wanted signal is downconverted

with a single positiveJrequency

, ~

The precision with which both demodulation paths (I and Q) can be matched determines how good the mirrored signal can be suppressed. The specifications on mirror suppression are not as severe for a zero-IF receiver as they are for an IF receiver. In an IF receiver extra suppression is needed because the signal on the mirror frequency can be bigger than the wanted signal. However, for high quality application a suppression of 50 dB is still needed in zero-IF receivers. The zero-IF receiver is thus very sensitive to matching and to phase and amplitude errors in the quadrature oscillator.

An other problem in zero-IF receivers is the DC-offset which is created during the downconversion [3],[4]. It is mainly a result of the crosstalk between the RF and LO inputs of the mixers. The multiplication of the LO signal with itself gives a DC (or almost DC) signal. This DC-offset is superimposed on the wanted signal in the baseband. It can only be removed by means of a very long time constant (at least a tenth of a second) and this always results in the loss of a part of the wanted signal

156

which has an effect that is comparable to distortion [11]. The distortion will be lower if the time constant is longer, but long time constants make the settling time of the complete receiver system too long and they can not be analog integrated. For instance, at each change of the carrier frequency the receiver would have to settle for at least a second when a highpass filter of 1 Hz is used. The principle of zero-IF receivers is already known for years. It is however the DC-offset problem that has kept the zero-IF receiver from use in practical applications. It is only with the introduction of DSP's that this problems has become controllable for systems with lower quality specifications [3]. In the DSP a complex non-linear algorithm can be used to determine the DC-level dynamically. This value can then be fed back in to the analog part. In this way saturation of the lowpass filters is prevented and the distortion is kept acceptable.

The crosstalk between LO and RF does not only result in a DC-voltage. The multiplication of the RF signal with itself results in a broadband baseband signal (twice the bandwidth of the RF signal) of which a considerable part of the power is situated in the lower baseband. This signal too is superimposed on the wanted baseband signal and once this is done they can not be separated anymore.

C. Low-IF receivers

The concept of the low-IF receiver topology starts from the observation that all information necessary to separate the mirror signal from the wanted signal is available in the two LF signals when two downconversion paths are used like in a zero-IF receiver. Fig. 5 shows that this is true for the zero IF receiver. Fig. 6 shows that this is also true for an IF different from zero. Mixing with a single positive frequency converts only negative frequency components down. In the complex IF signal the wanted signal is now situated at positive frequencies, the mirror signal is situated at the same, but negative, frequencies. In uj(t) and u/t) both signals are superimposed and unseparable. However, the phase relation between the two superimposed signals is different for uj(t) and uq(t). This is why the two signals are separable in u(t), the complex combination of both LF signals.

LO-slgnal

Mirror Wanted signal signal low-IF low-IF

Fig. 6 : The downconversion in a low-IF receiver is the same as in the zero-IF receiver

157

The low-IF receiver combines the advantages of the IF and the zero-IF receiver. In the low-IF receiver there is no need for any HF suppression of the mirror signal. The HFfilter can be broadband, untuned and cheap: The IF can be chosen low, about once or twice the bandwidth of the wanted signal (e.g. 455 kHz). The IF filters will be LF filters and this makes analog integration easy. The low-IF receiver has this high integratability in common with the zero-IF receiver, but it does not have some of its disadvantages. A low-IF receiver is totally insensitive to any DC-signal, whatever its origin. DC-signal induction is a non-existing problem in low­IF receiver. LO to RF crosstalk is no problem. The effect of RF to LO crosstalk is reduced in low-IF receivers as it is mainly situated around baseband. The main problem of low-IF receivers is the required mirror suppression. Different from the zero-IF receiver, the mirror signal can be bigger than the wanted signal in low-IF receivers and this requires extra suppression. A good choice of the IF is important here. It is best chosen such that the mirror frequency is located between two transmission channels.

Fig. 6 shows that for the actual separation of the wanted and the mirror signal at the low IF a filter is required which has a passband at positive frequencies and which suppresses the negative frequency components of u(t). Such a filter is a polyphase filter. A polyphase filter is a type of filter well known in digital signal processing. Complex signals are a kind of polyphase signals. Actually, they are the 2-phase signals. A polyphase filter operates on polyphase, in this case complex, signals and it can perform a different operations on the positive and negative frequencies which are applied. Polyphase filter are multipath signal processing building blocks and it is again, as for zero-IF receivers, the matching of the different paths that will determine the quality of the receiver. In a DSP this matching can be perfect, but in analog integrated implementations

158

mismatch is unavoidable. Analog polyphase filters have been presented in [12].

3. Polyphase filters

A real filter, this is a filter with a single input and a single output, has a real impulsresponse hr(t). The transfertfunction Hr(jm) is a rational real polynomial function in jm. The consequence is that H,(jm) = H;(-jm). The amplification or suppression of the filter is the same for positive and negative frequencies.

The impulsresponse of a polyphase filter, a multi input and multi output filter, is a polyphase signal. For a 2-phase filter is this a complex signal, h(t) = h,(t) + jhj(t). The transfertfunction H(jm) = H,(jm)+ jHj(jm) is a rational complex polynomial function and this means that the frequency response can be different for positive and negative frequencies.

The most important application for polyphase filters is the suppression of the negative or positive frequency component of a complex signal. This can be done with a bandpass filter which results from the linear transformation of a lowpass filter. The classic lowpass to bandpass transformation does not change the real properties of the lowpass filter.

. . ( ro mc) Jm-+Jm ---CO) m

c

(5)

In this case the bandpass filter has the lowpass fllter characteristic around 0) = ±O)c' After the linear transformation the bandpass filter has the lowpass filter characteristic only around m = +mc'

(6)

This transformation can only be realized as a polyphase filter because it introduces complex coefficient in the rational polynomial transfertfunction of the filter. Equation 7 gives this transform for a first order lowpass filter.

159

The most efficient implementation technique is the direct synthesis of the transfertfunction. Equation 8 is the worked out line¥ transformation of a first order lowpass filter. X(jlO) en Y(jlO) are complex signals.

Y(jlO) _ H (·1O) _ 1 X( . ) - bp J - 1 ·2Q . I JlO -J +JlOlOo

(1- j2Q + jlO/lOo)· Y(jlO) = X(jlO)

jlO/lOo . Y(jlO) = X(jlO) + (j2Q -1)· Y(jlO)

x ,(I)

X; (I)

1

jw/O\,

-1

-1

Y,(I)

y;(t)

Fig. 7 : Blockdiagram of one section of an active polyphase filter

(8)

The realization of equation 8 is given in fig. 7. It can be found by rewriting the complex signals as the sum of their real and imaginary part and then working out the complex multiplications. The required building blocks are summators, amplifiers and integrators.

160

The realization of translated higher order lowpass filters with only poles in their transfertfunction can be done by cascading the structure of fig. 7. The translation adds a complex term, equal to jcoc' to the position of each pole. Complex conjugate poles will not be complex conjugate anymore and all poles will have to be realized seperately. For the implementation of an nth-order filter 2n integrators are required. This is same as when two lowpass filters are used in a zero-IF and it is far less than what would be required when two bandpass filters are used.

The quality of the mirror suppression is determined by the matching in the polyphase filter. Mismatch between the amplifiers and integrators in the two paths results in a crosstalk from negative to positive frequencies and vice-versa. In a perfect polyphase filter the response to a negative frequencies is only this negative frequency. In a slightly mismatched polyphase filter this response is not only this negative frequency. There will also appear a small positive frequency component at the output. This determines the mirror signal suppression. The mirror signal is situated on the negative low-IF, the wanted signal is situated on the positive low-IF. Crosstalk from negative to positive frequencies results in a superposition of a small part of the mirror signal on top of the wanted signal and this superposition can not be corrected anymore.

Fig. 8 gives the topology of the low-IF receiver. The topology, and moreover the actual realization, is not much different from the zero-IF receiver. The lowpass filters are replaced by the translated lowpass filter. The HF and mixer part can be the same as in the zero-IF receiver. The AID-converter and the DSP can also stay exactly the same when the IF is taken equal to the sample frequency of the AID-converter. In this case the aliasing effect of the sample operation will perform the final downconversion to the baseband. The neighbour and aliasing suppressiqn will also be exactly the same if the polyphase filter is a translated version of the originallowpass filter of the zero-IF receiver. The required number of bits of the AID-converter can then stay the same too.

161

Demodulation

Fig. 8 : The low-IF receiver topology

4. A high performance polyphase filter

In this part of the text the implementation of a translated 5th order lowpass Butterworth filter is discussed. The filter is designed for high quality applications and this makes its specifications very high. The wanted signal is available at the output of the filter. It must have a signal to noise ratio (SNR) of 60 dB, even for the weakest signals. In some applications the weakest signals that must be detected can be 30 dB smaller than its neighbours. This means that the filter must be able to cope with input signals with a dynamic range (DR) of 90 dB. The filter must have a controllable gain which can vary with at least 30 dB.

The filter must have a high mirror signal suppression. The matching of the components in the filter is therefore very important. Especially for those components which determine the amplification in the passband.

Poles Lowpass 1 rad/s [rad/s] Lowpass 110 kHz [kHz] Bandpass 110 kHz [kHz]

P] -0.309 +j 0.951 -33.9 +j105 -33.9 -j 145

P2 -0.309 -j 0.951 -33.9-il05 -33.9 -j 355

P3 -0.809 +i 0.588 -89.0 +i 64.7 -89.0 -j 185

P4 -0.809 -j 0.588 -89.0 -j 64.7 -89.0 -j 385

P5 -1 -110 -110 -j 250

Table 1 : Pole positions before and after frequency translation

162

Table 1 gives the normalized poles of a 5 th order lowpass Butterworth filter, it gives also the poles for a bandwidth of 110 kHz and it gives the values of the uncompensated complex poles for a translated version on a centerfrequency of 250 kHz. The filter is designed for a system with a channel spacing of 200 kHz. The five uncompensated complex poles are realized by cascading the structure of fig. 7.

Fig. 9 gives the active-RC realization of fig. 7. Table 2 gives the values of the resistors for a standard capacitance of 20 pF. There are several reasons why the filter is realized with the active-RC implementation technique. First of all there is the required matching of the resistors. The filter is realized in a standard CMOS process. The matching of high ohmic polyresistors is much better than the matching of the MOS transistors in gm-C and MOSFET-C fllter. A good matching in these fllters requires the use of large V GS-VT's and with a single 5 V power supply the mismatch can not be made small enough. Here, the mismatch between the high ohmic polyresistor is less than 0.2 %.

\f

.'l

lin+ R/A ~ lout .., " L.J • -> ...,

Iin- R/A lout .., ...... L.J

~ ...,

R

\f " R/lQ

R/lQ

lllO

RI20

It .'1.

Q .l!!+ R/A ~ Q~ t+ ~ •

2 ~

in- R/A Qou -.., ..... Q t-

~ ...,

R

.1f

Fig. 9 : The active-RC realization of a section of the pol phase filter

163

Poles R[O] RIlQ[n)

Pl 232k 22.4k

P2 232k 54.8k

P3 89.4k 25.3k

P4 89.4k 42.9k

P5 72.4k 31.8k

Table 2 : Resistor values for 20 pF capacitors

A second reason for choosing the active-RC technique is the required dynamic range. After the first stage of the filter the neighbour signals, which can be a lot higher than the wanted signal, have only been partially filtered out. These signals can still be very high. Therefore, the distortion of this first stage must be very small. In this case lower than -80 dB. This can not be realized with switched-capacitor [13], gm-C [14] or MOSFET­C [15]. It is only with the active-RC implementation technique, proposed in [16], that these low distortion values can be realized. Active-RC is not suited for high frequency application, but it is ideally suited to realize the required low frequency low-Q filter.

The center frequency of the filter is digitally tuneable by means of switchable capacitor banks, as described in [16]. The gain of the first three stages is controllable by means of extra switchable resistors which can be put in parallel with the resistor at the input of the filter stages. The overall gain of the filter can vary from 4 to 256 in steps of 4.

5. Results

Fig. 10 gives the filter transfertfunction for positive and negative frequencies. The passband amplitude ripple is less than 0.1 dB. The mirror suppression is given in fig. 11. It gives the negative to positive frequency crosstalk. It is analysed with the Monte-Carlo simulation method assuming a 0.2 % mismatch on the resistors and a 0.1 % mismatch between the capacitors. Fig. 11 shows that the mirror suppression 60 dB is. The main contributor is the mismatch between the input resistors of the first filter stage.

164

40

20

a. E ·20 «

·40

·60

·1000 ·500 o 500 1000 Freq [kHz]

Fig. 10: Theftlrer transjertfunctionfor positive and negativejrequencies

40

20

i o

~ < ·20

·40

·60....-_--.. __ .................. ---. __ ....-__

o 200 400 800 800 Freq [kHz)

Fig. 11: Signal crosstalkfrom negative to positivejrequencies compared to the passband amplification

A microphotograph of the low-IF filter is given in fig. 12. The chip is realized in a 1.2 J.Un standard CMOS process. The total chip area is 7.5 mm2. Half the area is occupied by the switchable capacitorbanks. The noise requirements make that the capacitors have to be large. The extra switchable capacitors enlarge the total capacitor area with about 50 %. The chip runs on a single power supply voltage of 5 V. The total power consumption is 90 m W.

165

Fig. 12: Microphotograph o/the low-IF jilter, an active integrated polyphasejilter

6. Conclusions

In this paper the realization of an analog integrated active polyphase filter has been presented. The filter is designed for use in the LF part of a high quality and highly integrated receiver. This receiver is the low-IF receiver, an alternative for the zero-IF receiver topology.

With an active polyphase filter a translated lowpass filter can be realized. The lowpass filter characteristic is shifted to a positive IF frequency. The classic quadrature downconverter of a zero-IF receiver brings the wanted transmitter signal from its RF carrier frequency to this IF. The mirror signal, the problem in IF receivers, is downconverted to the negative IF frequency. The polyphase filter amplifies the signal on the positive frequency and it suppresses the negative frequencies. In the low-IF receiver the mirror signal on the IF can be suppressed at LF after downconversion by means of a polyphase filter. This enables the use of a broadband HF filter and a low IF. The consequence is that these receivers can have the same high degree of integration as zero-IF receiver. Intrinsic problems of the zero-IF receiver, related to the baseband operation, can be avoided.

The designed active polyphase filter is implemented with the tuneabre active-RC implementation. It is a 5th order lowpass Butterworth filter translated to an IF of 250 kHz. The filter is designed for a telecommunication system with a 200 kHz channel spacing. The filter can handle an input signal with a SNR of more than 90 dB. The overall amplification can be varied between 12 and 48 dB. The chiparea is 7.5 mm2, the power consumption is 90 mW.

166

7. References

[1] "Direct -conversion PM design," Electronics World, pp.962-967, Nov. 90.

[2] D. Sallaerts, D. Rabaey, A. Vanwetsenaers and M. Rahier, "A 270 kbit/s 35mW

Modulator IC for GSM Cellular Radio Hand-held Terminals," Proc. ISSCC, pp.34-35,

Feb. 90.

[3] D. Rabaey and 1. Sevenhans, "The challenges for analog circuit design in Mobile

radio VLSI chips," Proceedings AACD (Leuven), pp.225-236, March 93.

[4] P. Baltus, A. Tombeur, "DECT Zero-IF Receiver Front End," Proceedings AACD

(Leuven) , pp.295-318, March 93.

[5] K. Sam Shanmugan, Digital and Analog Communication Systems, pp.277-297,

New York: J. Wiley & Sons, 1979

[6] Yun-Ti Wang and A.A. Abidi, "CMOS Active Filter Design at Very High

Frequencies," IEEEJ. o/Solid-State Circuits, pp.1562-1574, Dec. 90.

[7] G. Groenewold, "The Design of High Dynamic Range Continuous-Time Integratable

Bandpass Filters," IEEE Trans. on Circuits and Systems, pp.838-852, Aug. 91.

[8] 1. O. Voorman, "Continuous-Time Analog Integrated Filters," in Integrated

Continuous-Time Filters, pp.27-29, New York: IEEE press, 1993.

[9] G.L. Haviland and AA Tuszynski, "A CORDIC Arithmetic Processor Chip,"

IEEE J. 0/ Solid-State Circuits, pp.4-14, Feb. 80.

[10] N. Boutin, "Complex Signals," RF-design, pp.27-33, Dec. 89.

[11] RA Brown, R.I. Dewey and C.I. Collier, "An Investigation of the Limitations in a

Direct Conversion Radio on PM-Reception," Int. Conf on LAnd Mobile Radio,

pp.157-164, Dec. 85.

[12] 1.0. Voorman, "Asymmetric polyphase filter," US Patent 4,914,408,1990.

[13] K. Halonen, W. Sansen and M. Steyaert, "A Micropower Fourth-Order Elliptical

Switched-Capacitor Low-pass Filter", IEEE J. 0/ Solid-State Circuits, pp.I64-173,

April 87.

[14] J. Silva-Martinez, M. Steyaert and W. Sansen, "Design Techniques for

High-Performance Full-CMOS OTA-RC Continuous-Time Filters",

IEEE J. o/Solid-State Circuits, pp.993-1001, July 92.

[15] 1. Van Der Plas, "MOSFET-C Filter with Low Excess Noise and Accurate

Automatic Tuning," IEEE J. 0/ Solid-State Circuits, pp.922-929, July 91.

[16] A.M. Durham, J.B. Hughes and W. Redman-\l.'hite, "Circuit Architectures for High

Linearity Monolithic Continuous-Time Filtering," IEEE Trans. on Circuits and

Systems, pp.651-657, Sept. 92.

TRANSCONDUCfOR - C FILTERS

John M. Khoury

AT&T Bell Laboratories 600 Mountain Ave. (2D-315)

Murray Hill, NJ 07974 USA

ABSTRACT

A discussion of the theory and practice of fully-integrated continuous-time transconductor-capacitor filters is given. A brief review of various transconductor designs in CMOS and BiCMOS is used to illustrate what performance can be achieved and where limitations exist .. Filter limitations will be examined in the context of the challenges presented by bigh-Q filtering needs. Future directions are suggested.

1. Introduction

Transconductor-capacitor continuous-time filters have recently found wide application in fully integrated circuits for video and disk drive applications [1-6]. These filters offer higher frequency operation than can be obtained with switched-capacitor networks and achieve these results with modest power dissipation. This paper reviews Gm-C filter operation, describes the performance limitations with respect to high-Q filters and discusses possible future directions.

2. Overview of Gm-C Filters

The basic concept of transconductor-capacitor filters, also called Gm-C or sometimes OTA-C filters, is illustrated in Figure 1, with a balanced integrator structure. The transconductance amplifier produces a differential output current that is linearly proportional to the differential input voltage, Vind. The amplifier's output current, lout, is integrated by the capacitor, C, to yield the following transfer function,

167

RJ. VQII de Plassche 1ft al. (etIs.J, Analog Circuit [)e.ign. 167-186. C 1995 Kluwer AcoMmic l'rIbIUher.. . .

168

H(s) = GmlsC = IDols (1)

The ideal integrator has infinite gain at DC, unity gain at the frequency COo

and a phase shift of -ft12 radians for all frequencies. In practice, each of these characteristics present difficult design challenges.

V1ND + 0-------1 - OM +

0-------1+

lOur

lOur

c

AGUREl:TRANSCONDUCTOR~INTEGRATOR

your

+

To implement state-variable filters only signal summation is required in addition to the integrator function. Signal summation is particularly straightfOlward with transconductance amplifiers, the outputs are just placed in parallel as shown in the bandpass state-variable biquad of Figure 2. The transconductor that is connected in a negative feedback configuration on itself is damping the biquad and is equivalent to a resistor of value Q IGm• In the design of transconductance amplifiers, signal summation is readily performed wherever the signal is in the form of a current, and often the summation can be performed before the output stage of the amplifier. Two or more signals can then share one output stage to save power, reduce area and provide a higher output impedance. Gm-G filters are typically implemented as a cascade of biquads or synthesized from LC passive prototypes based on signal flow graph techniques [7].

c

VIND + I>----~

+ OM -1----. +

c VOUT

FIGURE 2: TRANSCONDUcroR-C STATE-VARIABLE BIQUAD

3. Transconductor Design Approaches

169

The primary attributes of a good transconductor design are (i) high input and output impedances, (ii) large signal handling capability at the input and output terminals with low distortion, (iii) high DC gain (iv) wide bandwidth and (v) well defined and tunable voltage-to-current conversion mechanism.

Of the many approaches that exist for the design of the transconductor cell in CMOS, BiCMOS or bipolar technologies, they must each solve two separate issues: (i) voltage-to-current (V ->1) conversion and (ii) achieving high output impedance. A combination of active and passive devices is used to implement the V->I conversion, current source loads achieve high output impedance and common-mode feedback balances the outputs as shown in Figure 3.

170

1-----+--- + VOIIT

OM +- (V->I CONVERSION)

VIND

FIGURE 3: TRANSCONDUCTOR BLOCK. DIAGRAM

A direct V ->1 conversion, uses an MOS differential pair as in Figure 4(a) [8]. Here Gm = ...J2IJJ,CoxW1L and can be tuned by adjusting the tail current, 21. The corresponding bipolar implementation in (b) has Gm = 2qJ I kT. The primary drawback in each is that the total linear differential input signal range is small. The bipolar differential pair is about 50 m V at room temperature and the MOS differential pair is 2(V GS - V T)'

The input ranges can be expanded and linearized with many different techniques. Only a few will be mentioned here; the reader is referred to [9] for a more complete description.

171

~I I ~ ~I I ~ .:t

.-i-~MI M2 Ql Q2

+ VIND VIND

21 21

(A) (B)

FIGURE 4: BASIC V ->1 CONVERTERS IN MOS (A) AND BIPOLAR (B)

To expand the linear input range, additional transistors can be augmented to the basic differential pair as in Figure 5(a) [10]. For N large, approximately N~, a linear response with Gm = ...JJlCox(WIL)1 is obtained, typically with an input range on the order of 1 V. The bipolar countetpart in (b) obtains Gm = 0.641ql(kT) [11]. In both Figures 4 and 5, the Gm value is tuned with the tail current. The bipolar based transconductors have far wider tuning range than their MOS countetparts because Gm increases linearly with I rather than as {f. Such tunability is important for applications requiring programmability. These linearization schemes cancel the even-order nonlinear tenns in the overall Gm provided that the transistors are matched and the input signal is well balanced.

172

5 5 ~ !:i e e e + , + , ... ... ... ...

voo

XI X4 X4 XI XI XN N XI

+ + VIND VIND

(B)

FIGURE 5: LINEARIZED V->I CIRCUITS IN MOS (A) AND BIPOLAR (B)

Linearization schemes based on source degeneration are shown in Figure 6. Part (a) degenerates the source coupled pair with an MOS transistor biased in the triode region with zero drain-to-source voltage [12]. The drain current of an MOS transistor biased in the triode region with zero drain-to-source voltage is [13],

00

1= (WIL)J.1Cox [(VGS-VT)(VD -VS) + l:at(Vh - V~)] (2) i=2

If a differential signal is applied across the drain and source, then all even­order terms in (2) cancel. For many applications the odd-order tenns are low enough in value that the transistor behaves as a linear transconductor whose value, Gm = (WIL)J.1Cox(VGS-VT), can be adjusted with the gate voltage, Vc. Ideally, the transconductances of Ml and M2 should be much larger than Gm• Nonlinearity cancellation does not depend on device matching, but it does greatly depend on the electrical symmetry of the differential input signal. A

173

beneficial feature of this transconductor is that the value of Gm does not require modification of the bias currents.

vc

b 9 , ...

(A) (B)

b 9 , ...

FIGURE 6: MOS V ->1 STAGES WITH ONE (A) AND TWO (B) GM SETTING COMPONENTS

A variation of this scheme, shown in Figure 6(b), uses a second transconductance setting transistor, M5, and associated differential pair to cancel all the odd-order nonlinear tenns based on the principle in [14]. Figure 6(b) has the advantageous feature that the transconductance produced is proportional to (V C J - V C 2) so that substrate effects that modulate the threshold voltage of M3 and M5 appear as common-mode signals and are rejected.

In the schemes of Figure 6(a) and (b), the source followers need to be low impedance buffers so that all the signal voltage is dropped across the resistive elments, M3 or M5. One option is to use negative feedback around each of these source followers to lower their output impedance [15]; however, at high frequencies this adds parasitic poles. An alternative is to replace all four source followers with emitter followers for reduced buffer impedance and higher linearity.

Figure 7 depicts two MOS trans conductors that achieve high linearity by operating the MOS transistor in the triode/saturation regions, (a), and the triode region, (b). The operation of the transconductor in Figure 7(a) [2] will

174

be described initially with the simplifying assumption of triode operation for M3 and M4 and constant Vas for Ml and M2. M3 and M4 provide source degeneration and are the primary transconductance setting devices, similar to M3 in Figure 6(a). Using (2) and assuming balanced input signals and matched devices, one can see that linear operation occurs when the channel currents of M3 and M4 are summed. The resulting transconductance is proportional to the (WIL) of M3 and M4 and to the Vas - VT bias level of Ml and M2. The overall transconductance can be tuned by varying the two current sources that bias Ml and M2.

For large differential signals, the circuit operation changes in two ways. First, for large positive signal swings M4 is driven into saturation while M3 remains in triode and for large negative inputs M3 is saturated while M4 is in triode mode. Second, since Ml and M2 are not ideal source followers their gate-to­source voltages change with signal level and hence modulates the channel conductance of M3 and M4. Fortunately, with careful analysis and device scaling [2]. the overall nonlinearities of Ml, M2, M3 and M4 can be made self-compensating to yield a highly linear transconductor.

5 e + ..

5 9 , ..

+-1 VIND

FIGURE 7: CURRENT TUNABLE MOS V->I CONVERTERS

5 9 , ..

The V->I converter in Figure 7(b) [6,16], uses triode operated devices Ml and M2 with constant drain-to-source voltages to set the transconductance level.

175

From (2), we see that for constant V DS, all the nonlinear tenns vanish. Cascode transistors Ql and Q2 provide a low impedance on the drains of Ml and M2 to provide a constant V DS. The V DS bias point equals the voltage drop across RD, and is tuned with the ID current source.

vc

MI M2

VIND .--1-..,._-"1 L-_~I

M4 MS 1111

FIGURE 8: AN MOS TRANSCONDUcroR

A complete MOS transconductor design using a folded-cascode output stage is shown in Figure 8. To raise the impedance of the cascode output, amplifiers Al through A4 can be added as described in [17]. Realization of high output impedance can also be achieved with positive feedback [18]. The common­mode feedback circuit is not shown in detail; however, in general it must provide accurate output balancing to achieve good linearity in the transconductor stage that loads it. Common-mode feedback circuitry as described in [19] for balanced opamps is often necessary, depending on the V->I converter design. In [6] the triode based common-mode feedback is adequate because the V->I mechanism used (see Figure 7(b) ) is insensitive to input common-mode errors. IT signal swing is not a limiting factor, an unfolded cascode or telescopic design as presented in [6] can be used. Use of an unfolded cascode transconductor tends to minimize the input-referred differential offset and noise enhancement as described later.

176

4. Master-Slave Tuning

Transconductor-C filters require a tuning circuit to maintain an accurate frequency response because the GmlC ratios vary with processing and temperature. Typical variations are on the order of ±50%. Although the untuned absolute accuracy of the GmlC ratio is poor, the tracking of the ratios on-chip from one integrator to the next can be quite good. Therefore, with an accurate external reference and good on-chip matching of components continuous-time filters can be frequency tuned with the master-slave technique [1-4,8,20,21], depicted in Figure 9.

MASTBR REFERENCB

SIGNAL '-----7 B= -1f-

+ - V -1f-

INPUT

SIGNAL ~ 7

6

~ ~ ~ 8

01

SLA VB (MAIN FILTIlR) -1f-

VV B-1f-~.= • - ~.=-1f--ff- ~

G -1f- -1f--

FIGURE 9: MASTER-SLA VB TUNING

OUTPUT

SIGNAL

Although many tuning techniques are used, the most prevalent type will be discussed here. Frequency tuning uses a master circuit, such as a voltage controlled oscillator (VCO) or a voltage controlled filter (VCF) , that is constructed from the same type of transconductors and capacitors as the main filter, the slave. In the case of a master VCO, the VCO is locked to an an external reference digital clock with a phase lock loop, creating accurate GmlC values in the master and also in the slave because the two circuits use the same frequency tuning signal. Filter Q control loops are also possible and in the case of a master VCO, the Q control signal can be generated from the servo loop that controls the amplitude of the oscillations.

5. Gm-C Limitations and Challenges

Gm-C filters have found wide industry acceptance for applications requiring high frequency operation, low power, low to moderate Q (e.g. <10) and

177

moderate dynamic range (e.g. 60 dB). Many challenging problems remain to be overcome to improve the performance of these filters. Of the many different possible performance objectives none is more difficult or all encompassing than the goal of implementing high-Q bandpass filters. As will be shown, virtually al1 the present performance limitations in Gm-C filters are exposed by the high-Q goal. The high-Q requirement also aggravates the weaknesses inherent in other active filter techniques.

6. Frequency Response Accuracy

Obtaining accurate frequency responses with the design of high-Q filters, particularly bandpass, places severe challenges on the phase response of the transconductor-C integrators as well as magnitude response matching among integrators.

6.1 Integrator Matching

The bandwidth, BW, of a bandpass filter with center frequency, Ie is defined as,

BW =lelQ (3)

For many radio intermediate frequency applications the filter Q is about 65, so the bandwidth is only 1.5 % (i.e. lIQ) of the center frequency. Clearly, the filter's center frequency accuracy must be much better than 1.5 % to extract the desired passband.

If the Master-Slave tuning scheme [1-4,8,20,21] shown in Figure 9 is used, then two separate requirements are needed. First, to obtain the proper frequency response shape, the integrators within the slave filter much match to much better than lIQ. Second, to obtain the correct center frequency the master and slave must match to much better than lIQ.

A review of the present literature on lowpass filters employing master-slave tuning indicates the comer frequency accuracy that can be obtained over process, temperature and power supply extremes is about ±4% in the most careful designs [3]. In the case of a 10.7 MHz bandpass filter, ±1 % variation in the center frequency has been reported [21].

The many sources of integrator mismatch are now described. First, capacitors mismatch due to random effects as well as routing parasitic capacitances. Second, the transconductances mismatch because of inherent device mismatches, in those devices that set the Gm of the amplifier. Both capacitor and Gm matching is over the entire filter (and tuning circuit as well) making

178

layout designs to optimize matching difficult. Ideally all elements need to be co-located, but this is often difficult with high frequency designs that must minimize routing capacitances. Gm of the amplifiers can also mismatch due to biasing issues. Consider the Gm cell in Figure 6(a). Input common-mode offset appears directly as an error in the tuning voltage, V c for this amplifier. Depending on the tuning voltage range, an offset of even 50mV could cause significant errors. Since the tuning voltage is single-ended, ground differentials can also be problematical. Gm amplifiers tuned with currents similarly depend on current mirror matching.

Use of a differential tuning signal can negate both ground differential effects as well as common-mode offset. An example of such a Gm cell is shown in Figure 6(b). Capacitance mismatch due to parasitics can be alleviated by buffering the integrator output prior to routing to the next cell or by placing the load capacitor in a OTA feedback loop as in [5,15,20]. However, even with these improvements, the matching will not meet the necessary objective for very high-Q applications.

6.2 Gain Compression

The unity-gain frequency of integrators can also mismatch due to transconductor nonlinearities. Although nonlinearities give rise to harmonic distortion, the odd-order nonlinearities also modulate the fundamental component of the signal, giving rise to a signal dependent integrator gain. Such gain compression is extremely important because close matching of integrator unity-gain frequencies is required for high-Q applications. If the third harmonic distortion at the output of the integrator is D 3, relative to the fundamental, then the integrator's unity-gain frequency is in error by [23],

~coo - =9D3 (4)

COo

For a Gm--C integrator with 60 dB third hannonic distortion, the relative shift in the unity-gain frequency is 0.9%. For high-Q filters, such a signal dependent shift is unacceptable.

6.3 Integrator Phase Errors

Consider the ideal Gm-C biquad depicted in Figure 2. The loopgain around the main two integrator loop determines the pole locations with the phase shift being the mechanism that determines the filter Q. The loopgain's phase response is easily derived,

179

«I»(CO) = 1t/2 - arctan(mQ I coo) ::: COo'(mQ) (5)

The approximation is made for high-Q applications. Consider two examples: (i) a low-Q biquad, as found in the Bessel or equiripple filters of disk drive applications and (ii) a high-Q biquad desired for radio receiver applications. For (i), the biquad Q is less than 2, resulting in a loopgain phase shift of at least 26.6° at frequency coo. Clearly, the sum of the two integrator's phase errors must be much less than 26.6°, and assuming identical integrators, about 1 ° of phase error at COo in each is tolerable in practice. In contrast, (ii) may require a Q of 65, resulting in a loopgain phase at 0.88° at COo and individual phase errors of much less than 0.04°.

To gain practical insight into what is achievable with state-of-the art design techniques consider a non-ideal Gm-C integrator. First, the transconductor itself has a frequency dependent response due to the parasitic poles or zeroes. The transconductor also has a finite output impedance that can be modeled with the parallel combination of a resistor, rOUh and a capacitor, Couto Finally, the input capacitance of the next stage and associated routing can be modeled with a capacitor, Cin' Cin and Cout appear in parallel with the desired load capacitance C and will shift the nominal value of 000 unless the value of C is reduced to compensate. However, matching among integrators in the filter is often compromised when this is done. Cout usually consists of several components including junction capacitance that will degrade the integrator's linearity at higher frequencies. The nonideal transfer function of the integrator in Figure 1 is,

Gmo(1 + slco:) rout Ha(s) = (1 + slro,) 1 + srout(C+cout+cin)

(6)

where Gmo is the transconductance at DC, 00: is a parasitic zero in the amplifier and cop is the parasitic pole. The integrator's phase error for co < co:, cop is,

«I»/-error ::: 1t/2 + (col co:) - (COIro,) - arctan [Ao (col OOox)) (7)

where Ao=Gmorout is the DC gain of the amplifier, coox is the nominal unity­gain frequency of the integrator with parasitic capacitances included.

Consider an example of a 20 MHz Gm-C Bessel filter for a disk-drive read channel application that utilize transconductors as in Figure 8, without the amplifiers A 1 through A4. Most integrators will have unity-gain frequencies in the vicinity of 20 MHz. A typical low power design might use C = IpF resulting in Gmo = 12S.7J1S. With an output resistance, rout, of approximately

180

IMO, the resulting DC gain of the trans conductor is Ao = 126. If the amplifier's parasitic pole is at 300 MHz and the zero is at infini~ frequency, the phase error at 20 MHz is -3.40 • A modest amount of phase lead is readily achieved by intentionally moving the zero to lower frequencies to bring the phase error to 10 or less. Phase lead can be added in any G m-C integrator by placing a small resistor in series with the integrating capacitor. As an alternative, the zero can be placed in the transconductor of Figure 8 by placing a capacitor across M3 .

Relying on phase compensation techniques at design time requires accurate modeling of parasitics. To work around modeling uncertainty, phase control loops have been employed [3,21]; however, they are still a master-slave tuning technique that depends on matching as in Figure 9. In fact, the matching of parasitics and routing must be well controlled, which is difficult. In high-Q applications, master-slave phase tuning approaches must be done with extreme care to avoid filter instability.

7. Direct Tuning

For high-Q filters, tuning the frequency and Q (i.e. integrator phase) with a master slave tuning approach is not practical given the achievable levels of matching. Direct-tuning [22] has been proposed but it is complex to design and requires two filters to be used; one is being tuned while the other processes the signal. An example of how direct tuning might be performed on a 6th order bandpass leapfrog filter is shown in Figure 10. Part (a) shows the filter in normal operation, while (b) shows the direct tuning arrangement [23]. A bandpass leapfrog filter that has been realized with the lowpass-to-bandpass transformation has the property that each biquad resonates at the center frequency of the filter. One can then remove the coupling between the hiquads during tuning as shown in (b), forming a cascade of biquads. Since the center biquad has infinite Q, during tuning damping must be provided to prevent oscillations. The center frequency of each biquad can be tuned by applying a sinusoidal signal at the nominal center frequency of the bandpass filter and frequency tuning each biquad individually so that the input and output signals are in phase. Similarly, the Q of each biquad can be adjusted by measuring and adjusting the individual biquad gains at the tuned centet frequency. At the conclusion of tuning, the six tuning signals (3 for frequency, 3 for Q) are held, and the filter is available to process the signal.

The ideal approach is to tune the filter while it is in use. Rather than considering the filter as a single-input single-output network we could conceive of a dual-input dual-output network in which one set of I/O is used

181

for the signal to be processed and the other path is used for the tuning signal. In theory, the network zeroes could be chosen so that the tuning signal does not appear at the filter output and then the tuning loop could accurately place the filter poles [24]. In general, the reference signal would need to be kept at a low level to avoid reducing the available swing for the desired signal.

(A)

(8)

INPUJ'

+ BPBlQUAD BPBlQUAD

+ + '-'-----'----0 0I1I1'I1I'

2

FIGURE 10: DIRECl'TUNING OF ALEAPFROO FILTER (A) NORMAL MODE (B) TUNING MODE

8. Dynamic Range

Obtaining high-Q high dynamic range Gm-G filters is extremely difficult because of fundamental noise limitations, as well as signal swing issues. Although a thorough noise analysis of a Gm-G integrator requires the complete circuit details, the theoretical lower bound is simply the noise equivalent of a resistor of value lIGm, AV2 lnd I AI = 4kT IGm .

Many references have discussed the relationship of dynamic range to Q [8,18,25,26] so here the single bandpass biquad of Figure 2 is described. Assuming identical integrators the total output noise power can be computed for the core resonator as,

V20Uld = [4kTIGmH OloQ/2] (8)

182

For a maximum peak-to-peak differential signal swing of twice the power supply, the resulting upper bound on the dynamic range is:

DR = 10l0glO[V2 supplyC 1(4kTQ)]dB (9)

Attempting to implement a single biquad with Q=65, a power supply of 3.0 V and an integrating capacitor of 10 pF results in a best case dynamic range of 79 dB, far short of that needed for most radio IF filters. Use of large integrating capacitors reduces noise, however the Gm must be made proportionally larger resulting in higher power dissipation. Driving low impedances that implement Gm as in Figure 6, then becomes difficult.

Maximizing linear signal swing is also critical to realizing high dynamic range. Several factors limit the signal swing to levels significantly lower than the power supply. First, for the transconductor to achieve high output impedance, cascoded current sources as in Figure 8 are used. To maintain all the cascode transistors in saturation, the signal swing in practice can only come within several hundred millivolts of each power rail. Second, since in most of the transconductors the device setting the transconductance is nonlinear, linearization techniques that depend on device matching or balancing of signals must be used. However, imperfect balancing and matching causes nonlinearity that necessitates reduced signal swing. The Gm setting device is usually a transistor because tunability is needed to eliminate processing and temperature variations and is desired for programmability. In most Gm designs, the available signal swing is also a function of the tuning signal. A circuit approach that decouples tuning from signal swing can allow fundamentally linear elements (i.e. resistors ) to set the Gm while other elements provide tuning capability with minimum distortion.

Finally, signal swings and circuit balance are degraded with the relatively high differential offsets found in Gm amplifiers. Consider the folded-cascode transconductor of Figure 8. If M 3 is shorted we just have a one stage CMOS opamp. The input-referred offset is just that of the input differential pair and the offsets of transistors M6, M7, M12 and M13 reflected to the input. However, once we convert the amplifier to a GM cell, the offsets due to these transistors are not attenuated as much and the tail current transistors M4 and M5 now contribute to the offset. In a CMOS technology with typical opamp offsets in the 10m V range, it is not uncommon for the transconductor amplifiers to have input offsets of 20-40 m V. Depending upon the filter structure, these offsets can add and seriously reduce the available signal swing and balance.

183

In a similar way, the input-referred noise of the trans conductor is enhanced over the theoretical limit due to the low transconductance in the input differential pair. Noise from transistors M4, MS, M6, M7, M12 and M13 can enhance the input-referred noise significantly. If unfolded structures are used, as in [6], the noise and offset from M6 and M7 are eliminated and can have significant benefits. In general, the problems of differential offset and noise enhancement are much less significant in opamp based filters, such as the MOSFET -C filter technique.

1llN1NO

2C

CURRENT VOUIII

STEBRING +

VIMD

2C

FIGURE 11: GM-OTA-C INTEGRATOR

9. A GM-OTA-C Integrator

To solve many of the signal swing, output impedance and loading drawbacks of Gm--c integrators, others have successfully used the Gm-DTA-C approach [S,15,20], depicted in Figure 11. Such an integrator does not require cascoding to achieve high DC gain and is therefore well suited to low voltage operation. Since the second stage is an OT A, buffering is automatically provided and the integrator is minimally affected by parasitic capacitances. To minimize sources of nonlinearity, the transconductance setting element is a linear resistor. Continuous tuning can then be accomplished with a current steering mechanism as shown in Figure 11 and described [1S,27]. The circuit also decouples the problem of signal swing from tuning and should pennit maximum signal swing for all process and temperatures to maximize dynamic

184

range. Tuning the resistors or capacitors with discrete steps can also be perfonned as in [28] if the resolution is acceptable; however, maximum tuning resolution is needed for high-Q filters.

10. Conclusions

Although transconductor-C filters have found widespread use and acceptance in moderate dynamic range applications such as disk drives and video filters, high-Q filters present severe challenges in tuning and achievable dynamic range. The realization of viable direct tuning methods is required to obtain accurate frequency response characteristics. The fundamental issue of noise in high-Q filters may be the ultimate limitation; however, more work in the area of minimum noise filter networks and circuits is needed. If the tuning and noise issues are successfully addressed, only then can the high-Q high dynamic range filters as needed in wireless communications be considered as feasible with integrated continuous-time filters.

REFERENCES

[1] K. W. Moulding, J. R. Quartly, P. J. Rankin, R. S. Thompson, and G. A. Wilson, "Gyrator video filter IC with automatic tuning," IEEE Journal of Solid State Circuits, vol. SC-15, no. 6 pp. 963-968, December 1980.

[2] F. Krummenacher and N. Joebl, "A 4 MHz CMOS Continuous-time Filter with On-chip Automatic Tuning," IEEE Journal of Solid-State Circuits, vol. 23, no. 3, pp. 750-758, June 1988.

[3] V. Gopinathan, Y. Tsividis, K-S Tan, R. Hester, "Design Considerations for High-Frequency Continuous-Time Filters and Implementation of an Antialiasing Filter for Digital Video," IEEE Journal of Solid State Circuits, Vol. SC-25, no. 6, pp. 1368-1378, Dec. 1990.

[4] J. Khoury, "Design of a 15 MHz Continuous-time Filter with On-Chip Tuning", IEEE Journal of Solid-State Circuits, Vol. 26, No. 12, Dec. 1991, pp. 1988-1997.

[5] C. Laber and P. Gray, "A 20MHz 6th Order BiCMOS Parasitic Insensitive Continuous-time Filter and Second Order Equalizer Optimized for Disk-Drive Read Channels," IEEE Journal of Solid State Circuits, Vol. 28, pp. 462-470, April 1993.

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[6] R. Alini, A. Baschirotto, and R. Castello, "Tunable BiCMOS Continuous-Time Filter for High-Frequency Applications," IEEE Journal of Solid State Circuits, Vol. 27, No. 12, pp. 1905-1915, Dec. 1992.

[7] A. Sedra, and P. Brackett, "Filter Theory and Design: Active and Passive," Matrix Publishers, Inc., Beaverton, Oregon, 1978.

[8] H. Khorramabadi and P. R. Gray, "High-frequency CMOS continuous­time filters," IEEE Journal of Solid-State Circuits, Vol.- SC-19, No.6, pp.939-948, Dec. 1984.

[9] Y. Tsividis and J. Voorman, "Integrated Continuous-Time Filters: Principles, Design and Applications,", IEEE Press, New Yorlc., 1993.

[10] A. Nedungadi and T. R. Viswanathan, "Design of Linear CMOS Transconductance Elements," IEEE Transactions on Circuits and Systems, vol. CAS31, pp. 891-894, Oct. 1984.

[11] D. Calder, "Audio Frequency Gyrator Filters for an Integrated Paging Receiver," lEE Conference, Mobile Radio Systems and Techniques, No. 238, 1984.

[12] Y. Tsividis, Z. Czamul and S.C. Fang, "MOS transconductors and integrators with high linearity," Electronics Letters, vol. 22, pp. 245-246, Feb. 27, 1986.

[13] M. Banu and Y. Tsividis, "Detailed analysis of nonidealities in MOS fully integrated active RC filter based on balanced networks," Proceedings of the Institute of Elect. Eng., Vol. 131, Pt. G, No.5, pp. 190-196, Oct. 1984.

[14] Z. Czamul, "Modification of the Banu-Tsividis Continuous-Time Integrator Structure," IEEE Transactions on Circuits and Systems, Vol. CAS-33, No.7, pp.714-716, July 1986.

[15] S. Willingham, K. Martin, and A. Ganesan, "A BiCMOS Low Distortion 8-MHz Low-Pass Filter," IEEE Journal of Solid State Circuits, Vol. 28, No. 12, pp.1234-1245, Dec. 1993.

[16] J. Pennock, "CMOS Triode Transconductor For Continuous-Time Active Integrated Filters," lEE Electronics Letters, Vol. 21, No. 18, pp. 817-818, Aug. 29, 1985.

[17] K. Bult and G. Geelen, "A Fast-Settling CMOS Op Amp with 90 dB DC-gain and 116 MHz Unity-Gain Frequency," International Solid

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State Circuits Conference, pp. 108-109, 1990.

[18] Y. Tsividis, "Integrated Continuous-time Filter Design," IEEE 1993 Custom Integrated Circuits Conference, pp. 6.4.1- 6.4.7.

[19] M. Banu, J. Khoury and Y. Tsividis, "Fully Differential Operational Amplifiers with Accurate Output Balancing," IEEE Journal of Solid­State Circuits, Vol. 23, No.6, Dec. 1988, pp. 1410-1414.

[20] K. S. Tan and P. R. Gray, "Fully integrated analog filters using bipolar FET technology," IEEE, J. Solid-State Circuits, vol. SC-13, no. 6,pp. 814-821, December 1978.

[21] J. Silva-Martinez, M. Steyaert, and W. Sansen, "A 1O.7-MHz 68-dB SNR CMOS Continuous-Time Filter with On-Chip Automatic Tuning," IEEE Journal of Solid State Circuits, Vol. 27, No. 12, pp. 1843-1853, Dec. 1992.

[22] Y. Tsividis, "Self-tuned filters," Electronics Letters, vol. 17, no. 12, pp. 406-407, June 1981.

[23] 1. Khoury, "Realization of Lumped and Distributed Integrated Continuous-Time Filters," Doctoral Dissertation, Columbia University, 1988.

[24] V. Gopinathan, "High Frequency Transconductance-Capacitance Continuous-Time Filters,", Doctoral Dissertation, Columbia University, pp. 162-163, 1990.

[25] B-S Song, and P. R. Gray, "Switched-Capacitor High-Q Bandpass Filters for IF Applications", IEEE Journal of Solid State Circuits, Vol. SC-21, No.6, pp. 924-933, Dec. 1986.

[26] G. Groenewald, "The Design of High Dynamic Range Continuous-time Integrable Filters," IEEE Transactions on Circuits and Systems, vol. 38, pp. 838-852, Aug. 1991.

[27] U-K Moon, and B-S Song, "Design of a Low-Distortion 22-kHz Fifth­Order Bessel Filter," IEEE Journal of Solid State Circuits, Vol. 28, No. 12, pp.1254-1264, Dec. 1993.

[28] A. Durham, J. Hughes, and W. Redman-White, "Circuit Architectures for High Linearity Monolithic Continuous-Time Filtering," IEEE Transactions on Circuits and Systems, pp. 651-657, Sept. 1992.

RECENT ADVANCES IN SWITCHED-CURRENT FILTERS

John B Hughes, Kenneth W Moulding

Philips Research Laboratories, Redhill, Surrey, England

ABSTRACT Two recent advances in the switched-current tilter technique are re­ported. The first is an improved memory cell which brings enhanced perfonnance while avoiding many of the trade-offs of earlier attempts. The second is an improved integrator structure which has both bet­ter perfonnance and lower power dissipation. The techniques are demonstrated in an 8MHz, 80Msample/s 3rd order lowpass elliptic ladder filter implemented in a standard CMOS process. IC mea­surements confinn perfonnance which competes with the best of switched-capacitor filters.

1. INTRODUCTION Switched-Current (81) filters were introduced in 1989 [1] when digital circuits were beginning to dominate signal processing. The complexity available at the time was enabling complete systems to be integrated on a single chip leaving only the interface functions of data conversion and signal conditioning for analogue implementation. With digital circuits occupying the lion's share of the chip area, it made economic sense to use an analogue technique which needed no more than the bare 'digital' CMOS process and this was 81's principle claim. It seemed also, with the merging of the storage capacitor and buffer into the same device (the MOS transistor), that 81 circuits would be very compact. Further, since the op amp could be avoided, they should have better high frequency perfonnance than switched-capacitor circuits. The technique seemed set to succeed switched­capacitors, especially in mixed-signal integrated circuits.

The fact that, five years on, 81 has not yet become an industrial standard is in part due to the advances made by switched-capacitors but mainly due to 81's own

187

R J. WJ1I de Pla8sche ~t al. (~ds.), Analog Circuit Design, 187-202. C 1995 Kluwcr Academic Publisher •.

188

Vr~f ~--fI

)

L

Figure 1: Basic S I memory cell

circuit frailties. While basic circuits could perform all the required filter functions, they could not do so with competitive precision, linearity and noise. The same circuit simplicity which promised so much was exposing the MOS transistor's own limitations.

This paper describes two recent advances which should renew much of 81's early promise. The first brings enhanced performance to the memory cell in a way that avoids many of the trade-offs of earlier attempts [2,3,4]. The second is an improved integrator structure which has both better performance and lower power dissipation. Finally, the new techniques are demonstrated in an 8MHz elliptic ladder filter exhibiting highly competitive perfonnance.

2. NON·IDEAL BEHAVIOUR Perhaps the most primitive of all the S I cells is the basic memory or current copier [5,6] (fig. I). It is used to compose integrators, differentiators, delay lines etc and the analogue perfonnance of the 81 system arises directly from the errors of its constituent memory cells [7] .

• Settling Errors: On the input phase, cPh the input current, i, charges the nMOS transistor's gate capacitance causing its gate voltage and hence its drain cunent to rise. In practice, the closed ioop formed by the nMOS transistor and its closed switch behaves as a second-order system and usually this is designed to be critically damped. The monotonic rise leaves an error at the end of phase 4>1 which is held throughout the output phase tho In the S I integrator, this introduces magnitude and phase errors much as op amp finite bandwidth does in the switched-capacitor integrator [8].

189

• Drain Conductance Errors: On the holding phase. <h. when the cell delivers output current to its load. the drain voltage may change from that occuring on the input phase and this causes an error in the current flowing at the drain due to channel-length modulation and feedback to the memory capacitance via the gate-drain overlap capacitance. In the 81 integrator. this introduces a low frequency pole much as op amp finite gain does in the switched-capacitor integrator [8] .

• Charge Injection Errors: At the end of the input phase. 4>1. the memory switch is opened and during this process charge is fed through the switch transistor's gate-channel and drain-gate overlap capacitances into the memory capacitor C. The resultant disturbance of the gate voltage causes an error in the memory transistor's drain current. Its effect in the memory cell and 81 integrator are similar to that of drain conductance errors.

Cells designed for high bandwidth have shorter channel length with the result that both channel length modulation and capacitive feedback effects are larger. The higher transconductance value necessitates a higher value of switch on­conductance to ensure monotonic settling and this results in higher charge in­jection. Consequently, transmission errors resulting from both drain conductance and charge-injection effects increase with the memory cell bandwidth. Under large signal conditions, these errors all produce hannonic distortion.

Various circuit enhancements have been used to improve analogue perfonnance [3,9, 10, 11]. Drain conductance errors have been reduced by a variety of negative feedback techniques to stabilise the drain voltage of the memory transistor. They have made orders of magnitude improvements but there is an inevitable penalty of increased silicon area and power dissipation. Further, where voltage headroom is used by extra transistors, low supply voltage operation may be precluded. The more complex feedback loops can produce higher order systems and this reduces available bandwidth.

Various schemes have been proposed for reducing charge injection errors. The most common is the use of dummy switches whose gates are driven by inverted clock signals in an attempt to inject an equal and opposite charge into the memory capacitor. Unfortunately, complete cancellation is not usually possible and in practice the reduction may be modest. Fully differential circuits have lower charge injection and may be used with dummy switches to give a further reduction. However, despite these enhancements, charge injection remains perhaps the most troublesome error in S 1 cells, especially in cells with high bandwidth.

190

Figure 2: Sl I memory cell circuit diagram. clock wavelonns and symbol

3. COMPOSITE MEMORY CELL Whereas conventional circuit techniques are applied piecemeal to suppress indi­vidual errors produced by non-ideal behaviour, the approach adopted here is to provide total error reduction through the circuit operation (fig. 2). To achieve this, the process of memorising the sampled-and-held input cummt, i, is made in two steps: a coarse step in which the input sample is memorised approximately in an nMOS memory followed by a fine step during which the error of the coarse step is derived and memorised in a pMOS memory. The output is then delivered from both memory cells so that the coarse error is subtracted to leave an accurate memory of the input sample.

The composite memory cell which perfonns this two-step procedure [12], is called 821. The input phase cPl is divided into phases cPla and cPl6 during which the coarse and then the fine memorising occurs. During phase cPla, the pMOS is connected to ¥ref and generates bias current 1. The current in the diode-connected nMOS is J + i. At the end of phase cPla, the coarse memory switch is opened and the nMOS transistor holds a current J +i+4i where 4i is the signal dependant error current resulting from all the usual errors associated with the basic S I memory cell. During phase cPu, the pMOS is configured as a diode and, with the signal current i still flowing at the cell's input, it's drain current settles towards current J + 4i. At the end of phase cP16, as 4i <: J. the voltage at the nMOS and pMOS

191

transistor drains is close to the value with no signal present i.e. the circuit develops a voltage at both memory transistor's drains which is akin to a 'virtual earth'.

During phase 4>2, the gate of the pMOS is opened and an extra error 6i occurs in the fine memory mainly due to charge injection. If the output is fed to a second cell of similar type, the second cell establishes a similar 'virtual earth' voltage at its input during phase 4>2b. The drains of the first cell's memories are therefore held at nearly the same voltage at the end of both input and output phases; a condition established by negative feedback in conventional cells and which gives much reduced conductance ratio error. Further, because the current in the fine memory transistor and the voltage on its switch are similarly constant during these phases, the charge injection error of the fine memory is much reduced.

Clearly, the signal, i, is transmitted through the cell with an error 6i resulting from the intermediate error Ai rather than the full signal (as happens in the basic cell). So, the signal transmission error of the composite memory cell, C S2 I, is

(I)

where CN and ep are the combined errors of the separate memory cells and eSI is the combined error of the basic S 1 memory cell.

Even though the clock phases, 4>1 and 4>2, are sub-divided into 'a' and 'b' phases this does not double the required transistor bandwidths as the settling error on the 'a' phase is transmitted to the pMOS where settling may continue on the 'b' phase. This is shown in fig. 3 by the Scalp2 simulations of a non-inverting integrator made from s2 1 memory cells which are ideal in all respects except for finite bandwidth (gm/ C) of its nMOS and pMOS memory transistors. Also shown are simulations of the same integrator with infinite bandwidth (Ideal) and an equivalent integrator made from basic SI memory cells having transistors with the same bandwidth (SI). The clock frequency is IMHz and C / gm = IJ.ts. The bandwidth (159kHz) was chosen to be much smaller than would be used in practice to accentuate the effect. It is seen that finite bandwidth reduces the gain of the S2 I integrator little more than that of the S 1 integrator.

Fig. 4 shows Scalp2 simulations of the same integrator made from S2 I memory cells but now they are ideal in all respects except for gd8 errors. Also shown are the same integrator with zero gds (Ideal) and an equivalent integrator made from basic SI memory cells having transistors with the same gds (SI). The clock frequency is IMHzandgm /gds = 400givingcSI = 1%. The S21 integrator's low frequency gain is 40dB higher than that of the basic S 1 integrator, in accordance with equation (1).

In the basic S 1 memory cell both flicker and white noise are generated by the memory and bias transistors. During operation, low frequency flicker noise is

192

80

o

-20

-40~---~---~---~---~---~ 10 100 1K 10K 100K 1M

Frequency (HZ)

Figure 3: Scalp2 simulation of non-inverting integrators with finite bandwidth

80 IH(jw)1 (dB) 60

40 I------..:::~ 20

o -20~---~--~---~---~---~

10 100 1K 10K 100K 1M Frequency (Hz)

Figure 4: Scalp2 simulation of integrators with 9d. errors.

193

virtually eliminated by the cell's double correlated sampling action but the white noise, being under-sampled, is folded into the passband many times over and determines the noise performance of the S I system. In the SZ I memory cell similar sampling mechanisms prevail. At the end of the coarse input phase, <PIa, noise is sampled by the nMOS transistor as in the basic S I memory but then it is passed on as an error signal to the pMOS memory transistor during the fine input phase, <Pu. During the output phase, 4>2, this noise error is suppressed along with the other errors in the normal manner. However, at the end of phase <P1b the same noise sources are still active and a new sample will be stored in the pMOS memory. Consequently, the two-step operation of the S2 I memory cell incurs no noise penalty.

4. BILINEAR Z-TRANSFORM INTEGRATOR/SUMMER First-order filter building blocks which perform the bilinear z-transfonn have well knO\\lll advantages. Unlike Euler integrators, they have no excess phase and so map to the z-plane with guaranteed stability, giving the resulting filter a distortion-free amplitude response, even in filters with clock frequencies approaching the Nyquist frequency ..

Several SI bilinear z-transform integrators have been proposed [4, 13, 14]. They all employ single-ended circuits and require current mirrors to produce signal inversion. Unfortunately, these mirrors introduce excess phase errors and, to keep these small, the clock frequency must be made large compared with the filter cut-off frequency, thereby nullifying one of the major advantages of bilinear mapping. In common with standard SI Euler integrators [15], these bilinear integrators operate with only one sample per clock period.

An integrator made from balanced pairs of S2 I memory cells [16] is shown in fig. 5. It comprises a pair of single-ended integrators, one of which integrates the input current i 1 positively while the other integrates it negatively. The input change-over switch produces sampling on the falling edges of phases <PI and 4>2 i.e. twice during each clock period. The mirrored outputs are combined such that they produce an integrator output i A which also changes twice during each clock period. This frequency doubling at both input and output allows the integrator to operate with half the clock frequency of conventional integrators and its memory cells may be designed with half the nonnal bandwidth and hence half the power consumption. Further, the integrator has a 6dB higher signal-to-noise ratio than conventional integrators because halving the clock frequency halves the frequency with which it samples its own noise while the double-sampling maintains that of its input signal. There is a similar benefit to the low frequency gain and pole frequency. The maximum sampling frequency is also doubled.

194

a. 1 1 a.

Figure 5: Balanced ffl I integrator and waveforms

.+ IS i -S

Figure 6: Balanced $2 I summer

195

A balanced circuit configuration is desirable for several other reasons: it reduces cross-talk in mixed signal environments and simplifies filter architecture because signal inversion can be effected by simply crossing over signal pairs. It also enables the construction of integrators which perfonn bilinear z-transfonnation giving no excess phase error and allowing 'exact' filter design. The transfer function is given by,

(2)

where iA = i~ = -iA• When the input signal is purely common-mode, i.e. i~ = i A, the change-over switch is ineffectual and the signals are not integrated but instead simply mirrored to the outputs with attenuation detennined by the coefficient a. This gives the integrator common-mode rejection and so obviates the need for common-mode feedback circuits.

The integrator summer arrangement is shown in fig. 6. The balanced input signal is is applied directly to the integrator loops and the mirrored outputs of each single-ended integrator are connected to produce the summer output iB. The transfer function is given by,

h . .+ .-w ere, B = a B = -z B'

iB(Z) HB{z) = ~( ) = -{1

IS Z (3)

196

The combined integrator/summer and its symbol are shown in fig. 7. It is simply the superimposed circuits of figs. 5 and 6. The arrangement is the dual of the integrator/summer commonly used in switched-capacitor ladder filters [17] but with the advantage of bilinear mapping and double-sampling. The path between the I input and the A output provides integration while that between the S input and the B output provides gain and is used to produce the zero's of an elliptic filter. Fig. S shows the simulated response of the two signal paths for an ideal integrator/summer with Q = f3 = 1 and for a clock frequency of 40MHz (i.e. the sample frequency is SOMHz).

S. AN 8M HZ ELLIPTIC LADDER FILTER We now consider the design of a third order lowpass elliptic filter which simulates the state equations of a doubly terminated LCR ladder. It is designed with a sampling frequency of SOMHz and a -3dB cut-off frequency of SMHz with a 0.5dB equiripple response. The architecture is shown in fig. 9.

The above filter, complete with V-to-I interface, sample-and-hold, and clock generator, was integrated in a O.S pm standard CMOS process [1S]. Fig. 10 shows the measured amplitude response for various sampling frequencies, IB' with a normalised (f / IB) axis. Filter performance is summarised in Table 1.

6. CONCLUSIONS Two recent advances in the switched-current filter technique have been described. The first brought performance improvement to the memory cell through the use of a composite memory structure which retains the high bandwidth and circuit simplicity of the basic cell. The second produced an enhanced integrator which exhibited superior performance at lower power dissipation through the use of double-sampling. The techniques were demonstrated in an 8MHz, 80Msample/s 3rd order lowpass elliptic ladder filter. The excellent performance at such a high frequency indicates that switched-current filters can now compete with the very best of switched-capacitor filters and gain commercial advantage through simpler processing and small chip area, especially in mixed signal systems.

ACKNOWLEDGMENTS

This research was supported by the Switched-Current Analogue Design System (SCADS) partners, namely Philips Semiconductors (Southampton), Southampton University, Cadence (Bracknell) and the Department of Trade and Industry

197

Figure 7: Balanced gz I integrator/summer and symbol

198

60.-------------------------~

0.01 0.1 1.0 10 100 Frequency (MHz)

Figure 8: Scalp2 simulation of the amplitude response of the integratorlsununer

~ Bias I ~clockl""'·-

Figure 9: Third order 8MHz lowpass ladder filter architecture

199

Process 0.81lm standard CMOS Area 0.3mm2

Supply Voltage 5V Dissipation

Filter 70mW Clock 35mW

Cut-off Freq (-3dB) 7.76MHz (8MHz) Passband Gain (lookHz) 5.6dB (6dB) Stopband Attenuation 25dB (26dB) Notch Attenuation 37dB Harmonic Distortion (50% mod., fsig=lMHz)

2nd -61dB 3rd -48dB

Signal-to-Noise Ratio (50% mod.) 67dB (6OdB)

CMRR 39dB (4OdB) PSRR 43dB Output Swing 1.2mA DC Output Offsets 221lA

Table 1: Typical measured perfonnance of the 8MHz elliptic lowpass filter block with 80MHz sampling (design values in parenthesis)

200

""'" i " ~

~ ~ '" t ~ ~ ~~~: 1 ~ - r-. L::-e0MHz f' N 'dowH'} ~OOMHz t:: "OMHz r--SOMHz f • . 40MHZ

, fifo r--o 0.1 0.2 0.3 0.4

Figure 10: Measured amplitude response of integrated filter.

References

[l] J B Hughes, N C Bird, I C Macbeth" Switched Currents - A New Tech­nique for Analogue Sampled-Data Signal Processing" IEEE International Symposium on Circuits and Systems, 1989, pp.1584-1587.

[2] T S Fiez, D J Allstot, "CMOS Switched-Current Ladder Filters". IEEE Inl. Solid-State Circuits, vol.SC-25, Dec 1990,pp.1360-1367.

[3] J B Hughes, K W Moulding "Switched-Current Signal Processing for Video Frequencies and Beyond" IEEE Inl of Solid-Sate Circuits, Vol 28, No.3, March, 1993,pp314-322.

[4] N C Battersby, C Toumazou, "A 5th Order Bilinear Elliptic Switched-Current Filter" Proc.IEEE Custom Integrated Circuits Conference, May,1993, 6.3.1-4.

[5] S J Daubert, D Vallancourt, Y Tsividis " Current Copier Cells" Electronics Letters, vol.24, no.25,pp.1560-1562, Dec. 8, 1988.

[6] J B Hughes, I C Macbeth. D M Pattullo, "Switched-Current System Cells" IEEE International Conference on Circuits and Systems, 1990, pp303-306.

201

[7] J B Hughes, W Redman-White, "Switched-Current Limitations and Non­Ideal Behaviour" Switched-Currents: an analogue technique/or digital tech­nology, Peter Perigrinus Ltd, ISBN 086341 294 7, Chapter 4.

[8] K Martin, A S Sedra, "Effects of op amp finite gain and bandwidth on the performance of switched-capacitor filters" ,IEEE Trans. Circuits and Systems, CAS-28, Aug. 28, 1981, pp822-829.

[9] J B Hughes, K W Moulding, D M Pattullo, Switched-Currents: an analogue technique/or digital technology, Peter Perigrinus Ltd, ISBN 0863412947, Chapter 6.

[10] D Vallancourt, Y P Tsividis and S J Daubert, "Sampled-Current Circuits", 1989 IEEE International Symposium on Circuits and Systems,ppI592-1595.

[11] D Groeneveld, H Schouwenaars, H Termeer, C Bastiaansen " Self-calibrated technique for high resolution D-A converters" IEEE Journal 0/ Solid-State Circuits, December 1989,ppI517-1522.

[12] J B Hughes, K W Moulding, "521: A Switched-Current Technique for High Performance" Electronics Letters, Vol.29, No.16, 5th Aug. 1993, pp.1400-1.

[13] J B Hughes, N C Bird, I C Macbeth, "Switched-Current Architectures and Al­gorithms" Switched-Currents: an analogue technique/or digital technology, Peter Perigrinus Ltd, ISBN 086341 294 7, Chapter 3.

[14] I Song, G W Roberts, "A 5th Order Bilinear Switched-Current Chebyshev Filter", Proceedings 0/ IEEE International Symposium on Circuits and Sys­tems,1993,pp.1097-1100.

[15] J B Hughes, I C Macbeth, D M Pattullo, "New Switched-Current Integrator" Electronics Letters, 24 May, 1990, Vol 26, No 11, pp.694-695.

[16] J B Hughes, K W Moulding, "A Switched-Current Double-Sampling Bilinear Z-Transform Filter Technique" Proceedings 0/ IEEE International Sympo­sium on Circuits and Systems, 1994.

[17] G M Jacobs, D J Allstot, R W Broderson, P R Gray, "Design Techniques for MOS Switched-Capacitor Ladder Filters" IEEE Transactions on Circuits and Systems, Vol. CAS-25, No.l2, Dec 1978, ppl014-1021.

[18] J B Hughes, K W Moulding, "An 8MHz, 80Msample/s Switched-Current Filter", IEEE International Solid-State Circuits Conference, Feb,1994, pp60-61.

SWlTCBED CAPACITOR FILTERS

Robert C. J. Taylor.

Austria Milcro Systeme International AG, Schlo8 Premstlitten,

A-8141 Unterpremstlitten, Austria.

ABSTRACT

The design problems encountered when implementing switched capacitor filters onto silicon are examined.

This includes the practical limitations of capacitor size and matching, amplifier speed and the problems associated

with switch charge injection and resistance. Methods of overcoming these problems will be examined so that

highly accurate, switched capacitor filters, can be reliably designed.

1. INTRODUCTION

Switched Capacitor Filters (SCFs) are very accurate, sampled data filters; an analogue signal is acted upon using sampled data techniques (Le., switched capacitors). As they consist of amplifiers, switches (transmission gates) and capacitors, they can be easily and effectively implemented within silicon circuits. They are also much smaller and more accurate than their active-RC or Transconductor-C counterparts, therefore making them very attractive for integration within ASICs (Application Specific Integrated Circuits) and standard product devices.

Their frequency range is governed by the speed of the amplifiers which is governed by the speed of the process used. On a CMOS process, comer frequencies of 100s of KHz can be achieved (using clock rates up

203

RJ. VQII de P/am:hell' aL (lids.). AMlog Circuit Design, 203-225. C 1995 Kluwer AcodI!mic Publishers.

204

to approximately lOMHz}. If higher speed is required, then a faster process needs to be used, such as Gallium Arsenide (GaAs).

This paper will concentrate on the design problems encountered when designing SCFs for a CMOS process. Particular attention will be paid to the design of the components of an SCF (capacitors, switches and amplifiers) and to their layout. The calculation of the capacitor values will not be dealt with as the design engineer often does not need to worry about this area because it is automatically performed by software.

2. SWITCHED CAPACITOR FILTER DESIGN

As mentioned in the introduction, the capacitor values for most frequency responses can be obtained automatically using software synthesis tools. Most software tools use biquads (a 2nd order block with a biquadratic transfer function) as their building blocks[I.2]. This is because biquads can perform all the standard frequency responses, low pass, band pass, notch, all pass and high pass, easily. Any other response can be obtained by varying the pole-zero locations of the biquads. Usually, the designer enters the filter's transfer function, a filter template, or the filter's pole-zero locations and the programme calculates the capacitor values, and determines the switch phasing, to meet the required response. Cascading the biquads gives higher orders of filtration.

Some programmes base their architecture on ladder filters[3]. These are less sensitive to non-idealities than biquad filters[4J, but are more limited in their range of frequency responses. Often ladder filters are used if high orders of filtering are required with high Q (quality) factors.

Once the capacitor values have been calculated and simulated[s.6] to check their frequency response (most synthesis programmes include a simulator), the filter has to be implemented onto silicon and the realisability of the calculated capacitor values inve.stigated.

205

3. CAPACITOR DESIGN

3.1 Capacitor Spread

The main limiting factor in the type of frequency response that can be achieved is the capacitor spread (Le., the difference between the smallest, unit, capacitor and the largest one). If the spread is too large there are problems for the amplifiers to charge up the capacitors in a clock pulse, the matching between a large and small capacitor is less accurate, and the filter will physically use up more area on the silicon.

The capacitor spread increases as the clock frequency to corner frequency ratio increases and it also varies depending on the type of response being implemented; the higher the Q, the higher the capacitor spread tends to be. However, lowering the ratio causes increased problems with frequency warpingl and also means that more accurate anti-aliasing and smoothing is required, which can be difficult (see section 7). Therefore, often a compromise between the capacitor spread and the clock frequency to comer frequency ratio has to be made.

There are methods to reduce capacitor spreads, but these often have 'bad' side effects. For example, capacitor 'T -networks' can be used which reduce the ratios by a factor of 10, but the middle node of a 'T-network' is sensitive to capacitor parasitics and therefore causes inaccuracies in the filter response (see figure 1).

Scaling loops within a filter can be scaled differently to reduce the overall capacitor spread. For example, a unit capacitor of 05 units within one loop could be used which would halve the capacitance of all the other capacitors in that loop. However, doing this results in a very small 'new unit' capacitor and increases the problems of laying it out accurately

1 Frequency warping is caused when calculating from the s-plane to the z-plane. Often, a filter's transfer function will be given in the s-domain (s-plane) and therefore a conversion using the bi-linear z-transform has to be made to generate a transfer function in the z-domain so that the capacitor values can be calculated (as an SCF is a sampled data circuit, its transfer function is expressed in the z-domain). As the Fclk:Fo (clock frequency to comer frequency) ratio decreases, the warping distortion becomes more apparent and causes a deviation in the required comer frequency. This is a mathematical problem and therefore can be compensated for when calculating the capacitor values.

206

Ca Cb

-H--+ Cs

~T~ J:Ct

CaCb Cs = ------------

Ca+Cb+Ct

If Ca=Cb= 1 and Ct=8, then Cs=O.l.

100 10

1 0.1

-1 -1 1 ~ 1

-1Tf--~8

Figure 1: The use of 'T-networks' to reduce capacitor spread

and effects the matching accuracy. How small a unit capacitor can be made, depends on the process.

3.2 Capacitor Matching - Rounding Errors

The reason why SCFs can achieve so very accurate corner frequencies «0.5% error or better) is due to the capacitor matching, the absolute values are not important, but the matching between capacitors is. On silicon, precise absolute values can not be achieved, but very exact ratios between capacitors can, especially if certain design practices are used.

To improve the matching accuracy, capacitor values should be designed, before layout, to one or two decimal places of accuracy and not

207

to four or five places (as most synthesis programmes produce). This high number of decimal places cannot be achieved accurately on layout and therefore rounding errors occur which cause mismatching. It is better to remove this potential problem before going to layout.

The capacitor values should be scaled to one or two decimal places (or what can be accurately achieved by the layout tool) and re-simulated to check the accuracy of the frequency response. To keep the ratios accurate the capacitors can be scaled up, or increased in size. This has the disadvantage of increasing the capacitor size, but it has the advantage that the measured result will match the simulated result more closely.

The following example shows the benefits of scaling the capacitors before layout[7]:

Consider the following four capacitors within a scaling loop:

0- Switch.

)

C3

CI = 3.01674 units Cl = 1.022979 units C2 = 1.0 unit C3 = 4.444093 units

The ratio C2:Cl is very undesirable. If Cl was rounded to 1.02 units there would be a 0.29% error between the new ratio (1: 1.02) and the desired ideal ratio (1: 1.022979). This error is greater than a typical capacitor matching error. (If CI were 1.0555 units, the error would be even greater, i.e. 0.5%). If each capacitor within this scaling loop is

208

scaled (multiplied) by 1.4 and then rounded to two decimal places, the following values are obtained:

CI = 4.22 units Cl = 1.43 units C2 = 1.40 units C3 = 6.22 units

The C2:Cl ratio is now 1:1.0214 (1.43/1.4), this gives an error, compared with the ideal ratio, of 0.15%, this is 50% better than the previous error.

To obtain ideal ratios with two decimal places of capacitor layout accuracy, the capacitors would have to be greatly increased in size. However, with a little increase in size, substantially better ratio accuracy can been achieved. It is interesting to note, that this is an important factor when designing accurate comer frequencies, especially if a high Q filter is being implemented.

3.3 Capacitor Matching· Layout Using Unit Capacitors

Capacitors should consist of a number of unit capacitors added together to give the required value. Unit capacitors have equal area to perimeter ratios which removes the effects of fringe parasitic capacitances. A large capacitor made up of a number of unit capacitors will also be immune to fringe parasitic capacitance effects and thus a very accurate ratio can be achieved. Capacitors within a scaling loop should also be physically laid out close together to improve their matching.

For example, figure 2 shows the possible layout of two matched capacitors. From figure 2, let:

The dimensions of one unit capacitor The area is Capacitance per unit area Fringe parasitic capacitance

per unit length

Therefore, the total capacitance is

=d. d [J.1m . J.1m] =d2 [J.1m2]

=c/d2 [pF/J.1m2]

= fld [pF/J.1m]

= d2 X c/d2 + 4d x fld = (c + 40 pF per unit

am - Metal ti'lC - Pol Y 1 c:::::J - Poly 2

c A B

Figure 2: Layout of two matched capacitors

The ratio of the 1 unit capacitor to the 5 unit capacitors is:

c +4d 1 ------------- = ----5(c + 4d) 5

209

that is, the required ratio. The fringe parasitic capacitance has no effect. If the capacitors were laid out as two capacitors with a 1 :5 area ratio:

2

5d

then the fringe parasitic capacitance has an effect. The total capacitance of the I unit would be, as before,

d2 X c/d2 + 4d x f/d = c + 4f,

210

but the large capacitor would be,

Calculating the ratio gives: c +4f 1 c +4f ---------------- = -- x --------------5c + 4(5 112)f 5 c + 4(5- 112)f

There is an error in the ratio due to the fringe parasitic capacitance, because the area to perimeter ratio is not constant. If f=O (no fringe capacitance) then the ratio is correct.

If it is wished to realise a non-integer capacitor ratio (which is almost always the case), the constant area to perimeter ratio must be adhered to for fringe capacitance cancellation. There are two methods; one using stubs (which tends to use up area) and one which uses computer optimisation to keep the area to perimeter ratio constant (this tends to be more efficient on layout area and can be easily laid out automatically).

With the stub technique, a stub is added which is half the width of one side of a unit capacitor and whose length determines the fraction of the unit capacitor to be added. The following example shows such a structure:

d

CA d

O.2d

Area CA = d2 + dl2 x O.2d = 1.1d2

Area CB = d2

Perimeter CB = 4d

Perimeter CA = 3d + dl2 + O.2d + dl2 +O.2d =4.4d

Using the capacitance definitions as before:

CA = 1.1d2 x c/d2 + 4.4d x f/d

=1.1c+4.4f = 1.1 (c+4f)

CB = d2 X c/d2 + 4d x f/d =c+4f

The ratio:

CA 1.1 (c + 4f) ---- = -------.. ------ = 1.1 CB c+4f

211

Therefore, a 1.1: 1 ratio has been achieved without any affects of parasitic fringe capacitance.

The other technique uses a programme to optimise the layout of a non-unit capacitor (Le., larger than 1 but smaller than 2) to keep the area to perimeter ratio constant. This is achieved by elongating the capacitor to increase the perimeter. However, doing this can produce very long capacitors which are inefficient in area. Therefore, to decrease the area and keep it within the equivalent area of two unit capacitors, a hole is added into the top plate to increase the perimeter and thus keep the area to perimeter ratio constant:

dl

CA

d3 Dd4

1.1

d2

d

CB d

to 1 ratio

The programme then optimises the capacitor's dimensions iteratively so that:

Perimeter CA = dl + d2 + d3 + d4 = 4.4d and Area CA = dl x d2 - d3 x d4 = 1.1d2

212

Then, as before, the parasitic fringe capacitance will be cancelled out.

Around the complete capacitor bank are placed dummy capacitors. This helps to keep the parasitic fringe capacitance constant because it is influenced by the adjacent capacitors, therefore by adding dummy capacitors, the fringe capacitance at the bank edge is the same as that within the bank. Also, it helps to keep the etching of the top plates of the unit capacitors constant. The etching of one unit capacitor top plate is effected by the adjacent unit capacitor top plate, therefore the distance between the unit capacitors should be kept constant so that the etching effect is constant. By placing dummy capacitors around the capacitor bank the etching of the capacitors along the bank edge is the same as that within the bank. Inconsistent etching causes non-constant unit capacitor sizes and thus effects the area and the capacitor ratio.

The automatic programme method of generating the capacitor banks has the advantages that (i) a non-unit capacitor occupies, at maximum, the equivalent area of two unit capacitors, (ii) it is regular in shape and thus efficient in layout area, (iii) dummy capacitors can be easily added automatically, and (iv) different bank shapes can be experimented with to find the most efficient in terms of area.

With the stub technique, a non-unit capacitor can occupy the equivalent area of three units (if a stub to realise 0.9 units is being used) and it is not regular in shape which means more layout effort is required to produce an area efficient capacitor bank. However, the stub method is much easier to calculate by hand.

Note that near the comers, the fringe parasitic capacitance is different to that along the edges. In these calculations it has been assumed that the fringe parasitic capacitance is constant. The error caused by this assumption is negligible.

3.4. Other Parasitic Effects

As already mentioned, the effects of fringe parasitic capacitances can be removed by using unit capacitors. The effects of capacitor parasitics from the top and bottom plates to the substrate (or ground) can be removed by the switching scheme used (see section 5.3), this also removes the interconnect metal track parasitics to the substrate. However,

213

what cannot be removed is the parasitic capacitance from the metal interconnect to the capacitor bottom plate (the metal interconnect connects the top plates together, as in figure 2), but it can be minimised by layout[71•

The metal interconnect to bottom plate parasitic capacitance is relatively small and only becomes a problem if the fIlter is highly selective (high Q) and of high order. To minimise the effect, the top capacitor plate metal interconnect should not cross the bottom capacitor plate and having the top plate between the metal interconnect and bottom plate is also advantageous, which is the case for processes where contacts to metal are permissible on the top plate when it is above the bottom plate, as in figure 2. On most processes, the bottom plate must be larger than the top plate which means there will always be an overlap. If the bottom plate is much larger (as is often the case in auto-routed capacitor banks where the bottom plate acts as a common node), if possible, the bottom plate should be cut away underneath the metal to remove the parasitic capacitance.

3.5 Noise Considerations

Noise or signals can often be injected onto the bottom plate of a capacitor via the substrate. Usually, the substrate is connected to Vss (depending on the process) and any signals on this node can be transferred onto a capacitor bottom plate because it is physically close to the substrate. One straight forward method of greatly reducing this effect, and thus increasing the power supply rejection, is to design the fIlters so that the bottom plate is driven by the output of an amplifier, thus removing any spurious effects because the driven signal is usually much greater and therefore swamps the undesired signal. If the bottom plate was connected to the virtual earth of an amplifier, any signal on the bottom plate would be amplified onto the signal path.

Building the complete filter as a fully differential circuit also helps to remove the noise effects of the capacitors, amplifiers and switches. The noise of one half is effectively negated from the noise of the other half thus reducing the noise at the output of the fIlter. However, it has the undesirable effect of doubling the area of the filter.

214

4. AMPLIFIER DESIGN

The amplifier is the main limiting factor in how high the corner frequency can be (the amplifier band width dictates how high the clock frequency for the filter can be and thus the highest corner frequency) and how large the capacitors can be (if area is not considered). The speed of an amplifier (its band width) is determined by the process used; for example, Gallium Arsenide and bipolar are faster than CMOS and thus higher SCF corner frequencies can be achieved.

4.1 Slew Rate

When designing how fast an amplifier must function, it is essential to make sure that the amplifier can charge up its associated capacitors to a steady state within one clock pulse, the slew rate. Therefore, the higher the clock frequency, the narrower the pulse and the faster the amplifier must slew.

The integrating capacitors (those connected from the amplifier output to input) tend to be the largest in a filter. However, these are never completely discharged (in standard SCFs) because they are continuously driven and the amplifier only has to 'top up' the charge on the capacitor. The important capacitors are those that are switched to ground, these need to be charged and discharged on successive phases, fortunately, they are usually small (a few pFs).

When the amplifier's slew rate is being designed, it should be simulated with the largest grounded capacitance and it should be checked that it can charge the capacitor with the largest expected voltage within half a clock period:

+- 1/(20-+

I ~v I._t: __ f - clock frequency V - voltage to be charged

onto capacitor -----Amplifier response (VIs)

215

In actual fact, the amplifier should be designed to charge the capacitor in approximately half a clock pulse (Le., 11(40), to allow for settling, under worst case conditions.

IfV=2.5V and f=100KHz, a slew rate of IYJ!s-t is required with the capacitive load. This slew rate also depends on the accuracy required. If it is enough for the amplifier to slew, for example, to 95% of its final value, then the slew rate can be relaxed, but this may effect the accuracy of the SCFs frequency response.

4.2. Single Stage and Two Stage Structures

The amplifier structures that are commonly used in SCFs are single stage (usually folded cascode to give higher gain) or standard two stage amplifiers.

A single stage amplifier is a voltage controlled current source with a large output impedance, hence, the filter must be buffered to drive the next stage of the overall system. The single stage amplifier provides a current which must be great enough to charge the largest switched capacitor at the required frequency, as the following example shows:

Assume the switching clock frequency is f, therefore the period is lIf and, as already mentioned, the capacitors need to be charged within half a clock pulse, 11(40. If the capacitance to be charged is C by a voltage V, the current that the amplifier must provide is:

I =C V/t = 4CVf

If C = 2pF, V = 2.5V and f = 100KHz, then I = 2JlA. If the clock frequency or capacitor value is increased, a higher bias current is required.

A two stage amplifier is a voltage controlled voltage source with a very low output impedance, hence no buffering is required between the SCF and the next stage of the system.

Single stage amplifiers tend to be smaller than two stage amplifiers,

216

• Contact

CEll Poly

am Metal

c::::::J Active

A

gl-lnf- g2

dl d2

~mm~mmmmH·~« a·'mm~~ZEdl

Em~~~pmmm~~~~~_gl

:~A <

~ ~ .~~','~."'-'.'.~'.'.'.'j.

em~~~~~EBEB~mag2

~, ~ '" .>v .'·0 " ~ ..... , •... " d2

Figure 3: Example of matched layout of input devices

therefore an SCF will often consist of single stage amplifiers within the filter and a two stage amplifier at the last integrating stage, so that an extra buffer is not required.

4.3. Offset Considerations

Input offset voltage mismatches are chiefly caused by the input devices' WIL ratio, the load transistors and the transistor thresholds. The systematic offset caused by device mismatching can be simulated, but the layout and process dependant offsets, such as thresholds, cannot.

To reduce the offset effects of layout, the input devices of the amplifier should be designed to be large (by increasing the width), so that there is more transistor area with which to interleave the transistors (see figure 3) and thus improve the matching. Using this method, they are less likely to be effected by process gradients, because the gradient will effect the two devices the same and thus they will track each other well. Having a large area also means that any uneven effects are more uniformly

217

distributed throughout the devices. The load devices should also be well matched to reduce their offset contribution.

S. SWITCH DESIGN

The switches within an SCF charge, discharge and transfer the charge of the capacitors. They are usually constructed as transmission gates (an n-type and p-type transistor connected in parallel). This helps to remove charge injection and also means that the transmission gate will be ON or OFF (depending on the gate voltage) no matter what the voltage on the drains and sources are.

5.1 Switch Charge Injection

Charge injection is the charge added onto the signal path as the transistor switches. This adds noise to the output signal (spikes) and also adds a DC offset which can be more significant than the offset introduced by the amplifiers.

Using a transmission gate with the gate area of the n- and p-type transistors the same, helps to reduce the charge injection. As the gate capacitance is the same, the possible injected charge is the same. When the n-type transistor turns ON it injects charge, while as the p-type turns ON it accepts charge, and visa-versa when they tum OFF. Therefore, in theory, the charge injected onto the signal path is removed, but in practice this is not the case, because as one transistor turns ON the other does not tum OFF at the same time, because one gate has the inverted signal of the other gate and thus there is the delay of the inverter between the two signals.

The amount of charge injected depends on the speed of the clock edge on the gate and the gate capacitance. Reducing the size of the transistors reduces the charge injected onto the signal path, because the gate capacitance is lower and the effect of fast edges is reduced. However, the switch ON resistance will increase. Therefore, in practice, a compromise has to be made to obtain the optimum transistor size for switch ON resistance and charge injection.

218

There are schemes to try and completely remove the injected charge. One such schemelS) adds dummy transistors half the size of the transmission gate transistors, which switch in anti-phase to the transmission gate transistors, to try and remove the charge. As the transistor turns ON, the dummy transistor turns OFF and thus accepts the charge (see figure 4). This is very difficult to accurately simulate (it is difficult to simulate the charge distribution and charge conservation accurately) and must be tried, to varying degrees of success.

e - High. o-Low.

Figure 4: Charge removal using dummy transistors

Other methods store the offset generated by the switches (and the amplifiers) and then negates the charge from the signal path thus removing the offsetl9.10). One problem is that the amplifier output is often shorted to ground (its virtual earth) and thus the integrating capacitor, which is usually large, is discharged. Therefore, the amplifier has to have a very high slew rate to recharge the integrating capacitor, meaning that it will consume more current and probably occupy a larger area.

In most systems where SCFs are used the DC offset is not too important (in voice data processing there is often AC coupling), but where it is, such charge cancelling techniques that have been mentioned can be experimented with.

S.2. Switch Resistance

If, in the transmission gate, two transistors of the same size are used, then the ON resistance of the n- and p-transistors will be different (because the mobility is different). The resistance will therefore vary depending on the voltage across the two transistors (the variation will be non-linear rather than an ideal linear variation in resistance). This is not usually a problem because the ON resistance can be quite large. Consider the following calculation:

219

The switch ON resistance and charging capacitor can be represented as follows:

C R - Switch ON resistance

lR The current I is required to charge up the capacitor C in a quarter of a clock period (as discussed previously), Le., 1/(40. The time constant of the two switches and capacitor is:

T = (R + R) C = 2RC

This time constant must be equal to or less than the time to charge up the capacitor, Le.:

Therefore, T <= 11(40

2RC <= 11(40

R <= lI(8CO

If C = 5pF and f = IMHz, R = 25Kohms (assuming the amplifier can provide the current to charge up the capacitor in the desired time). As the clock frequency increases or the capacitance increases, the switch ON resistance must decrease. Therefore, the switch resistance only becomes important if high clock frequencies are used. In practice, a switch resistance of approximately lOKohms is aimed for, this means that the transistors are not too large (to decrease the resistance, the widths must be increased, assuming minimum length is used) and the resistance should not effect the charging of the capacitor. Also, having smaller transistors reduces the charge injection.

5.3. Standard Parasitic Insensitive Switching Scheme

Most SCFs employ the switching scheme in figure 5[11) to remove capacitor plate parasitics. It can be seen that when swl and sw2 are

220

Figure 5: Standard parasitic capacitance cancelling

switching scheme

closed, C is charged up to V. The bottom plate parasitic capacitance cpb is also charged, but this has no effect as long as it does not transfer its charge onto the signal path. The top plate parasitic capacitance (plus metal interconnect to ground parasitic) cpt is discharged because both of its plates are connected to ground (the top plate via the closed switch sw2). When the sw3 and sw4 switches are closed (swl and sw2 are open), cpb is discharged via sw3, therefore it does not contribute to the integration. cpt is not charged because its plates are both connected to ground and the virtual earth of the amplifier, therefore it also makes no contribution to the integration. Only the charge on C is integrated.

Using this technique, all the parasitic capacitances to ground are removed and, as mentioned in section 2, only the metal track to poly parasitics have an effect.

6. TIME-SHARING OF AMPLIFIERS

Time-sharing of amplifiers means that one amplifier performs the function of two different amplifiers. This can be done if one integrator in an SCF performs its integration during one clock phase, while another does it during the other; these two amplifiers can be replaced by one112,13]

(see figure 6). In theory, for certain filter structures, all the amplifiers can be time-shared onto one amplifierI14], but in practice there are many problems, such as amplifier speed and switch noise.

~ ~ ~ ~

~T~~ ~

~~~~ t ~~e zqt B i ~T~~

Figure 6: Simplified example of time-sharing two amplifiers onto one

221

The main advantage of time-sharing is that it can reduce silicon area and power consumption. However, in practice, if an amplifier is time-shared between two or more integrators its output has to swing to different voltage levels which usually means increasing the slew rate thus increasing its current consumption and silicon area (increasing the things that the time-sharing is trying to reduce!). Also, the extra routing and switches (for the integrator capacitors) require area. Therefore, time-sharing is not widely used unless area and current is of paramount

222

importance and even then it is possible that there would not be a great saving.

7. ANTI-ALIASING AND SMOOTHING

When designing an SCF, the requirements for anti -aliasing and smoothing must always be considered (unless the complete system into which the SCF is to be placed is band limited).

Often the anti-aliasing and smoothing filter characteristics are exactly the same and are usually implemented by a Sallen-Key second order, continuous time, active-RC filter. This usually attenuates the unwanted components by a sufficient amount.

Anti-aliasing occurs if high frequency signals are present at the input of the SCF. These spurious signals are folded back to the passband and can effect the frequency response of the SCF. An anti-aliasing filter can greatly reduce this effect.

As an SCF is a sampled data system (as is also the case with digital filters), the spectrum of interest is repeated at the clock frequency and at multiples of it. This appears as a high frequency signal at the SCF output in the time domain. A smoothing filter attenuates these signals and thus removes it from the output.

Figure 7 shows the type of response required by an anti-aliasing and smoothing continuous time filter.

As both anti-aliasing and smoothing filters attenuate the signal at the clock frequency (and beyond), the greater the difference between the SCF's comer frequency and clock frequency, then the greater the amount of attenuation that can be achieved by the RC filters. However, increasing the fc1k:fo ratio increases the clock frequency (amplifier considerations) and increases the capacitor spread (area considerations), therefore there is always a compromise between the fclk:fo ratio and the amount of anti-aliasing and smoothing attenuation. It must also be remembered that the accuracy of an active-RC filter is very poor (corner frequency accuracy of +/- 50% or worse), so allowances must be made

Amplitude (dB)

Smoothing! AA response , , ,

SCF response Repeated SCF spectrum ,

223

.... --!-, ..... ------..... +-, _-!,_-+, ...... Frequency SCF fo RC fo fclk-fo fclk fclk+fo (Hz)

Figure 7: Typical SCF frequency spectrum

for this spread (due to the spread of the resistors' and capacitors' absolute values) when designing the filter.

8. CONCLUSIONS

This paper has looked at the problems associated with the implementation of switched capacitor filters onto silicon. Most frequency responses can be quite easily met, however there are always instances when the practical considerations of implementing an SCF means that an alternative method, or a modification of the desired frequency response, has to be made.

REFERENCES

[1] "AutoFilter," Mentor Graphics Corporation, 8005 S. W. Boeckman Road, Wilsonville, OR 97070, USA.

[2] P. E. Fleischer and K. R. Laker, "A family of Active Switched Capacitor Biquad Building Blocks," The Bell System Technical Journal, vol. 58, no. 10, pp, 2235 - 2269.

[3] R. K. Henderson, Li Ping and J.1. Sewell, "A design program for digital and analogue filters: P ANDDA," Proc. ECcrD (Brighton, UK), pp. 289 - 293, Sep. 1989.

224

[4] Li Ping, R. C. J. Taylor, R. K. Henderson and J. I. Sewell, "Design of a Switched-Capacitor Filter for a Mobile Telephone Receiver," IEEE J. Solid-State Circuits, vol. 27, no. 9, pp. 1294 - 1298, Sep. 1992.

[5] "SCAP (Switched Capacitor Analysis Program)," Mentor Graphics Corporation, 8005 S. W. Boeckman Road, Wilsonville, OR 97070, USA.

[6] S. C. Fang, Y. P. Tsividis and O. Wing, "SWITCAP: A Switched Capacitor Network Analysis Program - Part 1: Basic Features," IEEE Circuits and Systems Magazine, pp. 4 - 9, Sep. 1983 ("Part 2: Advanced Features," pp. 41 - 46, Dec. 1983).

[7] R. C. J. Taylor and H. Horvat, "A High Precision, Multi-Notch, Low Pass Switched Capacitor Filter," Proc. The Fourth Mid-European Conference on Custom! Application Specific Integrated Circuits, Budapest, pp. 53 - 60, May 1993.

[8] C. Eichenberger and W. Guggenbtihl, "Dummy Transistor Compensation of Analog MOS Switches," IEEE J. Solid-State Circuits, vol. 24, no. 4, pp. 1143 - 1145, Aug. 1989.

[9] R. Gregorian and G. C. Ternes, "Analog MOS Integrated Circuits for Signal Processing," Wiley-Interscience, ISBN: 0-471-09797-7.

[10] K. K. K. Lam and M. A. Copeland, "Noise-cancelling switched capacitor filtering technique," Electronic Letters, vol. 19, no. 20, p. 810, Sep. 1983.

[11] M. E. Van Valkenburg, "Analog Filter Design," HRW Series in electrical and computer engineering, ISBN: 0-03-059246-1.

[12] D. J. Allstot and K. S. Tan, "Simplified MOS switched capacitor ladder filter structures," IEEE J. Solid-State Circuits, vol. 16, no. 6, pp. 724 - 729, 1981.

[13] K. R. Laker, P. E. Fleischer and A. Ganesan, "Parasitic insensitive biphase switched capacitor filters realised with one operational amplifier per pole pair," BSTJ, vol. 61, no. 5, pp. 685 -707, 1982.

225

[14] M. Powell, J.1. Sewell and R. C. J. Taylor, "On Time-Sharing and Noise Minimisation in Switched-Capacitor Filters," Proc. Colloquium on 'Electronic Filters,' lEE Savoy Place, London, pp. 211 - 216, May 1985.

Current-Mode Continuous-Time Filters

David J. Allstot and Rajesh H. Zele

Department of Electrical and Computer Engineering Carnegie Mellon University

Pittsburgh, Pennsylvania United States of America

ABSTRACT

A low-voltage high-frequency CMOS fully-balanced filtering technique is presented. The low internal voltage characteristic of current-mode circuits allows the operation at power supply voltages as low as 3-V with high dynamic range. The integrator time-constant is determined by a MOSFET small-signal transconductance and an additional non-critical MOSFET gate capacitance. For ladder filters derived from doubly-terminated LC prototypes, HSPICE simulations predict a -3-dB bandwidth of 125 MHz for a three-pole lowpass filter. Power dissipation is 6 mW/pole with a 3-V power supply.

1. Introduction

Continuous-time filters operating at cutoff frequencies exceeding 10 MHz constitute a large potential market in applications such as video signal processing and magnetic disk-drive read-channel systems [1]-[6]. Several impressive advances have been reported using voltage-mode gm-C techniques including: a 15 MHz linear-phase Bessel filter (19 mW/pole, 0.9 Jim CMOS) [4], a VHF biquadratic bandpass ftlter (6 mW/pole, 0.9 J1II1 CMOS) [5], and a 98 MHz third order elliptic lowpass filter (225 mW/pole,

227

R.J. van de PItuSCM fit al. (f!ds.). Analog Circuit IHrign. 227-235. C 1995 Kluwflr Academic PublisMrs.

228

Vdd=lOV, 3 /lm CMOS) [6]. The important issues involved are the integrator Q factor, highest cutoff frequency possible, tunability, power per pole, filter area per pole, minimum supply voltage and distortion performance. Recently, current-mode approaches to continuous-time filters gave promising results in the frequency range of several tens of megahertz [7]-[9]. In this paper we describe current-mode continuous-time integrators which can be used to construct filters with cutoff frequencies beyond 100 MHz while operating from a single 3-V supply.

2. Motivation

For the first generation CMOS switched-current (SI) integrator [10], clock feedtbrough/charge injection from the switches is one of the limitations on the accuracy of the filters. Clearly, the ultimate solution to this problem would be the removal of all sampling switches. The resulting circuit shown in Fig. I(a) forms the basis of a continuous-time current-mode integrator. The dominant time constant is established by adding MOSFET gate capacitance (C2) to the input of the second stage as shown [7].

A small-signal model of the integrator is shown in Fig. l(b) in which the output conductances are neglected. Assuming identical transistors, and applying KCL at nodes A and B yields

. gm (. . ) If = sC

2 lp - In • (1)

The integrator gain constant is established using a MOSFET gate capacitance; the unity-gain crossover frequency of the integrator is given by roo <::: (gmlC2) . Including the effect of output conductance (Fig. l(c», the

small-signal analysis yields

gm

4gds [ ( SgdsC2). ( SCI).J (

sC2 ) ( SCI) 1 - i lp - 1 - gm In • 1+- 1+- m

4~..I. ~_

(2)

Thus, the output conductance gds moves the dominant pole from the origin.

229

(a) (b)

(c)

Fig. 1. Continuous-time current-mode integrator. (a) The basic principle. (b) Small signal model without and (c) with output conductances.

to PI = IDc/a, where IDo = g,,/C2 is the unity-gain crossover frequency of the

integrator, and a = - g,,/4gds is its low-frequency open-loop current gain.

The total parasitic capacitance (C1) at the input inversely affects the

frequency of the non-dominant pole (P2 = g,,/C1), causing undesirable

excess phase shift at the integrator crossover frequency. By designing for C2»C1 and by using cascoding techniques to reduce the output

conductances, Q factors exceeding 20 can be achieved at high frequencies.

The ladder filter synthesis techniques using signal flow-graphs are directly applicable to design of current-mode continuous-time filters. Two such prototype third- and fifth order ladder filters have been integrated in 2-~ n-well CMOS technology. Figure 2 shows the measured frequency response of the five-pole Chebyshev filter. Table I summarizes the measured filter performance.

230

m ~ W o

20r---------------------------~ I I I I I 1111 I I I I 11111 I I I 1111

-I~ ~IWI~ -I-I~ UIUI- ~ ~ ~IWI

I I I 1111 I I I I 11111 I I I 1111 o t--...... ~-+I"ot+foto-"1'Ir'1"ft.o H I ttl - .. 'I 1" I nl

):i II111 I I 11111 -1-1 1IIIIif -1-1 1'{lIITI- I f !Iill

~ -20 z

I I I 111111 I I 1\\1111 I I I 1111 ------- ,.------I I I I I 1111 I I 11',\111 I I I 1111

" -I~ ~I~I~ -I-I~ J~l- ~ ~ +I~I 0'

I 11111111 Ift-J I I 111I1 -I. rlnlrr -I-I. ~i.- r r Tlnl

~ ~

-40 " I I I I I 1111 I I I I I II\~ I I I I I II --------- ~----I I I III I \\ I I 11111

\~ -60 1E6

Fig. 2. Measured frequency responses of a fifth-order low-pass filter (bias current 50 ~A, 100 ~A, 150 ~).

TABLE I. Summary of measured performance of a five-pole continuous­

time filter.

Technology

-3 dB frequency (mean)

RMS Noise (40 MHz BW)

Dynamic Range

(1% TIMD)

Power (V dd = 5 V)

Active Filter Area

2-J.1m n-well CMOS

38.5 MHz

7.4 nArms

69 dB

26mW

O.28mm2

231

3. Fully-Balanced Continuous-Time Integrator

Viewing from a different perspective, the main limitation in the high­frequency performance of single-ended current-mode filters is that the signal path for positive and negative inputs is different. The first inverting stage merely introduces a parasitic non-dominant pole, thereby degrading Q of the integrator and the filter response. Intuitively, this suggests that the fully-balanced structure will have identical paths for both positive and negative inputs and hence the filter bandwidth can be extended further.

Figure 3(a) shows the proposed balanced continuous-time integrator [8]. It consists of a pair of cross-coupled current amplifiers. Identical MOSFET capacitors are added at both positive and negative inputs to establish the dominant pole frequency of the integrator. Additional output branches provide multiple output currents. The completely symmetrical nature of the circuit allows easy analysis for fully-balanced small-signal inputs. Fig. 3(b) shows the simplified small-signal model of the balanced­mode 'half-circuit'. KCL at nodes A and B yields

(b)

(a) (c)

Fig. 3. Fully-balanced Continuous-time Integrator. (a) The basic principle. (b) Small signal model without and (c) with output conductances.

232

. . gm (. . ) lop - Ion = - lp - In •

sC (3)

This represents continuous-time integration of the balanced input currents similar to (1). A detailed small-signal analysis of the circuit including gds

and Cgd is carried out in Fig. 3(c):

where

and the DC gain is

(gm - gds)

2CRd

gds PI = ---­

(C+4CRd)

A = gm-gds. gds

The integrator unity-gain frequency is given by

co = A = (gm-gds). o PI C+4C

Rd

(4)

(5)

(6)

(7)

(8)

The gate-drain capacitance Cgd ofM2 (M4) causes a right half-plane (RHP)

zero which gives excess phase shift at the unity-gain frequency (coo) of the

integrator. To achieve high Q factor, the RHP zero should be positioned as far as possible from the unity-gain frequency.

Ideally the integrator should have infinite DC gain. An integrator implementation using a simple current-amplifier has a DC gain on the order of gm/gds (-10-40). Higher gains are achieved by using cascoded current amplifiers.

A typical HSPICE simulated frequency response of the three-pole Chebyshev continuous-time filter is shown in Fig. 4. The -3 dB bandwidth

233

of the filter (Fig. 5(a» is a square-law function of the bias current (IB).

Figure 5(b) shows the total hannonic distortion (THO) performance as a function of peak-signal to bias current (ill) ratio at different signal frequencies. Table II summarizes simulated performance characteristics of the 3-pole low-pass filter.

Fig. 4. HSPICE simulation results: 3-pole Chebyshev filter ac response with passband ripple = 0.1 dB.

130r----------,--------, -20

150 200 Iblasw,A)

(a)

-80 250 0.0

/ ::::: V Vfi

'V 0.2

10 ~ ~ V ~ V

----/'

V "1oc MHz

V ~Hz

0.4 0.6 0.8 I(peak)llblas

(b)

Fig. 5. HSPICE simulation results (a) Filter bandwidth vs.lbias (b) Filter THD vs. i(peak)lIbias.

234

TABLE II.HSPICE simulated performance of a three-pole Chebyshev

low-pass filter

Technology

Power supply voltage

3 dB Bandwidth

Power Dissipation

Active transistor area

Total rms input referred noise (100 MHz)

Maximum input signal current at 1 % THD

Dynamic range

4. Conclusions

1.2 f.U11 n-well CMOS

3 Volts

125 MHz

6mW/pole

3000 f.U112/pole

182nArms

300 JlA (peak)

62 dB

Simulation results of the proposed fully-balanced current-mode filters look promising. Compared to previous implementations, these integrators have identical signal paths for both positive and negative inputs. Also, the parasitic non-dominant pole is completely eliminated. The integrator Q­factor is limited by a zero (z]= g,,/Cgd), which can be pushed beyond I

GHz. This extends the possible filter bandwidths beyond 100 MHz consuming only 6 m W Ipole, while operating from a 3-V supply in standard digital CMOS technology.

S. References

[1] H. Khorramabadi and P.R. Gray, "High frequency CMOS continuous-time filters," IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 939-948, Dec. 1984.

[2] C.S. Park and R. Schaumann, "Design of a 4-MHz analog integrated CMOS transconduc­tance-C bandpass filter," IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 987-996, Aug. 1988.

[3] V. Gopinathan, Y.P. Tsividis, K.S. Tan and R.K. Hester, "Design considerations for high­frequency continuous-time filters and implementation of an antialiasing filter for digital

235

video," IEEE J. Solid-State Circuits. vol. 25, no. 6, pp. 1368-1378, Dec. 1990.

[4] J.M. Khoury, "Design of a 15-MHz CMOS continuous-time filter with on-chip tuning," IEEE J. Solid-State Circuits, vol. 25, no. 12, pp. 1988-1997, Dec. 1991.

[5] W.M. Snelgrove and A. Shoval, "A balanced 0.9-J1m CMOS transconductance-C filter tunable over the VHF range," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 314-323, March 1992.

[6] B. Nauta, "A CMOS transconductance-C filter technique for very high frequencies," IEEE J. Solid-State Circuits, vol. 27, no. 2, pp.142-153, Feb. 1992.

[7] S.S. Lee, R.H. Zele, 0.1 Allstot and G. Liang. "CMOS continuous-time current-mode fil­ters for high-frequency applications," IEEE J. Solid-State Circuits, vol. 27, no. 3, March 1993.

[8] R.H. Zele, S.S. Lee, and OJ. Allstot, "A 3V-I25 MHz CMOS continuous-time filter," in Proc. IEEE Int. Symp. Circuits Syst., 1993, pp. 1164-1167.

[9] S.L. Smith and E. Sanchez-Sinencio, "3V high-frequency current-mode filters," in Proc. IEEE Int. Symp. Circuits Syst., 1993, pp. 1459-1462.

[10] T.S. Fiez and OJ. Allstot, "CMOS switched-current ladder filters," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1360-1367, Dec. 1990.

SMART POWER

W.M.C. Sansen

Preface

The integration of more and more functions on one chip is leading to a considerable rise in temperature. Different analog blocks can therefore operate at different temperatures. Moreover, output drivers for line interfaces, for motor interfaces, audio, etc., provide large currents and hence power peaks. They thus generate important thermal transients, that can affect and even disturb sensitive input amplifying stages. Thermal detectors and protection networks have to be included not to impair reliability and life time of such devices. This is called smart power design. It is never limited to circuit design only, it also includes packaging and cooling considerations. It is system design.

The contributions of this Session all focus on different aspects of smart power design.

The first one by L. Borucki of Motorola, USA, shows that an electrothennal simulator can be a powerful tool towards predicting thennal transients. On the other hand it has also become clear that thennal conduction and convection heavily depend on the actual bond wires and packages used. More work is thus required on the development of thennal models for both the devices on chip as for the packages and the final system substrate.

The second contribution is by H. Zitta of Siemens Austria. He illustrates smart power design by means of a large number of circuits with emphasis on power switches. Their SIPMOS technology also includes DMOS and bipolar devices yielding a large flexibility in the actual circuit design. Examples are given of circuits operating at temperatures above 150°C.

The third contribution is by T. Szepezi. It follows the same lines but is focused more on switching voltage regulators. Some of them are in bipolar technology. Other ones use DMOS devices. Specific attention is paid to thennal runaway and how to cope with it by means of clever circuit design.

The fourth contribution is by F. Schoofs of Philips Research Laboratories in Eindhoven. He addresses the problems of chips, that are connected directly to the mains supply. Hence, breakdown voltages are required of above 1000 Volts.

237

R.J. van de Plassche ~t al. (eds.), Analog Circuit Design. 237-238. C 1995 Kluw~r Academic Publishers.

238

DMOS devices are used. Several industrial and consumer applications are included to illustrate the trade-offs.

The fifth and last but one contribution is by B. Graindourze from Alcatel Mietec Brussels. He focuses on the modeling aspects of the high-voltage DMOS devices used. A macro-model is used to represent the second-order phenomena of these devices leading to a high precision prediction of static and dynamic behavior. An electrothennal simulator is used as well to predict thenna1 transients.

The final contribution of this Session and of this AACD is made by B. Murari of SGS-Thomson, Milano. He points at the long lasting efforts of his company towards ever higher integration of power devices with circuits both analog and digital. He makes it clear that smart power integration has to be carried out at a higher level, involving mixed analog-digital circuit design, package design and system design. The evolution is such that smart power design is invading the design of any chip with high complexity and that the system partitioning is governed mainly by thennal aspects.

It thus becomes clear that smart power design has become an important part of mixed analog-digital design. Also electrothenna1 analysis has become a must in all analog and mixed analog-digital design automation systems.

Modeling of Transient Heating in Smart Power Applications

L. Borucki

Motorola, Inc. Advanced Custom Technologies

1300 N. Alma School Rd. Chandler, AZ 85224

USA

Abstract

Economic forces and integrated product designs are forcing the fabrication of some smart power applications on smaller die and on alternative substrates. This results in greater heating for a given application. Thennal models of possible advanced versions of an automotive fuel injector application suggest that while steady state heating is acceptable in these designs, transient heating may become a concern. The peak transient temperature in a 50% shrink of the injector application would be close to the empirical safe design limit, while a reduced device on bonded wafers is predicted to exceed the limit. This requires consideration of innovative energy management strategies and careful reliability assessment.

I Introduction

The potentially large market for smart power devices and the need to be competitive is pushing designers to ask for fabrication of applications on smaller die and with certain critical performance improvements, such as a decrease in on resistance. A desire to integrate smart power with other technologies on the same chip is also leading to consideration of alternative substrates, such as SOl with bonded wafers. Since the use of many of the advanced products has not changed, it is anticipated that some applications may face potentially serious heating problems that could affect their performance and reliability. The analysis performed here suggests that the heating problems may occur not in steady state operation, but rather during transient switching.

The modeling work that supports this concern will be described in the succeeding sections. First, a simplified thermal model used for the study will

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R.J. 1IQII U PI4ucIte III al. (1Id.r.), Analo, Circuil iHlIgn. 239-247. C 1995 KluwIIr AcoIlIImic Publl8lten.

240

00

f (t) = P~) ~PC4t1C1t [1 + 2 L (-I)n (e-~2n2 - "'i ~ n erfc (~n))], p n=1

u'[(t) is the unit step function at!='t, and ~=h/~.

3 Model Validation

Two approaches, analytic and experimental, were taken to validate the correctness and applicability of model (1). First, numerical solutions were compared with steady state linear and nonlinear analytic solutions of multilayer problems and with transient analytic solutions of single layer problems. The general finite element numerical solutions were found to be accurate in all cases. Comparison of linear and nonlinear solutions also indicated that a linear model with parameters evaluated at the heat sink (TAB) temperature underestimates the peak temperature rise by at most a few degrees under the conditions of interest. This fact was used to justify application of the quicker analytic solutions in some situations.

The error introduced by the power homogenization assumption was also studied by comparing the temperature distribution calculated from (1) with steady state results from the device simulator SIMUL [1], which can solve the energy equation for lattice heating through decoupled iteration with the temperature­dependent Poisson and current continuity equations. Heating terms in this program include electron and hole Joule heating, recombination heat, and the Thomson effect [2].

Figure l(a) shows a cross section through a 500 J.1m deep by 150 J.1m wide silicon substrate. Two full TMOSTM transistors are shown in addition to half of a transistor at the left side of the epi layer. Reflecting or insulating boundary conditions are applied to all solution variables (<p,n,p, T) along the left side of the domain, so that the model in fact represents the right symmetric half of a cross section through an active area five devices wide. The thermal portion of the problem assumes a fixed temperature (300 K) on the bottom of the substrate and insulating boundary conditions elsewhere. A gate bias of V GS=5 V was applied to the device and the steady state electrothermal problem was solved at various drain biases VDS. The resulting terminal currents were then used to calculate the power dissipated.

Figure 1 (b) compares the temperature profile along the silicon surface calculated using the thermal model (1) and the homogenization assumption with the microscopic SIMUL solution. The total power used in (1) was the

241

included [3]. In all cases, power was applied in the form of a periodic triangular pulse with a peak power of 65 W, 0.12 ms on time, 0.5 W power during the quiescent period, and 30 ms between pulses. Heat sink, die bond, substrate, and packaging materials were included and the heat sink was fIXed at 125°C. This corresponds to the engine compartment conditions experienced in the fuel injector application.

Figure (4) summarizes the results. At steady state, standard UPOD has a peak temperature rise of only a few degrees, while the proposed shrink devices have a steady state rise about four times higher, as one would expect based on the power density. The oxide layers in the bonded wafer structures can be seen to have little effect on the steady state temperature rise because their thinness precludes a high thermal resistance.

The situation is quite different for the transient temperature rise. For a fast transient power pulse, there is insufficient time during the pulse for the energy to be conducted to the heat sink. Thus, the temperature rise is influenced mainly by the immediately adjacent materials. While the rise for standard UPOD is calculated to be less than an acceptable 10°C, the rise for a 50% shrink is predicted to be approximately 40°C, placing it near the edge of the rule of thumb maximum temperature (about 165°C) used by designers. As Fig. 1 indicates, bonded wafer structures should have transient excursions significantly above this point.

5 Discussion

The temperatures predicted above for potential advanced designs are cause for concern, particularly for products on bonded wafers. However, the time during which the transient is critically high is generally only a portion of the on time ( < 0.12 ms for UPOD) and only a small fraction of the duty cycle. It is not known whether such operation would have a significant effect on device performance or a long term impact on device and metallization reliability.

Several strategies might be adopted to control the peak temperature. The simplest, substrate thinning, is not effective in this case, even when wafer bonding is not considered. The analytic solutjnl1 (2) implies that the peak temperature rise during a triangular pulse occurs approximately time M/2 and has magnitude

{iP(O) .... ~ ATmax <= T A -V pcp1m (3)

when the substrate thickness h is large relative to the diffusion length during the on time; ie, when f3=hlvo:t »1. The approximation (3) is independent of h when the substrate is thick for reasons explained above. Figure 4 illustrates

242

Heat SInk at 500 MIcrons

(a)

6 -; 110 (I)

a: ~ 100 e al Q.

E 90 ~

SIMUL

Model (1) with SIMUL Terminal -, Power .,

/ ~ ]

80 L-~ __ ~ __ ~ __ ~ __ ~~

o 50 100 150 Distance Along the Top Surface (Microns)

(b)

Figure 1: (a) Cross section of right symmetric half of five transistor TMOS structure used in 2D SIMUL steady state electrothermal simulations. (b) Comparison of temperature rise computed by SIMUL and by model (1) using total power calculated from SIMUL terminal characteristics.

10

9 Boxes

WidII1: Power Uncertainly

8 Height: +/. One Slgma T emperatur. RI ..

§; 7 j a: 6 ! ~ e 5 8. E ~ 4

3

2

2 3 4 5 6 Power (W)

7 8 9 10 11

Figure 2: Comparison of measured (boxes) and simulated temperature rise under steady state operation of the UPOD chip. Measured power is uncertain due to power dissipation in the drain bond wires.

~ ~ ________ ~ ________ ~r-________ ~ ________ -.

470

460

420

410

400

,;_ Global Maximum , , " , , , , , , , , , , , I ,

I \ I , " \ I ,

I , I

I I I

I I I

I , , I ,

3~L-----~--~----------~--------~--------~ 0.000 0.005 0.010 0.015 0.020 Time (Sec)

243

Figure 3: Comparison of the transient temperature response at a calibrated diode on a solid state relay with simulated local (solid curve) and global (dashed curve) temperature responses.

225 225

215 I Transient 215

205 I Steady State 205

195 195

§: a} l!! 185 185 ~ ;I CD

~ 175 iil

175 C c. iil E {!!. 185 165 :9

155 155

145 145

135 135

125 125 UPOD 50%Shr1nk Shr1nk+SOI Shrlnk+SOI

Figure 4: Model predictions of steady state and transient temperatures for the UPOD device, a 50% shrink of UPOD, and a 50% shrink on bonded wafers with two different oxide thicknesses.

244

~r---~--~----~--~--------~--------~

, ,

joo I I!! :

120 /

~ :

i 10 i

UPOD at 50% Shrink ,,------------------------------------------

UPOD

~ r7 °0~--------5~--------1~0--------~15--------~2O

Subatrale ThIckness (mUs)

Figure 5: For fast transients, the peak temperature rise is linearly proportional for the substrate thickness only when the substrate is thin. When the substrate is sufficiently thick, the effect of the heat sink cannot be felt during the heating process,· thus, the response is the same as it would be for an infinite substrate.

245

be outlined. Next, the model will be validated by comparison with steady state and transient measurements performed on actual power device products and by comparison of the simplified model with detailed device-level electrothermal simulations. Predictions of the model will be then be presented for possible advanced versions of the Motorola Universal Power Output Driver (UPODTM), a product that is currently widely used and known to be highly reliable, in an automotive fuel injector application. Finally, analytic approximations will be used to discuss possible thermal management strategies for the advanced designs.

2 Thermal Model

An ideal transient simulation of a macroscopic power device would simultaneously take into account the self heating of the individual microscopic transistors in the device, the temperature-dependent behavior of each transistor in their collective thermal field, and the conduction of heat to the heat sink and environment through bonding and packaging materials. Since this is not yet feasible at the chip level, a simplified approach was taken in which the heat equation,

(1)

was solved in various application models using a finite element / control volume method in space and a variable order, variable time step Gear method in time [4]. In the general case, material coefficients were temperature dependent and all important substrate, bonding, heat sink, metallization, passivation, isolation, and packaging layers were included in three-dimensional transient chip level simulations. One major simplification in the model is that the total power P(t) dissipated by the macroscopic device, as determined from measurement or simulation of terminal currents and voltages, was homogeneously distributed over the layout area A occupied by the individual power transistors down to a depth ~z, the vertical extent of the devices. Linear steady state and transient analytic ID and 3D solutions to simplified versions of (1) were also examined and found to be of value for obtaining quick temperature rise estimates and for gaining insight into thermal management strategies. For example, the linear ID analytic solution for the temperature rise in an infinite planar silicon substrate with thickness h subjected to a single triangular power pulse that decays from power P(O) at t=0 to 0 for t ~ 't is

1 t t-'t ~ T(h,t) = f(t) - t Jf(w)dw + u't(t) ~ jf(w)dw,

o 0 (2)

where

246

calculated from the SIMUL terminal characteristics. The error introduced by homogenization can be seen in this case to be at most SOC.

For experimental validation, model predictions were compared with steady state and transient temperature measurements. For steady state, packaged UPOD chips were obtained, inspected for die bond voiding, and then opened. Good units were then coated with a black antireflective paint to produce a uniform emissivity. Steady state measurements were performed on a hot chuck using an Agema thermal imaging system. Additional measurements to verify results from the Agema were performed on a Barnes thermal microscope. Voltage measurements for determining the dissipated power were made at the Kelvin contacts on the package. Thermal maps were produced at heat sink temperatures between 6S0C and 120°C and between S and 12 W of power. Because of significant Joule heating of the drain bond wires, calculations based on the bond wire length and cross section were used to estimate the power dissipated in each of the six power devices on the chip. In Figure 2, the measured temperature rise above the heat sink is compared with the calculated rise at each of the estimated power levels. The model is seen to be generally within the range of the data.

Additional comparisons were made with steady state measurements of the Motorola Euro-QIDTM device at higher power levels and similar heat sink temperatures, again with good results.

For transient validation, a solid state relay (SSR) used in automotive antilock brakes was obtained that has a built-in diode that can be calibrated and used for transient thermal measurements. SSR was operated on a 24-12S0C heat sink with power pulses that were approximately square waves of 1 to 12 ms duration and 170 and 760 W average power. Figure 3 compares the calibrated temperature rise at the diode observed in one case with the rise computed from a detailed 3D numerical model. It can be seen that the agreement is good during heating when the response depends mainly on the properties of silicon but deviates somewhat during cool-down when the effects of more distant materials become apparent. Note also that the global peak temperature predicted by the model is higher than the peak measured at the diode.

4 Model Predictions

Model (1) was used to compare the thermal behavior of the existing Motorola UPOD device, which has well-characterized thermal behavior and very high reliability, with possible advanced product designs. Two kinds of advanced designs were considered: a straightforward SO% shrink, and a SO% shrink on bonded wafers. In the latter case, effects of the thickness of the oxide and the details of the bonding structure were studied. The observed dependence of oxide thermal conductivity on layer thickness and annealing history was

247

how ~ T max varies with the substrate thickness in general. A linear effect from substrate thinning becomes apparent only for very thin materials; thinning of the 50% shrink device to one mil would be necessary to make it transiently equivalent to (and therefore as reliable as) the standard device.

Equation (3) suggests another alternative for controlling heating. The transient temperature rise depends on the material parameter product pCpK: the higher this product is, the lower the rise will be. Thus, it may be possible to design structures in which thermal reservoir materials with a high product are placed near the power transistors. The function of these materials would be to safely absorb and hold the energy during the on time and let it conduct away to the environment during the larger intervening off time.

6 Acknowledgements

Many individuals worked hard and creatively on this project. The author wishes to acknowledge Fran and Steve Robb, Dan Sullivan, Verne Hause, Mali Mahalingam, Clarance Tracy, Jon Candelaria, and Charles Cordonnier for experimental measurements, designers Randy Gray, John Pigott, and John Hargedon for layout and operational data, Tom Zirkle and Erik Egan for modeling assistance, and Dr. Avner Friedman of the Institute for Mathematics and its Applications for some of the analytic solutions.

7 References

[1] IIS, Simul Manual. Integrated Systems Laboratory, ETH Zurich, Switzerland, 1.0 (alpha) ed., 1992.

[2] G .K. Watchutka, "Rigorous Thermodynamic Treatment of Heat Generation and Conduction in Semiconductor Device Modeling," IEEE Trans. on Computer-Aided Design, Vol. 9, No. 11, Nov. 1990, pp. 1141-1149

[3] K.E. Goodson, M.I. Flik, L.T. Su, and D.A. Antoniadis, "Annealing­Temperature Dependence of the Thermal Conductivity of CVD Silicon­Dioxide Layers," AS ME National Heat Transfer Conference, Atlanta, GA, August 8-11, 1993.

[4] A.C. Hindmarsh, "ODEPACK, a systematized collection of ODE solvers," in Scientific Computing, R.S. Stepleman et. al. (eds.), North-Holland; Amsterdam, 1983 (Vol. 1 of IMACS Trans. on Scientific Computation), pp.55-64.

Smart Power Circuits for Power Switches Including Diagostic Functions

HeinzZitta Siemens-Entwicklungszentrum fUr Mikroelektronik

A-9500 Villach. Austria

ABSTRACT

Design concepts of smart power switches are described in this paper. Smart power technologi~s for low-side and high­side switches make it possible to include the diagnostic functions on chip. Also protection circuits. driver circuits and aspects of electromagnetic compatibility are discussed.

1. INTRODUCTION

Today power technologies make it possible to add on chip diagnostic functions and protection circuits for electronic power switches. For automotive application a voltage range up to 80 V and currents from few amps up to 25 A define an important segment for integrated circuits. Replacing discrete power semiconductors leads to a reduction in the overall component count and enables an increase in functional complexity with additional improved overall reliability. Especially the goal of continuous increasing quality emphasizes the development of self­protecting circuits. So the diagnostic circuits have to detect not only external error-conditions but also critical faults on the chip.

2. TECHNOLOGIES

There is no single power technology which could be chosen as the best for all applications. Classification of smart power technologies are based either on the isolation technique or on the type of the power device. including the path of current flow.

249

R.J. WIll. Plauche et aL (ed8.). AnaIo, Circuit Duign, 249-264. C 1995 Kluwe,. Academic Publishe,...

250

Common to all smart technologies is the combination of a DMOS-type power transistor with standard CMOS and/or bipolar components for the analog and control functions. Although there exists a range of smart bipolar circuits in automotive applications, our today tmderstanding will not include bipolar-only processes in the "smart" technology definition.

2.1 Smart SIPMOS Technology

As an example of a CMOS based self isolation technology the Smart SIPMOS Technology is shown in fig. 1. The power device, realised as a vertical n-channel transistor, uses an epitaxial drift layer, grown on a high doped substrate. The current flows in vertical direction from the top to the bottom of the wafer and the die attach area to the package itself. This allows very high current densities, which makes this technology very well suited for low-resistive, high current high side switches. But there is a limitation: The drain of the power transistor is always the n+ substrate. Therefore multiple power switches are only possible in common drain configuration.

LowVoJtage CMOS

poChannel

S G 0

n-Chamel

o G S

p+

High Voltage Mas-Translator

poChannel n-Channel

S GO o G

po no.

n-

n+

+ Vbatt

S

Vertical DMOS Power Transistor

S G

DRAIN of DMOS

Fig. 1: Cross section of the self isolated Smart SIPMOS Technology

Devices for low voltages, such as CMOS n- and p-channel transistors and capacitors are well isolated by p+ isolation rings and polysilicon guard­ring structures. Thus they are safely protected against the high voltage of the substrate. Each device can be located in such isolation tubs, which avoid the CMOS latching problem and other parastic interferences. A bipolar transistor is only available as a substrate npn, so its use in circuit­design is restricted.

251

2.2 Smart Power Technology

An example of a junction isolated smart power technology is shown in fig. 2. Based on a p- substrat and a n+ doped epitaxial layer, like a bipolar technology, it offers a combination of a high voltage DMOS device and low voltage bipolar (npn and pnp) and CMOS devices. The current path in the power device is vertical but the drain connection is brought to the surface via a buried layer and sinkers, also called an updrain configuration. This approach allows the integration of one or more isolated DMOS power devices connected in any configuration. But the current per device is restricted to a maximum value · of approximately 10 amps, which is enough for a number of automotive applications.

DMOS-Transistor NPN-Transistor PMOS-Tr. NMOS-Tr.

Fig. 2: Cross section of the junction isolated Smart Power Technology

The low voltage p-channel and n-channel transistors allow us to integrate medium complex CMOS logic parts into the power switches. The bipolar transistors are provided for the analog circuits due to the better characteristics like noise, offset and drift behaviour.

Each technology offers a different amount of components for the circuit designer. Table 1 shows this situation for the above mentioned technologies compared with a purely bipolar technology. In addition to the described transistors also zener-diodes, resistors and capacitors are available in all technologies.

252

Technology Component SMART SMART

BIPOLAR Self Junction Isolated Isolated

-{ npn X X

Bipolar =r npn (C = Substrat) X

-{ pnp X X

Low-Voltage 1~ P-channel X X

CMOS

1~ N-channel X X

High-Voltage 1~ P-channel X X

MOS 1~ N-channel X X

--;r N-channel vertical X Power 1l; drain = substrat

DMOS

1~ N-channel updrain X

Table 1: Active components available in smart power technologies compared to a bipolar technology

3. FUNCTION BLOCKS FOR SMART POWER SWITCHES

Today's automotive electronic systems must provide highest reliability and robust operation. This includes withstanding against voltage spikes, a high temperature range and immunity to electromagnetic interference, while not beeing a source of electromagnetic interference. Therefore a self diagnostic monitoring on chip is important to report the system condition to the controlling microprocessor and to protect the circuit. This leads to the function blocks, which are required for smart power switches in automotive applications.

The functional blocks which are necessary for smart power switches are listed in table 2. An interface part connects the smart power switch to the controlling microprocessor - a good application for the CMOS

253

components. The smart part is responsible for all the diagnostic and protective functions. It is the area of analog circuits using the bipolar or low voltage MOS components. Last but not least the power switch itself is dermed by the DMOS transistor.

INTERFACE SMART PART POWER OUTPUT over temperature

seriell short circuit -;::r parallel open load

high side switch 11:L. bus over voltage load dump protection

1r status output for under voltage diagnostics current limiting

low side switch ~ dildt-limiting

CMOS Digital Bipolar or PowerDMOS MOS Analog

Table 2: Functional blocks of smart power switches

The block diagram of a two channel low side switch, realised in a 75 V smart power technology, is shown in fig. 4. The characteristic data are listed in table 3.

InpUt 1 --0uIput1

InpUt 2

8IIduI OUtput 2

SUpply VoIIIIge + 15 V ... + 415 V

---------------------------, I I

LOGIC

E ~ 10UIput2

l.._._._._._._._._._._._._._~._._._._._. ___ ._._._._._._.J ..,

I- INTERFACE + SMART-PART +POWER-PART--!

Fig. 4 Block diagram of a 2 x 4 A low side switch with diagnostics

254

Ron (each channel) 0.25 Ohm typo Supply voltage 5 V to 45 V Maximum operating current 2x4A Output voltage protection integrated clamping to 60 V Short circuit protection yes Overtemperature shut-down yes Open load detection yes Logic control 2 control inputs, 1 enable input

2 status outputs for diagnostic Package P-DS024-L-16

Table 3: Characteristic data of the low side switch

Now the circuits which are necessary to fulfill the requirements of the "smart part", that means all diagnostic and protection circuits of the power switch will be presented. Required are overvoltage protection, current sensors, temperature sensors and special gate drive circuits including charge pumps.

3.1 Overvoltage Protection

The detection of overvoltage can be simply achieved by using a comparator as shown in fig. 5a. The overvoltage magnitude to be detected is set by the resistor ratio, compared with the reference voltage. An critical overvoltage that often occurs in power switches is the high voltage, which is generated from switching inductive loads. To protect the output transistor against that overvoltage the best way is to switch on the power DMOS via a chain of zener diodes, connected directly from drain to the gate. Fig. 5b shows this for a low side switch. The same principle will also be used for the high side switches.

VBaH

Fig. 5a: Overvoltage detection

L

Fig. 5b: Overvoltage protection of DMOS against inductive loads

255

3.2 Current Measurement Circuits

For the detection of overcurrent or open load conditions a current measurement possibility is required. Fig. 6 shows a simple direct measurement via a shunt resistor usually as a part of the metal layer. The reference voltage Vref defines the current threshold, the output of the comparator can be used only as diagnostic signal or directly connected to the gate in a feedback loop to control the current.

Over-Current

Fig. 6: Current measurement by using a shunt resistor

I~J ~ Over-

Current

R-ALU

Fig. 7: Current measuring circuit which needs no reference voltage

The circuit shown in fig. 7. needs no comparator and no voltage reference. Assuming the same collector currents for Q 1 and Q2, the current limit threshold is well defined by the ~ VBE of Q 1 and Q2, which is known as

~VBE = Vt .In (AreaQl / AreaQ2)

Vt = kT/q depends on the absolute temperature, but this temperature coefficient is first order compensated if the resistor RS is made using the aluminum interconnect metal. Therefore this circuit leads to a good temperature compensated current limiting and is therefore often used.

A disadvantage using a shunt resistor is the voltage drop, because the resistor is connected in series to the load circuit. To avoid this voltage drop, the use of a sensing transistor is known, as shown in fig. 8. For the sensing transistor M2 a few cells of the power transistor Ml are separated and used like a current mirror.

256

M1 Over­

Current

Fig. 8: Current measurement by using a sensing transistor

The current mirror MIIM2 does only work properly if the voltage across the resistor RS is low to ensure equal gate-source voltages. In some applications it would be better to use the power transistor itself as a shunt resistor. The circuit shown in fig. 9 uses the whole voltage drop at the power transistor as measuring voltage. A reference current is fed into a sense cell (M2) to achieve an accurate measurement and the voltage difference between the two drains is evaluated.

I Load

M1

Fig. 9: Current measurement with sensing transistor and reference current

This principle enables additional features in current measuring. By switching the reference current to different values it is possible to add a dynamic control to the overcurrent circuit.

257

A simple but also useable method for short circuit protection is to measure only the absolute value of the drain-source voltage (VDS) across the power device. This method can not detect an overcurrent as long as VDS is lower than the detection threshold, but it works well at the more critical low-ohmic short circuits which could destroy the device by the high power. So it is more a power limiting than a current limiting. The combination of both methods allows us to design a real power limitation, if required, by multipying the voltage and the current signal.

3.3 Temperature Sensors

The common way of measuring the temperature on chip is the use of a bipolar transistor. This is also possible in MOS-based smart power circuits by using the substrat npn. But the bipolar transistor is not always used in the same way. Fig. 10 shows a temperature sensor which is based on the leakage current dependence on temperature. The absolute value of the temperature switching point can not be forseen without practical experience, but it can be adjusted by the value of Rl. When the right value is found then the temperature switching point will stay very constant over production deviation. This type of sensor is used in the Smart SIPMOS power switches. This principle works well in the most interesting temperature range over 1500 C junction temperature, but is is not suited for defining temperature switching points below 1500 C.

v+

IeB

R1

'---+-"ovr

TIIIIpenIbn

Fig. 10: Temperature sensor by using the leakage current

The other type of circuits uses the well-known VBE-characteristic to measure the temperature. The circuit shown in Fig. 11 compares the

258

temperature dependence of VBE (QI) with a reference voltage. A temperature constant reference voltage is required, generally supplied from a bandgap reference circuit.

VBE

VREF

Fig. 11: Temperature sensor circuit with hysteresis

The CMOS output stage M2IM3 is connected to the gate of M 1 which switches an additional current IH on or off, this defines the hysteresis characteristic. This principle is often used, via the voltage divider RIIR2 it is possible to adjust a well defined switching temperature because the VBE voltage is not so sensitive to fabrication tolerances. A problem could occure if the bandgap reference does not stay constant in the very high temperature range. Fig. 12 shows the problem: If the reference voltage decreases with high temperatures then the switching point will be shifted to very high temperatures or -eventually- it will drop faster than the VBE-characteristic and so never switch on the temperature sensor Ql.

VBE

VREF

Temperature

Fig. 12: Possible nonfunction of the temperature sensor if VREF is not constant in the very high temperature range

259

To avoid this problem, an other circuit is shown in fig. 13. This circuit is based on the bandgap-reference principle, but not with the goal to having a temperature constant voltage. It operates directly by using the A VBE factor to generate a current proportional to absolute temperature (J7I' AT). Assuming the same temperature-coefficients of the resistors R I, R2 the circuit generates a voltage drop on R2 which is always increasing with temperature, this is valid also for very high temperatures above 1500 C without the need of any second order temperature compensation. On the other hand this circuit does only work correctly if all components have the same temperature, so not only Ql ist the "sensor" but the whole circuit.

Q2

ovrfL---------" _ t. TemperIIIUnt

Fig. 13: Temperature sensor circuit which is reliable also in a very high temperature range

The hysteresis circuit is not shown here, it can be added in the same way as in the circuit of fig. 11.

3.4 Gate Drive Circuits

According to the required switching speed or frequency of the power switch a driver circuit to switch on and off the power DMOS will be designed . To minimize the power dissipation during switching a fast transition seems always to be a good choise but it can cause significant problems due to radiated and conducted electromagnetic noise. An appropriate and simple countermeasure to control dildt-transients is the use of current sources for driving the power transistor, see fig. 14a. This

260

slows down the charging and discharging of the gate-source capacitance of the DMOS transistor and thereby limits diJdt-transients. However it also introduces a delay (fig.14b) into the switching operation until the threshold voltage Vt is reached. This may not be acceptable.

DMOS ... - , - - - - - - - .- - - - - - - Vt

- -90%

- -10%

a) b)

Fig. 14: Simple DMOS driving circuit

A gate driver circuit which minimizes switching delays is shown in fig. 15. The basic idea is to use a high current drive to initiate the tum-on and tum-off and to use a low current drive when the load current transition occurs. The changing points from low to high gate drive current are defined by detection circuits. These detection circuits consist of small DMOS mirror transistors and reference currents which correspond e.g. to 10% and 90% of the load current, divided by the DMOS area ratio. The tum-on and tum-off is initiated by Ihi and Ilo, in order to minimize delay times. When the transition of the DMOS current is detected, Ihi is switched off. This method allows maximum possible operating frequency of the system and EMC compliance. The circuit employing this drive method has been succesfully implemented in the 4A low side switch using 75V smart power technology.

261

Detection circuit

Fig. 15: Basic circut diagram of enhanced di/dt limited DMOS gate driver

3.5 Charge Pump Circuits

In a high side power switch the power transistor, which always is a n-channel device, is used in a source follower configuration. That requires a positive voltage - higher than the supply voltage - for the gate to achieve a low Rds-ON, see fig. 16.

DraIn

Fig. 16: High side switch requires a high

voltage for the gate

Fig. 17: High gate voltage improves the Rds-ON for a low side switch

Sometimes also low side switches could use a high gate drive voltage to improve the Rds-ON if they should work with low supply voltages (fig. 16). This high gate voltage is commonly generated by a charge pump circuit.

262

Fig. 17 shows a simple voltage doubler circuit. An oscillator is needed to activate the circuit. Frequency stability is in general not a question, so we can use simple circuits like a ring oscillator or a simple R-C oscillator. The working frequency will be in the range of few 100 kHz to few MHz.

Fig. 17: Simple charge pump circuit

For supply voltages below 8 V the output voltage of a simple charge pump will not be sufficient. Therefore a multiple stage configuration is required. A good design value is the goal to generate a gate voltage of 10 volts over the positive supply voltage to achieve the minimum Rds-ON for the high side switch. Fig. 18 shows a circuit which will generate from a 4.5 V input voltage a charge pump voltage of approximately 15 V . The zener diodes limit the maximum voltage to a value which is allowed to apply to the gateoxid (e.g. 15 V ). The five inverter stages are directly connected in a feedback loop as ring oscillator, therefore no additional oscillator is necessary.

Fig. 18: Multiple stage charge pump generates 15 V up from 4.5 V

263

The charge pump circuits shown need diodes, but bipolar diodes are not available in an only MOS-based self isolating smart process. In that case n-channel high voltage lateral transistors can be used as MOS-diodes in a charge pump circuit. In Fig. 19 the realisation of a charge pump for a Smart SIPMOS high side switch is shown.

(slbstrala)

r-----t~ vCP

J1...

Fig. 19: Dual stage charge pump circuit for a high side switch in a MOS-based self isolated technology

4. CONCLUSIONS

The realisation of low side and high side power switches in smart technologies enables the monolithic integration of diagnostic and protection functions on chip. A selection of circuits, which fulfill the requirements for the "smart" part of the power switches were presented. The choice of possible circuit design is influenced by the type of technology. The self isolated Smart SIPMOS Technology is very well suited to design low ohmic high side switches, the junction isolated Smart Power Technology have additional features due to the isolated DMOS devtce and including bipolar components.

264

REFERENCES

[1] S. Hobrecht. "An Intelligent BiCMOSIDMOS Quad I-A High-Side Switch", IEEE J.of Solid State Circ., Vo1.25, No.6, pp. 1395-1402, Dec. 1990.

[2] S.L. Wong, S. Venkitasubrahmanian, M.J. Kim, and J.e. Young, "Design of a 60-V 10-A Intelligent Power Switch Using Standard Cells", IEEE J. Solid-State Circ., Vol.27, pp. 429 - 432, Mar. 1992.

[3] P. Rossel, "MOS technologies for smart power and high voltage circuits", Onde Electr.(France), Vo1.67. No.6, pp 58-69, Nov. 1987.

[4] A. Elmoznine, J. Buxo, M. Bafleur and P.Rossel, "The Smart Power High-Side Switch: Description of a Specific Technology, Its Basic Devices, and Monitoring Circuitries", IEEE Trans. Electron Dev., Vol. 37, No.4, pp. 1154-1161, April 1990.

[5] W.C. Dunn, "Driving and Protection of High Side NMOS Power Switches", IEEE Trans. Industr. Appl., Vol.28, No. I. pp. 26-30, JanlFeb.1992

[6] J. Massoner, K. Wiesinger, "Intelligente Leistungs-IC fur die KFZ-Elektronik", Mikroelektronik (Germany), Vol.4, No.6, pp. 422-427, Nov.lDec. 1990.

[7] H. Zitta, A. Koroncai, J. Massoner, H. Rothleitner, "Ein integrierter Vierfach 60-V Speisungs- und Oberwachungsbaustein fur ISDN Obertragungsleitungen", GME-Fachbericht 6, GME-Fachtagung Bicmos und Smart Power, Bad Nauheim, Gennany, pp.123-128, Feb. 1990.

[8] W.M. Werner, J. Melbert, "Technologien fUr integrierte Leistungs­schaltungen" ,GME-Fachbericht 6, GME-Fachtagung Bicmos und Smart Power, Bad Nauheim, Germany, pp.l09-114, Feb. 1990.

[9] B. Murani, "The application of smart power technology", GME-Fachbericht 6, GME-Fachtagung Bicmos und Smart Power, Bad Nauheim, Germany, pp.115-122, Feb. 1990.

[10] P. Brauchle, V. Denner, "Protected Power Switch", Proc. 19th Intern. Intelligent Motion Conf., NUmberg, Germany, pp. 278-283, June 1991.

[11J J. Einzinger, L. Leipold, J.Tihanyi, and R. Weber, "Monolithic IC Power Switch for Automotive Applications", ISSCC Dig.Tech. Papers, pp. 22-23, 1986

Design and Circuit Techniques of Integrated Switching Voltage Regulators

Thomas Szepesi

National Semiconductor, Santa Clara, ea, USA

Abstract

This paper is a tutorial presentation of the techniques and circuits used in integrated "smart power" switching regulators. Regulators with both high-side and low-side switches are covered. Circuits used· in the output power stage, in the current limit section, and oscillator are discussed in detail, both in bipolar and BiCDMOS technologies. Methods to deal with switching regulator-specific issues, like short circuit runaway, leading edge blanking and parallel operation of multiple reg­ulators are also reviewed.

1. Introduction.

Monolithic power conversion started with the LMI09 IA linear regulator, introduced by NSC in 1969. The first integrated monolithic DCIDC converter, capable of delivering significant power (>IOW) was the L296 from SGS, unveiled in 1982 ([1]). Another first was the LTI070, the first monolithic current-mode DCIDC converter, designed by LTC in 1985. Finally, the first integrated switching regulator with internal loop compensation, the LM2575, was introduced byNSC in 1988 ([2], [3]).

265

R.J. van tk Plassche lit aI. (tub.), Analog Circuit Design. 265-291. C 1995 Kluwer Academic Publishers.

266

All the above circuits are fabricated on bipolar processes and are aimed at the medium voltage "industrial" market, with 40-60V maximum operating voltages. These processes usually have NPN transistors with ft=300MHz, and lateral PNP transistors with ft=4-10MHz. Consequently, they are limited below 1 00-150kHz operating frequency. Their typical efficiency is limited to about 80-82% in a typical 5V output step-down application by their composite PNP-NPN power switch. To increase the operating frequency, and with it decrease the size of the magnetic components, SGS developed a 60V BCDMOS process, and introduced its U97X series 500kHz buck converters ([4 D. These regulators reach 90% efficiency, but are more expensive, due to the complex 18 layer process. Similar processes have been introduced also by NSC, Motorola and TI. Switching regulators were slow to gain wide acceptance due to their non­linear, time variant nature, and consequent complex analysis and design procedures, as well as the large number of external components they required. These barriers were significantly reduced by the introduction ofNSC's Simple Switcher(TM) family of switching regulators in 1988. These ICs required minimum number of external components, by eliminating the need for external compensation. Also, they were accompanied by a free design software, Switchers Made Simple(TM), running on the IBM PC. The software created simple DCIDC converter designs from specification to full schematic and parts list, with guaranteed output accuracy. It was followed 2 years later by similar design aides from LTC and SGS­Thompson. Today, switching regulators are widely used in the industry and quickly gaining market share from their still dominant linear brethren.

2. Buck Regulators.

The most popular switching voltage regulators are the buck or step-down DCIDC converters. They depend on high side power switches, in their non-

Vow

low

FIG. 1 BUCK REGULATOR

FIG. 2 BUCK REGULATOR WAVEFORMS

267

268

isolated version. They are used as a high efficiency replacements for linear regulators. A typical buck regulator circuit is shown in Fig.I. Some essential blocks (e.g. internal regulator, thermal shut-down, under voltage lockout, etc.) are not shown for clarity. Fig.2 shows the typical wave forms. The circuit shown is a voltage-mode controlled design. The sawtooth or triangular timing wave form of its internal oscillator is used to create a pulse-width modulated (PWM) square wave signal that controls the on/off time ofthe power switch. The output voltage is the DC average ofthe square wave V sw signal:

Vout= D*Vin /1/

(assuming ideal switches).

2.1. Power Stages.

The power switch in modem bipolar designs is realized by an NPN power transistor, driven by a "deep base" PNP transistor. Deep base DBPNPs are used to improve the high current beta of the driver. This is important, because at the typical switch current levels of I-3A, IOO-300mA base current is needed for fast tum-on. This current would require impractically large 200-600x standard lateral PNPs. Deep base PNPs can be run at about 5 times current density, compared to standard lateral devices, which means that a much smaller 20-60x device can do the job. Fig.3 shows the bipolar high side power switch of a 3A Buck regulator, the LM2576 ([6]). The emitter follower output switch, Q9, a lOOOx NPN device is run at about 5mA/sqmil emitter current density (in current limit). It is driven by Q7, a 60x DBPNP transistor. Q7 is turned on by the gained up 320uA bias current. The current gain-stage consist of Q2-Q6, it has a controlled current gain of about 125:

269

11 = IC<Q3) + IC<Q4) = {lb*(5+120)+1.5/Ik)}*B/(B+I) = 121

= (I25*lb+ 1.5mA)*50151 = 40.7mA

This current provides the output NPN (Q9) with a worst case tum-on base current of about 300mA, via Q7. It significantly overdrives Q9, yielding fast tum-on, with a voltage rise time below IOOnsec. When Q9's emitter reaches its on-state stationary value of about 1.1 V at 3A Q8 sat-catcher transistor senses that Q7 starts saturating, and turns on. Its current is turned around by Q 1 O-Q 11 and reduces the input current of the Q2-Q6 current gain stage to a level that keeps the V ce of Q7 at about 200mV.

ON/OFF

--....... -------~....-~....-----....... Vin R2 60

11 ~

FIG. 3 BIPOLAR HIGHSIDE DRIVER STAGE

V1

270

This drive reduction has two advantages. It reduces the ground current of the driver stage to the minimum value necessary to maintain the targeted V sat voltage, i.e. increases efficiency. Also, by reducing the drive of Q7, its storage time is reduced, speeding up its turn-off. Q7 is the slowest stage in the driver circuit, its speed limits the switcher's maximum operating frequency. With the simple resistive base discharge, shown here, the operating frequency is limited to about 100kHz. Using a more complex active tum-off ([1]) would extend the operating frequency to 200kHz.

As mentioned in the introduction, to raise the operating frequency, a DMOS (or MOS at low input voltages) power switch can be used. Fig.4 shows a simple DMOS switch and driver stage, used in the L4970 from SGS-Thompson. DM1, DM2, and DM3 are 60V DMOS transistors,

Vin

CeOOT 02

Vsw

FIG. 4 OMOS OUTPUT STAGE

while Ql is a low voltage high beta NPN. To maintain high speed 0M2 and 02 have to be large. Also, it needs a static tum-on signal via Ml, M2 and OM3, that drains the bootstrap capacitor. The circuit provides O.SA peak gate charge/discharge currents, yielding SOnsec output commutation time ([4]). A different high-side OMOS driver is shown in Fig S .

.-----+--------------, BTS Va

M17

FIG. 5 FLOATING GATE DRIVER SCHEMATIC

DMOS GATE

271

It includes a flip flop in the floating driver (MI, M2, MlO, Mll), eliminating the need for a static tum-on signal. The tum-off signal remains static, to increase noise immunity, but MI7 makes sure that there is no static current drain when the output DMOS transistor is off. The rest of the circuit is essentially a BiCMOS power inverter, that is designed and sized carefully to ensure zero shoot through current across the QD2-QD4 gate driver stage. All the devices used are low voltage

devices, except the DMOS I and DMOS2 small signal level-shift transistors. The driver provides up to I.SA peak drive current to the DMOS gate, yielding IOnsec output transition times. The total tum-off delay of the circuit is 3Snsec from the "off' logic signal to the DMOS gate, while rise and fall-times on the power DMOS gate are 20nsec. This fast speed enables the circuit to operate up to IMHz efficiently ([5]).

272

Fig. 6 shows the output transitions of a buck converter using the output driver shown in Fig.5 driving an on-chip 120mOhm DMOS transistor.

INDUCTOR CURRENT

SOURCE VOLTAGE

O.SA I DIV

20V I DIV

FIG. 6 Output wave forms ofthe BiCDMOS buck converter with fast recovery diode.

2.2 Current limit/current sense circuitry.

The current limit circuits in most modem switching regulators limit the switch's peak current, cycle by cycle. In buck regulators this is closely related to the regulator's output current, so the current limit protects both the switch and the load. Fig.7 shows a typical bipolar current limit circuit, based on the one used in the LM2576 family ([6]). As long as neither Q 1 nor Q2 saturates, the collector current of Q2 mirrors the collector current of Ql, i.e. the switch current, scaled down by their emitter area ratio:

V(Rl) = Isw.(411000).Rl /3/

This voltage is compared by the current limit reference voltage, dropped on R2, by the comparator, formed by Q3 - Q8.

273

V(R2) = Ilset*2*R2 = Vref'll2*R21R4 141

With that the current limit value is:

leI = Vref'll500*R2/(RhR4) lSI

Both R2 and R4 are realized as base resistors, while RI, being a low value resistor (5.8 Ohm nominally for the 4.SA current limit ofa 3A switch) is best realized as a wide n+ resistor. The room temperature tolerance of the current limit is set primarily by the tolerance ofRI. Because RI is wide (lOu) and the emitter sheet-rho is well controlled, ±IS% room temperature tolerance is achievable without trimming.

V ref

r-------1~----------_--__ Vln

PWM COMP

FIG. 7 BIPOLAR CURRENT LIMIT CIRCUIT

If tighter limit is desired, R4 can be trimmed. The temperature coefficient of the current limit is set by the tempco of RI, which is typically 900pprn/degC. This is acceptable in most cases. If lower tempco is targeted, and R4 is trimmed, first order temperature compensation can be

274

achieved by realizing R2 as an implant resistor, with 2kohm/square sheet­rho. The difference between the tempco of the R2 implant resistor and the R4 base resistor provides a first order compensation ofRl's tempco. The response time of the circuit described is 300nsec, yielding 600-700nsec minimum on-time in current limit.

In case of a MOS or DMOS power switch the sensitivity and speed of the current sense circuitry can be substantially increased by using the Rdson as sense resistor [5]. A circuit utilizing this technique is shown in Fig. 8.

... ........ .. EXT-EiANAL""··: COMPONENTS

CLIMIT OUT TO LOGIC

FIG. 8 CURRENT LIMIT CIRCUIT IN BICOMOS TECHNOLOGY

275

To ensure tight current limit and low tempco, the current limit reference voltage is dropped on a small, 2x pilot device, that is created by using two separated source cells from the main 10,000x power DMOS device .. Dl and D2 are used to decouple the comparator from the DMOS devices' sources during the otT-time. The clamping is set up in such a way that the comparator enables the output (via not shown logic circuits) during the switch's otT-time. At tum-on, the current limit comparator is inactive as long as the DMOS' source does not rise above the emitter voltage of clamp transistor Q2. This feature provides automatic adaptive blanking of the leading edge current spike. It also yields fast operation of the comparator, because it is always kept in its active common mode region. The comparator is realized with two ditTerential amplifier stages followed by a high voltage level shift stage, that is similar to the one shown in Fig. 7 but uses HV PMOS transistors instead ofDBPNP devices. The response time of the current limit comparator circuit of Fig. 8 is 50nsec, yielding a minimum on-time in current limit of about 200nsec. The wave forms shown in Fig.6, illustrate the adaptive blanking capability of this current sense architecture. The D 1 and D2 decoupling diodes can be replaced by active DMOS switches to improve the current limit circuit's response time by 15-20%. The circuit shown does not provide protection against direct short of the DMOS's source to ground. A fail-safe timer is implemented on the chip to augment the current limit circuit ofFig.8.

2.3 Preventing short circuit runaway.

The speed of the current limit circuitry, including the tum-otT delay of the output driver/switch, is very important to prevent runaway in short circuit condition. The minimum on-time of the switch is set by this response time. In short circuit condition the ramp up time of the inductor current is tonmin' while the ramp slope is V inlL. During the otT-time the inductor current ramps down by the approximate slope of V dlL, which is orders of magnitude lower than during on-time. The ramp down time is T -tonmin' approximately T. To prevent runaway condition, the absolute value of the

276

current change during the on~time has to be equal or smaller than the change during the switch's off~time:

In this approximate expression IL denotes the average inductor current during off~time, R is the total DC resistance of the loop (inductor resistance, diode resistance and load resistance), and V d is the forward diode drop at low current. With the current limit and drive circuit shown in Fig. 3 and Fig. 7 tonmin is about 700nsec. The circuit operates at 52kHz (T=19.2usec), V d=O.4V for a Schottky diode, and let's use typical values IL = 2.5A and R=O.20hm. Using /6/ these numbers yield:

Vinmax <= 24.7V /7/

IfVin is higher than 24.7V the short circuit switch current will increase in every cycle, leading to the eventual destruction of the IC. To prevent this from happening, either a faster current limit and driver circuit is needed, or the operating frequency has to be lowered (T increased). The speed of the current limit comparator of Fig 7 could, in principle be increased by a capacitive feed forward around the slow PNP stage (from Q3 emitter to Q6 collector) but this would make the circuit very noise sensitive and would cause it to trigger on the leading edge current spike. The second option, lowering the operating frequency in short circuit condition, can be realized in many different ways. The LM2575 monitors the inverting input of the error amplifier and if it drops below about half of its nominal value (VREF) a comparator drops the oscillator frequency to about 20kHz (see Fig. 1). This frequency assures operation without short circuit runaway up to the maximum rated input voltage of the chip (60V) with adequate margin. SGS~ Thompson chose a different way to implement the same frequency shift ([4]). Every time the current limit is tripped a dead time of 50usec is inserted between tum~off and the next tum~on of the power switch, resulting in about the same 20kHz short circuit frequency.

277

Both methods yield essentially a foldback current limit. The approximate short circuit current is:

It can be significantly lower than half of the Icl peak current limit, at low (but non-zero) output voltages. An improved method is shown in [7] where both the cut-in point for the frequency shift and its slope can be programmed by 2 resistors. Another well-known but somewhat more complex solution is to implement a second level current limit, 20-40% above the normal, cycle by cycle current limit. If this second current limit level is reached by the switch

R2

R4 2

Jl.... CUM

Vsw

FIG. 9 SHORT CIRCUIT FREQUENCY SHIFT CIRCUIT

278

current, i.e. in runaway condition, a frequency downshift (time-out) is initiated ([7], [16]). This method is superior, because the frequency is shifted only in runaway condition. The most sophisticated circuit implementing this method is designed into the CS320 controller, from Cherry Semiconductor ([8]). Their idea is shown in Fig. 9, adapted to the power stage shown in Fig. 7. Transistors Q14-Q22 with R2 and R4/2 form a level shifter with a gain of R4/2*R2. The SIH circuit samples the gained-up voltage on Rl during the current limit's "active" time, i.e. it samples the voltage at the peak of the sawtooth current-sense wave form. Qll and QI2 form an error amplifier, that turns on QI3 if the current-sense voltage's peak is about 20% above the cycle by cycle limit value. Via the collector current of Q 13 the loop servos the oscillator frequency down to just the needed value to keep the peak switch current 20% above the nominal value, at any VinN out combination. This method has not yet been employed in any integrated DCIDC converter.

2.4. Loop-gain stabilization.

The loop-gain of a voltage-mode controlled buck DCIDC converter is directly proportional to the input voltage (Vin). As the input voltage can vary over a wide range, the loop compensation can be difficult. This is especially true for smart power ICs with internal compensation. There are a number of methods to stabilize the loop-gain. They all utilize the possibilities offered by the expression of the control loop-gain for buck regulators ([9]):

G = (Vin *V ref\' out)* AEA/(ST *T) 191

where AEA is the (frequency dependent) gain of the error amplifier, while ST is the slope of the timing wave form of the internal oscillator, that is used to implement the pulse-width modulation. One possibility to stabilize G is to make ST quasi-proportional to Vin' The simplest way to realize this is used in the LM2575 from NSC ([2]).

279

VT

+!N

Vref t---~--T--

FIG. 10 PEAKING OSCILLATOR CIRCUIT

The circuit is based on the fact that in most applications when Yin is high, the duty-cycle is low (D = VoutNin). In the circuit, the triangular oscillator timing wave form is distorted in such a way that its slope is increasing as the duty-cycle gets below 50%. The circuit and wave form are shown in Fig. 10. A single transistor, QI, is used to provide the extra current to make the timing wave form "spiky". The loop gain variation is less that 1:2 for a converter with V out = 5V, in the Yin: 8V to 40V input range. This is not perfect compensation, but quite adequate in practice and uses minimal silicon area. Another alternative is to keep the timing ramp linear but increase its slope by increasing its amplitude as Yin increases. This feed forward idea was first implemented on silicon in the NE5560 controller from Signetics, and first used in a monolithic switcher in the L4970 series les ([4]). The disadvantage of this method is that often it is difficult to change the amplitude of the timing ramp by a factor of 5 - 6. Also, there is usually a significant frequency modulation as a side effect. To alleviate this problem SGS-Thompson in the L4970 used separate ramps for timing and PWM. The first is fixed, while the second varies with

280

Yin. This, of course, means extra silicon area and more external components. A third solution to the problem is to make the error amplifier's gain inversely proportional to Yin (see /9/). This was done in LTC's LTI074 buck converter ([10]), where a single quadrant divider circuit is used between the error amplifier's output and the PWM comparator's input. Unitrode used a fourth method in its recently introduced second source of the LM2575. A simple nonlinear amplifier, realized by a 2 break-point piece-wise linear circuit, is placed between the error amplifier and the PWM comparator. Its incremental gain decreases with decreasing duty­cycle, keeping the loop-gain variation within a narrow range ([17]).

3. DCIDC converters with low-side switch.

A large variety ofDCIDC converters use a low side power switch. Among them are the Boost converters and all the low power isolated single switch converters like the flyback, forward, Cuk, etc. Many of these topologies have a right-haIf-plane zero in their control loop transfer function, if operated in the continuous MMF mode under voltage­mode control. This makes their compensation difficult in the presence of the second order roll-off caused by the equivalent L-C output filter. This is one of the reasons current-mode control was introduced in 1978 ([11], [12]). Under current-mode control the peak switch current rather than the pulse­width is controlled by the error amplifier. The pulse width is controlled only indirectly. One of the advantages ofthis method is, that one of the state variables (the switch or inductor current) is directly controlled. As a consequence, ideally the system would be a first order system with only one state variable. In practice, because peak and not the average current is controlled, the double pole of the L-C filter is split, yielding a single pole roll-off due to the dominant pole. The second pole is usually beyond the crossover frequency, at about 1/3 to 1/6-th of the switching frequency ([12]).

281

Cc

I Rc

FIG 11A. BOOST VOLTAGE REGULATOR

Vsw

Isw-+--------L-------~-=----~------~-=~-. Ip

10 Ip ............. .

lOUT

IL Ip

FIG. 11B BOOST CONVERTER WAVEFORMS

282

Also, as the timing wave form used to generate the PWM function is the inductor current, the slope of which is proportional with the input voltage, the loop-gain is stable over input voltage variations. Current-mode control also enables shared load parallel operation of multiple converters. The main disadvantage of this method is that the current sense signal that it uses for control, varies in a wide range in amplitude as the load of the converter varies. This can limit the dynamic range of the converter, and also makes the system very noise sensitive. A related issue is the presence of the leading-edge spike on the current sense signal. This spike is the result of the reverse recovery charge of the diode, as the switch turns on and the diode turns off (see Fig. I I b). It is a problem for the current limit sense circuits as well, as mentioned in section 2.2, but current-mode controlled converters are especially sensitive to it. If not eliminated from the current sense signal, the spike can prematurely terminate the on-time of the switch, leading to the loss of regulation. Another inconvenience of current-mode control is its inherent instability if operated above 50% duty-cycle. The problem can be solved by adding a constant voltage ramp to the current sense signal ([11], [12]). This essentially creates a transition between voltage and current-mode control, degrading pole splitting but decreasing noise sensitivity. All integrated current-mode DCIDC converters use this so-called compensating ramp to ensure stable operation above 50% duty-cycle. Fig. 11 a shows a boost DCIDC converter with the typical block diagram of a smart power IC with low side power switch. The block diagram is very similar to the one shown in Fig. 1 , except for the differences due to current­mode control. The burst comparator ensures that the converter can operate down to zero load without loss of control, albeit skipping cycles. Fig. 1 1 b shows the relevant wave forms.

3.1. Low-side power switch.

If the power IC is realized in MOS technology, the low-side power switch and driver circuitry does not need special attention.

283

Vin ------.----, SWITCH

C1 ON/OFF

FIG. 12 OUTPUT STAGE WITH SATURATION CONTROL

In the case of a bipolar power transistor however, high efficiency (low V sat) and high speed (no hard saturation) are contradictory goals. The time honored Baker-clamp on the output transistor is often not feasible because high voltage Schottky diodes are usually not available on bipolar processes. Fig. 12 shows a very simple and elegant solution to this problem, first used by Carl Nelson ([13]). In the circuit, used in both the LM2577 and LTI070 families of regulators, one of Q 1 's many emitters is tied back to the base of the Darlington driver transistor, Q2. As QI moves toward saturation, its C-B diode turns on. This turns on the EI-B-C inverted NPN transistor, and diverts some of Q2's base current to Q 1 's collector, effectively keeping Q 1 in soft saturation. A typical saturation voltage of O.6-0.7V can be achieved with this circuit at 3-5A current levels with 5-7mA1sqmil emitter current density, without significant degradation in switching speed. C 1 junction capacitor uses the capacitive current during the tum-off collector transition of Q 1 to increase the pull-down current provided by Q3. The high voltage (base-epi) junction capacitor can be put in Ql 's tub. It improves Ql's dV/dT rating by about 50% in an experimental circuit we built.

284

3.2. Leading edge current spike blanking.

The simplest and most often used way to eliminate the leading edge spike is by a simple R-C lowpass filter. It is most often applied in controllers using external R-C components. In integrated smart power circuits a constant blanking interval after tum-on is used instead, with internal timing elements. The blanking time has to accommodate the worst case (slowest) diode the user might use in an application. This results in over­designed blanking. In current-mode controlled DCIDC converters the blanking time limits the minimum controlled on-time of the switch. So, over-designed blanking can seriously limit the dynamic range (DmaxlDmin) of high frequency current­mode DCIDC converters. A solution for this problem was proposed in [14], using adaptive blanking. It yields the shortest possible minimum on-time for any diode, without the need for external components or adjustment. The block diagram of the circuit is shown in Fig. 13. The circuit's operation is based on the fact that during most of the leading edge spike the diode remains forward biased and the collector voltage of the switch stays high. By the time the collector voltage drops, most of the current spike is over. In the circuit of Fig.13 the switch comparator blanks the current sense amplifier until the collector voltage of Trl power transistor drops below 2V. The rest of the filtering action is accomplished by the speed limitation of the current sense amplifier and PWM comparator. The fail-safe comparator makes sure that Trl is turned off after a given time (set by CI) even if TRI's collector is hard shorted to V in. Fig. 14 shows the circuit realization of the block diagram. Q7 to Q 1 0 form the current sense amplifier. Its gain is set by the R61R5 ratio. It is disabled (blanked) by Q6. The switch comparator is realized by Ql, Q5 and Q6, its threshold is set by Vbe(Q6) and the voltage drop on R3. Q2-Q4 form the fail-safe timer. The signal from the fail-safe timer and the switch comparator are "or"-d on the base of Q5. Q6 is turned off and the current sense amplifier is enabled if either the collector voltage of Trl falls below the threshold, or the voltage on CI reaches the Vfst threshold.

Q

TO CURRENT LIMIT

COMPARATOR

H=OFF L=ON

285

FIG. 13 ADAPTIVE BLANKING BLOCK DIAGRAM

SWITCH COMPARATOR & FAIL SAFE TIMER

CURRENT SENSE AMPLIFIER r---..-....... ---.----.--...... --1~-................. VINTREG

15

CURRENT LIMIT

COMPARATOR

FIG. 14 SCHEMATIC DIAGRAM FOR ADAPTIVE BLANKING

286

The shown adaptive blanking circuit cut the minimum on-time of a bipolar switcher from the original I usec to 550nsec. It made possible a twofold increase of the operating frequency (from 52kHz to 100kHz) with the same dynamic range. The scope photos in Fig.15 show the switch current and voltage wave forms with different diodes in a bipolar boost converter circuit, operating close to its minimum controlled on-time. Notice that the minimum on­time closely tracks the reverse recovery time of the diodes, varying from 460nsec to 580nsec.

FIG. 15 Minimum on-time wave forms for boost regulator a: Schottky diode, IN5818; b: Ultra fast recovery diode, HERIOI c: Fast recovery diode, MR81!

3.2. Parallel operation of multiple converters.

One of the advantages of current-mode control is that multiple DCIDC converters can be operated in parallel with load sharing. This is useful to increase the available power from integrated converters, or can be used to create redundant power supply systems. Traditionally, in parallel systems, one of the DCIDC converters is the master, i.e. its reference and error amplifier controls all parallel converters,

287

FIG. 16 REDUNDANT PARALLEL OPERATION OF 2 BOOST CONVERTERS

M7

EAIN

0--1

Q022 .1---+---£. M9

FIG. 17 ERROR AMPLIFIER FOR PARALLEL OPERATION

288

while the error amplifiers of the slave converters are disabled. The disabling is sometimes done using an extra pin ([8]), or by pulling down the feedback pins of the slave converters, if, like in the case of the LM2577, the design makes this possible ([IS]). In both cases there is no true redundancy, because if the reference or the error amplifier of the master fails, the whole system fails. Fig. 16 shows the block diagram of a "truly" redundant system. To make this system work the error amplifier has to have an asymmetrical output stage (e.g. class A emitter follower). Also, it must be ensured that the switching noise on the output capacitor does not induce switch-over from one error amplifier to the other. Fig.17 shows a BiCMOS error amplifier circuit that can be used in the arrangement of Fig.16 ([5]). The maximum sink current of the output is set by the M9-M8 current mirror. The maximum sourcing capability of the output is limited by the current limit, set by R6 and QLl. It is set to be larger than (N+l)*ID(M9), if N is the maximum number of parallel converters to be used. In our practical realization N was chosen to 5. If the input of the error amplifier (EA IN) is forced above V ref QD5 and QD4 are turned on hard and the RI-R2 divider pulls down the non­inverting input of the amplifier to about 5% below V ret creating a hysteresis. In parallel operation, the system with the highest reference controls all converters. The error amplifiers with lower reference voltages are in negative saturation, presenting a DC load to the output of the only active error amplifier. Meanwhile the non-inverting inputs of the slave error amplifiers are lowered by 5% preventing the noise On the output from turning error amplifiers on and off. If the master amplifier fails, the output voltage of the switching regulator system first drops by about 5%. Subsequently, the error amplifier with the next highest reference takes over automatically as master and restores the output voltage to its normal value.

Parallel operation capability of DCIDC converters is gammg more importance lately with the increasing acceptance of modular power supplies and distributed power systems.

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4. Summary.

The paper reviewed medium voltage industrial integrated switching voltage regulators with high-side and low-side switches. Circuit techniques, used in both lower frequency, cost effective bipolar regulators and in high frequency BiCDMOS switchers were shown and analyzed. Methods and circuits were discussed to address short circuit run-away, leading edge spike blanking, and redundant parallel operation.

References:

[1]. C. Cini, B. Cotta, D. Diazzi: High power monolithic switched-mode power supply. Proceedings of Power con 9, pp. CI-5 1 to 8, 1982.

[2]. J.Scolio: New switching regulator's unique compensation scheme assures design simplicity. PCI Proceedings, October 1988, pp. 101-111.

[3]. T. Szepesi, J Bittner, H. Suzuki: Simple Switchers: a new breed of power+control ICs for DCIDC converter applications. PCI Proceedings, October 1989, pp. 437-449.

[4]. C. Diazzi, G. Gattavari: 80W to 400W Monolithic buck regulators integrated in multipower BCD technology. HFPC Proceedings, May 1988, pp. 212-226

[5]. T. Szepesi: IMHz lOA current-mode DCIDC converter 1991 ISSCC Technical Digest, pp. 274-275.

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[6]. H. Suzuki, H. Takagishi: LM2575 Design Review, February 1987. National Semiconductor Internal Document.

[7]. T. Szepesi, R. Frank, H. Santo: New IMHz off-line PWM controller chip-set for voltage-current-and-charge-mode control. HFPC Proceedings, May 1993, pp. 114-122

[8]. W. Gontowski, H. Neufeld: Advanced new integrated circuit for current-mode control. Proceedings of The Power Electronics Show & Conference San Jose, Ca, October 1986, pp. 341-353

[9]. A. Kislovsky, R. Redl, N. Sokal: Dynamic analysis of switching-mode DCIDC converters. Van Nostrand Reinhold, 1991.

[10]. LTC Data book, 1990. pp. 13-21 to 13-26

[11]. C. Deitsch: Simple switching control method changes power converter into a current source. IEEE PESC'78 Record, pp. 300-306.

[12]. R. D. Middlebrook: Topics in multiple loop regulators and current-mode programming. IEEE PESC '85 Record, pp. 716-732

[13]. M. Yamatake: Personal communication.

[14]. F. DE Stasi, T Szepesi: A monolithic boost converter for telecom applications. IEEE APEC'93 Proceedings, pp. 360-369.

[15]. 1. Bittner, T. Szepesi, Y. Ying: New switching regulator IC comes with a full feature thennally accurate macro model. IEEE APEC'90 Proceedings, pp. 451-459.

[16]. R Mammano: Voltage-mode control revisited - a new high frequency controller features efficient off-line performance. HFPC Proceedings, May 1993, pp. 40-50.

[17]. RA. Neidorff, L. J. Wofford: Computational circuit for transforming an analog input voltage into attenuated output current proportional to a selected transfer function. US patent # 5,130,577

291

High Voltage ICs for Mains Applications

F. Schoofs

Philips Research Laboratories, Eindhoven, The Netherlands

ABSTRACT

Ie processes with a breakdown voltage well above 1000 Volts have become possible. This allows for the use of les in an envi­ronment which was not accessed by ICs up to now. Amongst these new application environments are systems in which the high voltage and currents from the mains are directly converted into the required signals for the load. A number of aspects are dis­cussed which are relevant for the system and Ie designer. The ad­vantages of high-voltage Ie technique are illustrated with a number of application examples.

Introduction

At the moment, a high-voltage Ie process With a breakdown voltage well above 1000V exists. This allows for the use of les which can be directly fed from the mains and thus to the introduction of Ie techniques and complexity in an envi­ronment Where up to now only discrete devices dominated. A system designer is offered an extension to the range of hardware implementation possibilities. First products have proven to be reliable and to be technically and economically feasi­ble and the production of which run into the multi millions. Some aspects be­come more important compared to the standard Ie environment. In many cases the application area will include some form of power conversion, and the circuits implement so-called large-signal functions where high voltage and high current can be present. High could be taken as e.g. > 100 Volts or> 1 Amps for a single transistor. By doing so, a usable classification can be made between four applica­tion categories in which one also can place the various Ie process categories. This article aims at the voltage range> 100 V and at applications with low and high current. The size of conventional power control hardware is significant and 'electronic' power conversion offers an improvement in size, energy efficiency

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R.J. WIll de PlasSCM et al. (eds.), Analog Circuit Design, 293-304. C 1995 K~T Academic PublIsMTs.

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and control. In the relevant power conversion systems, considerable voltage can be present across supply wiring and signals of several Volts are still being called 'noise'. LC filters for energy storage and avoiding interference are still necessary due to required energy efficiency of the system For this reason no translation can be made into integratable electronic analog or digital filters. More complex con­trol can reduce the size of these components. The system designer must be aware of the possibilities and limitations of IC processes. With low-voltage ICs (LVICs) the properties of the devices are well known and can be described with a small set of parameters e.g. with bipolar ICs by the maximum transition frequency and a single breakdown voltage and with CMOS ICs by the feature size. In contrast to that, high-voltage ICs (HVICs)and power ICs (PICs) show a large variety in process approach, available devices and parameters. This depends on the aim of the process which often is intended for a specific application. Common IC technology has it's wiring and current flow on top of the silicon surface. There are also processes where the high currents flow vertically (between bottom and top of the silicon) as occurs in discrete power de­vices and where additional (smart) control electronics is present at the same chip. Such processes are referred to as 'smart discretes' or 'smart power' and aim each at a dedicated function e.g. in automotive electronics. Demands do not always justify the existence of a dedicated process and a general purpose HV IC process can provide IC techniques in many systems. A process which is continuously in production will also be more reliable. By extending the common IC technology to high voltage and power, some considerations are different from those known from low-voltage ICs. A number of aspects relevant for mains-fed high-voltage ICs are described in this article.

System partitioning

Mains terminated ICs will in most situations perform some kind of power con­version function. Examples for this are the conversion of electrical energy de­rived from the mains into chemical energy (rechargeable batteries), light (fluorescent lamps), motion (brushless motors), or to another voltage level (DC power supplies). The application categories cover a wide range of power. Such mains terminated systems include basically three parts (c.f. fig. 1). The HV pow­er output stage provides the relevant voltage and current for the load, the HV cir­cuits provide the control and drive signals for the output transistors and perform signal processing of HV signals. In the LV part a variety of small-signal circuits forms the remaining part of the system and these implement in general the sys­tem control function. Technically, the whole system can be built on a single chip. However, total system cost will limit the design of single chip systems in a number of cases. If the output power becomes too high, then discrete external power transistors are a better choice. Also if a very complex LV circuit part is re­quired, additional LV ICs provide a better solution. Existing VLSI and discrete

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power devices both have their own clear advantages. In short: sufficient HV com­plexity but limited power and limited LV complexity is required for achieving an attractive implementation on a single HV IC. The strength of an HV IC is it's ca­pability of reducing the total amount of components in the HV circuit functions by introducing IC techniques and performance in this environment, and to pro­vide local intelligence which simplifies constraints towards other system parts. In fig.l therefore the primary application target of HV les is indicated. The part of the LV part outside the scope of the HV IC refers to LV electronics of high com­plexity (e.g. a central processing unit) and the remaining part of the power block refers to high-power discrete devices. The modularity of such a system is en­larged since, for various output powers, the appropriate output transistors can be chosen. The LV system part contains all application specific functions. In such a structure, the HV Ie can contain amongst others the locally required start-up and protection provisions which are common to many output stages and provides the interface requirements towards the LV Ie. This system partitioning allows also for the design of non application-specific or generic HV les and thus cheaper systems.

Properties of the mains.

Since the mains is directly used as a voltage supply source for the les, the prop­erties of the mains voltage are relevant. Basically, the power companies specify average (long time) values. For the future a nominal value of 230 Vrms is speci­fied with a tolerance of +/- 5% for all European countries. Other relevant nominal mains voltages are 240 V (GB) and the industrial networks: 277 V (USA) and 340 V (Canada). The impedance of the sinusoidal wave can be considered as be­ing zero and thus a very high amount of energy is available. In practice, also (un­specified) fluctuations of tens of percents may appear during a number of cycles. In addition, also voltage transients up to many kVs can be superimposed on the sinusoidal wave. These transients can be caused by switching off of a heavy load (or blowing a fuse due to a short circuit) and the continuation of this current by the inductive mains wiring. A lot of long term voltage measurements of the tran­sients and their frequency of occurrence have been done for study of EMC be­haviour of equipment, but no consistent model or correlation is available with respect to peak voltage, peak current, impedance and energy content. Reported peak transient voltage may be up to many kilo Volts and the energy content may be up to tens of Joules. Fig.2 shows measured peak voltage amplitudes vs. occur­rence for various conditions. These data are generated by work groups from IEEE and ZVEI (Germany) and the wide lines of fig.2 cover the scattered data points for the several categories. In Europe, the IEC recommendations are usual­ly followed which specify a voltage transient with Vpeak = 1 kV, rise time = l.2 IJ.sec, half-value time = 50 lJ.Sec, series resistance = 5 n and an energy content of 2 Joule. However, when this test signal was defined, only appliances with high

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intrinsic insensitivity with respect to transients did exist. This insensitivity is e.g. caused by large time constants (motors, incandescent lamps, transformers or large electrolithic capacitors. The relevant parameters of mains fluctuations and transients are strongly determined by local conditions and the nature of connect­ed equipment.

Voltage requirements of mains-supplied electronics.

Due to the existence of high-energy voltage transients, electronic systems which are directly supplied from the mains require a voltage limiting configuration be­tween the mains terminal and the electronics. Since in normal operation a limited dissipation is allowed, in general, an energy storage capacitor after the rectifier bridge forms the basic voltage limiting configuration. This also answers part of the requirements with respect to suppression of mains conducted interference. The voltage increase across the storage capacitor due to transients will be much higher in case of miniaturisation, i.e. equipment in a small housing and thus a small storage capacitor, compared to high power equipment where generally a large capacitor and housing are present. The minimum breakdown voltage re­quirement is determined by the maximum sine wave amplitude e.g. 230V*1.41*120% = 390V (Europe) or even 340V*1.41 *120% = 577 V (Cana­da). Dependent on input filter requirements and additional voltage limiting provi­sions and thus additional size and cost of the equipment, the required breakdown voltage of the electronics can be determined. For larger equipment 450 V often appears often to be sufficient. With a moderate value of the storage capacitor and an additional series resistor the voltage might be limited to approx. 700 V for small and low power equipment. If protection must also be provided against tran­sients exceeding I k V, a voltage-clamping device might be required. A device that performs well is the voltage dependent resistor (VDR or varistor) by which the voltage can be limited also to approx. 700 V in-most situations. These VDRs are low cost devices since they are made from compressed and sintered grains. The clamping performance ranges over many decades up to a high current level and the dissipation is distributed over the whole bulk of the device. Introduction of an IC process for direct termination to the rectified mains will open up new ap­plication areas resulting in huge numbers of IC systems connected to the mains. The presence of the energy storage capacitor in front of the systems creates a bad power factor and a high inrush current and occupies considerable volume. For high power systems a preconditioner will then be required which draws a sinu­soidal current from the mains and generates a DC output voltage of about 400 Volts. For low cost and small systems the smallest possible capacitor will be used which leads to higher system voltage. When in the future many appliances with storage capacitors are present at a specific location, they will locally form a dis­tributed voltage clamp for mains transients. This creates a mutual protection and will influence the curves in fig.2.

297

Performance of a high-voltage MOS transistor.

High voltage bipolar transistors require a complex base-drive circuit since the proper amount of base current has to be delivered preferably at a low impedance level for avoiding breakdown limitation to BVCEo' MOS transistors break down at the BVCBo of the intrinsic bipolar structure which is generally much higher than BVCEo and MOSn are thus more easy to design for high voltage. Discrete MOSTs are built as vertical devices with a self-aligned source and backgate (dou­ble diffusion, masked by the gate) and are commonly known as DMOS transis­tors. Vertical devices require an increasing epitaxial thickness for an increasing breakdown voltage, In an IC, the isolation diffusion of the IC and the buried-N drain terminal cause an increasing problem for thicker epi-Iayers and a practical upper limit is typically 250 Volts. The properties of integrated VDMOSTs are equal to discrete transistors. For higher breakdown voltage the so-called lateral DMOSn (LDMOSTs) are ap­plied which are demonstrated with breakdown voltage well above 1000 V (ref.2). In fig.4 a cross section of such an LDMOST is depicted. The LDMOSTs have their electrical field in lateral direction in the drift region of the drain which is de­pleted by the high voltage between P-substrate and N-epi-Iayer. This operation method is known in literature as 'resurf' effect (resurf stands for REduced SUR­face Field, c.f. ref.1), Shown are lateral transistors with two alternative building methods i.e. field plate (LFP) and p-rings (LPR) which both can reduce the elec­trical fields near the source region. The LPR type enables the highest breakdown but has a higher 'on' resistance due to the reduction of the current path. The Ro­son of a high-side operated transistor of a half-bridge circuit will increase due to depletion of the epi-Iayer when the source is high. A very relevant performance parameter of power transistors is the RDSon * Area product which is a function of the breakdown voltage. The high field appears across the lightly doped drift region. When considering a vertical transistor, a breakdown improvement of a factor 2 requires double the depletion width and half the dope level of the drift region. This yields 4 times the Roson for a certain area. With integrated lateral transistors, also double the (lateral) depletion dis­tance is required, but now the same dope level can be used since depletion of the N-drift region is performed by the P-substrate (,resurf'effect). In order to achieve the same RDson double the width of the drift area is required which in total also yields 4 times the area for double the breakdown voltage at the same Roson' In addition to the drift region additional area is required for the drain and source ter­mination and for the transistor border. With high-voltage transistors the drift re­gion forms a dominant part of the RDSon and in practice, both with vertical and lateral devices, the relation RDson*Area:: BV2 still forms a usable rule of thumb. When a higher breakdown voltage is applied, it is clear that a penalty must be paid in terms of chip area and thus cost, but external voltage limiting can be sim­pler and thus cheaper. For miniature hardware systems, higher breakdown volt­age provide the more attractive solution. When comparing the performance of

298

discrete (VOMOST) and IC (LOMOST) transistors, the same area is required for a certain breakdown voltage and 'on' resistance. However, within a voltage range of 100 V to 1000 V this is possible within a single IC process with fixed epitaxial thickness and dope level, whereas with discrete devices for every breakdown a dedicated thickness and dope level is required. This means that within the IC process an optimal transistor for each required breakdown voltage can be layed out by the IC designer. The operation mode of the output transistors in power converters is mainly as a switch. MOS transistors are very fast switches since they are majority carrier de­vices. Reverse conduction of the switch activates the bipolar (backgate/drain- or body-) diode which has a rather slow recovery. In addition, parasitic bipolar tran­sistors can be activated and thus the reverse conduction of the switches must be avoided. The integrated lateral OMOS transistor can be considered as a cascode of a N-channel junction FET (lowly doped drift region together with the sub­strate) and a OMOST with a lower breakdown voltage. The voltage swing at the intermediate node is limited to the pinch-off voltage of the JFET. In this way no 'miller' capacitance is present for voltage above this pinch-off voltage and the LDMOST is advantageous to discrete devices in high-frequency circuits.

Electro-static discharge

During handling of the chip and when it is mounted on a printed-circuit board, discharge of electric charge may damage the IC. This charge is originated by fric­tion between materials which amongst others occurs during the production proc­ess. Commonly specified are the so-called 'machine model' and the 'human body model' which both describe a circuit containing a charged capacitor and a series impedance. The difference is given by the value of the parameters. When these circuits are connected to a device under test (DUT), energy can be supplied to the DUT which then may be damaged. If the OUT is an open or a short circuit, no energy is supplied to the OUT. Low voltage ICs are protected by low-voltage 'zener' type of clamps who approach the short-circuit condition and need to carry the short-circuit current of the ESO signal. For high-voltage transistors, the amount of energy supplied to a transistor is substantially higher than was the case with low voltage. If the open-circuit voltage of the ESO source is higher than the breakdown voltage, breakdown will occur with a higher risk of damage. Ava­lanche breakdown in a sub-surface 'zener' clamp or active turn-on of the transis­tor by a clamp between drain and gate can provide a solution. The lightly doped silicon of a HV process yields a high series impedance by which the voltage can increase beyond the avalanche-breakdown value. Avoiding the problem of exces­sive charge build-up in the production environment provides a better solution both for high- and low-voltage ICs.

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Merging power into a single package.

With low voltage ICs, it has always been the ultimate goal to create a single chip solution. In power conversion systems it may become disadvantageous to collect all silicon within the system on a single chip. The power transistors are generally operated as a switch i.e. dissipation = 12.Roson' The Roson and thus size of the transistor is chosen such that the chip temperature can reach 150 °C under worst case conditions. If now a second transistor in the system with the same dissipa­tion is also put in the same package, each transistor is allowed to dissipate only half the former amount, which means double the area per transistor on the IC compared to the initial situation. If even more dissipating transistors are collected which each occupy already a significant area by themselves, the area of integrat­ed silicon becomes much larger than if separate silicon was used. Since an IC process has twice or more masks than a discrete transistor process, IC price/mm2

is higher and this will lead to an expensive IC solution. In addition, also the yield formula Y :: e(-A.O) shows a disadvantage when one replaces separate silicon by a single large IC. For moderate power, still the single chip IC solution instead of many separate devices can be advantageous. In many systems, the losses must be strongly reduced and, since the Roson doubles with a temperature increase of 100 °C, good thermal properties of the IC packages will thus reduce the required sili­con area. The ambient operating temperature for the Ie can exceed 100 °C in au­tomotive or lighting applications. An exchange can be made between dissipation (smaller chip size) together with a more expensive power Ie package or the re­verse. With high dissipation higher demands are put on a heatsink when the dissi­pation is generated at a single spot. Since a wide range of output powers exist, fully integrated output stages would profit from a wide variety of power IC pack­ages. Voltage and power restrict the use of many existing IC packages. For spe­cific high-volume applications a dedicated package can be cost effective, whereas also a multi-chip package which includes a high-voltage IC and one or more discrete transistors forms an attractive implementation.

Merging power and high-density LV circuits.

Discrete power transistors operate generally at high temperature and high current levels. For avoiding electro-migration (transport of conductor material which leads eventually to open circuit) and current-distribution problems, a very thick layer of aluminium (4-6 Jlm) and thick bonding wires are applied with discrete power devices. Electro-migration increases rapidly with temperature. An LV IC circuit with high packing density requires a double-layer interconnect (thickness 1-2 Jlffi) with a small pitch. Both demands have to be met in a power Ie. The use of thin aluminium for high current is at the expense of additional area and multi­ple bonding. The design of efficient high-voltage transistors requires the use of dedicated process steps. The same is valid for high performance low voltage de­vices. Merging two processes yields a process with a higher mask count and price

300

or will yield a compromise of the device properties when compared to the possi­ble perfonnance of separate processes. When compared to mainstream (V)LSI process and support development, updates of dedicated processes lag behind mainstream (V)LSI process developments.

Design of LV circuits within a power IC.

With large dissipation on chip, the temperature operating range of the LV part has also to be specified up to 150°C, since the power transistors may become that hot. A number of applications for power converters can be found outside the house e.g. electronic ballasts for fluorescent lamps, electronic motor drives and automotive. This extends the operation range of the ICs also to temperatures far below zero. The extended operating temperature range of the LV IC part, possi­bly with a thennal gradient across the chip is at the expense of additional or more complex circuits and chip area. Due to the good thennal coupling, temperature sensing and protection of the power transistor can be implemented rather accu­rately.

Design of LV circuits within a high voltage IC.

A large part of the chip will be occupied by HV circuits and output transistors, but still a significant part will be fonned by the LV part. The supply of this LV part is relatively expensive if such a voltage is not yet available in the system. In many cases the LV supply is derived directly from the mains. The total current consumption of the LV circuit part thus has to be very low, e.g. 1 rnA. Derived from 300 V in a simple manner, this would yield already a dissipation of 300 m W but from 5 V supplies it would mean only 5 m W. Due to the required low current levels, the design of LV circuitry in such a high voltage environment becomes therefore often real low power electronics. The low bias current and high imped­ance levels cause extra sensitivity with respect to crosstalk on the chip. If one as­sumes a capacitance of 1 pF at a certain circuit node, then a parasitic capacitive coupling of 10 iF to a switching signal of 500 V at the same chip or nearby exter­nal component already generates 5V at that circuit node. A slew rate of 500V / 50nsec is also very common, and the same 10 iF will then generate a current of 100 J.lA. The high operating temperature range and the noisy circuit environment suggest the use of digital circuits. However, the systems involved basically con­trol an analog parameter such as charging current, DC supply voltage or power to a lamp and accurate analog measurement and control circuitry is then required. Circuit design and layout or special process features have to provide the neces­sary on-chip compatibility. Sometimes a low-voltage circuit is required which operates at a high voltage with respect to the substrate. A common circuit in HVICs is e.g. a gate-driver circuit for an upper power transistor of a bridge configuration. The output (the source)

301

and thus this driver swings with high slew rate between the supply voltage rails. This driver circuit is built with low-voltage transistors located in a single island which has a high breakdown voltage to ground. By this construction, no direct parasitic capacitance from wiring of intermediate circuit nodes to ground exists in which unacceptable capacitive currents would be generated. Such a single is­land contains normally at least LV-CMOS; in some processes (ref. 2 and 4) also a much larger choice of components is available for the design of these high-side circuit4t. A multi-layer structure in these islands provides also adequate shielding of the devices for interfering signals.

Output stage topologies.

The most simple HV output stage consists of a source-low NMOS transistor with open drain. Many processes provide just this HV device which fits in the applica­tion area of fly-back converters. These converters are applied in the lower power switched mode power supplies (SMPS). The loading of the drain with a trans­former adds to the supply voltage an additional amount of (fly-back) voltage at the drain. Conversion efficiency increases with a high fly-back voltage and thus a high drain voltage. Another common topology is the so-called half bridge. This consist4t of two transistors which are connected in series between the supply rail and deliver a square wave signal at the intermediate node. Two or three of those half-bridges yield the well known full-bridge and three-phase bridge. The bridge topology generally has to provide significant current and therefore, both output transistors are NMOSTs. For the higher voltage, in ICs, an LDMOST is com­monly used. As can be seen from figA no wrap around N-diffusion is present. This is due to the application of the 'resurf' effect by which thin epitaxial layers can be applied with HV transistors. Since the load shows generally an inductive behaviour, the current through each transistor will flow in both directions. When switched on, the transistor is operated strongly in its linear region and shows a re­sistive behaviour. When the current flows from source to drain, in parallel the so­called backgate diode becomes conductive. The P-backgate as emitter with the N-epi-Iayer as the base form an efficient parasitic vertical PNP together with the P-substrate. For the high-side transistor this means that almost all load current can flow from the positive to the negative supply rail (via the parasitic PNP) and a very high dissipation will occur. In integrated circuits there exists another para­sitic device at the low-side transistor. The N-epi-Iayer together with the P-sub­strate forms the emitter-base junction of a parasitic lateral NPN. Collectors are formed by other N-islands at the same chip. If this is an island which is tied to a positive supply (e.g. the high-side output transistor) also unacceptable dissipation may occur. If electrons are collected in other islands (e.g. of a bandgap reference circuit or a comparator) the circuit behaviour might heavily be affected. It is ob;­vious that this parasitic action must be avoided. The most effective way to elimi­nate the parasitic transistor action is the application of a process with

302

dielectrically isolated devices. A Si02 layer surrounds the devices and avoids the existence of parasitic junctions. In the lower cost junction-isolated processes, the reverse conduction of the output transistors can be avoided by connecting an NPN (diode) in series with the high-side drain and a PNP (diode) in series with the low-side drain. Both devices can be built with a wrap around N-tub. On-chip fly-back diodes are relatively slow and have parasitic transistor action by them­selves. Discrete external diodes provide the flyback- or reverse-conduction. A half-bridge circuit with integrated switches and series diodes in a junction-isolat­ed process and external fly-back diodes is depicted in fig. 3.

Application of high voltage IC technology.

In the above text a number of aspects are indicated which may influence the par­titioning of the system i.e. the combination or distribution of the various func­tions over one or more ICs or discrete devices within the system. With the increasing need to implement more complex circuits at the mains side of a sys­tem, HVICs contribute in the same manner as LVICs in LV systems. They reduce the number of components and provide the required complexity or reduction in size at acceptable cost. Research on high voltage IC technology started with the invention of the 'resurf' principle on which npw most high-voltage IC processes are based and up to the realisation of very high breakdown voltage (ref.2), has re­sulted in a DMOST process family running in production which is called BCD­PowerLogic and ranges from 70V to 750V. First HV ICs were created for non­mains application and include a range of video CRT driving amplifiers and large­signal telephone-set ICs. At the moment a number of HVICs do exist which show that single chip high voltage ICs also form an attractive solution for mains appli­cations. Examples are found in battery chargers, electronic ballasts and motor drive ICs. The attractive implementation possibilities exist amongst others due to process BCD-PowerLogic-750, which incOlporates an extensive range of HV components i.e.: NMOSTs and PMOSTs both with and without source and drain high and low capabilities, LIGBTs, vertical DMOST N-type and P-type junction PETs, floating HV tub for LV circuits, HV wiring and all these devices in LV as well, complementary bipolar transistors (isolated from the substrate), resistors, capacitors. This wide variety of components allows for a high degree of integra­tion and answers a diversity of circuit requirements which sometimes are quite bizarre in an HV environment and can be made with only 13masks (ref.2). An­other HV process called BCDPowerLogic-650 contains HV LDMOSTs and UG­BTs and LV CMOS and bipolar transistors. This process answers amongst others the requirements of electronic ballasts where limited HV diversity is required (ref.3). Ref A describes a 700V bridge driver IC which is intended for driving both power transistors of a half bridge without the use of coupling transformers, and interfaces to a dedicated LV control part. Applications are e.g. electronic bal­lasts and electronically commutated motors. The IC features separated grounds

303

for the power part and the LV control part such that large ground bounce voltage can be accommodated (as is the case with transfonners), integrated bootstrap di­ode, and adaptive control for non-overlap drive of the output transistors. Such a bridge driver IC includes the generic function for many dedicated HV ICs with a higher degree of integration. Ref.4 describes an IC for a NiCd battery charger. The system features accurate battery charging (0.1 A) from car batteries, up to 0.1/1.2A from world-wide mains voltage and is the first IC for universal mains application where production runs in multi millions per year for already some years. The two decades wide operating voltage range of the IC could be achieved economically by applying HV IC techniques. Ref.6 describes a motor control IC which accurately stabilises the rotational speed of small motors over the world­wide mains and mechanical load range. Departing from the rectified and filtered mains supply, the component count has been reduced from 19 components (i.e. LVIC, HV power transistor, fly-back diode, electrolythic capacitor, 15 small R's and C's) to 6 components (i.e. HVIC, flyback diode and 4 small R's and C). The external components independently set the nominal motor speed and static and dynamic load response. This improvement is due to the application of HV PMOSTs which transfer high-side measured signals to ground. Mains applica­tions for lighting mclude electronic ballasts for compact and large fluorescent lamps based on a half-bridge topology with a high-precision VCO, and a smart TL starter. This starter can replace existing two-tenninal starters and avoids con­tinuously flickering of the fluorescent tube lamps at the end of their life. As a re­sult of this, no direct service for a single lamp is required nor early replacement of all lamps.

References:

[I] J.A. Appels and H.MJ. Vaes, 'High voltage thin layer devices (Resurf devic­es)" IEOM technical digest, 1979, pp.238-241. [2] A.W. Ludikhuize, "A versatile 770/1200V IC process for analog and switch­ing applications". IEEE Trans. on Electron Devices, Vol. ED-38, no.7, pp.1582-1589, July 1991. [3] "LOMOS and LIGBT's in CMOS Technology for Power integrated Circuits" S. Mukherjee, M. Amato, I. Wacyk and V. Rumennik. IEOMTech. Digest, 1987, pp.778-781. [4] F.A.C.M. Schoofs and C.M.G. Dupont, 'A 700V interface IC for power bridge circuits'. IEEE Journal of Solid State Circuits, Vol. JSSC-25, no.3, pp.677-683, June 1990. [5] F.A.C.M. Schoofs and J.C. Halberstadt, "A high-voltage IC for a battery charger". Proceedings of the ESSCIRC'93, Sept.22-24 1993, Sevilla, Spain.pp.278-28I. [6] RJ. Fronen and J .A.M. Plagge, 'A HV control IC for small motors'. Proceed­ings of the ESSCIRC'93, Sept. 22-241993, Sevilla, Spain, pp.274-277.

304

Low Voltage High Voltage High Voltage

circuits circuits Power

Application target of HV ICs i 1.a.---------------- ------------~

Fig. 1 Partitioning of· otT-line systems

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DMOS TRANSISTORS IN SMART POWER BUILDING BLOCKS

B. Graindourze

Alcatel Mietec, Brussels, Belgium

In this paper, it is demonstrated that a DMOS macromodel, built with standard available MOS models, allows accurate simulation for normal working conditions. The strategy for extracting parameters and supporting the macromodel is presented.

1. INTRODUCTION

Control system interfaces can be viewed in many ways. Traditionally, smart power approaches have been limited to comparatively low level control circuits, due to the severe problems of interaction between high power switching devices and sensitive analog circuits. Alcatel Mietec's approach to smart power is to concentrate rather on the integration of more sophisticated analog and digital controVinterface systems, with high voltage capability to provide protection against aggressive external environments - an approach we have chosen to call Smart Interface. DMOS transistors are frequently used in Smart Interface building blocks. To predict the performance of these blocks, accurate simulations of DMOS transistors are required. No standard available compact model for a DMOS exists. Applications of DMOS transistors are studied to define the normal working region of the DMOS. A macromodel is presented together with a parameter extraction procedure; it is shown that measurements and simulations match well in that region. Tools to increase the design efficiency for Smart Interface circuit design are introduced in the last section.

30S R.J. van de Plassche etal. (eds.). Analog Circuit Design, 30S-319. C 1995 Kluwer Academic Publishers.

306

2. DMOS TRANSISTORS IN A BICMOS TECHNOLOGY

To implement control system interfaces using the Smart Interface approach a BICMOS technology has been developed. This technology (ref. 1 , ref.2) offers a wide variety of devices: precision resistors and capacitors, CMOS transistors, bipolar NPN and PNP transistors and both NDMOS and PDMOS devices. It is not a CMOS process with added bipolar, nor is it a bipolar process with added CMOS. As opposed to normal bipolar processes, it consists of a P-type epitaxial layer (i.o. N-type) based on a P-type substrate. This allows for N-well CMOS processing, which results in electrical compatibility of the CMOS part with present standard CMOS processes. The PMOS and the bipolar transistors are made in two different deep N diffusions: this is done in order to combine the best features of both. The N-well bulk influences CMOS parameters like mobility and body-factor and is therefore optimized. An N-type buried layer assures latch-up resistivity of the CMOS part, and provides for low collector resistance of the bipolar NPN . The bipolar devices need another kind of substrate, where breakdown voltage and Early voltage are primary constraints. Therefore a dedicated N-tub is used which contacts the N-buried layer. The free epi thickness is adjusted to ensure a BVceo of 40V. A less critical deep diffusion is the N-plug, this is used to optimize the on-resistance of the NPN device.

The DMOS devices are lateral, non-self-aligned, junction isolated structures (see fig. 1). These devices do not require additional layers; in the NDMOS, the P-base layer forms the substrate of the device. The PDMOS drain drift region is formed by the lightly doped P-epi layer.

p-epi J-----......

p-sub

Fig. I : Cross section of the DMOS devices

307

The key features of the devices produced in the basic technology are listed in table 1.

Table 1: Typical electrical characteristics of the basic technology

MOS transistors NMOS PMOS Bipolar transistors

NPN PNP

8@ 1J.1A 100 300 Vtlin 1.20 V -1.20 V @ 100J.1A 100 >40 81in (W IL=25J.1/25J.1) 3OJ.1AIV2 12JlA1V2 @lmA 100 Body factor y 0.35 VI/2 -1.00 Vl/2 BVceo@ Ic=lJ.1A >40 V >40 V

BVces@ Ic=lJ.lA >80 V >80 V Collector resistance

DMOS transistors NDMOS PDMOS minimal device 1200n 250n with NPLUG sink 200n

Vtlin 7.20 V -1.20 V Early Voltage -250 V 90V Breakdown Voltage >85 V >85 V Transition Frequency 600 MHz 7 MHz

The CMOS transistors can support supply voltages as high as 18V. Moreover, a total linearity for the NMOS output characteristics is achieved up to 11 V, which makes the process suitable for a wide range of analog applications. A vertical NPN and a lateral PNP are available. Both NPN and PNP offer a BVceo larger than 40V and a BVces larger than 80V. The Early voltage of the NPN is typical -250V, again meeting analog circuit requirements.

A breakdown voltage larger than 85V is achieved for the PDMOS. The NDMOS transistor sustains the same voltage and offers a typical on resistance of 2 Ohmemm2. Neither structure is connected to the substrate by any terminal; these fully floating devices allow flexible use in all kinds of circuits.

3. APPLICATIONS OF DMOS TRANSISTORS

Some applications will be discussed to illustrate the key parameters of the DMOS transistors.

a) High voltage digital cells Logic circuitry with a supply voltage higher than 18V cannot be implemented with MOS transistors in this technology; DMOS transistors, however, can operate at supply voltages up to 85V, provided that the voltage difference between gate and source is limited to 22V or less.

308

In the circuit of fig.2, the digital input signal with 15V supply is shifted upwards to drive the PDMOS output transistor (M7); OV at the input is shifted to VDD-VZEN+VT(M3), while 15V is shifted to VDD, which is equal to 80V. Transistors Ml, M2 are NDMOS devices; VDS can be close to 70V while VGS is limited to 15V maximum. PDMOS devices M3, M4 set the low level of OUT to about 11 V under VDD. For M5 and M6 PDMOS devices are chosen. The threshold level is determined by VT and Beta of Ml, M2 versus MS,M6.

---------r-------------r----------------~~--------~~-----VDD

B~sl

Fig.2: High voltage level shifter

b) High voltage switch The PDMOS transistor M7 of fig.2 acts as a high voltage switch. Important specifications besides breakdown voltage are VT, BETA and series resistance, since they determine the on-resistance and the required area.

c) High voltage current source In the circuit of fig.3 the voltage at node OUT is controlled by node IN. Currents up to 5 mA must be sourced for output voltages up to (VDD -IV). For the output transistor an NPN is chosen since it minimizes the area. The base current of this NPN is generated via a PDMOS current source. If a PNP was used, it wO\1ld require protection circuitry to prevent saturation of this transistor and the area would be larger.

309

--~--------~----------~~--VDD

I~ OUT

Fig.3: DMOS transistor as high voltage current source

d) Operational amplifiers For operational amplifiers (fig.4), the PDMOS transistors replace PNPs where the supply voltage prohibits the use of PMOS transistors. Precautions are taken to limit the voltage between gate and source. Compared to the PNP, the PDMOS transistor offers several advantages: the high frequency behavior is better, there is no extra delay due to saturation and there is also no base current. Important characteristics of the PDMOS transistors are IDS and gds for a vas a few hundredths of millivolts above VT, noise, matching and capacitances.

1----0 OUT

Fig.4: Operational amplifier: simplified schematic

310

4. SIMULATION MODEL OF DMOS TRANSISTORS

To predict the performance of circuits containing DMOS transistors, accurate simulation models and reliable worst case parameter sets are required. Since no compact DMOS model is available in commercial simulators and parameter extraction software, there are two alternatives: 1. Develop a DMOS model and parameter extraction routines; generate

documentation and support users; 2. Create a macromodel, containing only standard models; develop

parameter extraction strategy based on existing routines; document limitations of macromodel.

To limit the risks, required manpower, development time, and support effort we have chosen the macromodel approach. To develop the parameter extraction procedure, there are again two alternatives: 1. Extract parameters that are fairly good for all bias conditions and

dimensions; 2. Extract parameters that are accurate in normal working conditions and

poor in seldom used conditions.

Since the first approach produced poor results for MOS transistors, we did not evaluate this for DMOS transistors, and took alternative 2.

a) DCmodel The macromodel for an NDMOS transistor (ref.3) contains transistor MD to model the channel part in the P-base and transistor MP to model the channel part in the NTUB. The resistor RDS stands for the NTUB region under the thick oxide, and RSIM was added to improve DC convergence (see fig.S).

drain

RDS

MP gate _______ ....--1

RSIM

source

Fig.S: NOMOS macromodel

After evaluating circuit applications, the normal working conditions were defined: 1) Analog applications

IDS vs VDS: VDS: 0 V VGS: 7V

2) Switching applications IDS vs VDS: VDS:

VGS: IDS vs VGS: VDS:

VGS:

OV OV 0.1 V OV

80V 12V

2V 22V

22V

The need for accurate simulations in these regions determined the choice of a model for the transistors MD and MP, and the definition of the parameter extraction procedure. Since the macromodel is not a physical model for the DMOS, there is a trend to optimize the parameters for the devices on the test inserts. To detennine reliable worst case parameters valid for a large range of dimensions, we avoided optimization to a large extent. Parameters of MD were extracted analogous to MOS parameters, keeping in mind the physics behind them; fine tuning was achieved by optimizing the parameters of MP and RDS on a few batches and fixing them to a typical value. Parameters of MD are extracted on a regular basis to build up a statistical database and derive worst case models.

311

312

Typical measurement and simulation curves for NOMOS and PDMOS are shown in fig.6 (ref A ) and fig.7 (ref.S). For the NOMOS, the temperature effects, causing a negative gds (ref.6) and for the PDMOS, the transition from linear to saturation region, limit the accuracy of the model for higber gate-source voltages.

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313

b) ACmodel Components were added to the macromodel where needed, to model the capacitances. For the NOMOS (fig.8) a vertical NPN-transistor was added to model the junction capacitances between NTUB and P-substrate and between NTUB and P-base (ref.7).

Fig.8: Model for NDMOS

c) Temperature model The temperature dependency of the VTH of the PDMOS is simulated accurately with the Berkeley level=2 model for MD; but for the NDMOS, the simulations deviate strongly from measurements (fig.9). An enhancement to the level=2 model is required to solve this (ref.8 and 9).

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25 50 75 tOO 125 UO

'amp.,atur.

Fig.9: The threshold voltage of the NDMOS as function of temperature

314

d) Noise model The PDMOS is used quite often to replace PNP transistors as the input pair in operational amplifiers; therefore the noise is an important parameter for this device. The noise model can be seen in fig.lO.

source

iD~

iP ~

iR ~

drain

Fig.tO: PDMOS equivalent circuit with added noise sources

Several PDMOS transistors with different channel widths were measured. The equivalent gate voltage spectral density was measured in the frequency range from 10 Hz to tOO kHz for different gate voltages. One curve is given in fig.tl.

I ;

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I,

t 0

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I S I

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1 2 / I

I I

Z lQ- iS Ii.-____ ...!-____ -..J..1 _____ .l....-____ _

111,'3

Frt'lcuQ;'1cy Hz

Fig.II: Measured noise curve of PDMOS

The thennal noise could not be measured due to the background noise of the measurement set up. The lIf noise is voltage-independent for low gate voltages where the noise is only determined by the noise in MD. For larger gate voltages the equivalent gate voltage noise increases due to the noise in MP. In ref. 1 0 the noise fonnulas were derived and the parameters KF and AF of the level=2 models for MD and MP were calculated out of the measurements. The simulated lIf noise is compared with measurements for different gate voltages in fig.12.

315

316

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~ ~ I .OCE·14

., ~ I

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0 .1 10

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Fig.12: Simulated and measured equivalent input noise of PDMOS (0 is simulated;. is measured)

5. DESIGN OF SMART INTERFACE BUILDING BLOCKS

The wide choice of components offers many opportunities to the designer for implementing various functions in an economic way. The increased complexity however could cause a higher risk that something may go wrong; therefore extra tools were introduced.

a) Extra device error checking To improve the design efficiency, extra checks are included early in the design cycle to flag: - Improper use of the technology

e.g.: - A component dimension smaller than allowed by the layout rules

- Voltage over a component higher than allowed by the electrical rules

- Improper use of the simulation models e.g.: - A model that is used outside the region where it is valid

- Improper use of a component e.g.: - A bipolar transistor that saturates

Without these checks, violations of these rules would only be detected after layout or, even worse, after prototyping. Now these checks are incorporated in the analog simulator and violation of a rule is flagged on the schematic after simulation. Flags of all checks are default visible and the parameters for the various checks are included in the model files (ref. I 1, 12). The checks are divided into two classes. The fIrSt class includes all the types of checks to flag conditions that are not allowed for the chosen technology. These checks are called technology-checks. The model checks, on the other hand, flag that the model is used in conditions for which the accuracy is not verified. Flags of the second class are less severe and the designer can neglect a flag if that specific flag is not important for his application.

The flags can be set to be invisible by class or type. Examples of these checks are given in table 2.

Table 2: Examples of extra device checks

For all MOS-transistors (code=MOO9) Check on VDS: VDS ~ VGS + VDMINM and

VDS<VDMAXM if VGS ~ VTH - 0.3 and IDS ~ 0.1J.LA for VDMINM and VDMAXM see model file

To flag: use of the model outside its accurate area; gds not accurate

For all MOS-transistors (code=T01I) Check on VGS: abs (VGS) S VGSMAXT

for VGSMAXT see model file To flag: voltage between gate and source too high Note: this check is meant for MOS transistors

of the DMOS macromodel, where maximum allowed VGS, VGB and VGD may differ

For all Bipolar transistors (code=T020) Check on IC: IC S ICMAXT

for ICMAXT see model file To flag: collector current too high

317

318

b) Electro-thermal simulator and design rules Electro-thermal interaction can create unwanted effects when power devices are integrated together with complex digital and high performance analog circuits on the same chip. Inappropriate design and/or layout can cause major problems concerning the maximum temperature and temperature gradients between components. An accurate prediction of this behavior is required to design circuits with electrothermal coupling in a more efficient way. Therefore, a project was set up together with the ESAT-MICAS department of the K.U.Leuven, research was funded by I.W.O.N.L. Brussels under contract BR-074, to develop an electro-thermal simulator and to derive design rules (ref.13). The simulation results and predictions based on the design rules were verified with measurements. The design rules allow the designer to estimate the maximum temperature and temperature gradients on chip with simple hand calculations. Therefore thermal effects can be taken into account in an early phase in the design, even before any simulation takes place.

c) Layout of standard devices library To minimize the risk of unexpected parasitic devices reducing the performance and to limit the required characterization work, only a limited number of layouts are supported for use in circuits. For bipolar devices, a library of standard transistors is installed; each structure is fully checked for DRC errors and for each of them a SPICE model file is available. For MOS and DMOS devices, stretchable cells and SPICE model files are available for each type of transistor. Designers are strongly advised to use only these layouts.

CONCLUSIONS:

The macromodel and the parameter extraction procedure presented here allow accurate simulations of DMOS transistors in Smart Interface building blocks. The macromodel is built with standard, available MOS models and is therefore supported in commercial simulators. Tools to flag improper use of the DMOS transistor or its model are presented.

319

ACKNOWLEDGMENTS:

The author would like to thank Johan Ysebaert, Luc Vanden Bossche and Ronald Van Langevelde (student at T.U. Eindhoven) for their valuable contributions to the presented work; he would also like to thank Hennan Casier, Alun Foster, Jan Krikor, Geert Vandensande and Henri Vanderhenst for the discussions on applications of DMOS transistors.

REFERENCES:

(1) Witters, J.S., A modular BICMOS technology including 85V DMOS devices for analog/digital ASIC applications, Microelectronic Engineering, 19 (1992),555-560

(2) Graindourze, B., Mixed analog/digital in a mixed bipolar/CMOS technology, SMT/ASIC/Hybrid, 1990, Inter. Conf., 241-250

(3) Rodgers, T.J. et Al., An experimental and theoretical analysis of double-diffused MOS transistors, IEEE JSSCC, vol.SC-lO, no 5, Oct. 1975

(4) Ysebaert, J., DMOS modeling: NDMOS, Internal Alcatel Mietec report, Nov. 1993

(5) Ysebaert J., DMOS modeling: PDMOS, Internal Alcatel Mietec report, Oct. 1993 .

(6) Sharma, D. et Al., Negative dynamic resistance in MOS devices, IEEE JSSCC, vol.SC-13, no 3, June 1978

(7) Van Langevelde R., AC-parameters for DMOS transistors, Internal Alcatel Mietec report, Nov. 1993

(8) Van Langevelde, R., Temperature dependency of DMOS­Characteristics, Internal Alcatel Mietec report, Nov. 1993

(9) Precise Reference manual version 4.0, p.lII-84, Electrical Engineering Software

(10) Van Langevelde, R., Noise in DMOS transistors, Internal Alcatel Mietec report, Feb. 1994

(11) Graindourze, B., Release of extra checks and parameters in MADE, Internal Alcatel Mietec report, Oct. 1992

(12) Graindourze, B., Update extra checks in MADE, Internal Alcatel Mietec report, June. 1993

(13) Van Petegem, W. et Al., Electro-thennal simulation and design of Integrated Circuits, to be published in JSSCC

SUMMARY

Design Methodologies for Mixed Power Integrated Circuits

Bruno Murari SGS-THOMSON Microelectronics

Comaredo (Milano), Italy

ABSTRACT

Advances in mixed power IC technology make it possible to produce integrated circuits of VLSI complexity that combine CMOS, DMOS and bipolar elements. As a result new design methodologies are necessary. In this paper we describe the new technology trends and present an example of how an experi­mental circuit of this type has been designed.

INTRODUCTION

Power IC technology and complex logic technology travelled along sepa­rate paths until the mid eighties, when the invention of mixed bipolar-CMOS­DMOS technology brought the two together for the fIrst time.

Previously power ICs had been produced with pure bipolar technology, which does not lend itself to high complexity circuits because bipolar logic is not very dense, and because bipolar power transistors dissipate large amounts of power, limiting the amount of" installed" power that can be put in a package. BCD solved both of these problems. Integrating CMOS logic, it allows very complex digital and analog signal circuits to be integrated in a small area; and since DMOS power transistors dissipate veIY little power it is possible to house complex power stages in compact plastic packages.

Initially BCD technology was used to design simple ICs like H bridge motor drivers, having a single power stage and modest complexity. By 1988, however, designers began to take advantage of the high complexity achiev­able with this technology to produce circuits with multiple power stages and hundreds or thousands of gates.

321

RJ. van de Plassche etal. (eds.), Analog Circuit DeSign, 321-324. C 1995 Kluwer Academic Publishers.

322

FUNCTION-ORIENTED BASIC TECHNOLOGIES

t_

SYSTEM ICDIII ORIENTED

TECHNOLOGIES ICDII)

~ ICD(II)

ICDM

t_-------------------------------.~t-

Figure 1. In parallel with the evolution of single-junction technologies like CMOS there is also a trend towards increasingly versatile mixed technologies, which are changing the way mixed les are designed

Another important step forward came in 1993 when the convergence between power and signal technologies was completed with the development ofa third generation BCD technology. In addition to shrinking the lithogra­phy, this version brought the "c" in BCD into alignment with the mainstream CMOS processes used for memories and logic. As a result it became possible to use existing CMOS cell libraries, and even macrocells like microcomput­ers. At this point a radically new approach becomes feasible: modular technologies (figure 1). Rather than develop separately optimized technolo­gies for different applications, we can create a family of standardized process steps that can be combined to produce any kind of mixed technology. This, however, creates new problems for the circuit designer.

A NEW APPROACH TO DESIGN

Traditional power IC design methods are inadequate for mixed power ICs ofVLSI complexity. Designers must face new challenges, borrowing tech­niques from VLSI design and tackling the crucial problem of interaction between power and signal sections systematically. Other methods taken from

323

VLSI include new testing strategies and the use of development systems for application design.

A technology demonstrator IC developed in 199213 was used to experi­ment design methodologies for this new generation of complex mixed power ICs and to drive the development if software tools to mechanize the process. This IC, test pattern H081 (figure 2), consists of a DMOS power stage originally designed following second generation BCD rules, and an ST6 8-bit microcontroller in CMOS logic technology.

The goal of this work was to develop a methodology that allowed us to retain existing cell designs while minimizing the need for manual interven­tion. The method also had to be fast and dependable. In addition, because power ICs operate in a more hostile environment it would also be necessary to add extra layers to make the final IC more robust.

Figure 3 illustrates the basic design flow chart for the H081. One of the most critical steps, the CMOS to BCD layout conversion, occurs at the beginning of the process. Completely automatic conversion is the only practical solution for design on an industrial scale, though this is far from trivial. In fact it is not just a question of shrinking or enlarging linear dimensions, but all rules of the target technology must be respected and alternatives have to be realized where the solutions of the source design are not feasible because equivalent layers are not present in the two processes.

DRIVER &

INTERFACE FUNCTIONS

-STS- CHARGE PUMP

8-BIT

MCU THERMAL PROTECTION

H-BRiDGE

DMOS

POWER

STAGE

Figure 2. With technol­ogy available today it is posable to integrate an 8-bit mlcrocontro/ler on a BCD power IC. A teatcir­cult produced in 1993 combined an "ST6" core with a 3A DMOS power atage.

324

SCHEMATIC UPDATING

CIRCUIT VALIDATION

BACK ANNOTATION &

PARASITIC EXTRACTION

Figure 3. Thanks to software tools the de­sign of very complex mixed ICs is largely mechanized. CMOS macrocells, including microcomputers, are converted using these tools to adapt them to the "BCD" technology that acts as a frame­work, binding every­thing together.

Special software called LACE was developed by Rubicon to perform this conversion.

After this step we have the schematics with the correct components, but without valid values corresponding to the parameters. The next operation is therefore to derive the new correct sizes of the components from the con­verted layout and put these in the new schematic, a process called back annotation. This, too, was performed by a specially written procedure. The result of the back annotation process is reliable, except in cases where a component is realized by combining several gates in parallel.

After back annotation we obtain a schematic with the correct w/l values, ready for the validation phase, which is carried out with standard software tools. Only small adjustments are necessary after this phase -- mainly to maintain timing relations. Finally, once the validated blocks are available they are placed and routed automatically using existing layout tools. With the HOSt this procedure, though experimental,has yielded excellent results, confirming that complex CMOS cells can be combined with power elements and other cells with minimal intervention.

Slide Supplement

LOW-POWER LOW-VOLTAGE LIMITATIONS

AND PROSPECTS IN ANALOG DESIGN

Eric A. Vittoz CSEM

Swiss Center for Electronics and Microtechnology Maladiere 71

2007, NeuchAtel, Switzerland

Copies of transparencies

I INTRODUCTION I

• Low-power

• Till 1990: limited to niche products (watches, hearing aids, pacemakers ... )

• Recently: drastic change due to - need for portability (computer, telecom) - cost of power supplies - heat dissipation - limited power from network.

• Low-voltage

• Imposed by process or by system. • For reducing power of digital circuits. • Little influence on power of analog.

• Fundamental limits and practical limitations. • Existing and new techniques for LP analog. • Prospects.

325

R. J. vall de Plassche et aI. (eds. J. Analog Circult Design. 325-400. C 1995 Kluwer Academic Publishers.

326

I MIN. POWER FOR ANALOG PROCESSING I V+

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t P minlf (per pole in bandwidth) 10-12

• Very steep 10-15 V

• P= Pmin~ 10-18 SIN [dB] Vpp

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• Weak dependence on SIN.

• Process-dependent through Etr.

jMINIMUM POWER FOR VOLTAGEAMPLlF.1

I VB I, l in

VI ' Vo : RMS values VB, I : DC values.

ctive device VI equ. input noise resist. RN

• Signal-to-noise ratio: SIN .. ~ 4kTRNt.f

• Noise resistance: RN .. .1-.. :1-1 ...L. .. &...L. gm 9m P 9m

thus: • Power P so 41 ~ ~ kT. t.f.S/N

If the the active device is a bipolar transistor, then 119m .. UT and 1" 1/2, which gives:

I VB UT I P .. 2 VI Vi kT.t.f.S/N

Now, VB > 2/2 VI Av (Av" voltage gain), thus

Ip> 4/2 ~Av .kT.t.f.S/N I and, assuming Vimax "' UT//2

I P > SkT. Av·t.f·S/N I Similar results with source degener. and MOS.

I PRACTICAL POWER LIMITATIONS I • Parasitic capacitors,

- more power to achieve BW - if III-placed: do not reduce noise - if only small SIN required: 100 large.

• Current-inefficient amplifiers. • limitations on peak-Io-peak amplitude

- amplify as early as possible - avoid hlgh-Q circuits (excepl with L) - current mode not good approach.

• Additional noise sources - l/f noise - on-chip generated noise - power supply noise.

• Poor gmll of MOS transistors (strong inv.) - more current for C imposed by

parasitlcs extemalload.

• Need for precision -larger dimensions

larger parasitic capacitors. • Clock power in SC circuits.

327

328

I TRANSISTOR MODEL I 10 .. IF -IR = IS [f (VS,VG) - f (VO,VG) J

difference of forward (IF) and rav.ra. (IR) currents

'" trong inversion: f i! (Vi~:)l s ~o Jf(V,VGi ift9 I Vs Vo

vr/ moderate inversion

/ weak Inversion: f;o exp ( ¥ ) ... ~.~.?. .. ... . . .. . .. . . . I V T

V - VG-VTO P= n

.Slopefactor n=1+ J = 1+ J 2J2+F+Vp 1 2J2+F+VS

weak inversion 'Y. substrate modulation factor +F- Fermi voltage

• Specific current IS" 2n IlCox~ UT2 ~

13 • Approximation from low to high currents:

f(V, VG) == In2{ 1 + exp*} I MOS TRANSISTOR: MODES OF OPERATION I

equipotential channel (~o-O)

I WEAK INVERSION I

+ Similar to bipolar transistors + Minimum VOSsat (3 to 5Ur) + Maximum g""lo:

1 we!~,1nv_ets!o!, !,!y~ ~ot.

1 milD ",strong Inversion asymptota

nUr ',,~

10 °0.LO-1 --0-.-1 --.L---1~0--1-0-0-1s

(Inversion coefficient)

Thus: + min. RN for given 10 + max. voltage gain + min. input offset - max. noise current for given 10 - max. 10 mismatch.

- Low speed.

I LOW-VOLTAGE LIMITATIONS I • Poor precision of MOS current sources

~ bipolars.

• Low speed of MOS transistors (fr<f.LVP2 ) ~ bipolars. 21tL

• Analog switches on· conduct.

In 1+ Vanr9; ~B o·+--.:.....--o!L..,~-1.;.....

gap for VB < VBmin

~ on-chip clock voltage multiplier.

• No stacks of transistors ~ low-voltage cascodes

V4s~;}_ Vbias for V1=V01sat thus: V2min = 2Vp (strong inv.) V2min = 8 to 10Ur (weak inv.)

~i __________ ~~_ 1NIoMC0-' .....

329

330

I CLOCKAMPLITUDE MULTIPLICATION I

to n-channel ~h switches

unloaded amplitude: (n+1)(VB-VJ)

VB

---"-----"'-'-- 0 (p-substrate)

voltage

VB _ _ _ _ _ ell o --"--'----time

~: - lateral in polySi - diode connected *

p-ch. transistors = in separate wells: .... _-

I COMPACT CASCODE IN WEAK INVERSION I [R.Schober 1993 "self-cascod."1

~2 + I If T 2 saturated. small signal analysis yields r the output conductance:

-J-J I V 90 = (9ds1 + 9md1) 9ds2 T. 9ms2+9md1

(gmdl : drain transconductance dloldVo of non-sat. transistor TIl

The weak inversion model yields:

9ms2 = I/Ur. /32 VTQ1"VT02 and 9md1 = I/(FUr) with F= i31e n1h

Definin9 9ds1 = I N E1 • 9ds2 = I NE2

9ives finally: 9 = _1_ 1 + FUrNE1 o VE2 1+F

Now if W 1 is minimum to obtain narrow channel effect and W2"W1. then Vr01 >Vr02 and F,,1.

For F» VE1 /Ur "* 90 = _1_ Ur = 9ds29ds1 VE2 VE1 9ms2

(normal cascode mode)

~,-------------~~~ IVI-MCO-,",."

I LIMITATIONS IN OPAMPS I real feedback

with:

b. Integrated white noise at output

2 _ T df _ kTRN V No - 4kTRN 0 111 A + ~12 - ~'tu ~ndep. of 'tp I)

now: 'tu= CL/9ml thus

gain In bandwidth noise factor "(,

• Independent of current Ii Indep.of current

• Decreased by larger CL : limitation by T s'

I CMOS- iNVERTER AMPLIFIERS I -r------,--v+

---'--v· 2-phase operation: amplifying (shown)

Features: biasing (opposite)

+ intrinsically class AB (no slew rate limit.) + good power efficiency + max. DC gain (more by cascode)

+ mm~x'Rgm I for given current + In N + min r=gmRN + good low-f PSRR + no offset + elimination of 11f noise + choice of ground level - systematic output step.

~,-------------~~­~, .... ,.

331

332

I SYSTEM CONSIDERATIONS I for low-power analog

• Power management • voltage not critically related to power

- voltage multiplication • switch-off power when not needed.

• RF receiver front-end architecture • for f high: P II 8kTfS/N due to

parasitiC capacitors • min.num. active devices at carrier frequ.

- direct conversion - subharmonic mixer - passive SAW filters

• limit duty cycle (pagers, GPS).

• Digital proceSSing when large SIN needed.

• Minimize requirements on SIN (p .. SIN) • distinguish SIN from dynamic range

- automatic gain control (distortions) - automatic range selection - analog floating point technique.

I ANALOG FLOATING POINT TECHNIQUE I IBlumenkrantz,'993)

• Goal: dynamic range II SIN • Input signal x(t) multiplied by K, to keep

x'.Kx inside range min-max. • Processed signal y'(x') redivided by K. • State vector I update -+ no distortion

- z+ =z' K+/K at each change of range - between sampling instants - or: in time shorter than T mi.,l2.

state vector I

(out)

K state update

range K controller

example for 2 ranges: x

I PROSPECTS IN LP ANALOG DESIGN I • Signal processing : P dlg<P analog for large SIN

(typical limit: 60dB). • Advantage of digital reinforced by

- scale-down processes - reduced voltage.

Thus: • Digital proc. for tasks aiming at restitution

(after storage, transmlsion) • Power reduction in analog Interfaces:

- adequate SIN requirements - further improvements ~ limits (AID, D/A: 16blts audio -+ 100J,l.W)

- helped by improved processes.

• Signal processing: Panalog<Pdig for low SIN (typical limit: 4OdB)

Thus: • Analog proc. for tasks aiming at perception

(vision, audition, olfaction ... ) - massively parallel collective processing - large number of continuous signals - precision not needed, noise useful - exploitation of all device features.

bn

333

334

•

Paul R. Gray, U.C. Berkeley

Design Considerations for High­Speed, Low-Power CMOS AID

Converters

• Introduction: Technology and Architecture Considerations • Design of Low-Power Pipeline AID Converters • Comparison with Ahematlve Approaches • Possible Future Trends and Barriers

AACD-IIItI4. PAO BLIDE 1

High vs. low Integration level in AID Interface Systems

AACD-1994. PRG SLIDE 3

Key Problems in ADC Implementations

• Must be compatible with high-Integration solutions, quasi-digital technology

• Drive to lower supplies complicates all aspects of design

• ADC Performance can be optimized for system application

• Drive toward digital solutions tends to Increase ADC performance requirements

AACD·19R4. PRa SLIDE"

Example Applications for High-Speed CMOSADCs

• Wireless LAN Data Channel (1-50MS/s, 6-10b) • Magnetic Storage Read Channel(50-200MS/s,6-8b) • ADSL data channel (3-10MS/sec, l2-l6b) • Digital Multi-standard TV Baseband ADC(20MS/sec, 8-l0b) • Digital Video Camera ADC(20MS/sec, 8-l2b) • CATV Decoder Modem ADC(10-20MS/s,8-l0b)A • HDTV, various apps, (50-75MS/s, lOb) • Digital-IF for Multi-standard Broadcast TV rcvr(100-200Mb/sec,8-l2b)

AACD.t99-1, PAG SLIDE 5

335

336

Where does Power go in a High Speed ADC?

• Precision comparators

• Resistor string

• op amps, etc.

I<ey Aspm:ts of Arehitecture Selection:

• Minimum Number of precision comparators

• No R-string

• low power op amp

=>Promising Approach: Power-Optimized Pipeline ._-------._--------

AACO-t994. PRG SLIDE 7

,----------------------~------------

Two-step Flash ADCs

Coarse result Advantages:

• Much less hardware than flash Disadvantages:

• No gain in path- requires precision comparators • Requires at least three full clocks • Usually requires R-string • Exponential hardware growth with resolution

.. _-----_._---._---_._._--------------------j AACO·1994, PRO SLIDE 9

Quantized Feedforward ADCs

Advantages: Disadvantage: • Same throughput as flash • Much less hardware than

AACD·IIHM. PRO SLIDE 10

• Requires fast Interstage processing

Design of Low-Power Pipeline ADCs

• Some Basic Pipeline Concepts • Low-Power Interstage Gain Blocks • Dynamic Comparator Implementation • Bootstrapped Clock Driver Design • Capacitor Size Optimization • Experimental Results

"ACD·18I14. PRO SLIDE 12

337

338

Pipelilled ADC Stage-Typical CMOS Implementation

:t~+ +. 0 v~ _ ~-;~-------------t----~~~ + Vo

Comps \.~.L...,

k bits 100

o

Reference Level Generator

Cs I-.! IC, .......

~ Re': c. Conroy. VLSH12

AACD·ll1!14. PRG SLIDE 13

Typical Implementation: Capacitive DAC

VOUT

Code ~ ACC usually R-string flash or Cap-based flash.

AACD.Ut94, PRG SLIDE 14

Power Minirnization in Switched­Capacitor Gain Blocks

First consider simplest amplifiers:

Folded Cascade

AACD·1D94. PRO SLIDE fS

Unfolded Cascade (Telescopic)

I(ey Issue: What is the fastest attainable settling?

s~~~_ ri1rr-C1+Cp=Cu

Thla I •• alngle-Ilme-canllant clrcultl

Device Width and Drain Current

AACD-1994, PRG SLIDE 16

339

340

Max Attainable Speed, Cont'd What Is the best achievable speed as a functon of technology and charge

gain?

't min -

0.5ns -

0.2ns 0.1ns

-

1 [. CLI ] "min' 2Kfi 1 + (:pi

1 "min· 2iti;11 + (Aql I Where Aq = Cherge Gain of circuit

( Auumptlanl: 1. Squ ... 1_ opplleo 2. Noolowlng :so V .... Vt • O.5Y 4 ......... .u •• cond order _vic. "'.ctl.

0.8u1.0u 1.5u 3u

-----------------------_._---'

I

"ACD-I994. PRO SUDE 17

What is the Minimum Obtainable Power?

Minimize:'t!ci ~ Cgs(Opt) = [ Cs + C:~~L 1

Result:

2 CL 't = .--.. (1 + ... ) = 2't 2KfT \,oF min

AACD-IIMI4. PRO SLIDE II

Observations: • Optimum Cgs is equal to Cequiv

• Power is very sensitive to charge gain- use low gainl stage in pipelines • Power drops rapidly with technology line width • Analysis says pwr goes as square of speed, channel length, but actually it is more like linear because of Slew Rate, Velocity Saturation.

LeI!. Desired kTIC nol8e lor Power, nma C. c, C, Microns Cons .. 1161sb, Vswlng=1V Vdd=3V

O.B 400ps BbilS,6OOuVRMS IOf!'I'P ~n' 5f!' 72uW

0.8 400", IOhils, 1 50u VRMS 160pF HOpI' 8(~'F LlanW --

0.8 4flOJ" (2hits, J7uVRMS 2.SpF 1.25pP 1.2~pl' 18mW

0.8 400p. 16hiIS.9uVRMS 40pP 20pF 20pP 200lllW

~------------------------------------.---------AACO-199J1. PRG SLIDE 19

More Practical Amplifier Configurations

Design Issues with Fe, Telescopic: • Poor voltage gain-settling time trade-off • Poor voltage swing-settling time trade-off • Barely usable at 3V, not usable at 1.5V

Alternative Approaches: • Add broadband input stage to telescopic • Two-stage Miller compensated w/one stage cascaded

• Multi-stage Nested Miller amplifier

AACD-1994. PRO SLIDE 20

341

342

,---------------------------~--~-------.--------~

Telescopic Amplifier with Gain Boost Stage

Galn·Booot, AmpUII", I ......... ,

Vcid ail.3V

;I--~BI •• 1

AACO·'88ot. PAG SUOE 21

t. = 17n5(0.1%) C5=0.39pF Cf= 0.39pF CI= 1.8pF Pd=4.1mW Vdd=3.3V Av>60dB Swing = +l1Volt pop

Dynamic Comparators in Pipeline ADCs

Conventional Comparator Design:

dout

Broadband, ~ffset preamp

Key Goal: • Get rid of preamp with It's power dissipation, use dynamic latch as comparator

Key Question: • How much comparator offset can be tolerated?

AACD·1H4. PRG SLIDE 22

Vln

Effect of AOC Nonlinearity Errors

2-bit example: Case 1: Ideal AOC, OAC

Residual Vr 00 01 10

~ Residual -Vr

11

2 bits Positive Oeclslo Level Error

Key Point: Can remove AOC Errors by Increasing AOC range In nexl slg

AACO-I99 •• PRO SLIDE 24

Digital Correction in Pipelines

n1+n2-1 bits out

• Reduce Gain 10 Increase Conversion Range

• Correction Logic is Simple

.Comparators: Need additionsl, but they are much simpler

Final Result: OAC Linearity and amplifier gain errors ullhnalely 1111111 linearity

AACO-1994. PRG$LlDE 21

343

344

+1

o

-1

Vout

Important Case: 1.5 bit/Stage with Digital Correction

00 01 10

.2-bit

• 22_2 = 2 camps

• G = 22- 1= 2

reI.: C. Conroy, VLSI92, JU8uIICCAD90, Lee VLSI93, Jeapero ESSCIRC91

AACO·'994. PRO SLIDE 26

Dynamic Comparator Implementation latch/reset latch/reset

If w1 = M x w2, V decision = Vref J M

o Well defined built-in Vdec'.'on based on ratio

o Simple design for low input cap.

o No DC power!

AACO·1994. PAG suoe 28

Low Voltage Switched-Capacitor Gain Blocks

AACD-I994. PRGSLIDE 21

Low-Voltage Options for .MOS Transmission Gates

Conductance va. Voltage· (Vthn .. IVlhpl = O.8Y)

0: L><:==Ld~5V OND Vdd .v... -v ...

GND I=: ... ~ Vdd.3.3V I I/Gapl

GND b.....£vdd.,.SV

AACD· tOlI4. PRO SLIDE 30

345

346

Low-Voltage Transmission Gates, cont'd

"raw. I'

Possible Good (+) I Bad (-) solutions

Dual Vth process + standard design approach (OVth Native dev) - need process mod

Low Vth Process + Needed for digital anyway - Big cost In power due to limited swing to rail

Global charge pump - possible cross-talk to sensitive nodes - difficult to predict CL

Local charge pump + no cross-talk (can isolate sensitive nodes) + easy to predict CL

AACD·t994. PAG SLIDE 31

High-Voltage Clock Generator

C2 'hi = C +-c-+c- ---- ·2Vd,

2 L parasitic

• Only NMOS switch needed

• Less parasitic cap.

---------------------------_/ AACO·199<t, PRG SLiOE 32

OptiinUITI Scaling of Pipeline Stages for Power Dissipation

Power

N bit ADC. 8 bilslslage ex) N=10. 8=1

Vln

Vln

lObI! With Scaling Bbll

1"""---, ~TAGE -1-1 STAGE 41

AACD·1994. PRG SLIDe 33

Optimization result:

-, ~ <_~ Unsealed

Speed Limned (Due to parasitic capacitance)

~

'/.' I "r-i Senled!

• Approx. 40 - 50% reduction in slatic power consumptlonl

• Minimum performance degradation

• Requires auto-calibration to correct cap mismatches for front stages

Siage

--------- --- -- -- -- --- ----------------------AACO·1gg,l, PRG SLIDE 3"

347

348

. -.--..

Experhnentally Observed Power vs. Sampling Rate

• Master bias current adjusted for each sample rate

30

20

15

10

5

3

Power(mW)

Fs (MS/s)

---------.---.---AACO-I984. PRG SLiOE 31

SNDR versus Input Level 3.3V Supply, 25C

SNDR (dB)

60 ,-

55

50

• ..~~,~ .. #

45 \ ,/7 ~ 1~~~~

~~-"

35 ,'"

30 ~ /'" 1 0 Hz Inp t 25 -??' --:-~I------~------~------~----~ ·40 ·30 ·20 ·10 0

Input level (dB)

AACD-18114. PRO SUD£ 3'

Measurement Results

ADC Performance: 3.3V @ 25°C

Technology 1.2-l1m CMOS Resolution 10 b

Conversion Rate 20 MSls Active Area 3.2 x 3.3 mm<

Differential Input Range +1-1 V

Input Capacitance 1 pF (single-ended)

Power Dissipation 35 mW· at 20MSls (2.8 mW· at 1MSls)

DNUINL 0.5/0.6 LSB

SNDR 59.1 dB (F1n=100 kHz) 55.0 dB (Fin: 10 MHz)

AACO-'9U4. PRG SUDE 39

Power/fs vs. Technology Powerlfs

(mW/MSls)

100

10

0.1

·-'- .. -4. 190J ~ [91J A 192}

I!.. [92) n [94)

--+-\'I-+---ll--I-----t----..,II-+~ 1/Lblm) 111m 0.811m

AACD·'GG4. PRG SUDE 40

349

350

Comparison of Pwr in Pipelines, Sigma-Delta Converters

Typical Sigma-Delta Front End:

Vin+ ® Vdae- ='-Ih Vdac+ = ,..--11-/ -:::L. ~ To second and later stages

Vln-

In-band kT/C:

Conclusion: For each 2x increase in OSR, • Cs can be 2x smaller • Sample rate is 2x higher • Power remains constant for constant in-band noise

One-bit increase in SNR costs 4X in cap value, power

AACD-1994. PRG SLIDE 48

(.;omparisoll 01 HIIIJ tol' ::;igma LJelta, Pipelilles

Modul Output _tor Out Mod. Author Type Samp. SR Reoolull Techn PSV Pwr FM3

Rale on

1. Dedic, 61h 3.25M 200K 14b 1.2uC 5V 40mW 7.8e·16 200mWI ISSCC94 ord. MOS MS/.ee

2. Alex- 4th 12M 192K 14b(lIm luBIC 5V 150( •• 350e-16 ander. ord. by MOS I) ISSCC94 xtalk)

3. Rllo- 41h 2.5M 44K 16b 1.2uB 5V 100m 5.5e-16 2.3mWI neime, ord. ICMO W kSJaac ISSCC94 5

4. Ray, 41h IBM 584K 13b luCM 5V 25mW 6.6e-16 43mWI pc ord. OS MSJaec

5.Mat •. , 2nd 6M 380K 9b O.5uC tv 1.5mW 3ge-16 5mWI ISSCC94 ord. MOS MSJsec

5. Tcho pipe 20M 20M lOb 1.2uC 3V 35mW 15e-16 1.7mWI MOS MS/a.c

FM3. ----"'-f 228 5

AACD-1994, PRG SLIDE 49

Typical Power Performance Levels, Recently Published ADCs

Power,

mW/MS/sec

1000

100

10 4

..........•. j(J, ....... ~ .. ~ ... ""

10 12 14 16

Ellectlve Resolution, bits

AACD-I994. PRG SLIDE 50

Key Issues in High-Speed ADCs Going Forward

Where do we get another major power increment? • Class B op amps? • Charge-domain operation?

How do we get to 1.5 volts at reasonable power?

• Nested Miller op amps? • More coarse/fine sampling?

How do we solve the Digital supply noise problem? • More effective on-board sub-regulation? • Better CAD tools for simulation? • Process/package enhancements?

How do we push sample rates t0200-300 Mhz in CMOS?

• More parallelism plus self-cal? • Better analysis of MOS samplelhold?

AACD-1994. PRG SLIDE 52

351

352

Micro-Power Analog-Filter Design

Gert Groenewold Philips Semiconductors, Sunnyvale, CA, USA

Bert Monna Delft University of Technonogy,

Dept. Electrrcal Engineering Electronics Research Lab,

Delft, The Netherlands

Bram Nauta Philips Research lab, Eindhoven, The Netherlands

Scalin

0'7~ I ...-....... ...,..,........,--.....-,'""''"1

0.6 O.S ----. 0.4 ", 0.3 , 0.2 " 0.1 --_ O~~~~~~~MW

0.1 I 10 rrequency

unsealed

0.8 0.6 0.4 0.2

0.1 I &equency

scaled by maxima

10

O.S r-"'-f"T'~"-"'-rT"1"""" 0.4 0.3 0.2 0.1

0.1 I rrequency

scaled by area

10

Noise Estimate

C = Total Capacitance

C·=Q I n

noise = nlcT C

total noise = n~T

2 n2lcT Vnolse,out = (-c

v.2 - CRV.2 slgnal,out - nolse,out

r3gna, = VSigna"out(wC)2

";I~gnal VCR (n21cTCw p = \'suP " = \'suP f/

how small can C be made?

2 1v, Vampi = 2Vslgnal,out = 2" sup

353

354

Power estimate:

p = 2,f2CR(.n2 kTw.Q '1

Floating ttansconductor Integrators:

vaup~ bias out ,out

in<>- ---<>in

biaso- 2

VSUP""T.' bias~t; O~:o- .-c::t

"'-OJ' biaso--J/l

vauPR biaso- -out=-~ -oout in~";;;.)-o in

biaso-~

Yaup ""-.r-.J­biasc>-o~ol" Ol,lt<>-;t-L,,~,-o,?ut

tU:::'l~.rr'I"" In

biaso--t-j

Non-floating transconductot integrators: no bias noise.

bias in

bias

355

Performance in a fifth-order Butterworth filter:

• Dynamic range: 9BdB, can be extended to 104dB.

• Noise factor: O.9dB.

• Power: 10mW against an estimated minimum of O.6mW.

Performance In a second-order notch filter:

• Dynamic range: BOdB.

• Q=33

• Noise factor: O.4SdB

• Supply voltage: 3V.

• Power: l.SmW; estimated minimum: O.34mW.

Performance In a elgth-order bandpass filter:

• Dynamic range: 75dB.

• Q = 14

• Noise factor: O.7dB.

• Supply voltage: 3V.

• Power: 1.1mW; estimated minimum: O.2SmW.

356

Some don'ts: (for low power)

• Do not use gyrators or transconductors, especially not floating

ones.

• Do not use current mirrors or Gilbert gain cells in the signal path.

Some do's: (for low power)

• Use Opamp-MOSFET-C integrators

• with rail-to-rall class-AS outputs and

• in most cases a bipolar input stage.

Conclusions:

• There is a fundamental power minimum.

• To approach this minimum, low-noise rail-to-rail Integrators

must be used.

• Noise factors below IdS are realizable.

• There is no direct power or supply-voltage advantage in current

mode.

Low Power Oversampled AID Converters

Evert DIJKSTRA Olivier NYS Enrique BLUMENKRANTZ

CSEM, Swiss Centre for Electronics and Microtechnology

Maladiere 71, CH-2007 Neuchatel, Switzerland _In Analog Circuli Dellgn. Mardi 1994

Introduction (1)

- systems are increasingly battery operated ex,: seismic or shock detection

environmental control metering systems pOI'table telecom hearing aids

.. ,

- Nb. of battel'ies and battery life-time is big issue -> low voltage and low power design

- Trend towards more digital systems is also justified from consumption point of view

_c .. n Analog ClrcuI1 Design. Mardi 1994

357

358

Introduction (2) [Vltloz, ISCAS ) 990]

~1I1 + 1911111

f 10~

19141111 + 1971141 8 ..

19111101 1910(51

.. 191' III _ .. ----_ .... --> only valid if power consumption of data converters is reasonable

......... _.. 1912161 1914171 IPM (I pI) +. ~ ____ .. ____ -

..• t •••• -.·.···.·.· ••••••• 10-10

+ ... aIol

10-12 0 dipw

.0

Theoretical limit

- determined by thermal noise - depends on the Impedances Rln and Rref - SNR In terms of power:

Vinmax2

• min. power Pmln for full scale DC Input:

Pmin Vin~ax2 + v;e/; Rm re

- min. If Vlnmax=Vdd=Vref Pmin=32·k· T·SNR· BW

Dynamic r.nac in dB

10 100

...

_In Analog CIR:uII Do""". Man:h 1894 ...

Practical limits

For hia:h resolutions (>16 bits):

- power consumption proportional to Pmin, but 3 to 4 orders of magnitude higher

- power consumption is determined by thermal noise - proportionality is due to:

- addition of other white noise sources (switches, thermal noise factor of amplifiers)

- non rail to rail swing of the amplifiers - settling requirements or the amplifiers (S-R, OW) - bias circuitry - PSRR requirements

Advo .... lln Anlleg CIrculi Design, March 1994

Practical limits

For medium resolutions (10-16 bits):

- Power consumption is not determined by thermal noise -> criteria rulOlled by too high (unpractical) Input Impedance

- Power consumption is proportional to: - The Nb. or elemenlary operations per conversion - The energy consumed per elemenlary operation

-The number of elementary operations is determined by: - The cOllvenlon algorithm - The ovenampllng ratio - The use or electrical compensation tecbnlques employing more pbases

_In Anoleg CIr ... DuIgn, Ma"", 1994 ...

359

360

Why Qyersampline ? For hia=h resolution switched cap AID:

a). frequency-capacitor exchange

=> An increase in oversampling rate allows proportional reduction in Cin

For medium resolution switched cap AIDi b). small elementary cap's due to

- robustness to parasitic effects - modest matching requirements

_ In _1og0ln:ull DeoIgn. _ '1184

power Supply Requirements

Digital Decimation Filter: - minimize dynamic power consumption (Low VDD-dlg)

-> at 1.5 V and with suitable architectures the power consumption Is < 20 % of the total.

Analog circuitry: - theoreUcalllmlt Is Independent of supply

- In practical situations, the lower the beHer (e.g. 2V)

- OTA's are the most demanding blocks In terms of power consumption (appr. 4x the power consumption of a comparator)

Switches: - needs at least one Vt + few hundred mV above supply (e.g. 3V)

C>Ern _1n~CI_Dellgn,_ 11184 ....

Fully Differential Intel:ration Stal:e

AdvanCH In Analog Circuli Design, March 1994

Analol: floatinl: point Basic Idea:

distinguish dearly dynamic range and SNR (-> sleep power consumption reduction)

absolule accuracy can often be relalled In Ihe less sensitive ranges

EJanuzk:

Chpllenee:

f1V

100 dB ynamlc rangea d SNR

10 IlV "classical approach"

1V

1 mV

100 IlV

60dB SNR

20 dB pre-amp

10 IlV 20 dB pre-amp

"analog floating point"

""16

how 10 Iml,lemenluulomotic range swllchlng "llhoul oulput signal perturbations

~ _COl it Anllog CIrculi Detlgn, March 1994

N°n

361

362

Analoa: tloatina: point L-A converters

COMB lN1

IIR filter filtering

m+1 th order

fOMB) liter

lN2

'4------tAutomalic Gain Control

If N 1 > N2 => fast low resolution estimate of applicable gain

_ ...... In Analog Circuli Design. Ma.eII 1994

Example System: - BW= 10kHz - dynamic fange = 84 dB - SNR = 72 dB - oversampllng rate = 32x

Architecture: - 3 rd order modulator (2+1) - 4 th order COMB 'liter - 2 Wave Digital Filters

Electrical performance: _ VOD = 0.8 .. 1.4 V (Vdlg= 1.5 V; Vswltch = 2.8 V; Vana = 2.1V) - P< 1 mW

.. "

Advancolln Anolog Cifcult 0NIgn. Me"'" 1894 ....

Conclusions

1. Despite huge efforts on architectural and circuit level the power consumption remains several orders of magnitude above the theoretical limit

2. Oversampled converters are Inherently power efficient for high resolutions

3. The analog floating point AID converters are expected to bring radical power consumption reductions

_ .... In Analog ClraAt DoIIgn, _ 11194

N'"

363

364

1Il== Analog polyphase filters in highly integrated receivers

M.Steyaert. J.Crols

Goal: To reach a high degree of integration in the design of RF-receivers

t

AACO_IO.I994 =========== EMT-MICAS;;:;::::::;

Receiver design 1Il== • A typical receiver topology consist out of two parts:

- tbe downconversion p8l1 :

- the demodulaUon part:

dOWIICOnVel"sioll and/illering

data recovery

100 11Hz Downconvlfllan 10 MHz Dtomodulalian 76kHz

cos(ru,I ·Hp(1)) COS(UI,t + 91(1)) 91(1)

DSP

I

AA(.'O ..... h30.I!194 =========== ESAT-MiCAS ;;:;::::::;

IF receivers: mirror frequency IW==

t j o If

III 10

lo-If 10+lf

IIr sln[w...II.t).sln[w...t) = 111 (cos[(lIlIo.I ... !lIto).t)+cos[(!lIto~,+!lIto).t)}

= 1/1(cos[-IIlI'.I)+cos[o>.t .... II.I)} = 1I1~+cos[o>.t.I .. II.t])

sln[IIlIo.II.t).sln[Woo.t) = 1/1{cos[(!lIto ..... !lIto).t)+cos[(WOO.II+WOO).I]) = 1I1~+cos[o>.t.Io.II.I))

5

AACD M.ll:h 30, 1!194 :::::::::::::::::::::::::::::::::= ESAT·MICAS =:::

IF receiver: mirror frequency IW== e jwt + e-jwt

iE- '+r t+!l 1'I1' o joo

H (jw) = II'" aw)

+ +

+

mlr.nlt If-nit 0 If-filt mlr.fiIt joo

AAW_30.I994 ::::::====::====;;;:;: ESAT-MICAS =:::

365

366

Zero-IF: the solution?

jOOl e =

+

jOOl e

+ + +

o JOO AACD M ..... lO. 1m :::::::::::::::::::::::::::::::::: ESAT·MlCAS ;;::;:;:;

Low-IF receiver: polyphase filters

+

Complex Filter jOOl

e

+ + +

JOO

MCDMImllO.lm :::::::::::::::::::::::::::::::::: ESAT·MICAS ;;::;:;:;

Polyphase and complex signals

• A polyphase signal is a vector of signals

u(t) = (u/(t),Uz(/), ... ,un(r))

• Complex signals = 2-phase signals U(/)=u,.(t)+ ju/(t)

Its positive and negative frequency components must not be adjoint V(jro) = U,(jro) + jU/(jro)

e.g. :

~------------~~ H(jw)=Hr(jw)+jH l(jw) y.Ct)

L--- !-.

AACD 101_30. 1994

Active complex filters

Blok dlllOrlllll. : A .econd order comple. bancIp ••• Oller

(complex and real nolaUon)

to

Yr(t)

~ AAmMaR:hJO,I994 ==========;::: ESAT-MICAS ==

367

368

Filter Specifications 11

.30 dB I If\ If\ 60 dB Iz;\I

1M3

• SIN > 90 dB

• 1M3 < ·90 dB 1M3 = 311D3 '" IID3 + 10 dB

• f·3dB not so critical • Matching signal paths

AACD _h 30. 1994 ::::::::::::::::::::::::::::::::::: ESAT·UICAS ::::::

:::::::::::::::::::=:::::::::=:::::::::=====::::: &! === Capacitance Bank

• f.JdU =1/21tRC ~ ± 50%

• S/N-Fc ~c1'

5th order x 4 x 20 pF = 400 pF

C •. '" 600 pF ! S/Nopt = 108 dB

Nl<'", 11 dB SIN.lon '" 98 dB

['[E7)ITETi][!J I 251,F. bil]

1·1, I'I' I'II 17fil 2.5 pF.bil 1

hlHili±iliH±B 51'1'. WI I .. 2 1 I ] t 'II J

I 1 2 .. 2 .. I )

~ -~.~ ~. !- ~ .. ~ .~- 10 1,1: I 1 1 .. :a .. I J -.. 2 ) I l I .. J

0.625 pF.t

MalId .... 3O.1!194 ::::::::::::::::::::::::::::::::::: ESAT·MICAS ::::::

================== IfLI === Opamp: folded cascode Miller ~

• 1.2f.lmCMOS • GBW=20MHz

• RL =20kOhm => IbIas,oul ... 800 IlA => Current drain lOS 1.8 rnA

AACD"".",~JO.I!194 :::;;;:;:;;;:;:;;====;:;:;;= ESAT-MICA8 :;:;;;;;;;

================ IW=== Filter specifications

• Output Dynamic Range: 60 dB I gain 200

• Bandwidth: 220 kHz ± 5%

• Center Frequency: 250 kHz ± 5%

• Image Rejection (negative to positive) < -60 dB

• Current Drain: 18 rnA

• Power Supply: ± 2.5 V

• Chip area: 7.5 mm1

= AACD M • .,h 30.1994 :::;;;:;:;;;:;:;;;:;:;;;:;:;;==== ESAT-MICA8 ::::::;:

369

370

TRANS CONDUCTOR • C FILTERS

John M. Khoury

AT&T BeD LaboralOries Munay HiI1. NJ, USA

Marcb 30, 1994

COMMON G .. -C FILTER APPLICATIONS

• low 10 moderaIe Q

• low 10 moderaIe dynamic range

• disk drive _ cbanneI filleriDa

- 7m order 8esJeI or equiripple ~ response

- linearity requirement: I 'J>

- comer frequency aCCW1lCY: :l:1O'J>

- dynamic range: 4()..SO dB

• video filrers

- 8 bil level perfotllWlce

- comer frequency accuracy: <:I:10'J>

G,.-C FILTER REQUIREMENTS FOR WIRELESS

• IF rillers for Wireless applications

- overall filler Q > SO

- dynamic ranlle > 80 dB

G .. -C LIMlTATIONS FOR mOH-Q APPUCATIONS

• integratOr malCbing within tilter

• integralor matcbing between filler and tuning circuit

• integrator inherent gain errors

• integratOr inherent phase man

• effect of offset on signal swing

• noise and dynamic range

FREQUENCY RESPONSE ACCURACY - INTEORATOR OAINS

In/tgrmor Ma/ching lor high-Q bandpass fil/m

BW"leIQ

• for Q = 65. BW is 1.5% of Ie.

• Master-slave lUning: integrator in filter cit wning circuil mUsl match mucb bener than 1.5% (Le. 11Q) to capture desired passband

• InlegralOrs within slave muSI malCh 10 mucb better than 1.S% for correct shape

• MOIl careful designs provide wning accuracy of ±4%

SOURCES OF INTEORATOR MISMATCH

• capacitor mismatcb - across the chip

• Gm mismatch due 10 mismatch in tranSistor geometries across the chip

• poorly contro\1ed and nonlinear parasitic capacitances in paraI1el with load capacitor

• Biasing induced Gm mismatches

- input common mode offset often equivalent 10 Wning voltage error

- current source mismatches in current controUed filters

• Oain compression due 10 odd order nonlinearities

371

372

MINIMlZINO SOURCES OF INTEGRATOR MISMATCH

_+~GII+"""il'~ • + _ C

I' +

"""

FD...TER WITH RESONATOR ERRORS

8th OnUr uapfroglmpimwlltanoll

IdeaUNoII·ideai Magllllutk Response

UI I 1\\1 i ! : '71:111 i\\ iii

I 711-1 ! \ : i I I ... : ! i I -.1 Ii!

, !! -T ! l ! \J I:

/! i ! i ! I 1.\1

.. --....... ..&., .... - - • . .. FREQUENCY RESPONSE ACCURACY· INTEGRATOR PHASE

01, ~m)- = mQ

1. BeueJ ReIponIe for Disk Dri_

- Q = 2 (1111 poles _low Q)

- ~OI)- = 26.6'

- Each intepllOr pbue error must be <I"

2. High Q Response

- Q = 100

- tlm)- = 0.57" - Eacb iDtepor pbue error mUll be <0.03'

373

374

TRANSCONDUCTOR-C INTEORATOR PHASE CALCULATION

• 20 MJh G .. -C Bessel filter for • disk-dri..,

• C .. IpF, G_ EO 12S.7115

o r"",::IMO

, ...;.A. ,,126

o lrIIlSCOnduaor paruilic pole II 300 Mlh (no UfO)

o pllase error II 20 MHz: -3.4·

o modat pllase lead can be Idde4 willi Iaisu>r

• bigh Q requires pIwc conllOl .no loop

NONIDEAL TRANSCONDUCTOR-C INTEORATOR RESPONSE

....

....

....... ..,::&r.._.-

I ........... 1

, l

........... i

i """ , !

I I "" 1'-

! I I : I. .... - _.- ....

0T"~ ..... _ I

I 1. I \,

i ...

I I \ I " .

~

-:-­.---

--.-­.---

I -------,- --I I 'i,. I

, I \ I

i I I \ I I I i - .... - - .... -

nJNING HIGH Q FU...TERS

• Marer-slave lUning of I. would require matdling much better Ihan IIQ.

• Marer-slave tuning of inregrator phase would n:quire mar.cbinl mucb beller Ihan 10'1>

• Maler-slave tuninB nol practical for higb-Q circuits

• Potential Opcions:

- direct tuniDB - self tuninB

DIRECT TIJNlNG

• periodically remove filler from signal patb and tune

• two ftlren can be used for uninrerrupred processing of signal

DIRECT nJNING OF A LEAPFROG BANDPASS FU...TER

LC I'TiJIorype

o-N'

I ~ ii' I! 0

VIII

I ~ ~ 'lOUT

0 I, I 0

NormoJ O,n'lUion

NVr

.~----~----~~

TUlling Modi

375

376

SELl' TUNING

... ,.

• View filter as multiple-input multiple-output system

• keep tuning siJ1D81 at low level 10 minimize signal swing loss

• poles of main paIh IIId tuning paIh IIR the same

• zeroes of lUning paIh IIId siJ1D81 path IIR made different 10 preveru interference

DYNAMIC RANGE

FWllillmlIIIIJI TrtUlSCOMUClOr HoUl

11.2 /lldl 11{" 4I:T 10m

FllllliDnurual R •• onator Noil.

V2""", • [4I:T 10 .. )[ (II.Q 12]

Dynamic Rang. - D/ff.r.ruial Signal swing at 2 :c Vdd

DR.IOlog)O[V1,Itpp/yC/(4A:TQ)]dB

Exmnpk

• Q-UlO. VDD z 3.0 V. C • 10 pF

• => DR .. 77 dB

Mtuimizlog Dyllllmit: Rang.

• large capacitor .... > large Gm => large power dissipation

• large capacitor ==> large chip area • large Goo => difficult 10 drive large capacitances

• high sipaI swing => high vdd

• high signal swing _> bener linearization methods

• high signal swing difficult with high Gm offsets

• high signal swing often con1Iicrs with lUning range

TRANSCONDUcroR DIFFBREN'I1AL OFFSETS

.. III

-'---I--+..J

• offla mv-Iy JII'CIPOIIiOoIIIO G.

• bip offIet _ mWmmn IiJlll!IWiIIa Umilld -> 1_ dYJlllllic ranp

• eIecIrIcU bIIance depded wid! offset _ poonr !iDeality

• loa of elecaicll symmetry -> depadecl PSRR

DECOUPLINO SlONAL SWING FROM TUNINO

" _ •. - ...... --<1 L......-

• Wide IIII1ina ranp 0;;0 JiJaiIId IiJlll! rwinI -> Jower dyalmic ranp

CONCLUSIONS

• G .. -c allen ased widely iD InduIUy for low Q IIId mocIeraIe dYJllllliC: ranae appllCIIioDs (dIIII: drive _ cbIIIneIa IIId video)

• FIItcn for ~

- HlpQ - Hlp cIyn8mic ranp

• I'uuue dilecdOlll

- dIrecI/IeIf IIIIIiDI of biJb Q 811m

- low noise II1II_

377

378

Recent Advances in

Switched - Current Filters

John B. Hughes, Kenneth W. Moulding

sc

Philips Research laboratories Redhill. England.

~ PHILIPS

SWITCHED CURRENT FILTERS

• Basic CMOS

• Merged Storage and Buffer

• No OpAmps

• Simple Circuits

~ • Cost-Effective

• High Bandwidth

51 • Mixed Signal

Channel Length Modulation

gds

SI ERRORS

Capacitive Feedback

Switch Charge Injection

ERROR REDUCTION ...... Drain Conductance

Cascode Active Feedback

Regulated Cascode Grounded-gate Feedback

379

380

ERROR REDUCTION ...... Charge Injection

Dummy Switch Fully Differential q = q1 - q2

PIECEMEAL ERROR REDUCTION

• Reduced SNR

• Reduced BW

• Increased AREA

• Increased Vdd

• Increased Idd

GLOBAL ERROR REDUCTION

381

COMPOSITE MEMORY (521)

Fine Memory

1 cjl 2 ..-. -- Out

Coarse Memory

51

521 OPERATION

V,er ---u

Transmission Error. Es21 ~ (Es1 ) 2

382

STORAGE LOOP

INTEGRATOR

• Alternating inputs

• Mirrored outputs

DOUBLE - SAMPLING INTEGRATOR

• Half Memory BW

• Half Idd

• Double max f sample

• Increased SNR (+ 6dB)

• Increased LF Gain (+ 9dB)

383

ELLIPTIC FILTER

• Doubly-terminated LCR

• 8MHz LPF

• O.5d8 ripple

~MHZ

NORMALISED RESPONSE --- _. . --· --r·· - --"'-_.J : n.~

~ .. -~--! -. - .-T-=~ lOde -!--]·-~.--'~I· --. - . [--.101111' .. .- .. 100II11,-+.- _ __. __ .

"--:;::60 II", I ' ~~~&~~ II~I,~,

IdB

-+--+--.- -- U-1--

flfsample ~

NOISE SPECTRUM

~ - - - ~1~ 1---- --- - --J-. --- H f sample = 80MHz J---- --

1-7 Chip ower on

~ ~ --- I-~ .... L _.- ., " ...

1-

=-~F·~·F-· -- ---..-- --f--....

~ ----. f--- _.-_ J _ _ ----'---

o 20M Hz 40MHz

384

HARMONIC DISTORTION

I I - f sample = 80MHz I--

----- I fslg = 1MHz l-I '-

I I mod =50% -, I I ! 1--. I -

I I I

~ - ! - -, -- -- --- !

I o 5MHz 10MHz

COMMON-MODE REJECTION r--

._)Qlont.d InpUI~ -T-·-. __ .-~ . I-- • __ • • 0- I'< I f sample:: 80MHz -~

~ I --- r--I---I--

\./ 1--- -.-. -~ f--- ommon mode Inpute

.. ---- --- --"- --".---. 1-----f------- - .. -- ---

1----- - --- --- 1---.- .

0 20MHz 40MHz

PERFORMANCE

• Process O_81lm n-well 'digital' CMOS

• Supply voltage 5V! 10%

• Area 0_3mm 2

• Dissipation 105mW

• Sampling frequency BOMHz

• Cut-off frequency 7_76MHz (8MHz)

• Passband gain 5.6dB (6dB)

• Stopband attenuation 25dB (26dB)

• Notch attenuation 37dB

385

PERFORMANCE continued

• Harmonic Distortion (50% mod fslg=1MHz)

2nd -61dB 3rd -48dB

• Signal-to-Noise Ratio 67dB (GOdB) (50% mod)

• CMRR 39dB (40dB)

• PSRR 43dB

• Output swing 1.2mA (50% mod)

• DC offset 22pA

SUMMARY

• Composite Memory Cell

• Balanced Bilinear Integrator

• Fully Competitive Filter Performance

386

SWITCHED CAPACITOR FILTERS

Robert C. J. Taylor.

Austria Mikro Systeme International AG. SchloB PremsUitten.

A-8141 UnterpremsUitten. Austria.

CAPACITOR SCALING EXAMPLE:

CAPACITOR SCALING EXAMPLE:

Original. calculated, Rounding to two New Ratio: Ideal Ratio: Percentage values: decimal places: Error: --_._. --

C4a = 3.016740 units 3.02 C4a1C42 = 3.02 3.016740 (UI % -----. --- ._-_._--011 = 1.022979 units 1.02 C411C42 = 1.02 1.022979 -0.29% -------- --"------C42 = 1.000000 unit 1.0 ---.-.. ----------- ----- ------_. "--'--C44 = 4.444093 units 4.44 C44/C42 = 4.44 4.444093 -0.09%

.. --- .- - _.- . '-Multiply all the capacitors by 1.4 and round to two decimul places:

Rounding to two New Ratio: Ideal Ratio: Percentage Error: decimal piaces: - ._------_.

C4a = 4.22 units C4a1C42 = 3.014286 3.016740 ·0.08% --C41 = 1.43 units C411C42 = 1.021429 1.022979 -0.15% -C42 = 1.40 units -C44 = 6.22 units C44/C42 = 4.442857 4.444093 -0.03% ... -- -

CAPACITOR PARASITIC CAPACITANCE.

Parasitic capacitance between metal tracks and bottom polysilicon (polyl) plate:

1',,',1= t.klll _ ''''''''=1 Bcfore Modification. After Modification.

RESULTS OF CAPACITOR BANK MODIFICATIONS:

BefOl"c Mod.:

After Mod.:

• C"nlac:1

c:::J" .. ,. c=:J Mel"1

.::::::J Active.

%age Error In Notch Frequcncy:

1st Notch: 2nd Notch:

0.08

0.06

0.73

0.26

A

·,--J0f-·l dl 02

==;;:====;;:==dl ,I A

~~~12 ====iJI::=:===dl

Ea •• nple or III.tched layout or Input devlus

3rd Notch:

1.10

0.32

387

388

DMOS Transistors in Smart Power Building Blocks

., "HIIWI

MIElEC

B. Graindourze Alcatel Mietec (Belgium)

A Generic Control System Interface

Power switch conlrol

Swllchlng Device

Three partitions : Sensor & low-power actuator - Control System - Power actuator

., ' ·'HIII'

MIElEC The IISmart Powerll Approach

Integrate low-level control functions and a power driver

., •..... , MIETEC The "Smart Interface" Approach

Swilching Device

Integrate more analog & digital functionallity - leave high power handling to specialized devices (IGBT, Power MOS, ... ' .

., '.' ••• 1.,

MIElEC

., '· •••• ,11

MIElEC

T MOS:

T BIP:

T OMOS:

• Alternative 1:

N-well 3 ~lm poly-gate Linearity of NMOS up to 11 V

of PMOS up to 18 V Maximum supply voltage = 18 V

Vertical NPN Lateral PNP BVCEO > 40 V , BVCES > 80 V High early voltage

Lateral, non-self-aligned Fully floating Breakdown voltage> 85 V RON (NOMOS) = 2 Ohm. mm2

Devices

Parameter Extraction

• Parameters fairly good for - all bias conditions - all dimensions

• (Alternative 2: ) • Parameters accurate for normal working conditions

• Parameters poor in seldom used conditions

389

390

... 1.11_1111

Working Conditions for NOMOS MIElEC

... Analog applications: • IDS vs VDS for: - VDS: 0 V ... 80 V - VGS: 7 V ••. 12 V

... Switching applications: • IDS vs VDS for: - VDS: 0 V ... 2 V - VGS: 0 V .•. 22 V

• IDS vs VGS for: - VDS: 0.1 V

... '.'1.1111

MIElEC

- VGS: 0 V •.. 22 V

Extra Device Error Checking

... Improper use of the technology e.g.: - A component dimension smaller than

allowed by the layout rules - Voltage over a component higher than

allowed by the electrical rules

... Improper use of the simulation models e.g.: - A model that is used outside the region

where it is valid

... Improper use of a component e.g.: - A bipolar transistor that saturates

... , ....... . Electro-thermal Simulations and Design Rules MIElEC

Design rules derived

• to avoid major problems e.g. maximum temperature

temperature gradients between components

• via simple thermal models measurements simulations

T ' .•••• ,11

MIETEC Example

Maximum Temperature Rise in a Square Source

"

~Tmax = Qo d/k tanh (b/d I

with Qo: b: d: k:

power density half of source width wafer thickness thermal conductivity

, ....... . Standard Devices Library MIETEC

T Bipolar:

T MOS:

T DMOS:

" '."."'1 MIETEC

Library of standard transistors Separate SPICE model for each transistor

Stretchable cell for e~ch type Separate SPICE model for each type

Stretchable cell for each type Separate SPICE model for each type

Conclusions

T Macromodel, built with standard MOS models, +

T Parameter extraction, based on standard routines,

f T Accurate simulations for normal working conditions

+ T Checks to flag improper working conditions

f T Reliable simulations of DMOS transistors

391

392

B. Murari, SGS-Thomson, Cornaredo AUTOMOTIVE SYSTEM PARTITIONING

~A~ERYI POWER &UPPl. Y

::-::-7'Ti~1

Power DMOS transistor Ron-A vs. BV in BCD processes

Speclnc ON~, •• llt.ne. Roo.A (otvn.mml )

100 ~----------':"-..-~-----------, o '.13: .t.rt genera lion (4 11m)

o 1917: .I.r1 goneroUon 112.$ IIml KDMPl.8f!.

/ /

10 I------------+--~~~~~-_~/~~

oeD>. -~--

tICD::t ••

/ /

/ /

/

,;/ ..".....,.Ik~ ... 11

0.1 L-_______ ___ __________

10 100 1000 Drain-Source br.ak,down voltage M

-_ ....

CU ~!:}lfJ!l!~2.~I __ -- .---------_ -:Hi!WEIi~-~. "", ... oa

BCD TECHNOLOGY ROADMAP

TECHNOLOGY COMPLEXITY TRENDS Comp''''1Y (H •• oil •. )

+ POW. ---

1895 2000

~ 80S -THOMSON DEDICAteD PRODUCTI OROUP

· ~I MICAOElIC'AONICI --------

BIPOLAR & MIXED PROCESSES EVOLUTION

• BIPOLAR ROAD MAP IN THE PAST YEARS SHOWS (POWER & HV) A SLOW EVOLUTION.

EMITTER POWER AREA LIMITED BY EFFICIENCY OR CLEARANCES FOR H.V. ALLOWS ONLY SMALL SIZE REDUCTION DESPITE IMPROVEMENT IN MICROllTHOGRAPHY.

• MIXED PROCESSES ROAD MAP IS FOLLOWING THE VLSI (BCD & BICMOS) EVOLUTION WITH SOME YEARS OF

DELAY. THIS IS DUE TO THE FACT THAT POWER-DMOS Ron DEPENDS ON L/W AND THEREFORE CAN BE REDUCED WITH MICROLITHOGRAPHY.

Dec. 91

INSIDE THE H081 INTEGRATED CIRCUIT

.r;-II-

.ou.

-- """". ,

t----f---<)OUOl , , -9 0mn

.. - w' \l'SPWl vspwn 1.,,..,IJ.'1

393

394

SGS-THOMSON H'C.OIUCT.OIUC.

DfDICATlD PRODUCTS OROUI'

HOS1 KEY POINTS POWER STAOE

• DMOS FULL BRIDGE 0.3 Ohm

• OVERCURRENT PROTECTION

• OVERVOLTAGE PROTECTION

• THERMAL PROTECTION

MICROPROCESSOR

• ROM LESS V.ERSION 14K ADDRESSING SPACE'

• 64 INTERNAL RAM LOCATION

• 8 BIT INTERNAL TIMER WITH PRESCAlER

• WATCHDOG

• FULLY CONFIGURABlE B BIT DIGITAL 1/0 PORT

• 6 STACK LEVELS

Cell Composition Tool Flow

Sprate

YI ... l"o'o .,.E Spdte

"'"118' Layout

(II"om CAIlF.'NCE)

"herln ••

THERMALLY~ORIENTED SILICON DESIGN APPROACH

HIGHER INTEGRATION LEVEL MEANS

DRAMATIC GROWTH IN

POWER DISSIPATION DENSITY (UP TO 13W/mm2

FOR TDA7265)

CAR-RADIO POWER DISSIPATION 50 -----,--,--,--.---,- - .. ----

--'l--f--t----i---- -: 40 I I __ ~ ___ ~- __ ~_ -l I I t I I

--i:--}-:----~- --_._-; 30 I I I I I

~ 20 - ==:=r==~i--~:--~=~j I 1 :--t-----1

10- I~---+---+_---: I I I I I i i ----,--r---,

0- t--i---f---i----i 74 78 82 86 90 94

YEAR

ACCURATE ELECTRO~THERMAL DESIGN IS MANDATORY, HENCE:

ELECTRO-THERMAL SIMULATION USEFUL FOR

A) ISOTHERMAL LINES FOR OPTIMUM DEVICES PLACEMENT

B) POWER TRANSISTORS LAY-OUT FOR SAFE AND RELIABLE OPERATION

C) DESIGN OF TEMPERATURE-GRADIENT DEPENDENT CIRCUITS (e.g. PROTECTIONS)

395

396

i: .... SCS-mOMSON _______ c_-_.-_ .. _ .... _ .. "_-"_~ • J •.• ~11\JIIC1I1IIi!Jf

p

.... , '.11

r-LlL TIWATT

.,.11.

on ell. dl .Ipollng ••• 1'.C •• q ... II.

Pel • 2 Urt l ....unl. on b • ..,.eI

'.1 t t. Tit[ 011 PUl.S[ U10TH ( • ,

... laee

"-__________________ MONOltTtliC MICAOSYSTU'S DIVISIOH ____ ~

I J NON RESISTIVE LOAD ELLIPSE AND PROTECTION I

, CURVES FOR CLASS B STAGE.

}

'.

'--__________ MONO"T.'C MICOOSYSUMS O'Y,.,ON J

SHORT CIRCUIT PROTECTION

IN PRESENCE OF REACTIVE LOAD.

v. CAPACITIVE.

"'0-l'------\:------:r--.."

~----------~~--------~---Wl

'-____________ MONOLITHIC MIC"OSYSTIMS DIVISION

TIIERMAL BEHA VIOUR OF CHIP

DURING A POWER STEP.

S".dy nil.

Power transiSlor Ifl

0, rp 0,

Silicon chip

'-____________ MONOLITHIC MICJIIOSVSTEMS DIVISION

397

398

SHonT CIRCUIT CURJiENT BEJIAVIOUR

MODULATED BY THERHAL FEEDBACK.

I.

o "

'-___________ :,,*ONOLtTHIC IroIICROSVSTlMS DIVISION

DELAYED SHORT CIRCUIT PROTECTION.

"

-Vco __ ..:.L=_~.--_____ -" ___ ---,rn- Vel

'-___________ MONOLITHIC MICAOSYSTEMS DIVISION

I I

1 I , I

I

i. "''1 ~~·'·1Hl' ,~~~p.~ 'Jill .......... ~ ................ _ ................ ______ _

PROTECTION TECHNIqUES.

'_ _______ MONOLITMIC ".C"nYITIMI DIVIIION

SGS-THOMSON MICROELECTRONICS DEDICATED PRODUCTS GROUP

Power DMOS Full Bridge Major Cross Section & Parasitics

01 G1 81 G101 B 02G2 82 G202

-1~~r~~l~~!;1 , Subs 1 l' . -.-......... -.......... --... 1-·-.... · .. --.. · .... -----.. ·

E· w' PRO"C' ~.--•• -, 0-.--'-"6-'N"· ..... ,-&-.-,-•• -. M:A:'-RB.-;;;;iii·- - ----.... --... - .. --.. iii so, •. __ •••• _ ... _ ••• __ •. _._ .. ____ ..•.• __ .• ' ,N_,' Jun '~3 .

399

400

I'

SGS-THOMSON MICROELECTRONICS DEDICATED PRODUCTS GROU.P

....... · .. Power DMOS'''Full Brldge--.-.... V + V Major Dla Xsactlons

H~~~~ C·!~t~~h -.p -._ ~ ~~~ A-A' ED ED -v (I) ___ 'ED _ ___ D

III III EB III N N Xsection B-B' -- --- -- ._--- _.-

h p e~ .. -"-~GND GND ............ _. . .- "'-.7

~c~s~: . -'-r:~~J e

L j LS.2 • _GND

• N N • ---- V 0