An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 11, NOVEMBER 2012 2481

An All-Digital PLL Frequency Synthesizer Withan Improved Phase Digitization Approach and anOptimized Frequency Calibration Technique

Liangge Xu, Student Member, IEEE, Kari Stadius, Member, IEEE, and Jussi Ryynänen, Member, IEEE

Abstract—This paper presents an all-digital phase-locked loop(ADPLL) that features separate use of integer and fractional partsfor the phase digitization in the feedback path. This separationsimplifies the circuit implementation allowing reduced power con-sumption and silicon area. The proposed arrangement frees theADPLL from potential metastability hazard during fine-tuning op-eration. Furthermore, it eliminates spurious tones associated withfrequency reference retiming. In addition, the ADPLL employs anoriginal frequency calibration technique that allows an extremelyfine calibration resolution with minimized calibration time. Theo-retical analysis is provided for both the architectural modificationand frequency calibration technique. The ADPLL has been imple-mented in a 65-nmCMOS. Its simulation andmeasurement resultsare presented.

Index Terms—All-digital phase-locked loop (ADPLL), binarysearch, frequency calibration, frequency synthesizer, phasedigitization, time-to-digital converter (TDC), variable phaseaccumulator (VPA).

I. INTRODUCTION

O VER the last decade, we have seen the emergence and in-creasing adoption of all-digital phase-locked loops (AD-

PLLs) for frequency synthesis in RF systems [1]–[6]. The mostrepresentative and popular ADPLL architecture for frequencysynthesis is probably the one shown in Fig. 1 [3]–[6]. A keyfeature of this architecture is the presence of frequency errordetection in the digital domain, which is enabled by phase andfrequency digitization of the RF output signal in the feedbackpath. The availability of frequency error in the digital domainconstitutes a unique advantage for configurability.Despite all the advantages, a major drawback of the archi-

tecture is the joint operation of the variable phase accumulator(VPA) and the time-to-digital converter (TDC) for phase digi-tization of the RF signal. Working simultaneously, the two cir-cuit blocks supposedly complement each other with the VPAdigitizing the integer part of the RF signal phase and the TDC

Manuscript received April 26, 2011; revised August 19, 2011; accepted De-cember 15, 2011. Date of publication April 12, 2012; date of current versionOctober 24, 2012. This work was supported by the Finnish Funding Agency forTechnology and Innovation (TEKES) under NORDITE project. Paper recom-mended by Associate Editor S. Cho.L. Xu was with the Department of Micro- and Nanosciences, Aalto Univer-

sity, 02150 Espoo, Finland. He is now with Renesas Mobile Corporation, 00018Helsinki, Finland (e-mail: [email protected]).K. Stadius and J. Ryynänen are with the Department of Micro- and

Nanosciences, Aalto University, 02150 Espoo, Finland (e-mail: [email protected];[email protected]).Digital Object Identifier 10.1109/TCSI.2012.2189055

Fig. 1. Representative ADPLL architecture.

digitizing the fractional part. This however introduces some se-rious issues in real circuit implementation. First, inevitable mis-alignment of the respective outputs from the two circuits gen-erates glitches in the loop and consequently entails additionalcorrection circuitry [4]–[7]. Unfortunately, all known glitch cor-rection techniques are based on the assumption either the fre-quency error is sufficiently small, and thus can only work prop-erly after a certain stage of frequency acquisition. Second, ref-erence clock synchronization performed by the retimer to avoidmetastability in the VPA sampling is itself subject to potentialmetastability with likelihood increasing over operating time [8].As a result, its continuous operation in the ADPLL increases therisk of metastability that can occasionally disrupt the ADPLLoperation. Moreover, extra spurious tones can arise in the outputspectrum due to the reference retiming [9], [10].In this paper, we present an ADPLL that features separate

operation of the VPA and TDC. The VPA is used for phase dig-itization exclusively during the coarse tuning. After the coarsetuning, phase digitization is performed only by the TDC. Thisseparation allows the outputs of the two circuits to be used in-dependently instead of in combination. It is thus free of all theabove issues associated with joint operation of the two circuits.Meanwhile, the ADPLL employs an optimized binary searchtechnique for adaptive frequency calibration (AFC). This tech-nique allows each step in the binary search to use a minimumnumber of reference cycles as required for reliable frequencycomparison, resulting in remarkably faster frequency settlingthan before. This paper is organized as follows. Section II de-scribes the ADPLL top-level architecture. Section III examinestheoretical basis of the separate operation. Section IV outlinesthe principle of the fast AFC technique and its circuit implemen-tation. Experimental results are given in Section V.

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2482 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 11, NOVEMBER 2012

Fig. 2. Proposed ADPLL architecture.

Fig. 3. Progression flowchart of the proposed ADPLL.

II. PROPOSED ADPLL ARCHITECTURE

Fig. 2 shows a simplified block diagram of the proposedADPLL. The VPA and TDC are separated into coarse-tuningand fine-tuning loops built around the digitally controlledoscillator (DCO). The VPA-based coarse-tuning loop performscoarse AFC, whereas the TDC-based fine-tuning loop is forboth fine AFC and normal phase locking. The operation isillustrated with a flowchart in Fig. 3. Upon due initialization,the ADPLL frequency settling process starts with the coarseAFC, which is followed with the fine AFC before it proceeds tothe phase locking operation. The progression between differentoperation modes goes as follows. The ADPLL is initializedwith the reset signal as an input. The dis-assertion of resetactivates the coarse-tuning loop for coarse AFC, during whichthe fine-tuning loop remains inactive to maintain its initial state.The completion of AFC is detected in its core logic, upon whichthe core logic for coarse AFC asserts a done signal and freezesits output. The assertion of the done signal from the coarseAFC logic activates the fine-tuning loop for fine AFC, with thewhole coarse-tuning loop deactivated. During the fine AFC, thedigital loop filter (DLPF) branch also remains inactive. Whenfine AFC is finished, its core logic raises its own done signal

and deactivates itself with its output frozen. The assertion ofthe done signal from the fine AFC logic activates the digitalloop filter (DLPF) branch for phase locking.In the coarse-tuning loop, phase digitization is performed

solely by the VPA. The absence of a TDC in this loop is based onthe observation that a TDC could only play an ineffective roleover the corresponding period of time. As to be demonstratedin next section, the initial frequency calibration performedby this loop only needs to ensure the output frequency errorto be smaller than one half of the reference frequency with asmall margin, for correct operation of the following fine-tuningloop. This large frequency tolerance, exploited by the AFCtechnique, allows the initial frequency calibration to be finishedwithin a negligibly short time despite the coarse resolution of aVPA. It also obviates the need for most of the fractional bits inthe overall frequency control word FCW. As a result, the inputFCW(H) comprises only the FCW integer part and two or threeMSBs of the fractional part just to ensure the truncation error issmaller than the frequency tolerance.In the fine AFC and phase locking operation modes, phase

digitization is performed exclusively by the TDC that covers asmall range of one RF cycle. The dramatically reduced rangecompared with that of a VPA is sufficient because of the rel-atively small frequency errors after the coarse AFC. As to bedemonstrated theoretically in next section, the range has no ef-fect as long as the output frequency error is kept within roughlyone half of the reference frequency. Meanwhile, the AFC logicin this loop exploits the fine resolution of the TDC to achieve afine and fast final frequency calibration. It provides such a finecalibration resolution that the output frequency could be imme-diately used by the upper-level system after its completion. Inother words, no additional frequency settling is required afterthe loop is closed with DLPF becoming active. The exclusionof VPA from this loop eliminates the need for clock retimingand the frequency reference can be used directly as the clocksignal for the digital logic in fine tuning. Meanwhile, the inputFCW(L) comprises only the FCW fractional part.With the separate operation of the VPA and TDC in different

operation modes, the modified ADPLL architecture is free ofall those issues arising from the joint operation of the two cir-cuits. Moreover, the separation of two loops allows almost theentire coarse-tuning loop to be switched off during normal oper-ation of the ADPLL, thus saving the associated power consump-tion of the loop. With the use of two loops, the word length formost of the arithmetic logic is also dramatically reduced, whichallows reduction in both silicon area and power consumptiondespite duplication of some simple digital blocks. Meanwhile,the two-stage arrangement of coarse and fine frequency calibra-tion along with an innovative AFC technique optimally exploitsthe different resolutions of the VPA and TDC, minimizing fre-quency settling time.

III. FREQUENCY ERROR DETECTION

In this section, we explore the basic principles of frequencyerror detection in an ADPLL through mathematical models. Itprovides a theoretical rationale for the proposed separate op-eration of VPA and TDC. We start by describing the ideal sce-nario, which sets a reference point for subsequent consideration.

XU et al.: ADPLL FREQUENCY SYNTHESIZER WITH AN IMPROVED PHASE DIGITIZATION APPROACH 2483

Effects of finite ranges and resolutions of the functional blocksare then considered with relevant requirements on the ranges de-rived. Finally, it is demonstrated how the small range of a TDCcan be adequate in the fine-tuning loop.

A. Ideal Scenario

The frequency error detection in the ADPLLs is accom-plished essentially in three steps.1) The first step is phase quantization or phase digitization,where the RF signal phase is sampled and quantized peri-odically at the reference frequency.

2) The second step is frequency detection, where the RFsignal frequency is detected by taking the difference oftwo consecutive samples of the quantized signal phase indigital domain.

3) The final step is frequency comparison or subtraction,where the detected RF signal frequency is subtractedfrom the target frequency to derive the frequency errorinformation.

The ideal function of each step can be described respectivelyas follows:

(1)

(2)

(3)

where is the sample index number. Thein (1) represents the RF signal phase in radian at th samplingtime instant and the normalization by means thatquantized phase is in units of cycles. The frequency con-trol word FCW defines the target frequency, denoted as , inthe form

(4)

with being the reference frequency.Considering phase is an integral of frequency, we can write

in terms of the RF frequency as

(5)

with being the signal frequency as a function of time ,and an arbitrary initial value. The detected frequency (2) canbe rewritten as

(6)

with being the output frequency in Hertz averagedover the time interval between and . In an ADPLL,the DCO frequency control word is updated only at the samplingtimes. Consequently, the RF signal frequency can be consideredas a constant between two consecutive updating moments, andits value is determined by the DCO frequency control word up-

dated at time . The above equation shows that the overallfunction of the feedback is to measure the RF signal frequencyin the form of its ratio to the reference frequency. It is worthnoting that there is a unit delay associated with the detection.The normalized frequency detected at time is the frequencyupdated at the previous sampling moment .By substituting (4) and (6) into (3), we can write the detected

frequency error as

(7a)

with

(7b)

being the output frequency error in Hertz over the time periodfrom to . Equation (7) represents the ideal result offrequency error detection, which is essentially the output fre-quency error normalized to the reference frequency. The signinversion between the output frequency error and the detectionresult reflects the basic characteristic of a negative feedbackloop. The ideal result is not achievable in practice, but it setsa reference point for circuit designs. Next we will discuss hownon-ideal factors, particularly the finite range and resolution ofeach function block, can affect the detection result.

B. Effect of Finite Range and Resolution

In a hardware realization of frequency error detection, eachfunctional block is characterized with a finite range and reso-lution, limited by the finite word length. Particularly, the phasedigitization is an analog-to-digital conversion process. Its rangeand resolution are additionally constrained by circuit realiza-tion feasibility of the conversion process. Its finite resolutioninevitably introduces quantization errors, limiting the resolutionof frequency error detection. As the RF signal phase as given in(5) can grow boundlessly with time, the finite range phase digiti-zation leads to unavoidable overflows in the conversion process.As a necessity, the overflows are simply ignored, wrapping anyout-of-range phase values back to a finite range. This wrappingaround of out-of-range signal values in phase digitization andsubsequent steps is equivalent to an additional modulo opera-tion applied to each digital output.To acknowledge the effects of finite ranges and resolutions,

we can reformulate the function of each step in frequency errordetection from (1) to (3) respectively as follows:

(8)

(9)

and

(10a)

with

ifotherwise.

(10b)

The modulus at each step is represented by and ,respectively, in the above formulas. and are the lengths


of integer parts used in the fixed-point binary representations.The modulo operation in function (8) suggests that phase quan-tization wraps around the otherwise boundless phase values toa finite range from 0 to (with excluded). Apparently, theeffect of phase wrapping needs to be undone at a later stageto ensure correct result of frequency error detection. In the fre-quency detection described by (9), the modulo operation foldsany potential negative result of the subtraction to the nonneg-ative range from 0 to . This is a characteristic of a simplemodulo subtraction with unsigned input and output numbers forthe phase and frequency signals. The situation is different withthe subtraction as the final step of frequency detection. Unlikethe phase and frequency, the frequency error can also be nega-tive. This entails two’s complement representation of the sub-traction output as a signed number. Its effect is represented in(10) by the term that modifies the output of an other-wise unsigned subtraction. Basically, it undoes the folding ofthe potential subtraction result into the positive range with theunsigned modulo subtraction. The in (8) represents thequantization error during phase digitization. For simplicity, wehave assumed no further quantization errors introduced in thenext two steps that are realized with pure digital circuits. Thiscauses no loss of generality, since quantization errors in the dig-ital circuits can be either avoided or minimized to a negligiblelevel.In the following, we derive the general frequency error detec-

tion result including the effects of finite ranges and finite phasedigitization resolution. By substituting (8) into (9), we can writethe function of the entire feedback path as

Based on congruence properties of modulo operation [11] andthe fact that and are both integers, we can rewrite the aboveequation as

(11)

The means the smaller of and . Substitution of(11) into (10) yields

(12)

which is the detected frequency error with the finite phase dig-itization resolution and finite ranges of each functional blocktaken into account.

C. Design Consideration on the Ranges

Considering the large magnitude of any potential error intro-duced by the finite ranges, their overall effect must be null in

the final detected frequency error. In other words, we need toreduce (12) to the following form:

(13)

for all values. This sets the requirements on choice of rangesrepresented by the corresponding moduli. We will derive andexamine these requirements in the following.Suppose the moduli in the feedback path are chosen to meet

the following condition:

(14a)

or

(14b)

It allows us to reduce (12) to

which can be further reduced to (13) for all values on thefollowing condition:

(15)

By using (6) and (7), we can rearrange (14) and (15) into thefollowing conditions:

(16a)

or

(16b)

and

(17)

The above condition constitutes an important guideline thatmust be followed in ADPLL designs to ensure correct outputfrom the frequency error detection. Otherwise, it can be shownthat (12) cannot be reduced to (13) for all values, whichsuggests misrepresentation of detected frequency error andfailure of the ADPLL operation due to inadequate ranges of thefunctional blocks.According to (16a), the range of the feedback path can be

designed to be large enough for the maximum ratio of outputfrequency to the reference frequency with phase quantizationerrors taken into account. This is somehow intuitive, but notnecessary if (16b) allows a smaller range. According to (17),the range of final step frequency subtraction is required to coverthe maximum of output frequency error to the reference fre-quency with phase quantization taken into account. Accordingto (16b), the range of the feedback path does not need to belarger. This is significant because the ADPLL output frequencyerror can be much smaller than the output frequency itself. Es-pecially in a narrowband application, the output frequency can


be very high but vary over only a small frequency range, sug-gesting small frequency errors over time. More importantly, theoutput frequency error changes over time and approaches zeroin the frequency settling process. Suppose the functional blockshave changeable ranges. They can be made very small after acertain stage of frequency settling.

D. Separate Frequency Error Detection

From above result, it is clear that the range requirements onrelevant functional blocks are different with the coarse-tuningand fine-tuning loops of the proposed architecture for the sep-arate frequency error detection. In the coarse-tuning loop, theentire output frequency range with all possible target frequen-cies must be taken into account. This results in a requirementfor relatively large ranges, entailing the use of VPA for phasedigitization and sufficiently large word lengths for the VPA andthe following blocks. In the fine-tuning loop, the range of TDCis however restricted to one RF cycle with . This range issufficient provided that the output frequency error is within therange of one half of the reference frequency, as indicated previ-ously in Section II. Specifically, after the coarse tuning, we have

(18)

It allows us to choose

according to (16b) and (17), and justifies the use of TDC alonefor the phase digitization in the fine-tuning loop. In the fol-lowing, we examine more closely the frequency error detectionin the two loops.1) Frequency Error Detection in Coarse Tuning: The coarse

tuning performs the initial frequency acquisition to secure thecondition (18) as needed for the subsequent fine-tuning opera-tion. The phase digitization is performed with the VPA based ona modulo integer counter with a word length of bits. It countsthe whole cycles of the RF signal with counting result sampledat the reference frequency. An -bit modulo counter has a mod-ulus of and can count from 0 to . Clocked by the RFsignal, the counter increments by one for each cycle, namelyphase advance of the signal. Whenever the maximum value

of is reached, it wraps around to zero at the next clockrising edge and starts counting up again. The above operation ofVPA for phase digitization is illustrated in Fig. 4, whereis the counter output considered in the continuous-time domainbefore sampling.The integer nature of the counter triggered by each of signal

rising edge quantized off the entire fractional part of the signalphase. As a result, the VPA output can be given as

(19)

where

(20)

Fig. 4. Phase digitization with VPA. (a) Simplified timing diagram, and (b)output relationship to signal phase.

is the quantization error accounting for the fractional part quan-tized off.In the following, we consider the ranges or word lengths of

different functional blocks in frequency error detection of thecoarse-tuning loop. From (20), we have andthus

(21)

This allows us to rewrite the conditions (16) and (17), respec-tively, as

(22a)

or

(22b)

and

(23)

In the specific ADPLL design, the reference frequency is40 MHz. It is for a wide-band application with target frequencyrange from 3 to 6 GHz. To cover this target frequency range,the minimum frequency from the DCO can possibly go as lowas 2 GHz and the maximum 8 GHz, with PVT variations takeninto account. Before the frequency settling starts, the DCO fre-quency control words are initialized to their center values in theADPLL reset state. Consequently, the DCO initial frequency isexpected to be around the center of its frequency range, withits distance to the center frequency mainly determined by theDCO coarse tuning linearity. Obviously, the maximum possiblemagnitude of frequency error occurs at the starting point offrequency settling, when the target frequency is the further end(minimum or maximum) of frequency range from the initial


Fig. 5. Phase digitization with TDC. (a) Output and related quantities, and (b)output versus signal phase.

frequency. This maximum frequency error magnitude can beestimated as half of the DCO frequency range plus the distanceof DCO initial frequency from its center frequency, and itis assumed to be 4 GHz with a relatively large safe margin.Substitution of all parameters into (22) and (23) yields

or

and

As a result, we can choose , which gives

(25)

In this specific case, conditions (22a) and (22b) happen to givethe same result. The situation would be different for a narrow-band application, where (22b) tends to allow smaller ranges.With the selected word lengths given by (25), we can obtainthe detected frequency error Fec in the form of (13).2) Frequency Error Detection in Fine Tuning: During the

fine tuning, phase quantization is performed by the TDC system.As illustrated in Fig. 5(a), the TDC measures the time interval,from the sampling time instant back to the preceding rising edgeof the RF signal, and normalizes the time interval to the mea-sured RF period. With representing the th sampling timeinstant and the preceding RF signal rising edge, the cor-responding time interval between the two time instants can begiven by

(26)

Normalization of the above time interval to the RF signal pe-riod yields

(27)

where the relation of has been used.The finite time resolution of TDC introduces quantization errorsin the measured time interval and the RF signal period

. In general, the TDC output can be expressed as

(28)

where represents the overall quantization error as a com-bined effect of all the involved quantization errors, and themodulo one operation accounts for the fact that TDC outputusually includes no integer part and any overflow would beignored. Substituting (27) into (28) gives us

(29)

This shows that the range of TDC is one RF cycle. Fig. 5(b)illustrates the above relationship of to the signal phase .With a relatively small range to cover, the TDC can be designedfor a high resolution, resulting in very small quantization errors.In our implemented ADPLL, the magnitude of phase quantiza-tion error is expected to be smaller than 0.05, which gives

(30)

The requirement (18), which makes TDC range sufficient forthe fine-tuning loop, translates to

(31)

With the 40-MHz reference frequency, the frequency errorshould be smaller than 16 MHz to ensure the correct operationof the fine-tuning loop. It is a clearly realistic requirement thatallows relatively easy implementation.

E. Summary and Discussion

In this section, we have used mathematical models to ex-amine fundamental principles of frequency error detection inan ADPLL. The result validates the separate operation of VPAand TDC for phase quantization in the proposed architecture.Particularly, it is demonstrated that the TDC alone with a rangeof one DCO output cycle is adequate for phase quantization ifcondition (18) is fulfilled, or in other words, if the actual fre-quency error has a magnitude smaller than half of the referencefrequency by a margin adequate to accommodate the quantiza-tion errors.The condition (18) is in effect the same condition required

for proper operation of glitch correction techniques as usedin [4]–[7]. This common requirement of frequency error canbe better understood by examining the effect of the actual


Fig. 6. Effect of frequency error range in fine tuning mode. (a) Proposed sepa-rate operation (TDC alone for phase quantization), and (b) joint operation. Casea-1 and b-1 represent a pseudo-ideal case where only quantization noise effect istaken into account; Case a-2 represents a real case where the TDC covering onecycle of the RF signal is used for phase digitization; Case b-2 represents a realcase where glitches corrupt the detected frequency error; case b-3 represents areal case where there is a glitch corrector.

frequency error range on the detection result. Such an effectis illustrated in Fig. 6 for both the proposed architecture and atypical architecture in the fine tuning mode.For the proposed architecture, comparison of the two cases

(a-1 and a-2) shows that all the frequency errors would bemapped to the detection range with out-of-range part beingfolded down. The actual frequency error needs to stay withinthe detection range to avoid the folding. This is indicated asthe allowed range in Fig. 6(a), which can be detected withoutdistortion introduced by the finite detection range.In an ADPLL with joint operation of TDC and VPA for phase

digitization, the skew or misalignment between the two circuitblocks generates glitches. The net effect of the glitches is theshifting of detected frequency errors up or down by a magnitudeof one, as illustrated in Fig. 6(b). If the actual frequency errorsare within the same allowed range as indicated in the figure, theglitches can be detected and corrected—the occurrence and po-larity of glitches are equivalent to those of detected frequencyerrors out of the allowed range. To the best of our knowledge,this is the principle of all the known glitch correction techniques.On the other hand, glitch detection and correction would be-come infeasible when the actual frequency errors can go beyondthe allowed range because there would be aliasing effect intro-duced with the glitches.

IV. AUTOMATIC FREQUENCY CALIBRATION

In a conventional PLL, a voltage controlled oscillator (VCO)is typically designed to cover an overall tuning rangewith amul-tiple of sub-band tuning curves in order to minimize its gain fornoise consideration. Likewise, in an ADPLL, it is necessary forthe DCO to cover the overall tuning range using a number ofoverlapping sub-bands such that a fine frequency resolution can

Fig. 7. Flow chart of an idealized binary search AFC.

be used during the ADPLL normal operation to lower the fre-quency quantization effect. In other words, a DCO is often de-signed with more than one frequency control words with onlyof them used during normal PLL phase locking. The role ofautomatic frequency calibration (AFC) in a PLL is to locatethe optimal VCO or DCO sub-band tuning curve for the sub-sequent normal PLL phase locking operation [12]–[14]. As aresult, speed and accuracy of the AFC process is usually keyfor fast PLL frequency settling.In this section, we present a binary search AFC technique

that allows high calibration speed with a very fine resolution.Using an innovative frequency comparison method, the tech-nique minimizes the number of reference cycles used at eachsearch step for a given calibration resolution. Along with themultistage arrangement that optimally exploits different resolu-tions of the VPA and TDC in the coarse-tuning and fine-tuningloops, it greatly reduces the overall frequency settling time ofthe ADPLL.

A. Binary Search AFC Overview

Various binary search AFC techniques have been publishedfor different PLL architectures [12]–[19]. The popularity of bi-nary search for AFC is associated with the implementation sim-plicity and the relatively small number of search steps for agiven resolution. Fig. 7 illustrates an idealized binary search forfrequency acquisition. The binary search works by adjusting theDCO frequency through its control word step by step with thefrequency step size halved for each iteration. It starts by set-ting DCO frequency control word and the step size to their ap-propriate initial values. For each step, a frequency comparisonis performed between the output frequency and the target fre-quency. According to the comparison result, the control wordmay then be changed to step up or down the output frequency.


The iteration goes on until the last step or the target frequencyis reached.A key consideration in real circuit implementations is the fi-

nite resolution of frequency comparison or frequency error de-tection. In analog-intensive approaches such as period-basedfrequency comparison in [12], [13], the resolution is limitedby non-ideal factors such as current mismatch and comparatorinput offset voltage in the analog-intensive approach. In digitalfrequency comparison approaches [14]–[19], the resolution issubject to the limitation of quantization errors.Particularly, the detected frequency error in an ADPLL as

given by (13) is subject to the effect of phase quantization.Whenthe output frequency is close to the target frequency, the quan-tization errors prevent reliable detection of whether the outputfrequency is higher or lower than the target frequency, and thuslimit the frequency calibration resolution. By rewriting (13) as

(32)

we have

(33)

which accounts for the frequency quantization error in Hertz asa result of phase quantization. Let be the peak-to-peakmagnitude of phase quantization error. The frequency quantiza-tion error have a peak magnitude of

(34)

If the detected frequency error is within the range of, it is unknown whether the output fre-

quency is higher or lower than the target frequency. However,it suggests that the output frequency is within a correspondingrange of .Frequency comparison can be performed by comparing

the detected frequency error , respectively with theestimated values of ( and ). Thebinary search finishes whenever falls within the rangeof . As a result, the achievable calibrationresolution in Hertz with the binary search is

(35)

For the TDC phase digitization resolution given by (30), wehave estimated to be 0.1. For a 40-MHz referencefrequency, this corresponds to an 8-MHz calibration resolutionachievable with the binary search. In other words, the outputfrequency error can be as large as 8-MHz after the binarysearch calibration. With this large frequency error, a relativelylong frequency settling time is still needed after the frequencycalibration.A known approach to improve the frequency calibration

resolution is to effectively lower the reference frequency byfrequency division as can be seen from (35). However, thisis simply a tradeoff between time and resolution, and theimprovement of calibration resolution is achieved at the cost ofproportional increase of calibration time. For a fine resolution,the approach tends to excessively slow down the calibrationspeed.

B. The Proposed Binary Search AFC Technique

1) Basic Idea: The common issue of existing binary searchtechniques as in [14]–[19] is that they apply the same compar-ison resolution to each binary search step. This is unnecessarysince the output frequency errors can be much larger than thetarget calibration resolution except for the final step. Therefore,applying the same frequency comparison resolution to each stepleads to waste of time considering the tradeoff relationship be-tween the resolution and time.In the proposed binary search technique, an innovative fre-

quency comparison method is employed to assign a minimumnumber of reference cycles to each step, just to provide adequatefrequency comparison resolution required of the specific step.Suppose the detected frequency error , as given by (32),

is accumulated for cycles from to . It gives us

(36)

If the DCO frequency control word is fixed over the whole timeinterval from th to th reference cycle, theactual output frequency error can be considered as a constantand we can rearrange the above expression as

(37)

with

(38)

where (33) has been used. Apparently, the quantization errorhas the same peak magnitude as given by (34), and we

have

(39)

When the accumulated frequency error is comparedwith , three different scenarios can be distinguishedaccording to (39):a) If , we have , namelythe output is lower than the target frequency.

b) If , we have , namelythe output is higher than the target frequency.

c) If , it is unknownwhether the output frequency is higher or lower thanthe target frequency. However, it suggests the followingrelationship is true:

or

(40)


Fig. 8. Proposed binary search technique in AFC core logic blocks.

The basic idea is that the above frequency error accumula-tion and frequency comparison can be performed simultane-ously without having the number of accumulation cycles fixedfor each step. Instead, the comparison result and the number ofaccumulation cycles can be monitored constantly to allow eachstep to use a minimum number of cycles. The operation can goas follows. Whenever scenario (a) or (b) is detected, the binarysearch proceeds to the next step with the accumulation restarted.In scenario (c), the binary search stays at the current step unlessthe number of accumulation cycles reaches a specific constant.This constant is defined as

(41)

The binary search is terminated whenever the number of cyclesreaches the above value. As a result, we have the following re-lationship at the termination of binary search:

which suggests the calibration resolution is guaranteed.2) Circuit Design: Fig. 8 shows a hardware realization of

the proposed binary search technique in the AFC core logicblocks. It can be roughly divided into four functional blocks.The common functionality of a binary search is performedmainly in the step value generation and step execution blocks.The extended frequency comparison block in conjunction withthe end detection block is largely responsible for the uniquefunctionality required by the proposed approach.The circuit operation is illustrated with the flow chart shown

in Fig. 9. The relevant signals are initialized accordingly duringthe reset state of the ADPLL. For each reference cycle, the fre-quency error is accumulated and the accumulator outputis compared with the predefined values that correspondto the estimated peak-to-peak magnitude of phase quantizationerror.Three different scenarios as previously described can arise

with the comparison result.a) In the first scenario, we have , which tells theoutput frequency is lower than the target frequency. As a

Fig. 9. Flow chart of the AFC technique ( being the word length).

result, the signal up is raised to direct the step executionblock to step up the frequency control word.

b) In the second scenario, where , it suggeststhe output frequency is higher than the target frequency.As a result, the down signal is raised to step down thefrequency control word.

c) The third scenario arises when the accumulated frequencyerror becomes small and we have . Inthis scenario, none of the above signals would be assertedand the binary search stays in the current step with thefrequency control word and step size unchanged.

In both of the first two scenarios, the signal nxtStep is as-serted, which allows the step value to be halved by a simplebit shifting for next search step. The content of the frequencyerror accumulator and the accumulation cycle counter would becleared in the next reference cycle by the signal clr that is de-rived from nxtStep with a unit delay. In the third scenario, thefrequency error is accumulated for each reference cycle with thenumber of accumulation cycles counted. If the ADPLL outputfrequency error is larger than the expected calibration resolu-tion, the circuit would get out of the third scenario and enterone of the first two scenarios after a certain number of referencecycles. Otherwise, the counted accumulation number cnt would


reach the predefined maximum value and terminate thebinary search. Upon completion, the done signal is raised, whichwould stall the clock for the AFC circuit.Note that the binary search would also finish if the last step

is reached, which can be detected by monitoring the step value.This however means the minimum frequency step is too largefor the expected calibration resolution, and its occurrence isusually prevented by ensuring in design that the minimum fre-quency step is adequately small. This exit condition, as indi-cated by the dashed line in the flow chart, is only for backuppurpose. It makes the circuit more robust by avoiding the possi-bility of indefinite iteration when the minimum step accidentallyhappens to be too large due to design or implementation issues.In a proper design, the exit condition corresponds to a possibleoccurrence of the rare retiming metastability, which can be cor-rected by rerunning the binary search.Another important consideration is related to the loop latency

of a digital PLL. When the DCO output frequency is updatedwith its frequency control word, its detection comes one refer-ence cycle later since there are two unit delays in the ADPLLloop, one at the DCO input and the other at the phase detection.In the reference cycle following the frequency word update tothe DCO, the detected frequency error is an outdated one. It cor-responds to the frequency prior to the updating, and thus shouldnot be used. This is done in the circuit by clearing the accu-mulator when one step is finished as shown in both the circuitschematic and flow chart. This leads to an additional delay ofone reference cycle introduced to each iteration step. However,it should be noted that the loop latency of two unit delays is theresult of digital frequency control, which entails a unit delayat the DCO input to align and synchronize different bits of thefrequency control word. It is neither associated with any binarysearch technique, and nor is it unique to the specific ADPLL ar-chitecture.3) Performance Evaluation: The number of reference cycles

for the th step in the binary search is can be estimated as

(42)

where represents the magnitude of the correspondingoutput frequency error seen at the search step. The total numberof reference cycles for the binary search can be expressed as

(43)

where the index number of the last binary search step is givenby

(44)

Let us define as the magnitude ratio of the effective fre-quency quantization error to the target frequency calibration res-olution, namely

(45)

It allows us to rewrite (43) to the following:

(46)

Apparently, the worst case scenario corresponds to the situa-tion where all the for each step assume possible minimumvalues and there are a maximum number of steps performed. Inthis worst case scenario, we have

(47)

The represents the th minimum value of for allthe steps and can be estimated as

The maximum number of steps in the binary search can beexpressed as

with being the frequency range covered by the binarysearch. Substitution of allows us to rewrite (47) as fol-lows:

(48)

with each being a constant given by

It is noteworthy that we would arrive at the total reference cyclenumber for a conventional binary search technique if we seteach to 1 in (48). Speed gain of the proposed binary searchtechnique over a conventional one is reflected in the fact that

for all relevant values. This speed gain can be de-fined as

(49)

where the denominator represents a conventional binary searchwith the number of reference cycles fixed for each step.The gain of (49) is plotted in Fig. 10 as a function of and. It grows almost proportionally with the number of total

binary search steps, which means that speed advantage of the


Fig. 10. Calibration speed gain of the proposed approach.

Fig. 11. Numerically evaluated as a function of with .

proposed technique over a conventional one becomes more sig-nificant for a higher calibration resolution. For , thespeed gain is about 3. Fig. 11 shows an example of the totalreference cycle number needed for both the proposed approachand a conventional one where the number of reference cyclesfor each step is fixed. It suggests that the number of referencecycles for reach step increases almost linearly with the targetfrequency calibration resolution in both approaches, but the in-crease is much slower in the proposed approach than a conven-tional one.

C. Summary and Discussion

In this section, the proposed binary search AFC technique forthe ADPLL has been presented. With an innovative frequencycomparison approach, the technique minimizes the number ofreference cycles for each search step and thus minimizes theoverall search time for a given calibration resolution. Allowingfully digital implementation, it is perfectly compatible with theADPLL architecture and has the benefit of good programma-bility associated its digital nature. Particularly, by using a mul-tistage arrangement, it is capable of optimally exploiting the dif-ferent phase quantization resolutions of VPA and TDC.One thing is that the possibility of the metastability due to the

frequency reference retiming remains during the coarse tuning.This potential metastability could in principle generate incorrect

detected frequency error and lead the binary search AFC to thewrong direction. This however can be detected based on theresulted unusual binary search state and corrected by simplyrerunning the binary search process.Other techniques based on adaptive loop bandwidth have

been reported for PLL fast frequency settling [20]–[22], wherefrequency calibration is essentially achieved by means ofPLL phase locking. A major limitation of adaptive frequencycalibration techniques is that their performance is subject tothe effect of PVT variations of DCO gain. Different DCO gainleads to different PLL loop bandwidth. As a result, optimumsetting and timing for the loop bandwidth could be difficult.Meanwhile, the techniques of frequency estimation and pre-

setting to speed up PLL frequency settling has also been ex-plored in the literature [23], [24]. However, the limitation ofthese type of techniques is that the achievable resolution is typi-cally very coarse in comparison. Accurate frequency presettingis very difficult to achieve due to the PVT variation of DCO gainand nonlinearity of DCO coarse tuning.

V. EXPERIMENTAL RESULTS

The ADPLL has been implemented using a 65-nm CMOSwith both the architectural modification and the proposed AFCtechnique. The DCO is based on a ring oscillator to cover awide frequency range from 3 to 6 GHz. Four current-switchingbanks are employed in the DCO for frequency tuning to allowa large tuning range with a fine frequency resolution. Two ofthe tuning banks are used for initial frequency calibration bythe coarse-tuning loop. Correspondingly, there are two binarysearch stages in the coarse AFC logic, with most of the logicshared using multiplexing. The final ADPLL fine-tuning branchcontrols the last tuning bank with the finest resolution. Theo-retical calculation based on (47) predicts a worst case settlingtime of about 6 s for a 200-kHz frequency tolerance. Withboth simulations and measurements, the ADPLL was shown tohave a maximum settling time slightly shorter than the theoret-ical predication. The result amounts to a reduction of 14 s anda speed gain of over three compared with our previous ADPLLdesign [19], which was based on the typical architecture witha basic binary search technique. Fig. 12 shows an overall fre-quency settling process of the ADPLL for a target frequencyof 4.5-GHz. Measured frequency settling process for the sametarget frequency is shown in Fig. 13. The achieved frequencysettling performance is clearly beyond the current state-of-art.It should be noted that DCO nonlinearity and other nonidealfactors are the reasons causing the difference between the simu-lated andmeasured frequency settling processes. However, theireffect on the overall settling time was shown to be very limited,which confirms the usefulness of the previous analysis result.A die photograph is shown in Fig. 14, where the whole

ADPLL occupies an active area of about 0.07 mm . Besidesthe DCO, the VPA and TDC are also custom designed forhigh-speed operation to handle the RF signal. The rest loopcircuitry is realized as a pure digital logic block, which occu-pies about 0.05 mm . This digital area is about one third ofthe digital area in our previous ADPLL design [19]. The sub-stantial reduction can be mainly attributed to the architectural


Fig. 12. Simulated ADPLL frequency settling.

Fig. 13. Measured frequency settling.

Fig. 14. Die photograph.

modification associated with the improved phase digitizationapproach.

Fig. 15. Measured and simulated ADPLL phase noise.

Fig. 16. Measured ADPLL spectrum (the major spurs appear at intervals ofreference frequency).

TABLE IPERFORMANCE SUMMARY

The whole ADPLL has a maximum power consumption ofabout 10 mW from a 1.2-V supply. The measured output fre-quency range is from 2.7 to 7.3 GHz. The measured phase noiseat 1-MHz frequency offset is about 80 dBc/Hz and the in-bandphase noise level is about 70 dBc/Hz. Fig. 15 shows an ex-ample of measured phase noise at 4.5-GHz output frequencyalong with the simulated result. It should be noted that the noisyring DCO also limits the ADPLL in-band phase noise perfor-mance. This is because the excessive in-band phase noises ofthe DCO can still be dominating even after greatly suppressedby the feedback loop. Meanwhile, the DCO far-off phase noises


TABLE IIPERFORMANCE COMPARISON ON PLL FREQUENCY SETTLING

are folded back to low offset frequencies due to sub-sampling ef-fect of the feedback path [25]. The measured spectrum is shownin Fig. 16. The relatively high reference spurs as observed in thespectrum are associated with the use of a digital loop filter andthe ring oscillator. A ring oscillator as adopted in our implemen-tation is sensitive to the supply and ground disturbance, whicheffectively picks up the interferences from digital switching inthe reference clock domain and generates reference spurs in theoutput spectrum. Meanwhile, a digital loop filter, does not sup-press reference spurs but instead contributes to them due to itsclocking at reference frequency.Table I provides a performance summary of the implemented

ADPLL, where the values refer to the worst case scenarios. Theoverall achieved result is overwhelmingly favorable comparedwith existing ADPLL designs for a wide-band application. Itfully demonstrates the advantages of the modified ADPLL ar-chitecture and the frequency calibration technique. A perfor-mance comparison with prior works on fast PLL frequency set-tling are given in Table II.

VI. CONCLUSION

In this paper, we have presented a new ADPLL design thatfeatures separate use of VPA and TDC in the feedback forphase digitization as opposed to commonplace joint use of thetwo circuit blocks. The separation simplifies implementation,resulting in reduced silicon area and lower power consumption,while it also allows more robust operation of the ADPLL.In addition, the ADPLL also employs a new binary searchtechnique for frequency calibration. By allowing a minimumnumber of reference cycles to be used for each search stepaccording to the target calibration resolution, the technique iscapable of achieving a fine frequency calibration resolutionwith a greatly reduced time as compared with a conventionalbinary search technique. The validity and advantages of theoriginal techniques have been demonstrated through theoreticalanalysis, numerical simulations as well as experimental resultswith an ADPLL implementation in a 65-nm CMOS.

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Liangge Xu (S’08) received the B.Sc. degree inmaterials engineering from Northeastern University,Shenyang, China, in 1996, and the M.Sc. degreein electrical engineering from Helsinki Universityof Technology, Helsinki, Finland, in 2007. He iscurrently pursuing the Ph.D. degree at the sameuniversity now known as Aalto University.He was also a Researcher with the Department

of Micro and Nanosciences, Helsinki University ofTechnology, from 2007 to 2011. He is currently a Se-nior RFIC Designer and a team lead with Renesas

Mobile, Helsinki, Finland.

Kari Stadius (S’95–M’03) received the M.Sc., Lic.Tech., and Doctor of Science degrees in electricalengineering from the Helsinki University of Tech-nology, Helsinki, Finland, in 1994, 1997, and 2010,respectively.He is currently working as a Senior Researcher in

the Department of Micro- and Nanosciences, AaltoUniversity School of Electrical Engineering. His re-search interests include the design and analysis of RFtransceiver blocks, and new emerging RF technolo-gies, such as graphene.

Jussi Ryynänen (S’99–M’04) was born in Ilmajoki,Finland, in 1973. He received theM.Sc., Lic.Sci., andDoctor of Science degrees in electrical engineeringfrom the Helsinki University of Technology (HUT),Helsinki, Finland, in 1998, 2001, and 2004, respec-tively.He is currently working as an associate professor

in the Department of Micro- and Nanosciences,Aalto University School of Electrical Engineering.His main research interests are on integrated trans-ceiver circuits for wireless applications. He has

authored or coauthored over 90 refereed journal and conference papers in theareas of analog and RF circuit design. He holds six patents on RF circuits

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An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique