AMC1302 CMTI ±50mV の広帯域に対応(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states

HV+

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RSHUNT

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AMC1302

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OUTN

VDD2

GND2GND1

INP

INN

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英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SBAS812

AMC1302JAJSFO3C –JUNE 2018–REVISED JANUARY 2020

参参考考資資料料

AMC1302 高高精精度度強強化化絶絶縁縁アアンンププ高高CMTI、、±50mVのの入入力力電電圧圧範範囲囲、、280kHzのの広広帯帯域域にに対対応応

1

1 特特長長1• ±50mV の入力電圧範囲により低消費電力のシャン

ト抵抗方式電流測定を実現• 固定ゲイン、低ドリフト：41 ±0.3%、±50 ppm/• 小さい入力オフセットとドリフト：±100µV、±

0.8µV/• 小さい非線形性とドリフト：±0.03%、±1ppm/• 3.3V 電源での動作時、絶縁されたハイサイドは超

低消費電力• システム・レベル診断機能• 安全関連の認定

– DIN VDE V 0884-11: 2017-01 に準拠した強化絶縁耐圧：7071VPK

– UL 1577 に準拠した絶縁耐圧：5000VRMS (1 分間)

• 拡張産業用温度範囲：-55°C ～ +125°C• 高いCMTI：80kV/µs（標準値）、55kV/µs（最小

値）

2 アアププリリケケーーシショョンン次のような機器で使用する、シャント抵抗方式電流センシング

• モータ・ドライブ

• 航空

• パワー・デリバリ

• 産業用輸送

• 家電製品

• グリッド・インフラストラクチャ

3 概概要要AMC1302は高精度の絶縁アンプで、磁気干渉に対して

高い耐性のある容量性絶縁膜を備えています。この絶縁

膜は耐用年数が非常に長く、低消費電力で、5kVRMS (最大値)の強化絶縁を実現します。絶縁電源と組み合わせて

使用することで、異なる同相電圧レベルで動作する部品を

互いに絶縁できます。さらに、AMC1302は低電圧デバイ

スを損傷から保護します。

AMC1302の入力は、シャント抵抗または他の低電圧レベ

ルの信号源との直接接続用に最適化されています。±50mVの入力電圧範囲により、シャントを経由する消費電

力が大幅に低減されます。また、AMC1302のハイサイド

電源電流/電圧は低いため、低コストの絶縁電源ソリュー

ションを採用できます。優れた性能により、電流を正確に

制御して、システムレベルの消費電力の削減と、特にモー

タ制御において重要な低トルク・リップルを実現します。

AMC1302には入力同相過電圧検出機能とハイサイド電

源電圧喪失検出機能が内蔵されているため、システムレ

ベルの診断が容易になります。

製製品品情情報報(1)

型型番番パパッッケケーージジ本本体体ササイイズズ（（公公称称））

AMC1302 SOIC (8) 5.85mm×7.50mm

(1) 提供されているすべてのパッケージについては、巻末の注文情報を参照してください。

概概略略回回路路図図

http://www-s.ti.com/sc/techlit/SBAS812.pdf

http://www.tij.co.jp/product/jp/amc1302?qgpn=amc1302

http://www.tij.co.jp/product/jp/AMC1302?dcmp=dsproject&hqs=pf

http://www.tij.co.jp/product/jp/AMC1302?dcmp=dsproject&hqs=sandbuy&#samplebuy

http://www.tij.co.jp/product/jp/AMC1302?dcmp=dsproject&hqs=td&#doctype2

http://www.tij.co.jp/product/jp/AMC1302?dcmp=dsproject&hqs=sw&#desKit

http://www.tij.co.jp/product/jp/AMC1302?dcmp=dsproject&hqs=support&#community

2

AMC1302JAJSFO3C –JUNE 2018–REVISED JANUARY 2020 www.ti.com

Copyright © 2018–2020, Texas Instruments Incorporated

目目次次1 特特長長.......................................................................... 12 アアププリリケケーーシショョンン ......................................................... 13 概概要要.......................................................................... 14 改改訂訂履履歴歴................................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 46.2 ESD Ratings.............................................................. 46.3 Recommended Operating Conditions....................... 46.4 Thermal Information .................................................. 56.5 Power Ratings........................................................... 56.6 Insulation Specifications............................................ 66.7 Safety-Related Certifications..................................... 76.8 Safety Limiting Values .............................................. 76.9 Electrical Characteristics........................................... 76.10 Switching Characteristics ........................................ 96.11 Insulation Characteristics Curves ......................... 106.12 Typical Characteristics .......................................... 11

7 Detailed Description ............................................ 187.1 Overview ................................................................. 18

7.2 Functional Block Diagram ....................................... 187.3 Feature Description................................................. 197.4 Device Functional Modes........................................ 21

8 Application and Implementation ........................ 228.1 Application Information............................................ 228.2 Typical Application .................................................. 228.3 What to Do and What Not to Do ............................. 24

9 Power Supply Recommendations ...................... 2510 Layout................................................................... 26

10.1 Layout Guidelines ................................................. 2610.2 Layout Example .................................................... 26

11 デデババイイススおおよよびびドドキキュュメメンントトののササポポーートト ....................... 2711.1 デバイス・サポート ................................................... 2711.2 ドキュメントのサポート ............................................. 2711.3 ドキュメントの更新通知を受け取る方法..................... 2711.4 コミュニティ・リソース ................................................ 2711.5 商標 ....................................................................... 2711.6 静電気放電に関する注意事項 ................................ 2711.7 Glossary ................................................................ 27

12 メメカカニニカカルル、、パパッッケケーージジ、、おおよよびび注注文文情情報報 ................. 28

4 改改訂訂履履歴歴資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。

Revision B (November 2018) かからら Revision C にに変変更更 Page

• 「特長」の「安全関連の認定」の箇条書き項目の VDE 認定を DIN V VDE V 0884-11 (VDE V 0884-11) から DIN VDE V0884-11 に変更 ...................................................................................................................................................................... 1

• Changed VDE certificate format from DIN V VDE V 0884-11 (VDE V 0884-11) to DIN VDE V 0884-11 in DIN VDE V0884-11: 2017-01 header row of Insulation Specifications table ........................................................................................... 6

• Changed VDE certificate details in Safety-Related Certifications table ................................................................................. 7

Revision A (September 2018) かからら Revision B にに変変更更 Page

• 「特長」セクションで「高いCMTI」の仕様を「140kV/µs（標準値）、70kV/µs（最小値）」から「80kV/µs（標準値）、55kV/µs（最小値）」に変更 ............................................................................................................................................................................. 1

• Changed PSRR specifications in Electrical Characteristics table ......................................................................................... 8• Changed footnote 3 in PSRR parameter from output referred to input referred .................................................................... 8• 変更 Power-Supply Rejection Ratio vs Ripple Frequency figure.......................................................................................... 16• 変更 CMTI value in 表 1 from 140 kV/µs (typical) to 80 kV/µs (typical) ............................................................................... 23

2018年年6月月発発行行ののももののかからら更更新新 Page

• デバイスのステータスを「事前情報」から「量産データ」に変更 .................................................................................................... 1

http://www.ti.com/product/amc1302?qgpn=amc1302

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1VDD1 8 VDD2

2INP 7 OUTP

3INN 6 OUTN

4GND1 5 GND2

Not to scale

3

AMC1302www.ti.com JAJSFO3C –JUNE 2018–REVISED JANUARY 2020


5 Pin Configuration and Functions

DWV Package8-Pin SOICTop View

Pin FunctionsPIN

I/O DESCRIPTIONNO. NAME

1 VDD1 — High-side power supply, 3.0 V to 5.5 V.See the Power Supply Recommendations section for power-supply decoupling recommendations.

2 INP I Noninverting analog input3 INN I Inverting analog input4 GND1 — High-side analog ground5 GND2 — Low-side analog ground6 OUTN O Inverting analog output7 OUTP O Noninverting analog output

8 VDD2 — Low-side power supply, 3.0 V to 5.5 V.See the Power Supply Recommendations section for power-supply decoupling recommendations.


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4



(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratingssee (1)

MIN MAX UNIT

Power-supply voltageVDD1 to GND1 –0.3 6.5

VVDD2 to GND2 –0.3 6.5

Input voltage INP, INN GND1 – 6 VDD1 + 0.5 VOutput voltage OUTP, OUTN GND2 – 0.5 VDD2 + 0.5 VInput current Continuous, any pin except power-supply pins –10 10 mA

TemperatureJunction, TJ 150

°CStorage, Tstg –65 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000

(1) Steady-state voltage supported by the device in case of a system failure. See the specified common-mode input voltage VCM for normaloperation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.

6.3 Recommended Operating Conditionsover operating ambient temperature range (unless otherwise noted)

MIN NOM MAX UNITPOWER SUPPLY

High-side power supply VDD1 to GND1 3.0 5 5.5 VLow-side power supply VDD2 to GND2 3.0 3.3 5.5 V

ANALOG INPUTSVClipping Differential input voltage before clipping output VIN = VINP – VINN ±64 mVVFSR Specified linear differential input full-scale VIN = VINP – VINN –50 50 mV

Absolute common-mode input voltage (1) (VINP + VINN) / 2 to GND1 –2 VDD1 VVCM Operating common-mode input voltage (VINP + VINN) / 2 to GND1 –0.032 VDD1 – 2.2 VTEMPERATURE RANGETA Specified ambient temperature –55 125 °C


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5



(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

6.4 Thermal Information

THERMAL METRIC (1)AMC1302

UNITDWV (SOIC)8 PINS

RθJA Junction-to-ambient thermal resistance 85.4 °C/WRθJC(top) Junction-to-case (top) thermal resistance 26.8 °C/WRθJB Junction-to-board thermal resistance 43.5 °C/WψJT Junction-to-top characterization parameter 4.8 °C/WψJB Junction-to-board characterization parameter 41.2 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

6.5 Power RatingsPARAMETER TEST CONDITIONS VALUE UNIT

PD Maximum power dissipation (both sides)VDD1 = VDD2 = 5.5 V 98.45

mWVDD1 = VDD2 = 3.6 V 56.52

PD1 Maximum power dissipation (high-side supply)VDD1 = 5.5 V 53.90

mWVDD1 = 3.6 V 30.60

PD2 Maximum power dissipation (low-side supply)VDD2 = 5.5 V 44.55

mWVDD2 = 3.6 V 25.92


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http://www.ti.com/lit/pdf/spra953


6



(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must betaken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printedcircuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such asinserting grooves, ribs, or both on a PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured bymeans of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.(4) Apparent charge is electrical discharge caused by a partial discharge (pd).(5) All pins on each side of the barrier are tied together, creating a two-pin device.

6.6 Insulation Specificationsover operating ambient temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VALUE UNITGENERALCLR External clearance (1) Shortest pin-to-pin distance through air ≥ 8.5 mmCPG External creepage (1) Shortest pin-to-pin distance across the package surface ≥ 8.5 mm

DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation(2 × 0.0105 mm) ≥ 0.021 mm

CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 VMaterial group According to IEC 60664-1 I

Overvoltage categoryper IEC 60664-1

Rated mains voltage ≤ 300 VRMS I-IVRated mains voltage ≤ 600 VRMS I-IVRated mains voltage ≤ 1000 VRMS I-III

DIN VDE V 0884-11: 2017-01 (2)

VIORMMaximum repetitive peakisolation voltage At AC voltage 2121 VPK

VIOWMMaximum-rated isolationworking voltage

At AC voltage (sine wave); see 図 4 1500 VRMS

At DC voltage 2121 VDC

VIOTMMaximum transientisolation voltage

VTEST = VIOTM, t = 60 s (qualification test) 7071VPKVTEST = 1.2 × VIOTM, t = 1 s (100% production test) 8485

VIOSMMaximum surgeisolation voltage (3)

Test method per IEC 60065, 1.2/50-µs waveform,VTEST = 1.6 × VIOSM = 12800 VPK (qualification) 8000 VPK

qpd Apparent charge (4)

Method a, after input/output safety test subgroup 2 / 3,Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s ≤ 5

pCMethod a, after environmental tests subgroup 1,Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s ≤ 5

Method b1, at routine test (100% production) and preconditioning (type test),Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s ≤ 5

CIOBarrier capacitance,input to output (5) VIO = 0.5 VPP at 1 MHz ~1 pF

RIOInsulation resistance,input to output (5)

VIO = 500 V at TA = 25°C > 1012

ΩVIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011

VIO = 500 V at TS = 150°C > 109

Pollution degree 2Climatic category 55/125/21

UL1577

VISO Withstand isolation voltage VTEST = VISO = 5000 VRMS or 7071 VDC, t = 60 s (qualification),VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test) 5000 VRMS


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7



6.7 Safety-Related CertificationsVDE UL

Certified according to DIN VDE V 0884-11: 2017-01, DIN EN 62368-1:2016-05, EN 62368-1: 2014, and IEC 62368-1: 2014

Recognized under 1577 component recognition andCSA component acceptance NO 5 programs

Reinforced insulation Single protectionCertificate number: 40040142 File number: E181974

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The ISand PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. Theselimits vary with the ambient temperature, TA.The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board forleaded surface-mount packages. Use these equations to calculate the value for each parameter:TJ = TA + RθJA × P, where P is the power dissipated in the device.TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.PS = IS × VDD1max + IS × VDD2max, where VDD1max is the maximum high-side voltage and VDD2max is the maximum low-side supplyvoltage.

6.8 Safety Limiting ValuesSafety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISSafety input, output,or supply current

RθJA = 85.4°C/W, TJ = 150°C, TA = 25°C,VDD1 = VDD2 = 5.5 V, see 図 2 266

mARθJA = 85.4°C/W, TJ = 150°C, TA = 25°C,VDD1 = VDD2 = 3.6 V, see 図 2 406

PSSafety input, output,or total power (1) RθJA = 85.4°C/W, TJ = 150°C, TA = 25°C, see 図 3 1463 mW

TS Maximum safety temperature 150 °C

(1) The typical value includes one sigma statistical variation.(2) See 図 47.

6.9 Electrical Characteristicsminimum and maximum specifications apply from TA = –55°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP= –50 mV to +50 mV, and INN = GND1 = 0 V; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unlessotherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITANALOG INPUT

VCMovCommon-mode overvoltagedetection level (VINP + VINN) / 2 to GND1 VDD1 – 2.1 V

Hysteresis of common-modeovervoltage detection level 60 mV

VOS Input offset voltage (1) initial, at TA = 25°C, VINP = VINN = GND1 –100 ±10 100 μVTCVOS Input offset drift (1) –0.8 ±0.15 0.8 µV/°C

CMRR Common-mode rejectionratio

fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max –100dB

fIN = 10 kHz, VCM min ≤ VCM ≤ VCM max –98

CINSingle-ended inputcapacitance (2) INN = GND1, fIN = 300 kHz 4 pF

CINDDifferential inputcapacitance (2) fIN = 300 kHz 2 pF

RINSingle-ended inputresistance (2) INN = GND1 4.75 kΩ

RINDDifferential inputresistance (2) 4.9 kΩ

IIB Input bias current INP = INN = GND1; IIB = (IIBP + IIBN) / 2 –48.5 –36 –28.5 μATCIIB Input bias current drift ±1.5 nA/°CIIO Input offset current IIO = IIBP – IIBN ±10 nA


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8



Electrical Characteristics (continued)minimum and maximum specifications apply from TA = –55°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP= –50 mV to +50 mV, and INN = GND1 = 0 V; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unlessotherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(3) This parameter is input referred.

ANALOG OUTPUTNominal gain 41

EG Gain error (1) initial, at TA = 25°C –0.3% ±0.05% 0.3%TCEG Gain error drift (1) –50 ±15 50 ppm/°C

Nonlinearity (1) –0.03% ±0.01% 0.03%Nonlinearity drift ±1 ppm/°C

THD Total harmonic distortion VIN = 100 mVPP, fIN = 10 kHz, BW = 100 kHz –85 dBOutput noise VINP = VINN = GND1, BW = 100 kHz 260 μVRMS

SNR Signal-to-noise ratioVIN = 100 mVPP, fIN = 1 kHz, BW = 10 kHz 80 84

dBVIN = 100 mVPP, fIN = 10 kHz, BW = 100 kHz 70

PSRR Power-supply rejectionratio (3)

PSRR vs VDD1, at DC –113

dBPSRR vs VDD1, 100-mV and 10-kHz ripple –108PSRR vs VDD2, at DC –116PSRR vs VDD2, 100-mV and 10-kHz ripple –87

VCMoutCommon-mode outputvoltage 1.39 1.44 1.49 V

VFAILSAFEFailsafe differential outputvoltage VCM > VCMov or VDD1 ≤ VDD1UV –2.6 –2.5 V

BW Output bandwidth 220 280 kHzROUT Output resistance On OUTP or OUTN < 0.2 Ω

Output short-circuit current ±14 mA

CMTI Common-mode transientimmunity |GND1 – GND2| = 1 kV 55 80 kV/µs

POWER SUPPLY

VDD1PORVDD1 power on resetthreshold voltage VDD1 falling 1.75 2.15 2.7 V

IDD1 High-side supply current3.0 V ≤ VDD1 ≤ 3.6 V 6.2 8.5

mA4.5 V ≤ VDD1 ≤ 5.5 V 7.2 9.8

IDD2 Low-side supply current3.0 V ≤ VDD2 ≤ 3.6 V 5.3 7.2

mA4.5 V ≤ VDD2 ≤ 5.5 V 5.9 8.1


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VINP - VINN

VOUTP

VOUTN

50% - 10%

0.05 V

0 V

50%

50% - 50% 50% - 90%

10% 50%

tr tf

VCMout 90%

9

AMC1302www.tij.co.jp JAJSFO3C –JUNE 2018–REVISED JANUARY 2020


6.10 Switching Characteristicsover operating ambient temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITtr Rise time of OUTP, OUTN See 図 1 1.3 µstf Fall time of OUTP, OUTN See 図 1 1.3 µs

INP, INN to OUTP, OUTN signaldelay (50% – 10%) Unfiltered output, see 図 1 1.0 1.5 µs



tAS Analog startup time VDD1 step to 3.0 V with VDD2 ≥ 3.0 V,to OUTP, OUTN valid, 0.1% settling 500 µs

図図 1. Rise, Fall, and Delay Time Waveforms


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Stress Voltage (VRMS)

Tim

e to

Fa

il (s

)

500 1500 2500 3500 4500 5500 6500 7500 8500 95001.E+1

1.E+2

1.E+3

1.E+4

1.E+5

1.E+6

1.E+7

1.E+8

1.E+9

1.E+10

1.E+11Safety Margin Zone: 1800 VRMS, 254 Years

Operating Zone: 1500 VRMS, 135 Years

20%

87.5% TDDB Line (<1 PPM Fail Rate)

TA (°C)

I S (

mA

)

0 25 50 75 100 125 1500

50

100

150

200

250

300

350

400

450

D001

VDD1 = VDD2 = 3.6 VVDD1 = VDD2 = 5.5 V

TA (°C)

PS (

mW

)

0 25 50 75 100 125 1500

200

400

600

800

1000

1200

1400

1600

D002

10

AMC1302JAJSFO3C –JUNE 2018–REVISED JANUARY 2020 www.tij.co.jp


6.11 Insulation Characteristics Curves

図図 2. Thermal Derating Curve for Safety-Limiting Current perVDE

図図 3. Thermal Derating Curve for Safety-LimitingPower per VDE

TA up to 150°C, stress-voltage frequency = 60 Hz,isolation working voltage = 1500 VRMS, operating lifetime = 135 years

図図 4. Reinforced Isolation Capacitor Lifetime Projection



VDDx (V)

VO

S (P

V)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5-100

-75

-50

-25

0

25

50

75

100

D007

vs VDD1vs VDD2

Temperature (°C)

VO

S (P

V)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125-100

-75

-50

-25

0

25

50

75

100

D009

Device 1Device 2Device 3

VOS (PV)

De

vic

es (

%)

0

10

20

30

40

50

-10

0

-90

-80

-70

-60

-50

-40

-30

-20

-10 0

10

20

30

40

50

60

70

80

90

10

0

D005 VOS (PV)

De

vic

es (

%)

0

10

20

30

40

50

-10

0

-90

-80

-70

-60

-50

-40

-30

-20

-10 0

10

20

30

40

50

60

70

80

90

10

0

D006

VDD1 (V)

VC

Mo

v (

V)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.51

1.4

1.8

2.2

2.6

3

3.4

3.8

D003Temperature (qC)

VC

Mo

v (

V)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 1252.9

2.95

3

3.05

3.1

3.15

3.2

3.25

3.3

D004

11



6.12 Typical Characteristicsat TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VINP = –50 mV to 50 mV, VINN = GND1, and fIN = 10 kHz (unless otherwisenoted)

図図 5. Common-Mode Overvoltage Detection Levelvs High-Side Supply Voltage

図図 6. Common-Mode Overvoltage Detection Levelvs Temperature

VDD1 = 3.3 V

図図 7. Input Offset Voltage Histogram

VDD1 = 5 V

図図 8. Input Offset Voltage Histogram

図図 9. Input Offset Voltage vs Supply Voltage 図図 10. Input Offset Voltage vs Temperature



VCM (V)

I IB (P

A)

-0.5 0 0.5 1 1.5 2 2.5 3 3.5-80

-60

-40

-20

0

20

40

60

D014VDD1 (V)

I IB (P

A)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5-45

-43

-41

-39

-37

-35

-33

-31

-29

-27

D015

fIN (kHz)

CM

RR

(d

B)

0.001 0.01 0.1 1 10 100 1000-120

-100

-80

-60

-40

-20

0

D012Temperature (°C)

CM

RR

(d

B)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125-115

-110

-105

-100

-95

-90

-85

-80

-75

D013

TCVOS (PV/qC)

De

vic

es (

%)

0

10

20

30

40

50

60

70

80

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

D010 TCVOS (PV/qC)

Devic

es (

%)

0

10

20

30

40

50

60

70

80

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

D011

12



Typical Characteristics (continued)at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VINP = –50 mV to 50 mV, VINN = GND1, and fIN = 10 kHz (unless otherwisenoted)

VDD1 = 3.3 V

図図 11. Input Offset Drift Histogram

VDD1 = 5 V

図図 12. Input Offset Drift Histogram

図図 13. Common-Mode Rejection Ratiovs Input Frequency

図図 14. Common-Mode Rejection Ratiovs Temperature

図図 15. Input Bias Currentvs Common-Mode Input Voltage

図図 16. Input Bias Currentvs High-Side Supply Voltage



Temperature (°C)

EG

(%

)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125-0.3

-0.2

-0.1

0

0.1

0.2

0.3

D020


TCEG (ppm/qC)

Devic

es (

%)

0

5

10

15

20

25

30

35

40

-45

-40

-35

-30

-25

-20

-15

-10 -5 5

10

15

20

25

30

35

40

45

D021

VDDx (V)

EG

(%

)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5-0.3

-0.2

-0.1

0

0.1

0.2

0.3

D019

vs VDD1vs VDD2

EG (%)

De

vic

es (

%)

0

10

20

30

40

50

-0.3

-0.2

5

-0.2

-0.1

5

-0.1

-0.0

5 0

0.0

5

0.1

0.1

5

0.2

0.2

5

0.3

D018

Temperature (°C)

I IB (P

A)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125-45

-43

-41

-39

-37

-35

-33

-31

-29

-27

D016 EG (%)

Devic

es (

%)

0

10

20

30

40

50

-0.3

-0.2

5

-0.2

-0.1

5

-0.1

-0.0

5 0

0.0

5

0.1

0.1

5

0.2

0.2

5

0.3

D017

13




図図 17. Input Bias Current vs Temperature

VDD2 = 3.3 V

図図 18. Gain Error Histogram

VDD2 = 5 V

図図 19. Gain Error Histogram 図図 20. Gain Error vs Supply Voltage

図図 21. Gain Error vs Temperature

VDD1 = 3.3 V

図図 22. Gain Error Drift Histogram



Differential Input Voltage (mV)

No

nlin

ea

rity

(%

)

-50 -40 -30 -20 -10 0 10 20 30 40 50-0.03

-0.02

-0.01

0

0.01

0.02

0.03

D026VDDx (V)

No

nlin

ea

rity

(%

)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5-0.03

-0.02

-0.01

0

0.01

0.02

0.03

D027

vs VDD1vs VDD2

fIN (kHz)

Outp

ut P

hase

0.01 0.1 1 10 100 1000-360°

-315°

-270°

-225°

-180°

-135°

-90°

-45°

0°

D024Differential Input Voltage (mV)

VO

UT (

V)

-70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 700

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

D025

VOUTN

VOUTP

fIN (kHz)

Norm

aliz

ed G

ain

(d

B)

0.01 0.1 1 10 100 1000-40

-35

-30

-25

-20

-15

-10

-5

0

5

D023TCEG (ppm/qC)

De

vic

es (

%)

0

5

10

15

20

25

30

35

40

-45

-40

-35

-30

-25

-20

-15

-10 -5 5

10

15

20

25

30

35

40

D022

14




VDD1 = 5 V

図図 23. Gain Error Drift Histogram 図図 24. Normalized Gain vs Input Frequency

図図 25. Output Phase vs Input Frequency 図図 26. Output Voltage vs Input Voltage

図図 27. Nonlinearity vs Input Voltage 図図 28. Nonlinearity vs Supply Voltage



|VINP - VINN| (mV)

SN

R (

dB

)

0 5 10 15 20 25 30 35 40 45 50 5530

35

40

45

50

55

60

65

70

75

D032VDDx (V)

SN

R (

dB

)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.565

66

67

68

69

70

71

72

73

74

75

D033

vs VDD1vs VDD2

Temperature (°C)

TH

D (

dB

)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125-100

-95

-90

-85

-80

-75

-70

D030


Frequency (kHz)

Nois

e D

ensity (P

V/

Hz)

0.1 1 10 100 10000.1

1

10

D031

Temperature (°C)

No

nlin

ea

rity

(%

)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125-0.03

-0.02

-0.01

0

0.01

0.02

0.03

D028


VDDx (V)

TH

D (

dB

)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5-100

-95

-90

-85

-80

-75

-70

D029

vs VDD1vs VDD2

15




図図 29. Nonlinearity vs Temperature 図図 30. Total Harmonic Distortion vs Supply Voltage

図図 31. Total Harmonic Distortion vs Temperature 図図 32. Output Noise Density vs Frequency

図図 33. Signal-to-Noise Ratio vs Input Voltage 図図 34. Signal-to-Noise Ratio vs Supply Voltage



VDD2 (V)

BW

(kH

z)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5240

250

260

270

280

290

300

310

320


BW

(kH

z)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125240

250

260

270

280

290

300

310

320

D039

VDD2 (V)

VC

Mo

ut (V

)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.51.39

1.4

1.41

1.42

1.43

1.44

1.45

1.46

1.47

1.48

1.49


VC

Mo

ut (V

)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 1251.39

1.4

1.41

1.42

1.43

1.44

1.45

1.46

1.47

1.48

1.49

D037

Temperature (°C)

SN

R (

dB

)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 12565

66

67

68

69

70

71

72

73

74

75

D034


Ripple Frequency (kHz)

PS

RR

(d

B)

0.001 0.01 0.1 1 10 100 1000-120

-100

-80

-60

-40

-20

0

20

D035

vs VDD2vs VDD1

16




図図 35. Signal-to-Noise Ratio vs Temperature 図図 36. Power-Supply Rejection Ratiovs Ripple Frequency

図図 37. Output Common-Mode Voltagevs Low-Side Supply Voltage

図図 38. Output Common-Mode Voltage vs Temperature

図図 39. Output Bandwidth vs Low-Side Supply Voltage 図図 40. Output Bandwidth vs Temperature



VDD2 (V)

Sig

nal D

ela

y (P

s)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.50.2

0.6

1

1.4

1.8

2.2

2.6

3

3.4

3.8

D044

50% - 90%50% - 50%50% - 10%

Temperature (°C)

Sig

na

l D

ela

y (P

s)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 1250.2

0.6

1

1.4

1.8

2.2

2.6

3

3.4

3.8

D045

50% - 90%50% - 50%50% - 10%

VDD2 (V)

t r / t

f (P

s)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.50.2

0.6

1

1.4

1.8

2.2

2.6

3

3.4

3.8


t r/t

f (P

s)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 1250.2

0.6

1

1.4

1.8

2.2

2.6

3

3.4

3.8

D043

VDDx (V)

IDD

x (

mA

)

3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.53.5

4

4.5

5

5.5

6

6.5

7

7.5

8

8.5

D040

IDD1 vs VDD1IDD2 vs VDD2

Temperature (°C)

IDD

x (

mA

)

-55 -40 -25 -10 5 20 35 50 65 80 95 110 1253.5

4

4.5

5

5.5

6

6.5

7

7.5

8

8.5

D041

IDD1 at VDD1 = 5 VIDD1 at VDD1 = 3.3 VIDD2 at VDD2 = 5 VIDD2 at VDD2 = 3.3 V

17




図図 41. Supply Current vs Supply Voltage 図図 42. Supply Current vs Temperature

図図 43. Output Rise and Fall Timevs Low-Side Supply Voltage

図図 44. Output Rise and Fall Time vs Temperature

図図 45. VIN to VOUT Signal Delayvs Low-Side Supply Voltage

図図 46. VIN to VOUT Signal Delay vs Temperature



TX

Retiming and

4th order

active

low-pass filter

û-Modulator

Bandgap

Reference

OUTP

OUTN

GND1

AMC1302

RX

RX TX

Data

CLK

VDD2

GND2

Bandgap

Reference

Oscillator

INP

INN

Reinforced

Isolation

Barrier

VCM

Diagnostic

VDD1

VDD1

Detection

18



7 Detailed Description

7.1 OverviewThe AMC1302 is a fully-differential, precision, isolated amplifier. The input stage of the device consists of a fully-differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator uses the internalvoltage reference and clock generator to convert the analog input signal to a digital bitstream. The drivers (calledTX in the Functional Block Diagram) transfer the output of the modulator across the isolation barrier thatseparates the high-side and low-side voltage domains. The received bitstream and clock are synchronized andprocessed by a fourth-order analog filter on the low-side and presented as a differential output of the device.

The SiO2-based, double-capacitive isolation barrier supports a high level of magnetic field immunity, as describedin ISO72x Digital Isolator Magnetic-Field Immunity. The digital modulation used in the AMC1302 (see also theIsolation Channel Signal Transmission section for more details) and the isolation barrier characteristics result inhigh reliability and common-mode transient immunity.

7.2 Functional Block Diagram



http://www.ti.com/lit/pdf/slla181

GND1

INP

VDD14 pF

VCMop = 2 V

INN

4 pF to VCM

Overvoltage

monitor

100 N

100 N

16 pF

50 k

2.5 N 50 N

2.5 k

GND1

VDD1

VDD1

19



7.3 Feature Description

7.3.1 Analog InputThe differential amplifier input stage of the AMC1302 feeds a second-order, switched-capacitor, feed-forward ΔΣmodulator. The modulator converts the analog signal into a bitstream that is transferred over the isolation barrier,as described in the Isolation Channel Signal Transmission section.

図 47 depicts the equivalent input structure of the AMC1302 with the relevant components. The total gain of thedevice results from a combination of the gain of the fully-differential input amplifier and the gain of the activeoutput filter.

図図 47. Equivalent Analog Input Circuit

There are two restrictions on the analog input signals (INP and INN). First, if the input voltage exceeds the rangeGND1 – 6 V to VDD1 + 0.5 V, the input current must be limited to 10 mA because the device input electrostaticdischarge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are ensured onlywhen the analog input voltage remains within the specified linear full-scale range (VFSR) and within the specifiedcommon-mode input voltage range (VCM); see the Recommended Operating Conditions table for detailedspecifications.



TX IN

Carrier Signal Across

the Isolation Barrier

RX OUT

TX IN

Oscillator

OOK

Modulation

Transmitter

TX Signal

Conditioning

Envelope

Detection

RX Signal

Conditioning

Receiver

RX OUT

SiO2-Based

Capacitive

Reinforced

Isolation

Barrier

20



Feature Description (continued)7.3.2 Isolation Channel Signal TransmissionThe AMC1302 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstreamacross the SiO2-based isolation barrier. As shown in 図 48, the transmitter modulates the bitstream at TX IN withan internally-generated, high-frequency carrier across the isolation barrier to represent a digital one and does notsend a signal to represent the digital zero. The nominal frequency of the carrier used inside the AMC1302 is 480MHz.

The receiver demodulates the signal after advanced signal conditioning and produces the output. The AMC1302also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiatedemissions caused by the high-frequency carrier and IO buffer switching.

図図 48. Block Diagram of an Isolation Channel

図 49 shows the concept of the OOK scheme.

図図 49. OOK-Based Modulation Scheme



21



Feature Description (continued)7.3.3 Fail-Safe OutputThe AMC1302 offers a fail-safe output that simplifies diagnostics on a system level. The fail-safe output is activein two cases:• When the high-side supply VDD1 of the AMC1302 is missing, or• When the common-mode input voltage, that is VCM = (VINP + VINN) / 2, exceeds the minimum common-mode

overvoltage detection level VCMov of VDD1 – 2 V

図 50 and 図 51 show the fail-safe output of the AMC1302 as a negative differential output voltage value thatdoes not occur under normal device operation. Use the VFAILSAFE voltage specified in the ElectricalCharacteristics table as a reference value for the fail-safe detection on a system level.

図図 50. Typical Negative Clipping Output of the AMC1302 図図 51. Typical Failsafe Output of the AMC1302

7.4 Device Functional ModesThe AMC1302 is operational when the power supplies VDD1 and VDD2 are applied, as specified in theRecommended Operating Conditions table. The device does not require any specific power-supply sequence.Consider the analog startup time tAS as defined in the Switching Characteristics table when the high-side powersupply VDD1 powers up with the low-side power supply VDD2 already operating in the specified range.



+VBUS

L1

L2

L3

Motor

VOUTP

VOUTN

VDD2

GND2GND1

SHTDN

VIN

VDD1

AMC1311B3.3 V 3.3 V

-VBUS

OUTP

OUTN

VDD2

GND2GND1

INN

INP

VDD1

AMC13023.3 V 3.3 V

Analog

Filterto ADC

RFLT

RFLT

CFLT

OUTP

OUTN

VDD2

GND2GND1

INN

INP

VDD1

AMC13023.3 V 3.3 V

Analog

Filterto ADC

RFLT

RFLT

CFLT

RSHUNT

RSHUNT

OUTP

OUTN

VDD2

GND2GND1

INN

INP

VDD1

AMC13023.3 V 3.3 V

Analog

Filterto ADC

RFLT

RFLT

CFLT

RSHUNT

RFLT

CFLTAnalog

Filterto ADC

22



8 Application and Implementation

注注Information in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe low input voltage range, very low nonlinearity, and temperature drift make the AMC1302 a high-performancesolution for industrial applications where low-power dissipation, shunt-based current sensing with high common-mode voltage levels is required.

8.2 Typical ApplicationIsolated amplifiers are widely used in frequency inverters that are critical parts of industrial motor drives,photovoltaic inverters, uninterruptible power supplies, and other industrial applications. The input structure of theAMC1302 is optimized for use with very low-value shunt resistors in current-sensing applications.

図 52 shows a typical operation of the AMC1302 for current sensing in a frequency inverter application. Phasecurrent measurement is accomplished through the shunt resistors, RSHUNT (in this case, a two-pin shunt). Thedifferential input and the high common-mode transient immunity of the AMC1302 ensure reliable and accurateoperation even in high-noise environments (such as the power stage of the motor drive). The high-impedanceinput and wide input voltage range make the AMC1311 suitable for DC bus voltage sensing.

図図 52. Using the AMC1302 for Current Sensing in Frequency Inverters



http://www.ti.com/product/AMC1311

AMC1302

GND2

TLV6001

+

±

VDD1

INP

INN

GND1

VDD2

OUTP

OUTN

GND2

VCMADC

To ADC

23



Typical Application (continued)8.2.1 Design Requirements表 1 lists the parameters for this typical application.

表表 1. Design RequirementsPARAMETER VALUE

High-side supply voltage 3.3 V or 5 VLow-side supply voltage 3.3 V or 5 V

Voltage drop across the shunt for a linear response ±50 mV (maximum)Signal delay (90% settling) 3 µs (maximum)

High common-mode transient immunity (CMTI) 80 kV/µs (typical)

8.2.2 Detailed Design ProcedureThe high-side power supply (VDD1) for the AMC1302 is derived from the power supply of the upper gate driver.Further details are provided in the Power Supply Recommendations section.

The floating ground reference (GND1) is derived from one of the ends of the shunt resistor that is connected tothe negative input of the AMC1302 (INN). If a four-pin shunt is used, the inputs of the AMC1302 device areconnected to the inner leads and GND1 is connected to one of the outer shunt leads.

Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measuredcurrent: VSHUNT = I × RSHUNT.

Consider the following two restrictions to choose the proper value of the shunt resistor RSHUNT:• The voltage drop caused by the nominal current range must not exceed the recommended differential input

voltage range: VSHUNT ≤ ± 50 mV• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes

a clipping output: VSHUNT ≤ VClipping

For systems using single-ended input ADCs, 図 53 shows an example of a TLV6001-based signal conversionand filter circuit as used on the AMC1302EVM, where VCMADC is the common-mode input voltage of the ADC.Tailor the bandwidth of this filter stage to the bandwidth requirement of the system and use NP0-type capacitorsfor best performance.

図図 53. Connecting the AMC1302 Output to Single-Ended Input ADC

For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data AcquisitionBlock (DAQ) Optimized for Lowest Power, available for download at www.ti.com.



http://www.ti.com/lit/pdf/SBOS779

http://www.ti.com/tool/amc1302evm

http://www.ti.com/lit/pdf/SLAU515




http://www.ti.com/

Differential Input Voltage (mV)

No

nlin

ea

rity

(%

)

-50 -40 -30 -20 -10 0 10 20 30 40 50-0.03

-0.02

-0.01

0

0.01

0.02

0.03

D026

VOUTN

VIN

VOUTP

24



8.2.3 Application CurvesIn frequency inverter applications, the power switches must be protected in case of an overcurrent condition. Toallow for fast powering off of the system, a low delay caused by the isolated amplifier is required. 図 54 showsthe typical full-scale step response of the AMC1302. Consider the delay of the required window comparator andthe MCU to calculate the overall response time of the system.

図図 54. Step Response of the AMC1302

The high linearity and low temperature drift of the offset and gain errors of the AMC1302 (see the TypicalCharacteristics section) allows design of motor drives with low torque ripple.

図図 55. Typical Nonlinearity of the AMC1302

8.3 What to Do and What Not to DoDo not leave the inputs of the AMC1302 unconnected (floating) when the device is powered up. If both deviceinputs are left floating, the input bias current drives these inputs to the output common-mode of the analog front-end of approximately 2 V. If the high-side supply voltage VDD1 is below 4 V, the internal common-modeovervoltage detector turns on and the output functions as described in the Fail-Safe Output section, which maylead to an undesired reaction on the system level.



OUTP

OUTN

VDD2

GND2GND1

INP

INN

VDD1

AMC1302

HV+

HV-

to Load

Floating

Power Supply

15 V

3.3 V or

5.0 V

RSHUNT

5.1 V

R1

800

Z1

1N751A

C2

2.2 F C1

0.1 F

C3

0.1 F C4

2.2 F

ADS7263

14-Bit ADC

Gate Driver

Gate DriverR

ein

forc

ed

Iso

latio

n

CFLT RFLT

RFLT

25



9 Power Supply RecommendationsIn a typical frequency inverter application, the high-side power supply (VDD1) for the device is derived from thefloating power supply of the upper gate driver. For lowest system-level cost, a Zener diode can be used to limitthe voltage to 5 V or 3.3 V ± 10%. Alternatively, a low-cost low-dropout (LDO) regulator (for example, the LM317-N) may be used to minimize noise on the power supply. TI recommends a low-ESR decoupling capacitor of0.1 µF to filter this power-supply path. Place this capacitor (C1 in 図 56) as close as possible to the VDD1 pin ofthe AMC1302 for best performance. Use an additional 2.2-µF decoupling capacitor (C2) for filtering lower-frequency noise. The floating ground reference (GND1) is derived from the end of the shunt resistor, which isconnected to the negative input (INN) of the device. If a four-pin shunt is used, the device inputs are connectedto the inner leads, and GND1 is connected to one of the outer leads of the shunt.

To decouple the digital power supply on the controller side, use a 0.1-µF capacitor (C3) placed as close to theVDD2 pin of the AMC1302 as possible, followed by an additional capacitor from 1 µF to 10 µF (C4).

図図 56. Zener-Diode-Based, High-Side Power Supply



http://www.ti.com/product/LP2951-Q1

http://www.ti.com/product/LP2951-Q1

To Filteror ADC

Clearance area,to be kept free of any conductive materials.

AMC1302

OUTN

GND2

OUTP

VDD2

0.1 µF

SMD0603

LEGEND

Copper Pour and Traces

High-Side Area

Low-Side Area

Via to Ground Plane

Via to Supply Plane

2.2 µF

SMD0603

INP

INN

GND1

To Floating Power Supply

Sh

un

t R

es

isto

r

VDD1

0.1 µF

SMD0603

2.2 µF

SMD0603

CFLT

SMD0603

RFLTSMD0603

RFLTSMD0603

26



10 Layout

10.1 Layout Guidelines図 57 shows a layout recommendation with the critical placement of the decoupling capacitors (as close aspossible to the AMC1302 supply pins) and placement of the other components required by the device. For bestperformance, place the shunt resistor close to the INP and INN inputs of the AMC1302 and keep the layout ofboth connections symmetrical.

10.2 Layout Example

図図 57. Recommended Layout of the AMC1302



27



11 デデババイイススおおよよびびドドキキュュメメンントトののササポポーートト

11.1 デデババイイスス・・ササポポーートト

11.1.1 デデババイイススのの項項目目表表記記テキサス・インスツルメンツ、『絶縁の用語集』アプリケーション・レポート

11.2 ドドキキュュメメンントトののササポポーートト

11.2.1 関関連連資資料料関連資料については、以下を参照してください。

• テキサス・インスツルメンツ、『ADSxxx3 Dual, 1-MSPS, 16-, 14-, and 12-Bit, 4×2 or 2×2 Channel, SimultaneousSampling Analog-to-Digital Converter』データシート (英語)

• テキサス・インスツルメンツ、『半導体および IC パッケージの熱評価基準』アプリケーション・レポート

• テキサス・インスツルメンツ、『ISO72x Digital Isolator Magnetic-Field Immunity』アプリケーション・レポート (英語)• テキサス・インスツルメンツ、『AMC1311x 高インピーダンス、2V 入力、強化絶縁アンプ』デーシート

• テキサス・インスツルメンツ、『TLV600x-Q1 低コスト・システム用の低消費電力、レール・ツー・レール入出力、1MHzのオペアンプ』データシート

• テキサス・インスツルメンツ、『LM117, LM317-N Wide Temperature Three-Pin Adjustable Regulator』データシート(英語)

• テキサス・インスツルメンツ、『AMC130x Evaluation Module』ユーザー・ガイド (英語)• テキサス・インスツルメンツ、『18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and

Noise』ユーザー・ガイド (英語)• テキサス・インスツルメンツ、『18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest Power』ユー

ザー・ガイド (英語)• テキサス・インスツルメンツ、『SN6501 絶縁電源用の変圧器ドライバ』データシート

11.3 ドドキキュュメメンントトのの更更新新通通知知をを受受けけ取取るる方方法法ドキュメントの更新についての通知を受け取るには、ti.comのデバイス製品フォルダを開いてください。右上の「アラートを受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。

11.4 ココミミュュニニテティィ・・リリソソーーススTI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and donot necessarily reflect TI's views; see TI's Terms of Use.

11.5 商商標標E2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.6 静静電電気気放放電電にに関関すするる注注意意事事項項すべての集積回路は、適切なESD保護方法を用いて、取扱いと保存を行うようにして下さい。

静電気放電はわずかな性能の低下から完全なデバイスの故障に至るまで、様々な損傷を与えます。高精度の集積回路は、損傷に対して敏感であり、極めてわずかなパラメータの変化により、デバイスに規定された仕様に適合しなくなる場合があります。

11.7 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.



http://www.ti.com/lit/pdf/SLLA353

http://www.ti.com/lit/pdf/SBAS523



http://www.ti.com/lit/pdf/SLLA181




http://www.ti.com/lit/pdf/SNVS774

http://www.ti.com/lit/pdf/SNVS774

http://www.ti.com/lit/pdf/SBAU256





http://www.ti.com/lit/pdf/SLLSEA0

http://e2e.ti.com

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://www.ti.com/lit/pdf/SLYZ022

28



12 メメカカニニカカルル、、パパッッケケーージジ、、おおよよびび注注文文情情報報以降のページには、メカニカル、パッケージ、および注文に関する情報が記載されています。この情報は、そのデバイスについて利用可能な最新のデータです。このデータは予告なく変更されることがあり、ドキュメントが改訂される場合もあります。本データシートのブラウザ版を使用されている場合は、画面左側の説明をご覧ください。



重重要要ななおお知知ららせせとと免免責責事事項項

TI は、技術データと信頼性データ（データシートを含みます）、設計リソース（リファレンス・デザインを含みます）、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。

これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。

TI の製品は、TI の販売条件（www.tij.co.jp/ja-jp/legal/termsofsale.html）、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用されるTI の保証または他の保証の放棄の拡大や変更を意味するものではありません。IMPORTANT NOTICE

Copyright © 2020, Texas Instruments Incorporated日本語版日本テキサス・インスツルメンツ株式会社

http://www.tij.co.jp/ja-jp/legal/termsofsale.html

http://www.tij.co.jp/

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

AMC1302DWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 AMC1302

AMC1302DWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 AMC1302

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

http://www.ti.com/product/AMC1302?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/AMC1302?CMP=conv-poasamples#samplebuy

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

AMC1302DWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Jan-2020

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

AMC1302DWVR SOIC DWV 8 1000 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Jan-2020

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

TYP11.5 0.25

2.8 MAX

TYP0.330.13

0 -8

6X 1.27

8X 0.510.31

2X3.81

0.460.36

1.00.5

0.25GAGE PLANE

A

NOTE 3

5.955.75

BNOTE 4

7.67.4

(2.286)

(2)

4218796/A 09/2013

SOIC - 2.8 mm max heightDWV0008ASOIC

NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

18

0.25 C A B

54

AREAPIN 1 ID

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 2.000

www.ti.com

EXAMPLE BOARD LAYOUT

(10.9)

0.07 MAXALL AROUND

0.07 MINALL AROUND

8X (1.8)

8X (0.6)

6X (1.27)

4218796/A 09/2013


SYMM

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE:6X

NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

OPENINGSOLDER MASK METAL

SOLDER MASKDEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

8X (1.8)

8X (0.6)

6X (1.27)

(10.9)

4218796/A 09/2013


NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:6X

SYMM

SYMM

重重要要ななおお知知ららせせとと免免責責事事項項

TI は、技術データと信頼性データ（データシートを含みます）、設計リソース（リファレンス・デザインを含みます）、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。

これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。

TI の製品は、TI の販売条件（www.tij.co.jp/ja-jp/legal/termsofsale.html）、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用されるTI の保証または他の保証の放棄の拡大や変更を意味するものではありません。IMPORTANT NOTICE

Copyright © 2020, Texas Instruments Incorporated日本語版日本テキサス・インスツルメンツ株式会社

http://www.tij.co.jp/ja-jp/legal/termsofsale.html

http://www.tij.co.jp/