ALICE Silicon Pixel On Detector Pilot System OPS2003 - The ...akluge.home.cern.ch/akluge/work/alice/spd/spd_documents/ALICE-INT-2004... · System overview of the on detector Pilot

EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH European Laboratory for Particle Physics

CERN Internal Note/ ALICE reference number

ALICE-INT-2004-030 version 1.0 Institute reference number

[-] Date of last change

CH-1211 Geneve Switzerland

2005-04-28

ALICE Silicon Pixel On Detector Pilot System OPS2003 - The missing manual

Authors: A. Kluge

Abstract: This document describes the on-detector read-out architecture of the ALICE Silicon On-Detector Pilot System 2003 (OPS2003) and is a user document for the Pilot2003 chip. The following information can be found in this document: • The general architecture of the ALICE SPD read out system • Data format • Internal functionality of the Pilot2003 chip • Inputs and outputs of the Pilot2003 chip • Access to configuration registers and internal test registers in the Pilot2003 • Detailed explanation of the internal logic of the Pilot2003 • The entire design process of the Pilot2003 from functional description to the final layout design process.

28 April 2005

1

ALICE Silicon Pixel On Detector Pilot System OPS2003 - The

missing manual

A. Kluge

This document describes the on detector read-outstructure of the ALICE Silicon On-Detector Pilot System2003 (OPS2003) and is a user document for the Pilot2003chip.

First created: 27April 2005Modification date: 27 April 2005

The following information can be found in this document:

•

The general architecture of the ALICE SPD read out system

•

Data format

•

Internal functionality of the Pilot2003 chip

•

Inputs and outputs of the Pilot2003 chip

•

Access to configuration registers and internal test registers in the Pilot2003

•

Detailed explanation of the internal logic of the Pilot2003

•

The entire design process of the Pilot2003 from functional description to the final layout designprocess.

2

ALICE Silicon Pixel On Detector Pilot System OPS2003 - The missing manual

Version 1.0: 27. 4. 2004 edited by Alexander Kluge

3

1. System overview of the on detector Pilot system OPS2003 5

2. On-detector multi chip module and ASICs 6

3. Pilot2003 data structure 7

3.1 PILOT2003 data format 93.2 Signal description: Control and feedback signal description

(frame 0/ slot 0 and 1) 103.3 Synchronisation of the link receiver to the OPS 14

4. PILOT2003 command deserializer - BOB 16

4.1 Specifications 164.2 Functionality 17

4.2.1 Principle of functionality 174.2.2 Commands 174.2.3 LHC clock synchronisation 184.2.4 Operation modes 19

5. Programmable features in the OPS 19

5.1 Programmable features in the PILOT2003 19

6. PILOT2003 periphery 20

6.1 Control room ports: Clock and command inputs 206.2 Pixel chip ports 216.3 Ports connected to the GOL chip 23

7. Configuration, internal registers and test structure in the chip 23

7.1 JTAG instructions 247.2 Configuration registers 247.3 Boundary Scan (JTAG) on Inputs and Outputs 257.4 Internal registers 26

8. Pinout of the PILOT2003 chip 27

9. Additional features in PILOT2003 32

9.1 10 FastOr lines 329.2 Data format 339.3 Chip enable sequence 339.4 Pixel control signal logic levels are changed from GTL to

CMOS 339.5 Pixel chip clock signals are changed to CMOS levels 339.6 Synchronisation of 10 MHz PILOT system clock to LHC

clock 379.7 Changes of the inputs and outputs 379.8 JTAG timing and synchronisation 399.9 ESD protection 409.10 Reset signal length 409.11 Voting on cnt4 register 40

4

10. Implementation details 40

10.1 SEU in the OPS 4010.2 Synchronisation of the PILOT command deserializer 4110.3 Interface between clock domains in the PILOT2003 chip 4210.4 Core implementation 43

10.4.1Strobe and busy generation 4310.4.2L2queue 4310.4.3Config 4610.4.4Clk_div 4610.4.5reset_filter 4610.4.6fastor 4610.4.7vote1_err 4610.4.8or_seu 4610.4.9pilot_sm 4610.4.10gtl_in 4710.4.11gtl_out 4710.4.12serial_in 4710.4.13cmos_in 4910.4.14cmos_out 49

10.5 Implementation process 49

10.5.1GTLrx layout 4910.5.2Functionality description of the PILOT2003 4910.5.3Functionality verification before synthesis 4910.5.4Logic synthesis 5010.5.5Post synthesisation functional check 5010.5.6Place and route of the layout 5010.5.7Post layout simulation 5110.5.8Post layout SEU simulation. 5110.5.9Manual changes in the layout 5210.5.10DRC, LVS, Dracula, Hercules 52

11. Appendix 54

11.1 Data format of PILOT1 5411.2 Design files 54

11.2.1Design_analyzer script: pilot.script (/user/akluge/pilot/design_analyzer/pilot.script) 55

11.2.2Silicon Ensemble script files 5511.2.3Verilog files 55

11.3 Digital part of the ANAPIL3 55

11.3.1Implementation 5611.3.2Input and Outputs 5611.3.3JTAG interface 57

12. References 62

System overview of the on detector Pilot system OPS2003

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1. System overview of the on detector Pilot system

OPS2003

The ALICE silicon pixel detector (SPD) is a 2-layer barrel hybrid pixel detector with 9.83 x 10

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pixel cells in 120 half staves. Each half stave consists of a linear array of 10 ALICE pixel chipsbump bonded to two silicon sensors and is read out using a multi-chip-module (MCM).

The ALICE trigger has three stages (L0, L1, L2) whereas the SPD system uses L1 and L2triggers only. The pixel chips provide binary hit information, which is stored in a delay lineduring the L1 decision time. In case of a positive L1 decision the hit is stored in one out of fourmulti event buffers where the data wait for the L2 decision to be read out or discarded. TheALICE trigger scheme foresees a non-pipelined architecture and allows the detector read-outsystems to temporarily reject triggers by sending a busy signal to the central trigger processor. InTable 1 some key features of the SPD are summarized.

Figure 1 shows a block diagram of the full SPD read-out chain. Configuration and trigger dataare sent from the VME-based electronics (router and link receiver card) in the control room tothe on-detector electronics via two optical fibers, one carrying the clock and one carrying serialdata. On the detector the PILOT2003 chip initiates the read-out of the pixel chips and controls

TABLE 1.

SPD features

Parameter Value

L1 rate

≈

1 kHz

L1 latency

6.5 μs

L2 rate

40 - 800 Hz

L2 latency

100 μs

Read-out time

256 μs

Multi-event buffers

4

TID (inner layer)

2.5 kGy (10 years)

Neutron fluence (1 Mev equivalent)

3 x 10

12

cm

-2

(10 years)

Material budget per layer

<1% X

0

FIGURE 1. System block diagram of the ALICE silicon pixel read out.

On-detector multi chip module and ASICs

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the ANAPIL chip, which provides analog bias voltage to the pixel chips and measures supply,bias voltages of the pixel chips and the temperature on the detector. Once read-out has beeninitiated the non zero-suppressed data are sent from the pixel chips via the PILOT2003 and anoptical link driver chip GOL [1] on an optical fiber to the control room. There the data are zero-suppressed and formatted in the FPGA-based link receiver mezzanine board. Three such boards,each one serving 2 data channels, are located on one router module. The router performs datamultiplexing and establishes the interface to the ALICE trigger and data acquisition. In total 20router cards read out the 120 half staves. One ALICE standard data link DDL [2] per router isused to transmit the data stream to the ALICE DAQ.

Data processing such as zero suppression and encoding is performed off detector. This avoids theneed for radiation tolerant memories and makes it easier to adapt data processing capabilities toany possible new requirements.

2. On-detector multi chip module and ASICs

The read-out and control electronics of the pixel chips is located on a multi chip module (MCM).The MCM is 110 mm long and less than 13 mm wide.

The ASICs are mounted on the MCM as bare die for space constraints. Data communication isvia optical fibres. The PILOT2003 chip receives the configuration and trigger signals on anoptical link, converts the electrical signals from the PIN diodes to electrical signals, initiates theread-out of the data in the pixel chips and sends back the data to the control room using the GOLchip. The GOL chip is an 800 Mbit/s G-link compatible serializer and optical link driver. TheANAPIL chip provides analog bias voltages needed on the pixel chip and measures voltages andtemperatures on the half stave. Communication between the chips on the MCM is established viathe JTAG protocol. A mode selector pin on the PILOT2003 allows the choice between LVDSinputs or signals connected to an optical PIN-diode and the receiver chip RX40.

A custom developed optical transceiver module is used for data communication. Two 40 Mb/sdata channels are used to send the clock and data to the detector and one 800 Mb/s channel isused to transfer data to the control room. The optical module contains two PIN diodes and onelaser diode, housed in a silicon package. The module is extremely compact with a floorprint of16 mm x 6 mm and a thickness of 1.2 mm. The module has bond pads for electrical connections.Space constraints prevent the implementation of strain relief on the fibre pigtails, whichtherefore require very careful handling.

The 40 MHz LHC clock is connected to the PILOT2003 chip and is passed on to the G-linkserializer GOL using LVDS signals. On the PILOT2003 chip the clock is divided by 4 togenerate the 10 MHz OPS system clock. The pilot logic and the pixel chip logic work with the 10MHz clock. As a result all signals within the on detector pilot system OPS with the exception ofthe GOL signals have a time binning of 100 ns. Time correlation between the LHC clock and thesystem clock is required when the FastOr signals from the pixel chips are used in the ALICE L0system [3]. The 10 MHz clock signal for the pixel chips is distributed on differential CMOSlogic level signals. The 40 MHz clock for the ANAPIL3 is provided using a single ended CMOSoutput.

Several documents are available describing the system architecture and implementation. [3, 4, 5,6, 7]. Fig. 2 shows the MCM. The functionality of the pilot system is based on the VMEprototype of the pilot system [10].

Pilot2003 data structure

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3. Pilot2003 data structure

This chapter describes how the PILOT2003 uses the optical link and shows the data formatwhich is used on the optical link.

The optical G-link from the detector to the control room employs the GOL chip, which transmits16 bit data words every 25 ns (16 bit x 40 MHz = 640 Mbit/s). Two control signals,

tx_data

(or

dav

- data valid) and

tx_cntl

(or

cav

- control valid), determine whether a data word, a controlword or no word is transmitted. When transmitting control words, 14 bits can be transmitted in a40 MHz cycle only. Fig. 3 illustrates the operation of the optical link in the G-Link mode. Theuser receives the same signals on the output as on the input of the link. Hence it can be seen as avirtual ribbon cable.

The data transmission of pixel data from the pixel chips to the PILOT2003 is performed using a32 bit data bus with a transmission frequency of 10 MHz. That means four 25 ns long 16 bit widetransmission cycles are available before the next data word from the pixel chips arrives. Thus theGOL provides twice the necessary transmission bandwidth.

Two GOL cycles will be used to transmit 16 bits of pixel hit data each. The other two cycles areused to transmit control data. Each two cycles used either for control or for hit data are calledtransmission frames (see fig. 4). Each data frame is sent in two consecutive 25 ns transmissionslots. If no pixel data read-out is performed only frame 0 is used to send control and feedback

FIGURE 2. Kapton MCM (SBU). (chips from left to right: RX40, ANAPIL3, PILOT2003, GOL, OPT)

FIGURE 3. G-Link interface.


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data to the control room. Then neither tx_data nor tx_cntl is active during frame 1. In case theread-out process has been started control bits in frame 0 indicate the immediate start of pixel hitdata transmission. When a pixel data read out has started after the first transmission of data inframe 0 a special data frame (frame 1a) is transmitted. It describes the event which is sentsubsequently. After that frame 0 and frame 1b are sent alternatively. Frame 1b contains the pixelhit data. The principle is illustrated in fig. 4. Fig. 5 shows the principle of implementation. Fig. 6

gives a detailed block diagram.

•

Frame 0:In frame 0 ‘data control & signal feedback’ signals are transmitted. The pixel router forwards the trigger information to the corresponding PILOT2003. There thedata read out of the pixel chips is initiated, data are transferred to the control room and arereceived by the link receiver. The link receiver card uses the information in the data controlblock to synchronize the control-room-located logic to the arriving data stream. Data in frame0 indicate whether the corresponding read out cycle contains the first word or the last word ofthe transmission. Also it indicates whether the event has been aborted by an active L2n signal.Control signals such as the trigger signals which are sent from the control room to the OPSare sent back in data frame 0. This enables the control room logic to verify the proper signalreception and timing of the trigger signals in the OPS.

•

Frame 1a:Data describing the event which is going to be transmitted is sent in this block.

FIGURE 4. Transmission of frames and slots.

FIGURE 5. Structure of data frames and slots.


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•

Frame 1b:is reserved for the pixel hit data. The 10 x 256 pixel data rows are sent out one after the otherstarting from chip 0.

Frame 0 is a control word. The control signal

tx_cntl (cav)

of the G-link interface is activatedduring the two 25 ns transfer cycles.

Frame 1a and 1b are data words. The control signal

tx_data (dav)

of the G-link interface isactivated. (see table 2)

3.1 PILOT2003 data format

Two different formats can be selected using the configuration register, see paragraph 5.1. Thedefault format sends the FastOr

1

signals. Table 2 gives the data format in detail. The bit numbers

1. Each pixel chip provides an output which is active when at least one single pixel has been hit. All 10 fastOr outputs are transmitted to the control room via the PILOT2003 and the GOL.

FIGURE 6. Block diagram of control and transmission units.


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correspond to the bit numbers of the PILOT2003 chip output

link_bus<15:0>

. Table Figure 12on page 54 gives the data format when the configuration bit data_format_trig is not selected.

Mebstate encodes busy_violation [11], idle_violation [10], busy [01], none [00]. All signals with the extension _i are low active. All others

are high active.

3.2 Signal description: Control and feedback signal description (frame 0/ slot 0 and 1)

The feedback and control signals transmitted from the PILOT2003 chip to the control room aredescribed.

•

first_word:This signal is active when in the corresponding pixel readout cycle (= 10 MHz cycle) theevent description (frame 1a) is sent. It is also active when an event has been aborted and nodata are going to be sent, see signal clear_event. Fig. 7 illustrates the wave view diagram of atransmission start.

•

last_word:This signal is active when in the corresponding pixel readout cycle (= 10 MHz cycle) the lastdata line is sent (pixel row [10 chips * 256 row - 1 =] 2559). It is also active when an event hasbeen aborted and no data are being sent, see signal clear_event.

TABLE 2.

PILOT2003 Data in link_bus<15:0>

frame 0 frame 0 frame 1a frame 1a frame 1b frame 1b

slot 0 slot 1 slot 2 slot 3 slot 2 slot 3

bit data control & signal feedback

data control & signal feedback

event description

pixel hit data line

pixel hit data line

pixel hit data line

signal name, frame bits






15 no data no data eventnumber [9] remainingchips [3] pixel hit data [31] pixel hit data [15]

14 no data no data eventnumber [8] remainingchips [2] pixel hit data [30] pixel hit data [14]

13 first_word first_word_trig eventnumber [7] remainingchips [1] pixel hit data [29] pixel hit data [13]

12 last_word last_word_trig eventnumber [6] remainingchips [0] pixel hit data [28] pixel hit data [12]

11 clear_event clear_event_trig eventnumber [5] row_add [7] pixel hit data [27] pixel hit data [11]

10 temp error_bob eventnumber [4] row_add [6] pixel hit data [26] pixel hit data [10]

9 fastorbus[9] idle_bob eventnumber [3] row_add [5] pixel hit data [25] pixel hit data [9]

8 fastorbus[8] tck_return eventnumber [2] row_add [4] pixel hit data [24] pixel hit data [8]

7 fastorbus[7] tdo_return eventnumber [1] row_add [3] pixel hit data [23] pixel hit data [7]

6 fastorbus[6] tms_return eventnumber [0] row_add [2] pixel hit data [22] pixel hit data [6]

5 fastorbus[5] meb_state[1] remainingchips [9] row_add [1] pixel hit data [21] pixel hit data [5]

4 fastorbus[4] meb_state[0] remainingchips [8] row_add [0] pixel hit data [20] pixel hit data [4]

3 fastorbus[3] feedback[2] remainingchips [7] meb_val [2] pixel hit data [19] pixel hit data [3]



0 fastorbus[0] feedback[3] remainingchips [4] ‘0’ pixel hit data [16] pixel hit data [0]


11

•

clear_event:Once a L2n signal has been issued data in the frontend electronics are discarded and nottransmitted. However, one readout cycle is still initiated to confirm the abort. In this case theclear_event signal is active, as well as first_word and last_word signal. The event counter isincremented, see signal event_number. Fig. 8 illustrates the wave view diagram of a L2nabort.

•

first_word_trig, last_word_trig, clear_event_trig:As the three afore mentioned signals are vital for the proper synchronisation of the linkreceiver to the OPS they are sent twice in the data flow. In addition in frame 0 slot 1 thesignals first_word_trig, last_word_trig and clear_event_trig are sent. These signals areidentical to the afore mentioned signals with the only exception that they are active for threeconsecutive transmission cycles. This ensures that the signals are received in the control roomeven if a transmission error in a single frame has occurred.

•

error_control:indicates that the PILOT2003 command deserializer has decoded an undefined command.

FIGURE 7. Wave view diagram showing the transmission signals during the start of the data transmission (First word).


12

•

idle_control:indicates that the PILOT2003 command deserializer has decoded the predefined idlecommand. It is useful to monitor this signal during the setup of the optical links.

•

temp:A single input bit to the PILOT2003 chip is transmitted to the control room. It can be used totransmit temperature information.

1

•

tck_return, tms_return:The JTAG input signals are returned.

•tdo_returnis the return signals of the JTAG chain.

•fastorbus<9..0>are the fastor signals of all pixel chips.

•event_number <9..0>:The OPS attaches a 10 bit event number to each event. Upon reset the event counter is set to 0.However, it can be loaded to any value after a reset.

1. A 10 bit temperature code is sent on this channel in a serial way. It is generated by the ANAPIL3 chip [11].

Fri Feb 23 17:18:18 2001�

time (ns)�

583300.31� 583400.0� 583500.0� 583600.0� 583700.0� 583800.0� 583900.0�

clk�clk_i�reset�

reset_pixel�pixbus_i�cav�clear_event�dav�first_word�last_word�link_bus�cnt4�

0ffe� ffff� 0040�0ffe� ffff� 0040�0ffe� ffff� 3f40�09fa�027f�f000�0040�0ffe� ffff� 0040�0ffe� ffff� 0040�0ffe�ffff�

1� 2� 3� 0� 1� 2� 3� 0� 1� 2� 3� 0� 1� 2� 3� 0� 1� 2� 3� 0� 1� 2� 3� 0� 1� 2�

FIGURE 8. Wave view diagram showing the transmission signals during the abort of the data transmission (Clear event).


13

•remaining_chips <9..0>:is a 10 bit mask which defines which chips are included in the readout stream. This mask isdefined in a PILOT2003 configuration register.

•row_add <7..0>:in case the G-link GOL loses synchronisation during readout of an event one out of twooptions can be selected. Option one is that the event readout is terminated and data which arestill remaining in the pixel chips are discarded. The other option is that the transmission isresumed as soon as the link is up again. However, depending on where the transmission wasinterrupted up to 3 data lines may be lost. Thus the row address number is sent in order torecover data synchronisation. In this case again the first_word signal is sent.

•meb_val:The number of events stored in the multi event buffers of the pixel chips is sent.

•pixel hit data <31..0>:is the pixel hit data line.

Signals encoded in meb_state <1..0>:

•busy:The busy signal indicates that the multi event buffers in the pixel chips are full. No L1 triggersignal can be accepted any more.

•busy_violation:This busy violation signal indicates that a L1 trigger signal has been received by thePILOT2003 chip although all multi event buffers in the pixel chips were full and the busysignal is asserted. It can only be cleared by reset of the PILOT2003. Data transmission is notstopped when a busy violation has occurred. However, data might be corrupted.

•idle_violation:The idle violation signal indicates that a L2y or L2n signal has been received by thePILOT2003 chip without a corresponding reception of a L1 trigger signal. It can only becleared by reset of the PILOT2003. Data transmission is not stopped when a busy violationhas occurred. However, data might be corrupted.

Table 3 gives the decoding scheme for the meb_state status word. In case more than one statusbit is active the priority encoder sends the one with the highest two bit value.

Signals encoded in feedback <3..0>

•seu_error:indicates the presence of an undefined state or a single event upset within the PILOT2003. Ifthis signal stays active during one to three consecutive cycles a single event upset has beendetected and the original state has been recovered. Should the signal remain active duringmore than three cycles a reset of the corresponding unit is recommended.

TABLE 3. Meb_state decoding scheme

status word 2 bit value

busy_violation 3

idle_violation 2

busy 1

none 0


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•L1, L2y, L2n:Trigger signals sent by the pixel router are immediately sent back on the optical link. Thisserves as error detection and can be used to adjust the timing of the signals.

•strobe_i, nevr_i, clev_i, test_pulse:These signals are control signals generated by the OPS to control the pixel chips. In order tofacilitate error detection they are sent to the control room.

•trst_return:

Table 4 gives the decoding scheme for the 4 bit feedback value. The table also shows the priorityin case more than one feedback status bit is active.

3.3 Synchronisation of the link receiver to the OPS

The synchronisation of the link receiver to the data flow from the OPS is described.

The synchronisation process works in two steps. First the link receiver must identify the fourdifferent slots. For this process the following two signals are used.

•clk40 - directly available from the G-link interface on the receiver.

•rx_cntl/cav - directly available from the G-link interface on the receiver.

The signal rx_cntl/cav is active always during the two transmission cycles of slot 0, 1 andinactive otherwise. When no data are transmitted the signal rx_data/dav is inactive and indicatesthe idle state. Using the clk40 signal delivered by the G-link receiver to strobe rx_cntl/cav thefour slots can easily be identified (see fig. 9). The signal slot_number <1..0> is created andindicates the transmission slot active at the moment. After a programmable number of constantrx_cntl/cav cycles the link receiver is considered to be in lock. The link receiver and the ondetector pixel chip system are synchronized with respect to the slot_number.

In the next step the synchronisation process searches for the signal first_word to be active inorder to detect the start of the data transmission. Using the signals first_word, last_word andevent_clear it is simple to synchronize the link receiver to the data flow or detect errors in thetransmission protocol (see fig. 10).

TABLE 4. Decoding scheme for the 4 bit feedback value

Feedback value

4 bit value (hex) Priority

strobe_i 9 8

test_pulse_i a 7

L1 b 6

L2y or L2n c 5

nevr_i d 4

clev_i e 4

trst f 2

seu 8 1

None 0 0


15

Depending on which slot is transmitted the data bits have different meaning. Using a multiplexerstructure (see figure 11) the data stream is decoded and strobed into an output register where it isavailable at the end of the transmission cycle synchronous to clk10.

•Loss of lock count optionThe system (GOL + PILOT2003) can be set to a state where it sends a command word once theinternal PLL goes into a locked state.

This will happen after startup. However, the PLL might loose lock due to a SEU and again relockduring normal operation. After the PLL is considered to be locked again a command word issent. This command word contains the number of times the PLL has lost lock after the last reset(data bits 7 downto 0). Data bits 32 downto 8 are ‘0’. Neither first_word nor last_word are active.The loss of lock count can arrive in any slot but of course only after the link just started up.

FIGURE 9. Synchronisation of the link receiver to the slot number of the OPS.

FIGURE 10. Synchronisation of the link receiver to the data block sent by the OPS.

PILOT2003 command deserializer - BOB

16

4. PILOT2003 command deserializer - BOB

4.1 Specifications

The purpose of the PILOT2003 command deserializer is to receive the trigger signals - L1, L2yand L2n -, the test pulse signal and the JTAG signals - tck, trst, tms, tdi on the serial input anddeserialize the commands

•Following signals are recognized:- L1.- L2y.- L2n.- test pulse.- reset.- JTAG signals: tck, tdi, tms, trst.

•The required time binning of the signal arrival on detector is 100 ns. Any trigger signal mightarrive in a time grid of 25 ns to the router. However, as soon as they enter the on detector pilotsystem OPS they are synchronized to the 10 MHz clock system.

•The deserializer may introduce dead time for all signals except the L1 signal. Once a L1 signalhas been received no other L1 signal can arrive within more than 5 μs [12]. A problem ariseswhen a L2 signal command is in the process of being serialized when a L1 signal is received.In this case the PILOT2003 command serializer in the control room must make certain thatthe transmission of L1 signals has priority over all other commands.

•The serial data protocol ensures a DC balanced transmission on the data line as the PIN diodeamplifier is AC coupled.

•The returning data path of the JTAG chain, TDO, is transmitted using the (G-link) serial link.

FIGURE 11. Link receiver block diagram and output signals.


17

4.2 Functionality

This section describes the functionality of the PILOT2003 command deserializer.

4.2.1 Principle of functionality

The 40 MHz clock is used to strobe the serial bit stream arriving on the data input of the PILOTcommand deserializer into a 8 bit shift register. This allows decoding of commands of 8 bitslength. Internally four 40 MHz (25 ns) cycles form a 10 MHz (100 ns) transmission cycle. Thatmeans that when at the rising edge of this 10 MHz clock a command has been decoded it is sentto the parallel port of the deserializer. This allows to maintain a 100 ns time binning even toughthe commands are 8 bits long.

Before the startup phase a reset pattern is sent. Once detected it resets the internal logic of thereceiver. During the startup phase an idle pattern is sent from the control room to the commanddeserializer. This pattern defines the timing of the 10 MHz transmission cycle. Once the receiverfinds the idle pattern to be stable in time the deserializer is considered to be in lock. Thedeserializer searches for 63 consecutive received idle patterns with the same phase. After thesynchronisation data from the input shift register are copied to the parallel port at the time of therising edge of the synchronized 10 MHz. Fig. 28 shows a simplified schematic diagram. Fig. 29shows a wave view diagram. A detailed description can be found in chapter 10.2.

4.2.2 Commands

The idle pattern is a command which is 4 bits long. The serialisation and deserialisation of theidle commands takes (4*25 ns cycles =) 100 ns. After the transmission of an idle command anycommand can be transmitted. This ensures that the transmission time grid is 100 ns. The controland configuration commands are 8 bit long. As a result transmission takes 200 ns. However, thiscontributes to latency but does not influence the time grid. Table 5 shows the availablecommands and the corresponding bit stream. All commands are DC balanced. Thus noadditional precaution to DC balance the transmission is necessary. Although the signalreset_control_receiver has an all 0 pattern the DC balance will be maintained by sending a‘10101010’ code using a 80 MHz clock. The digital receiver will see only the ‘0’ of this code.Having commands of different length (idle command 4 bit, all others 8 bit) has the disadvantagethat the idle command must not be contained in any other command or must not be created bysending two other commands after each other.

The command for the JTAG signal is 8 bit long. 4 bits define a JTAG transmission. Theremaining 4 bits define the JTAG data bits (TMS and TDI). As the transmission of 8 bits takes200 ns the maximum JTAG transmission frequency is 5 MHz.

Table 5 summarizes all valid commands. Each command activates the corresponding paralleloutput of the deserializer. As the commands are all 8 bits long commands, signal outputs areactivated at least for a duration of 200 ns. When commands are sent more than once


18

consecutively the output is activated as long as the command is sent, but always a multiple of200 ns.

Exceptions are the trst_standard_on and trst_standard_off signals and the JTAG command. ThePILOT2003 chip has to distribute the JTAG chain to both the pixel chips and the GOL chip.However, the pixel chips require the trst input signal to be high during normal data readout whilethe GOL documentation suggest to activate (low) the trst signal when JTAG is not being used. Asa result two independent trst outputs, one for the pixel chips and one for the GOL chip have beenforeseen. The trst_pixel command activates the corresponding output only during the commandtransmission. The trst_standard_on signal activates the corresponding output and the outputremains in this state until the trst_standard_off deactivates the signal again.

The idle_control signal is activated each time an idle pattern has been detected. Each time anunknown pattern has been found the error_control (see paragraph 3.2) signal is activated. Bothsignals are sent back to the control room via the G-link in order to facilitate the setup and errordetection.

4.2.3 LHC clock synchronisationThe PILOT2003 chip transmits the fastOr information from the pixel chip to the ALICE triggersystem. In order to synchronize the rising edge of the 10 MHz clock of all half staves to the same25 ns bunch crossing, the on detector 10 MHz clock must be synchronized to the LHC 40 MHzclock.

The phase of the OPS 10 MHz clock can be adjusted. The idle command bit stream sent from thecontrol room to the PILOT2003 chip is a 10 MHz square wave. The on detector 10 MHz clockphase will follow the phase of the idle command. In order to adjust this phase by a multiple of25 ns the phase of the idle command must be shifted accordingly. The PILOT commanddeserializer will detect this shift and realign the on detector 10 MHz phase after 128 consecutiveidle cycles have been sent with the new phase.

TABLE 5. Pixel control receiver commands.

commandscode binary

code hexadec.

reset_control_receiver 00000000 00

reset_global 11101000 e7

reset_gol 11100100 e4

reset_pixel 11100010 e2

trst_pixel 11100001 e1

trst_standard_on 10110100 b4

trst_standard_off 10110010 b2

l1 01010110 56

l2y 01011010 5a

l2n 01010101 55

testpulse 11011000 d8

jtag 1010,(tms,tms,tdi,tdi)

a.....

idle 1100 c

Programmable features in the OPS

19

4.2.4 Operation modesThe PILOT command deserializer can work in two operation modes.

Serial input data and the clock can be sent to the chip using the optical input serial_opt, clk_optor the LVDS inputs serial_plus, serial_minus, clk_plus, clk_minus. The pin OPT_INT definesthe input mode. OPT_INT set to logic ‘1’ activates the optical inputs.

5. Programmable features in the OPS

5.1 Programmable features in the PILOT2003

The configuration register can be programmed using the JTAG protocol. After a reset defaultvalues are resumed.

•data_format_trigIf set ‘1’ to the data format as described in paragraph 3.1 is applied. This data format supportsthe transmission of the fastOr signals. If set to ‘0’ the same data format as used in PILOT1,see section 11.1, is used. Default value is ‘1’.

•seb_meb (single event buffer / multi event buffer):If seb_meb is set to ‘0’ only one out of the four multi event buffers in the pixel chips are used.If seb_meb is set to ‘1’ all (four) multi event buffers in the pixel chips are used.Default value is: 1.

•mask_chip <9..0>:Mask_chip allows skipping chips from the readout process. A ‘1’ in the mask_chip vectorstands for the activation of the readout of the corresponding chip. A ‘0’ skips the readout ofthe chip.Default value is ‘1’ for each chip.

•event_number <9..0>:Event_number can be preset to any value. It is increased after each reception of a L1 signal.Default value is: 0.

•strobe_cyc_number <3..0>:Strobe_cyc_number sets the length of the strobe signal in steps of (10 MHz) clock cycles.Strobe_cyc_number = 0 corresponds to a strobe signal length of one 100 ns clock cycle.Default value is 0.

•wait_before_ro <2..0>:wait_before_ro defines the number of clock cycles after ce_i on the pixel chips has beenactivated before the first valid data row arrives on the pixel data bus. Default value is 1.

•hold_ro:in case the G-link loses lock during data transmission the transmission is stopped until thelink is up again. The OPS resumes the transmission of the same event if the option bit hold_rois set to 1. However, three pixel row data lines might be lost. Thus when the transmission isresumed data slot 1a is sent again. The register mask_chip defines the chips still to be read outand the row address indicates the first row being sent in slot 1b. If hold_ro is ‘0’ the eventtransmission is aborted and the corresponding data in the pixel chip readout buffers cleared.Default value is 1.

•skip_jtag_mode <2:0>:In the on detector pilot system OPS the pixel chip distributes the JTAG signals (see fig. 12).The default JTAG chain starts in the PILOT2003 chip. Then the pixel chips are connected in adaisy chained way. The tdo signal of the last pixel chip is connected to the PILOT2003 chip.The JTAG tdo signal from the pixel chips are connected to the ANAPIL chip. From there thetdo of the ANAPIL is connected to the tdi of the GOL. The tdo output of the GOL is

PILOT2003 periphery

20

connected to the PILOT2003 chip. The configuration register skip_jtag_mode allows tobypass either the pixel chip JTAG chain or the ANAPIL - GOL chip chain or both of them. Bit2 of the register skip_jtag_mode defines whether the tdo bit of the last pixel chip (tdo9) of thetdo of the last but one pixel chip (tdo8) should be read.skip_jtag_mode <2> = ‘1’ tdo8skip_jtag_mode <2> = ‘0’ tdo9

skip_jtag_mode <1:0> = ‘00’ skip_noneskip_jtag_mode <1:0>:= ‘10’ skip_golskip_jtag_mode <1:0>:= ‘01’ skip_pixelskip_jtag_mode <1:0>:= ‘11’ skip_all

•enable_ce_sequif set the 10 ce_i signal which are sent to the 10 pixel chips are activated only one after theother in order to reduce digital noise. If the bit is reset (‘0’) all pixel chips receive the ce_isignals at the same time. Default value is ‘1’.

•l2_rd_ptr <1:0>, l2_wr_ptr <1:0>, l2_y_fifo <1:0>, l2_n_fifo <1:0>are read only registers. L2_rd_ptr and l2_wr_ptr give the value of the L2 fifo read and writepointers for the L2y and L2n FIFOs in the copy of the multi event buffers of the pixel chips inthe PILOT2003 chip. L2_y_fifo and l2_n_fifo give the content of the FIFO itself.

6. PILOT2003 periphery

This section describes the inputs and outputs of the pilot2003 chip.

Fig. 13 shows the internal structure of the chip. Fig. 14 illustrates the input and output signals ofthe PILOT2003 chip. There are three groups of inputs and outputs:

•ports connected to the control room,

•ports connected to the pixel chips and

•ports connected to the GOL and ANAPIL.

6.1 Control room ports: Clock and command inputs

The PILOT2003 chip has two connections for signals coming from the control room. One is theLHC-40 MHz clock and the other is a serial data input. The mode pin opt_int allows selectionbetween LVDS inputs (serial_plus, serial_minus, clk_plus, clk_minus) or inputs (serial_opt andclk_opt) for PIN diodes connected to optical fibers.

FIGURE 12. JTAG chain switch.

PILOT2003 periphery

21

The command deserializer in the PILOT2003 decodes the serial data stream and provides thesignals to the PILOT2003 chip core. The PILOT2003 core receives the control signals, L1, L2y,L2n, test_pulse, reset_global, reset_gol, reset_pixel, and the JTAG signals, tck, tdi, tms, tdo (seeblock diagram in fig. 13).

The output signals from the pilot_core (busy, the JTAG return path, the control signals for thetransmission, status and error signals, and the pixel data are sent to the pilot transmitter (GOL).

6.2 Pixel chip ports

The output drivers of the pixel chip are implemented as open drain outputs and resemble GTLlogic. (The low logic level is put to 0V instead of 0.4 V, the logic high state is defined by thevoltage of the external pullup resistor Vtt = 1.8V). The voltage on pin Vgtlref defines the thresholdbetween logic 0 and logic 1 for all open drain inputs. All inputs and outputs of the pixel chip arelow active with the exception of the JTAG signals and the fastOr signal.

Upon reception of a L1 signal in the PILOT2003 a strobe_i signal is sent to all pixel chips whichloads the hits into the multi event buffers of the pixel chips. In case a L2y signal has beenreceived the PILOT2003 chip sends the shreg_reset_i signal to clear the readout buffers. Then anevr_i (next event read) and ce_i is sent to all pixel chips. The PILOT2003 sends next event readcommands to all chips one after the other in order to reduce digital noise. The configurationregister enable_ce_sequ can be reset to disable this function. In this case the next event readcommands are sent to all pixel chips at the same time. As a result all 10 ce_i lines will be activeat the same time. The next event read command moves the hit data from the corresponding multievent buffer into the readout buffer. Now the PILOT2003 asserts ce_i for (256 + 2) clock cyclesto each pixel chip one after the other in order to shift out 256 columns onto the 32 bit wide outputbus. On each negative PILOT2003 clock cycle one row is shifted out. The pixel chip clock inputclk is connected to the PILOT2003 chip clock signal output clk_i (inverted PILOT2003 chipclock) and the pixel chip clk_i input to the PILOT2003 chip clock output clk. This assures that

FIGURE 13. PILOT2003 internal structure.

PILOT2003 periphery

22

setup and hold time requirements for both the PILOT2003 and the pixel chips are not violated asthe pixel chip validates the data bus with the falling edge of the PILOT2003 chip clock and arelatched with the rising edge. The pixel chip control signals arrive shortly after the falling edge ofthe pixel chip clock and are latched on the rising edge of the clock (with the exception of theJTAG signals). The draw back is that signals have 50 ns only to settle (compared to 100 ns).However, 50 ns are still more than sufficient. Between the assertion of ce_i and the actual arrivalof the first row on the output bus there is a time delay of 2 clock cycles. The waveview diagramin fig. 15 illustrates the process. For simulation purposes the time between L1 and L2y has beenreduced.

In case of reception of a L2n signal the PILOT2003 chip sends a clev_i (clear event) and the ce_isignal to all pixel chips one after the other (unless the sequential option is disabled) to advancethe multi event buffer pointer without shifting data to the readout buffer.

tck_gol

tdo_gol

tms_gol

trst_gol

link_bus<15:0>

temp

reset_in

fastor_bus<9..0>@

pixbus_i<31:0>@

opt_int

cavdav

reset_i_golclk_40_gol

VDD_p_e1GND_p_e1

VDD_c_n

GND_c_n

ready_glink

tdi_gol

VDD_p_n1

GND_p_n1

vgtlref#

GND_p_n3

VDD_p_s2

GND_p_s2

clev_i

clk_out_iclk_out

nevr_i

reset_pixel_i

shreg_reset_istrobe_i

test_pulse_out

ce_i<9:0>

tck_pixel

tdo_pilot_tdi_pixel

tms_pixel

trst_pixel

tdo_pixel9_tdi_pilot_in@

VDD_p_w1 VDD_opt1

VDD_p_s1

GND_p_s1

GND_p_w2

clk40_minusclk40_plus

serial_minusserial_plus

GND_c_e

clk_opt#

serial_opt#

VDD_p_n2

VDD_c_s

GND_c_s

GND_p_n2

control room

pixel chips

GOL

pixel chips

GOL

supply

control signals

pixelbus

GOLstatus

JTAG pixel chip

JTAG GOL

inputs

pixel control

GOL control & data

JTAG pixel chip

JTAG GOL

outputs

clk40_1_outclk40_lvds_minus

clk40_lvds_plus

tdo_pixel8_tdi_pilot_in@

VDD_p_n3

VDD_p_w2

GND_p_w1

VDD_c_w

GND_c_w

GND_p_e2GND_p_e3

VDD_opt2VDD_opt3

VDD_c_e

FIGURE 14. Inputs and outputs of PILOT2003.

Configuration, internal registers and test structure in the chip

23

The 32 bit GTL logic data bus of the pixel chips is called pixbus_i<31..0>.

Each pixel chip provides a fastOr signal which indicates that at least one pixel within a chip hasbeen hit. The 10 fastOr signals are connected to the PILOT2003 chip which transmit the 10 bitsto the SPD trigger system to be used as L0 input for the ALICE trigger system [8].

The CMOS level input temp of the PILOT2003 can be used to transmit information on a singlebit to the control room. In the OPS this is used to transmit temperature information provided bythe ANAPIL3 on a serial data bit stream.

6.3 Ports connected to the GOL chip

All signals are implemented using CMOS logic levels. The interface is implemented using thesignals GOL status and GOL control & data as shown in fig. 14. [1] describes the GOL chip indetail. In the on detector pilot system the GOL is used in the 16 bit mode where 16 bit data arelatched and transmitted on the falling edge of the 40 MHz clock. (The GOL input pinconf_negedge is set to ‘1’). As a result the data are encoded in a 800 Mbit/s stream. The GOLallows transmission of 16 bit control data if the control bit dav is active. It sends 14 bit controldata if the bit cav is active. If neither cav nor dav is active an idle pattern is sent which allows theG-link receiver to synchronise the PLL. Flag bits are not used.

7. Configuration, internal registers and test structure in the chip

The JTAG interface complies to the standard with two exceptions. The timing of TDO and TMSwith respect to TCK is different. TDO and TMS are updated already before the falling edge ofTCK and stay active until the rising edge of TCK. The second exception is that when an

FIGURE 15. Pixel chip control and data signals.


24

unknown instruction is sent to the controller the connection between TDI and TDO is completelyinterrupted.

7.1 JTAG instructions

Table 6 gives the instruction codes and the corresponding instructions.

7.2 Configuration registers

The configuration registers are accessed via the serial JTAG interface of the PILOT2003. Table 7gives the configuration registers and their order in the JTAG chain. The configuration registersare triplicated in order to recover from SEU. The data stream of the read process contains allthree triplicated configuration registers. Thus also the value written to the configuration registershas to be triplicated in the data stream.

TABLE 6. JTAG instructions.

instruction code <4:0> instruction

hex’00 exttest

hex’01 idcode

hex’02 sample

hex’03 intest

hex’09 configuration register creg; read/write

hex’0A configuration register creg; read only (status)

hex’0B internal state machine register access

hex’0F bypass

TABLE 7. Pilot 2003 Configuration registers.

number access length A B C

Read or Read/Write bits bits bits

l2_rd_ptr_in Read 2 48:47 A + 49 A + 98

l2_wr_ptr_in Read 2 46:45 A + 49 A + 98

l2_y_fifo_in Read 4 44:41 A + 49 A + 98

l2_n_fifo_in Read 4 40:37 A + 49 A + 98

meb_val_in Read 3 36:34 A + 49 A + 98

data_format_triga Read/Write 1 33 A + 49 A + 98

enable_ce_sequa Read/Write 1 32 A + 49 A + 98

skip_jtag_mode_jtaga Read/Write 3 31:29 A + 49 A + 98

hold_ro_jtag Read/Write 1 28 A + 49 A + 98

strobe_cyc_number_jtag Read/Write 4 27:24 A + 49 A + 98

event_number_jtag Read/Write 10 23:14 A + 49 A + 98

mask_chip_jtag Read/Write 10 13:4 A + 49 A + 98


25

7.3 Boundary Scan (JTAG) on Inputs and Outputs

Almost all pins can be read and written to using the JTAG interface. The order and accessoptions of the inputs and outputs of the chip using the JTAG chain (boundary scan) is given intable 8.

seb_meb_jtag Read/Write 1 3 A + 49 A + 98

wait_before_ro_jtag_jtag, Read/Write 3 2:0 A + 49 A + 98

a. was not available in PILOT1. (B was A+45, C was A + 90)

TABLE 8. JTAG accessibility of I/O ports (Boundary scan).

number direction/logic access length bits

Read or Read/Write

clk40_lvdsa

a. serial_plus and serial_minus LVDS inputs are not connected to a boundary scan cell.

LVDS_in Read 1 81

reset_in cmos_in Read 1 80

ready_glink cmos_in Read/Write 1 79

temp cmos_in Read/Write 1 78

opt_int cmos_in Read 1 77

pixbus_i gtl_in Read/Write 32 76:45

fastor_bus gtl_in Read/Write 10 44:35

reset_i_gol cmos_out Read/Write 1 34

link_bus cmos_out Read/Write 16 33:18

dav cmos_out Read/Write 1 17

cav cmos_out Read/Write 1 16

reset_pixel_i cmos_out Read/Write 1 15

shreg_reset_i cmos_out Read/Write 1 14

ce_i cmos_out Read/Write 10 13:4

strobe_i cmos_out Read/Write 1 3

nevr_i cmos_out Read/Write 1 2

clev_i cmos_out Read/Write 1 1

test_pulse_out_ cmos_out Read/Write 1 0

TABLE 7. Pilot 2003 Configuration registers.

number access length A B C

Read or Read/Write bits bits bits


26

7.4 Internal registers

Most of the internal registers of the state machine can be read and written to via the JTAGinterface for test reasons. To access internal registers a reduced JTAG cell has been implemented.Fig. 16 shows the schematics. It complies with the JTAG standard with the exception of themissing update flip flop. This configuration allows to read the new value (signal in) of an internalstate machine and allows to write the new value to the state machine. After one single systemclock cycle the results of a previously conducted write operation can be read back. Table. 9 givesthe name of the accessible registers and their order of the JTAG chain.

All internal logic is triplicated in order to recover from SEU. Thus both when writing andreading the triplicated registers are accessible individually as separate registers.

TABLE 9. Internal registers.

number A A B C

length bits bits bits

i_pilot_sm.first_event_new 1 C + 128 C + 64 64

i_pilot_sm.remaining_chips_new 10 C + 128 C + 64 63:54

i_pilot_sm.event_number_new 10 C + 128 C + 64 53:44

i_pilot_sm.row_add_new 8 C + 128 C + 64 43:36

i_pilot_sm.wait_before_ro_new 3 C + 128 C + 64 35:33

i_pilot_sm.state_new 5 C + 128 C + 64 32:28

i_l2queue.clear_new 1 C + 128 C + 64 27

i_l2queue.start_ro_new 1 C + 128 C + 64 26

i_l2queue.l2_rd_ptr_new 2 C + 128 C + 64 25:24

i_l2queue.idlecnt_new 2 C + 128 C + 64 23:22

i_l2queue.id3_new 1 C + 128 C + 64 21

i_l2queue.l2_n_fifo_new 4 C + 128 C + 64 20:17

i_l2queue.l2_y_fifo_new 4 C + 128 C + 64 16:13

i_l2queue.l2_wr_ptr_new 2 C + 128 C + 64 12:11

i_strobe_busy.idle_violation_new 1 C + 128 C + 64 10

FIGURE 16. Simplified JTAG cell for internal registers.

Pinout of the PILOT2003 chip

27

8. Pinout of the PILOT2003 chip

The layout of the pixel chip is pad limited. There are 107 I/Os and 29 VDD/GND connections.The die size is 4.22 mm x 6.22 mm. Fig. 17 and 18 show all pins and their location on the chip.In the middle of each side a VDD/GND core connection has been provided. Connections to thepixel chip can be found on the left side and top/left side of the chip. Connections from the pixelchip (pixel bus and fastor) are to be found on the bottom. Connections to the GOL are on theright and top right side. Connections to the pilot from the control room are on the right bottomside. For each 10 to 12 CMOS outputs a VDD/GND pair has been foreseen. VDDcore andVDDperiphery are not connected together on the chip. GNDcore and GNDperiphery areconnected together on the chip. Table 10 gives the pin numbers and the corresponding padnames. Fig. 18 shows the location of the PIN diodes.

i_strobe_busy.busy_violation_new 1 C + 128 C + 64 9

i_strobe_busy.busy_new 1 C + 128 C + 64 8

i_strobe_busy.meb_val_new 3 C + 128 C + 64 7:5

i_strobe_busy.strobe_cyc_cnt_new 4 C + 128 C + 64 4:1

i_strobe_busy.strobe_i_new 1 C + 128 C + 64 0

TABLE 9. Internal registers.

number A A B C

length bits bits bits

FIGURE 18. Die size and pad location.


28

The pilot is intended to be used without package and directly wire bonded onto the pilot multichip module pilot MCM. Fig. 17 and 18 illustrates the location of the pins on the chip.

TABLE 10. Pad names, location and description.

IC Pad

Pin # Name Type Description

1 link_bus<15> CMOS_out data bus between pilot and GOL; values are updated on the rising edge of clk40

2 link_bus<14> CMOS_out data bus between pilot and GOL



5 link_bus<11> cmos_out data bus between pilot and GOL



FIGURE 17. Pad location on the chip.


29


9 VDD_p_n3 supply peripherie

10 GND_p_n3 supply peripherie









19 tck_gol cmos_out

20 VDD_c_n supply core

21 GND_c_n supply core

22 tms_gol cmos_out

23 tdi_gol cmos_out

24 tdo_pixel8_tdi_pilot_in gtl_in

25 tdo_pixel9_tdi_pilot_in gtl_in



28 clk_out cmos_out negative clk for pixel chips

29 clk_out_i cmos_out positive clk for pixel chips

30 reset_pixel_i cmos_out global reset for pixel

31 tdo_pilot_tdi_pixel cmos_out

32 tms_pixel cmos_out

33 trst_pixel cmos_out

34 tck_pixel cmos_out



37 ce_i<0> cmos_out chip enable for PILOT2003 chip 0










IC Pad



30


47 GND_p_w2 supply periphery

48 VDD_p_w2 supply peripherie

49 nevr_i gtl_out new event read signal for all pixel chips

50 clev_i gtl_out clear event signal for all pixel chips

51 strobe_i gtl_out strobe signal for all pixel chips

52 shreg_reset_i gtl_out shift register reset for all pixel chips

53 test_pulse_out gtl_out test pulse for all pixel chips

54 temp cmos_in single bit transmitted to router

55 GND_c_w supply core

56 VDD_c_w supply core

57 fast_or_in<9> gtl_in fastOr signal from pixel chips





62 GND_p_w1 supply periphery

63 VDD_p_w1 supply peripherie






69 pixbus_i<31> gtl_in data bus from pixel chips








77 VDD_p_s2 supply periphery

78 GND_p_s2 supply periphery







IC Pad



31






89 VDD_c_s supply core

90 GND_c_s supply core















105 VDD_p_s1 supply periphery

106 GND_p_s1 supply periphery

107 Vgtlref analog_in Threshold voltage for GTLrx.

108 reset_opt_receiver cmos_out when the serial optical data input sees 8 consecutive ‘0’ a the input becomes active (low). Can directly be connected to reset_in.

109 reset_in cmos_in global reset, low active, minumum length is 200 ns.

110 opt_int cmos_in input mode selector (‘1’ is optical input, ‘0’ is electrical input)

111 GND_p_e3 supply periphery

112 VDD_OPT_LVDS supply optical amplifier

113 vdd_opt3

114 serial_opt PIN diode input PIN diode of serial data

115 vdd_opt2

116 clk_opt PIN diode input PIN diode of clk40

117 vdd_opt1


IC Pad


Additional features in PILOT2003

32

9. Additional features in PILOT2003

The functional differences between the pilot1 and PILOT2003 chip are highlighted.

9.1 10 FastOr lines

The 10 fastOr lines coming from the 10 pixel chips connected to the PILOT2003 are transmittedvia the G-link. As the timing of the fastOr signal of the pixel chip is varying according to thepixel chip settings the fastOr input stage of the PILOT2003 chips has been implemented asuniversal as possible.

The fastOr signal in the pixel chip gets updated on or after the falling edge of the pixel chip 10MHz clock and stays active until the rising edge of the clock. However, tests with test pulseshave shown that the pulse length is dependent on the location of the pixel within the matrix andthe latency depends on the arrival time of the test pulse with respect to the clk10 signal. Thepulse length can be as short as 20 ns. Tests with real particles (in the beam or sourcemeasurements) have not been conducted before the PILOT2003 chip has been submitted. As aresult neither a 10 MHz nor a 40 MHz clock edge could be identified where the fastOr signalsafely can be latched into the PILOT2003 state machine.

118 serial_plus LVDS_in electrical conn. for serial control

119 serial_minus LVDS_in electrical conn. for serial control

120 clk40_minus LVDS_in electrical conn. for clk40

121 clk40_plus LVDS_in electrical conn. for clk40


123 ready_glink GOL status signal, if high GOL is ready00f

124 reset_i_gol CMOS_out

125 dav CMOS_out control signal to GOL

126 VDD_c_e supply core

127 GND_c_e supply core

128 cav CMOS_out control signal to GOL

129 clk_40_gol CMOS_out CMOS clk output for GOL chip

130 clk_40_1_out CMOS_out spare clk output


132 VDD_p_e1 supply peripherie

133 clk40_lvds_plus LVDS_out LVDS clk output for GOL chip

134 clk40_lvds_minus LVDS_out LVDS clk output for GOL chip

135 trst_gol cmos_out

136 tdo_gol cmos_out


IC Pad



33

Thus, the fastOr inputs to the PILOT2003 set a flip-flop asynchronously. This has the advantagethat the fastOr pulse will be registered regardless to its length, but noise on the fastOr line willalso be registered as fastOr pulse. The flip-flop is reset during the time when the fastOr is certainto be inactive. The transmission of the fastOr within the PILOT2003 to the GOL has beenimplemented in such a way that a minimum latency within the PILOT2003 is guaranteed.

9.2 Data format

The data format has been changed to accommodate the fastOr information.

A control register data_format_trig allows the change to the data format used in the pilot1 chip,see section 5.1.

9.3 Chip enable sequence

In order to reduce digital noise levels on the bus an operation mode has been implemented where10 pilot chips are not addressed at the same time but sequential one after the other.

The L2 decision is forwarded to the pilot chips on the nevr_i and clev_i signals. These controlsignals are validated by asserting the pixel chip enable ce_i signals. If the configuration registerenable_ce_sequ is ‘1’ (default) the ce_i signals are asserted one after the other for all 10 chips.This feature increases the readout time by 900 ns. In case the register is set to ‘0’. All ce_i signalsare activated at the same time.

9.4 Pixel control signal logic levels are changed from GTL to CMOS

In order to decrease the noise level on the MCM and bus all control signals to the pixel chipshave been implemented as CMOS level signals.

The GTL signals used in the PILOT1 required a pullup resistor for each control signal. This tookspace on the pixel bus and consumed up to 18 mA per control line. This current is very likely toincrease the ground bounce between MCM and pixel bus.

In the PILOT2003 all control signals to the pixel chip are implemented using slew rate controlled(~7 ns rise time) CMOS output buffers (OBS16mA_ESD). The power supply of the outputdrivers (VDD_p_w2, VDD_p_n1) are separated from the other supplies. This allows to connectthe pixel chip power supply level to the control signal output drivers. The supply voltage levelsof the pixel chips on the MCM are created using a voltage divider (see fig. 19 and 20). Thisavoids the connection of the pixel chip power supply to the MCM which possibly wouldintroduce noise. Thus the voltage swing of the control signals is between 0V and Vdd_pixel. Fig.17 shows the concerned output drivers in the top left corner of the chip.

Concerned signals are: reset_pixel_i, tdo_pilot_tdi_pixel, tms_pixel, trst_pixel, tck_pixel, ce_i<9..0>, nevr_i, clev_i, strobe_i, shreg_reset_i, test_pulse_out.

9.5 Pixel chip clock signals are changed to CMOS levels

The clock signals from the PILOT1 to the pixel chip have been implemented using GTL logic.The GTL logic drivers structure is asymmetric. As a result the time of rising/falling edge of thenon-inverted clk_out signal was not at the same time as the falling/rising edge of the invertedclk_out signal (see fig. 21 and fig. 22). Thus a skew between clk_pixel and clk_out_i arised. The


34

FIGURE 19. Schematic of pixel chip control signal distribution with PILOT2003.

FIGURE 20. Simulated wave view diagram of slew rate controlled control signals in the PILOT2003 configuration.


35

pixel chip uses the two clock inputs independently and not as differential inputs. Measurementshave shown that a skew of higher than 3 ns degrades the pixel chip performance.

Both clk_out and clk_out_i are implemented as slew rate controlled (~ 7 ns) CMOS drivers(OBS16mA_ESD). The power supply of the two signals is connected to VDD_p_n2 exclusively.Two connection schemes are possible. VDD_p_n2 is connected to the power supply levels of thepixel chip (VDD_pixel = 1.8V). In this case the logic levels of the clock signals are correct andthe signals can directly be connected to the pixel chips. The other option is to power the outputswith VDD_MCM= 2.5V and terminate the output signal in such a way that the terminationattempts an adaptation to the pixel bus and reduces the logic levels on the pixel chip inputs toVDD_pixel = 1.8V. Fig. 23 and 24 show the logic diagram and SPICE simulations. Theimpedance of the pixel bus is estimated to be 14 Ohm. The output drivers do not allow a propertermination of such a low impedance transmission line. However, the values given in fig. 23 are agood compromise.

As all GTL output drivers have been removed the analog bias voltages for the output driversVcsn_gtl_out, vcsp_gtl_out have been removed. The analog bias voltages for the GTL signal

FIGURE 21. Schematic of pixel chip clock distribution with PILOT1


36

receivers Vcsnr_gtl_in, vcspr_gtl_in have been connected inside the chip to Vdd and Gnd. Thusthe ability to modify the slew rate of the input signals within the chip has been taken away.

FIGURE 22. Simulated wave view diagram of GTL-like pixel clock signals in the PILOT1 configuration.

FIGURE 23. Schematic of pixel chip clock distribution with PILOT2003.


37

9.6 Synchronisation of 10 MHz PILOT system clock to LHC clock

In view of the fastOr trigger implementation the OPS 10 MHz clock must be aligned to the LHCclock. The OPS operates on a 10 MHz clock. As a consequence the fastOr trigger system cannotidentify single bunch crossings, but four consecutive bunch crossings. In order to ensure that all120 PILOT2003 systems point to the same for bunch crossings the 10 MHz system clock mustbe synchronized accordingly.

The PILOT2003 chip uses the idle command sent on the data link as reference. The internal logicmonitors the phase of the idle command. The idle command is a 10 MHz square wave. Theresulting 10 MHz clock which is derived from the 40 MHz input clock is in a fixed phase relationto the 10 MHz idle square wave. In case adaptation of the phase between 10 MHz OPS systemfrequency and the 40 MHz LHC clock is required the control room located electronics changesthe phase of the idle square wave. The PILOT2003 logic detects the phase change, verifies thatthe phase change persists for at least 128 clock cycles and readapts the phase of the 10 MHz OPSfrequency. Fig. 25 shows a wave diagram illustrating the phase readaptation process.

9.7 Changes of the inputs and outputs

The electrical single ended CMOS trigger and control inputs have been removed as only theserial input stream is used. The signals which have been removed are listed below:

•All 5 JTAG signals: tck, tms, tdi, tdo, trst.

•L1, L2y, L2n, test_pulse_in.

FIGURE 24. Simulated wave view diagram of CMOS symmetric and terminated clock signals in the PILOT2003 configuration.


38

FIGURE 25. Wave Diagram illustrating the 10 MHz clock re synchronisation process.


39

The operation mode inputs opmode[1:0] have been replaced by a single input opt_int. The testport feature has been removed.

Separate clk40 connections for the GOL (1 LVDS output; clk40_lvds_plus, clk40_lvds_minusand 1 CMOS output; clk_40_gol) and for the ANAPIL (1 CMOS output; clk40_1_out) has beenimplemented.

A JTAG chain input to the PILOT2003 connected to the pixel chip chain has been added. Innormal conditions the tdo_pixel9_tdi_pilot_in is used. However, in case the JTAG chain isbroken in pixel chip 9 the JTAG chain must be tapped off the pixel chip 8 and connected totdo_pixel8_tdi_pilot_in. The configuration register skip_jtag_mode defines the input to be used.

The input polarity of the serial data input has been corrected and is now inverted compared topilot1.

The output reset_opt_receiver has been added as CMOS output to the chip. It is connected to thereset output of the PIN diode amplifier rx40. As soon as eight or more consecutive logic ‘0’ arereceived by the amplifier this signal becomes active. It can be directly connected to the reset_ininput of the PILOT2003 to perform a global reset of the PILOT2003 chip.

9.8 JTAG timing and synchronisation

The PILOT2003 fully supports the non-standard JTAG ports of the pixel chips. Asynchronisation problem found in PILOT1 has been removed.

The PILOT2003 chip updates the data and control lines (TMS, TDO) of the JTAG lines going tothe the pixel chip, the GOL and the ANAPIL 50 ns before the falling edge of the JTAG clockTCK. Data stay valid until 50 ns after the rising edge. This ensures that both the non-standardJTAG controller in the pixel chip and the standard JTAG controllers in the GOL and ANAPIL areoperating with the same PILOT2003 JTAG controller. Fig. 26 shows the timing of the signals.

In PILOT1 a synchronisation problem was found which introduced an uncertainty of the arrivaltime (0 ns to 75 ns) of TDO, TMS to the pixel chips. This uncertainty has been removed.

FIGURE 26. Timing diagram of the PILOT2003 JTAG controller.

Implementation details

40

9.9 ESD protection

All inputs and outputs have been connected to protection diodes. Power supply, pheripherysupply and GND have been connected to power clamps.

The library components IB1_EDS, OBS16mA_ESD, LVDStx_ESD, LVDSrx_ESD have beenused. The analog PIN diodes receivers have been modified to accommodate protection diodes.

Five power clamps in series have been added between all power supplies and GND.

9.10 Reset signal length

The minimum length of the reset signal on the input pin is 100 ns (compared to 200 ns in thepilot1). When sending the reset on the serial link the command only has to be sent once (insteadof two consecutive reset commands in the pilot1).

9.11 Voting on cnt4 register

The register used to create the 10 MHz clock from the 40 MHz clock is now triplicated and votedon to reduce effects caused by single event upsets. However, in order not to increase the skewbetween clk10 and clk40 on chip the clk10 is distributed from one of the three clk40 registersand not from the voted result.

10. Implementation details

10.1 SEU in the OPS

The architecture to make the OPS2003 resistant to SEU is discussed.

Although the ASIC process seems to be quite resistant against SEU itself, especially in theALICE environment [13], several precautions have been undertaken to prevent failure due toSEU.

All internal logic is triplicated. Fig. 27 shows the principle. The three outputs of the independentblocks are connected to an output voting gate where a 2 out of 3 majority voting logic recoversthe original output value in case of a SEU.

However, all storage elements which have to keep the values for more than one clock cycle suchas configuration or state registers, are not protected by this scheme. A SEU in one of theseregisters would corrupt the data output of the corresponding block until the next reset. Thus theseregisters are built in a self recovering manner. The output of the state machines (in the threeidentical blocks) are fed to a voting gate. The recovered state is fed back to the state machine oflogic block a. The output state of logic block a is received by logic block b and the state of logicblock b is received by logic block c. This configuration ensures recovery after the maximum ofthree clock cycles even if the output of the voting gate was set up. Additionally an error signal isasserted once a mismatch in the voting logic is detected. In case of a single SEU in the logic itwill be recovered within one to three clock cycles. Should the error signal stay active for a longertime than 3 consecutive clock cycles data transmission will be sustained but data might becorrupted and a reset is recommended.


41

10.2 Synchronisation of the PILOT command deserializer

Fig. 29 illustrates the synchronisation process. Four 40 MHz clock cycles form a 10 MHztransmission cycle. In the synchronisation process the PILOT command serializer sends the idlecommand “1100” which allows the PILOT command deserializer to identify the differenttransmission cycles. In other words during the synchronisation process the receiver finds the40 MHz clock cycle after which the 4 bit command has fully arrived in the deserializer.

The serial data stream is loaded into a shift register. As soon as the idle pattern is recognized inthe receiver the found_idle signal is activated and the position of the arrival cyc of the idle signalwithin the data stream is stored in the register idle_cyc. The next arrival of the idle signal is againrecognized and the position cyc is compared to the previously stored. If the new and old positionmatch the counter cyc_match_cnt is increased by one. This is repeated as long as the countercyc_match_cnt equals 63. Then the position cyc is loaded into the register idle_cyc_locked andthe internal state is advanced to locked state. From now on every time the cycle counter cyc

FIGURE 27. Voting scheme.

FIGURE 28. Data flow in PILOT command deserializer.


42

equals the value of idle_cyc_locked the parallel output of the shift register is copied into theregister data_int. Fig. 28 illustrates the data flow. The parallelized command is encoded and thecorresponding outputs are activated. However, the encoding is controlled by the 10 MHz clockwhereas the parallelization is clocked by the 40 MHz clock. In order to establish an interfacebetween the logic working with two different clocks the register data_int is strobed into anintermediate register data_int_s1 by the negative falling edge of the 40 MHz clock in order toavoid setup or hold time violations caused by a skew between the two clock systems. All outputsignals can be directly decoded from the received command word except trst_standard_on,trst_standard_off and tck. The two trst_standard commands set and reset the internal single bitregister trst_standard. The signal tck is generated each time a JTAG command has been received.JTAG standard requires tms and tdi to be stable before the rising edge of the JTAG clock signaltck. Thus both signals change during the falling edge of tck. However, the pixel chip JTAGinterface does not comply with JTAG standards. It strobes tdi and tms during the falling edge oftck. As a result the PILOT command deserializer already provides the signals tdi and tms beforethe falling edge of tck. The timing can be seen in fig. 26. When no JTAG command is receivedtck, tms, trst_pixel and tdi are set to ‘1’. Each time a JTAG command is received the internalsignal generate_tck is activated. One 40 MHz clock cycle or 25 ns later tdi and tck are updated.One cycle or 75 ns after generate_tck tck is set to ‘0’. tck remains low for 100 ns. The resultingJTAG transmission speed is 5 MHz.

10.3 Interface between clock domains in the PILOT2003 chip

The on detector pilot system OPS uses two different clock systems. The serial control receiver,the GOL and its interface in the PILOT2003 run on 40 MHz. The PILOT2003 internal statemachine and the pixel chips run with a 10 MHz clock. Data transfer from the control receiver tothe PILOT2003 state machine is performed on the negative falling edge of clk40. Thus setup and

FIGURE 29. Synchronisation procedure of the PILOT command deserializer.


43

hold time violations are prevented as there is 12.5 ns time delay between the rising edge of clk10and the falling edge of clk40.

When transferring data from the PILOT2003 state machine to the GOL interface the problem isless critical as there will always be a positive delay between clk10 and clk40 since clk10 isderived from clk40. As a result the rising edge of clk40 will always occur before the rising edgeof clk10.

10.4 Core implementation

Fig. 30 shows the top level schematics of the PILOT2003 chip. The building blocks of the coreare described in the following sections. Fig. 31 shows the schematics of the core block.

10.4.1 Strobe and busy generationBlock strobe_busy generates the pixel chip control signal strobe and the status signal busy.

If L1 is active and busy inactive strobe_i is activated for the time duration programmed bystrobe_cyc_number_jtag.

If L1 is active the multi event buffer counter value meb_val is increased. If start_ro or clear isactive the multi event buffer counter value meb_val is decreased by one.

Busy signal is asserted upon the occurrence of L1 if the multi event buffer counter value meb_valis 3. In case the multi event buffer is enabled by the configuration register seb_meb_jtag busy isasserted already upon the occurrence of L1 if the multi event buffer counter value meb_val is 0.

Busy_violation is asserted upon the occurrence of L1 if busy has already been activated.

Idle_violation is asserted upon occurrence of either L2y or L2n if the multi event buffer countervalue meb_val is 0.

10.4.2 L2queueBlock L2queue keeps track of the status of the multi event buffers in the pixel chips.

Upon arrival of either L2y or L2n the L2 write pointer L2_wr_ptr is increased by 1.

The synchronisation signal id3 is activated three cycles after the readout state machine signalledidle state and the glink_ready signal has been active.

The L2y or L2n occurrences are stored in the L2_y_fifo and L2_n_fifo at the position given byL2_wr_ptr.

The signal start_ro is activated and sent to the readout state machine if the L2y_fifo at theposition given by the l2_rd_ptr has an entry and id3 has been activated. The L2_rd_ptr isincreased by 1.

The signal clear is activated and sent to the readout state machine if the L2n_fifo at the positiongiven by the l2_rd_ptr has an entry and id3 has been activated.

Upon activation of id3 the L2n_fifo and L2y_fifo at the position given by the l2_rd_ptr is cleared.


44

FIGURE 30. Top level schematics of the PILOT2003 chip.


45

FIGURE 31. Internal structure of pilot core in pilot2003.


46

10.4.3 Config

Block config stores the configuration registers. Chapter 5 describes the meaning of the registers.Table 7 list the registers and their location within the JTAG chain.

10.4.4 Clk_divBlock clk_div divides the 40 MHz clock into a 10 MHz clock.

Additionally the multiplexer control signal cnt4<1:0> is provided which indicates thetransmission slot and cycle.

10.4.5 reset_filterBlock reset_filter synchronizes the input signal reset.

10.4.6 fastorBlock fastor synchronizes the input signal fastor.

The input is assumed to be high active. The input flip-flop is set asynchronously and reset on thefalling edge of clk40 during the transmission slot 0/1. The transmission of the fastOr signal onthe G-Link is conducted in slot 0/0.

10.4.7 vote1_errBlock vote1_err is the voting gate.

All output signals and internal states are connected to a voting gate. The schematic diagram isgiven in fig. 32. The outputs are the voted inputs and the error output signal. The error signalindicates a mismatch between inputs.

10.4.8 or_seuBlock or_seu is the multiple input or gate of all voting gates.

The output is delivered as seu_error to the control room.

10.4.9 pilot_smBlock pilot_sm represents the pilot readout state machine. Fig. 33 shows the state diagram.

The pilot state machine pilot_sm communicates with the other blocks using the input signalsstart_ro and clear and the output signal idle.

The dark (green) arrows in the state machine illustrate the readout process in case of a L2ysignal. The light (red) arrows follow the states processed in case of a L2n signal. The states notmarked with bold arrows are processed in case the G-link system gets out of lock and interruptstransmission. Depending on the programmable bit hold_ro_jtag the event read out is cancelled

TABLE 11. Relationship between cnt4 value and slot/cycle number.

cnt4<1..0> slot/cycle

0 0/0

1 0/1

2 1/0

3 1/1


47

and the interrupted event is discarded or the transmission is only put on hold and is resumed oncethe G-link is operative again.

The pixel control output signals are directly derived from the states.

10.4.10 gtl_inBlock gtl_in contains all GTL input pads and receivers.

All inputs are read and write accessible by JTAG except tdo_pixel and tdi_pilot_out. Thereceiver gtl_rx is a modified version of the rx1 block used in the pixel chip. The design waschanged from 6 metals to three metals and adapted to cmos6sf25PadLib specifications. Timinginformation was not attached to the cells (all 0 ps).

10.4.11 gtl_outAll GTL output drivers have been replaced by OBS16mA_ESD CMOS slew rate controlleddrivers.

All outputs are read and write accessible by JTAG except clk_out, clk_out_i and all pixel JTAGsignals.

10.4.12 serial_inBlock serial_in contains the LVDS input stage for the serial control data receiver connection.

No JTAG connection has being made.

FIGURE 32. Schematic diagram of vote1_err.


48

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49

10.4.13 cmos_inBlock cmos_in contains all CMOS input pads and receivers IB1_ESD.

Additionally the LVDSrx_ESD receiver for the clock signal are contained in this block.

Clk40, reset and opt_int are read accessible by JTAG. All other signals are read and writeaccessible by JTAG.

10.4.14 cmos_outBlock cmos_out contains all CMOS output pads and drivers OB16mA_ESD.

All signals are read and write accessible by JTAG except JTAG signals and clk40_gol.

10.5 Implementation process

Briefly the various implementation steps are discussed.

The policy trough out the implementation process was to automate as many processing steps aspossible in order to allow for reproducibility. Where ever possible script files were employed.They can be found in the appendix.

10.5.1 GTLrx layout

The layout of GTLrx was produced by modifying a similar cell in the pixel chip (rx1 andcsBpadfin). The original six layer metal design was changed to three metal layers. The layoutwas adapted to fit the cmos6sf25PadLib requirements. No timing information was added, alltimes are 0 ps. Analog simulations have been performed.

10.5.2 Functionality description of the PILOT2003

The functionality of the chip was described using both a schematic entry editor (CadenceComposer) for the top level schematics and VERILOG description code for the building blocks.Time critical blocks have been entered in schematic way.

10.5.3 Functionality verification before synthesis

The PILOT2003 chip logic was tested together with

•a behavioural description of the pixel chips readout. All columns were read. Multi event bufferswere not available. Data in the read out buffers were not constant. The JTAG interface was notpresent.

•a behavioural description of the G-link chip GOL (including JTAG interface).

•a behavioural description of the G-link deserializer.

•a behavioural description of the link_receiver.

•a behavioural description of the pixel control transmitter.

The PILOT1 was tested with more simulation configurations. The PILOT1 chip logic was testedtogether with

•a simplified gate level description of the pixel chip readout. Only two columns were read out.Multi event buffers were not available. Data in the read out buffers were constant. No JTAGinterface was present.

•a behavioural description of the pixel chips readout. All columns were read. Multi event bufferswere not available. Data in the read out buffers were constant. JTAG interface was not present.


50

•a full gate level description of the G-link chip GOL (including JTAG interface).

•a behavioural description of the G-link chip GOL (including JTAG interface).

•a behavioural description of the G-link deserializer.

•a behavioural description of the link_receiver.

•a behavioural description of the pixel control transmitter.

Internal states trough out the system were not checked. The data stream coming out of thelink_receiver was used to build the event corresponding to the input stimulus. In other words theoutput signals of the link_receiver were checked with respect to their timing and their propervalue.

During simulation the JTAG read and write operations have been checked. Single event upsetswere initiated and checked if the original state recovers.

Due to the demanding project schedule the simulations could not have been conducted in a fullyexhaustive manner. JTAG simulations with the pixel chips have not been conducted. Only fourevents in a row were read out. Special cases as when the G-link chip GOL losses synchronisationwere not tested fully. Only the most important features of the configuration registers were tested.

10.5.4 Logic synthesis

All logic except the input and output blocks are contained in the block pilot_core as seen in fig.30. Although some of the logic contained in pilot_core are described using schematics the entireblock has been treated in synthesis tool design_analyzer (Synopsis). The script file used to rundesign_analyzer can be seen in the appendix.

Several instances were used more than once. These instances were compiled only once. As aresult the logic implementation of the instantiation of these instances is identical. (command‘uniquify’ was not used.)

10.5.5 Post synthesisation functional check

Using VERILOG simulations the design was checked after synthesis using timing informationgiven by syntheziser ‘design_analyzer’. Although design_analyzer seems to heavilyoverestimate propagation times the design was error free.

10.5.6 Place and route of the layout

The design was imported into Silicon Ensemble 5.3 using a VERILOG netlist. The entire placeand route process was performed automatically using the script files verilog_in.mac, pilot.macand pilot_cont.mac (see Appendix) invoked one after the other. Automatic clock tree generationwas used to connect the three clock signals, clk40, clk10 and JTAG clock tck.

In the following paragraph the main actions are summarized.The die size is set to 4220 x 6220 micron. I/O to core distance is 1100 micron. I/O cells areplaced using the file pilot2003.ioc referenced in the appendix. In order to gain space on the rightside of the chip for the optical receiver the cell row length is decreased. Special filler cells whichbreak up the IO ring are inserted to build the different IO supply domains. The scriptadd_cap_cells.mac adds terminations cells on the cell rows. Power rings are build around thecore. Three pairs of power stripes each 30 micron wide are build which cross the core. IO fillercells are placed using the script io_filler.mac. Place and routing layers are added on to of thepower stripes. Placing of the components is performed. Automatic clock tree generation isperformed using the constraints file pilot2003_placed.constraint. The power rings are connected


51

to the pads VDD_core and GND_core. No automatic command could be found for that. Theconnection is produced manually and the commands have been pasted into the script file. Fillercells are distributed using the script core_filler.mac. Blockage layers are removed. The powerring is connected to the cell rows. The clocks are routed. Global routing is performed.

10.5.7 Post layout simulation

The VERILOG netlist including the generated clock tree was simulated using timing informationgiven by silicon ensemble (including interconnection delays). No violations could be found inbest, typical and worst case (P=0.57, 1, 2). The clock tree was resimulated using PEARL. Figure34 shows the clock skew using the PEARL calculation after the routing. Times are better thangiven by silicon ensemble before the routing.

10.5.8 Post layout SEU simulation.

Only during the design of the PILOT1 a second SEU simulation using the VERILOG netlist wasconducted. The original digital core library was replaced by a modified one. Each flip flop in themodified library sends its path and component name to a file the first time it is initialized. Thisfile is used to artificially set up the flip flop at least once during simulation. It was checked thatthe original state were recovered. All registers in the design are safe against one SEU during the

FIGURE 34. Clock skew calculated by Silicon Ensemble.


52

time of three clock cycles with the exception of the registers in the JTAG controller andboundary scan cells.

10.5.9 Manual changes in the layout

Once the layout from silicon ensemble was exported to design framework 2 (DFII) some manualchanges had to be applied. All IO cells which are longer than 350 μs (standard cmso6sf25PadLiblength) which are placed either in the top row or in the right row were moved to their properposition. Corner cells and chip edge was placed. RXexclude and PCexclude was placed over theprotection diodes of the input pads. Connection to the Power clamps and Protection diodes weremade. Fig. 35 illustrates the layout of the design.

10.5.10 DRC, LVS, Dracula, Hercules

Design rule checks and layout versus schematics checks have been performed both beforestreaming out the GDSii file and again afterwards.


53

FIGURE 35. Layout of the PILOT2003 chip.

Appendix

54

11. Appendix

11.1 Data format of PILOT1

11.2 Design files

All flles are stored on the micro-electronics cluster machines and the EDMS file server(Keyword: OPS2003)

TABLE 12. Data in link_bus <15:0> when the configuration bit trig_format is inactive

frame 0 frame 0 frame 1a frame 1a frame 1b frame 1b

slot 0 slot 1 slot 2 slot 3 slot 2 slot 3

bit data control & signal feedback

data control & signal feedback

event description

pixel hit data line

pixel hit data line

pixel hit data line







15 no data 31 no data 15, eventnumber 9, 31 remainingchips 3, 15

pixel hit data 31 pixel hit data 15

14 no data 30 no data 14 eventnumber 8, 30 remainingchips 2, 14


13 first_word 29, L2y 13 eventnumber 7, 29 remainingchips 1, 13


12 first_word 28 L2n 12 eventnumber 6, 28 remainingchips 0, 12


11 last_word 27, strobe_i 11 eventnumber 5, 27 row_add 7, 1 pixel hit data 27 pixel hit data 11

10 last_word 26 ce_i <1..0> 10 eventnumber 4, 26 row_add 6, 10 pixel hit data 26 pixel hit data 10

9 clear_event 25, ce_i <1..0> 9 eventnumber 3, 25 row_add 5, 9 pixel hit data 25 pixel hit data 9

8 clear_event 24 tck_return 8 eventnumber 2, 24 row_add 4, 8 pixel hit data 24 pixel hit data 8

7 error_control 23 tdo_return 7 eventnumber 1, 23 row_add 3, 7 pixel hit data 23 pixel hit data 7

6 idle_control 22 tms_return 6 eventnumber 0, 22 row_add 2, 6 pixel hit data 22 pixel hit data 6

5 temp 21 trst_return 5 remainingchips 9, 21

row_add 1, 5 pixel hit data 21 pixel hit data 5

4 seu_error 20 test_pulse 4 remainingchips 8, 20

row_add 0, 4 pixel hit data 20 pixel hit data 4

3 busy 19 nevr_i 3 remainingchips 7, 19

meb_val 2, 3 pixel hit data 19 pixel hit data 3

2 busy_violation 18 clev_i 2 remainingchips 6, 18


1 idle_violation 17 shreg_reset_i 1 remainingchips 5, 17


0 L1 16 fastor 0 remainingchips 4, 16

‘0’ 0 pixel hit data 16 pixel hit data 0

Appendix

55

11.2.1 Design_analyzer script: pilot.script (/user/akluge/pilot/design_analyzer/pilot.script)

11.2.2 Silicon Ensemble script files

•/user/akluge/pilot/se/verilog_in.mac

•/user/akluge/pilot/se/pilot.mac

•/user/akluge/pilot/se/pilot_cont.mac

•/user/akluge/pilot/se/add_cap_cells.mac

•/user/akluge/pilot/se/io_filler.mac

•/user/akluge/pilot/se/core_filler.mac

•/user/akluge/pilot/se/ioplace.mac

11.2.3 Verilog files

The script pilot.script for design_analyzer gives all verilog files used.

11.3 Digital part of the ANAPIL3

This section contains information about the digital part of the ANAPIL3. The chip has beendesigned by G. Anelli, R. Dinapoli and A. Kluge.

The functionality of the digital core can be divided in four groups.

1. It allows programming of six 8 bit DACs via the JTAG interface.

2. It controls the AD-conversion sequence of 16 analogue values and storage of the digital values in internal registers.

3. The internal registers are read out via the JTAG interface.

4. It allows transmission of two analogue values on a serial output.

•Programming of DACs

The digital core allows programming of a 48 bit internal register via the JTAG interface. Eacheight bits are connected directly to six 8-bit DACs. No additional control signals are required bythe DACs.

•Conversion of 16 analogue values

The analogue pilot chip contains one ADC and a 16 channel analogue multiplexer. Once the‘start conversion’ instruction is sent to the JTAG (TAP-) controller, the measurement sequence isstarted. The controller selects the first input (input 0). After the multiplexer output has settled theAD conversion is started and consequently the ADC output is stored in the first register. Thissequence is repeated automatically for all 16 analogue inputs. The last input, input15, is a specialcase. As it is not clear wether a positive or a negative value has to be read by the ADC, twoconversions are conducted for the same input, however, once with an additional signal providedto the analog part passive and once active. As a result for input15 two values are stored.

•Reading the measured analogue values

90 μs after the ‘start conversion’ command has been sent the stored values can be read via theJTAG port. The 17 10-bit registers can be read via the JTAG interface. The first bit must beshifted out is bit0 of input0. The last but one register to be shifted out is input15 with specialsignal 0. The last register is input15 with special signal 1.

•Serial temperature transmission

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It is planned to connect one temperature sensor line to each input0 and input1. A special input,‘auto_temp’, allows to automatic AD-conversion of the two inputs 0 and 1 only and serialisationof the result. The serializer output is available as an output pad of the chip. Measurement of allinputs initiated by the JTAG command ‘start measurement’ is not influenced by thisfunctionality.

A very simple serializer protocol is used. A 20 bit idle word is sent before the 20 bit data registerperiodically. The idle word is: ‘00000000001111111111’ (bit 0, LSB, to the right is sent outfirst). The data word consists of: [input1 [9:0], input0 [9:0]] where the first bit sent out is bit0,LSB, of input0.Complete data frame:[input1 [9:0], input0[9:0], ‘00000000001111111111’]; bit 0, LSB, to the right sent out first.

11.3.1 Implementation

The digital core has been designed and synthesized using VERILOG. Digital simulations havebeen performed. However, the behaviour of the ADC and the DAC have not been modelled bythe designer, as a result it is not evident that this model is correct.

All registers and the ADC controller have been triplicated in order to reduce the influence ofsingle event upset errors. However, the triplication has not been simulated to ensure that thevoting scheme implemented error free.

A post layout (back annotated) VERILOG simulation has been successfully conducted. Themaximum clock frequency of this circuit exceeds 40 MHz. The maximum clock skew is 110 ps.The number of components is about 8000.

11.3.2 Input and Outputs

The digital core is supposed to be operated at a 2.5 V supply voltage. All inputs and outputs areCMOS levels.

•clk40 (input)

The device requires a 40 MHZ clock.

•reset_i (input)

reset_i is a active low asynchronous reset.

•tck, tms, tdi, trst (input), tdo (output)

are standard JTAG CMOS level signals.

•auto_temp (input)

High selects the automatic measurement of the inputs 0 and 1 and send the data out on the serialoutput t_serial. Low on this input deselects the automatic serializer and switches off the clock ofthis part.

•t_serial (output)

is a CMOS level output, where inputs 0 and 1 are serialized, provided auto_temp is active.

•seu_err_out (output)

If one of the voting gates within the chip detects a SEU the output goes active.

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11.3.3 JTAG interface

The JTAG instructions are summarized in the following table.

The order and access options of the inputs and outputs of the chip using the JTAG chain(boundary scan) is given in table 14.

TABLE 13. JTAG instruction registers

command

instruction register 5 bit-hex data register length

exttest 5’h0 6

id_code 5’h1 32’h12011973

sample 5’h2 6

intest 5’h3 6

bypass 5’h1f

start_conversioninitiates the adc scan of all registers

5’h9 no data is shifted

adc_read_only: (>=90 μs after start_conversion)

5’ha 170 (reg15_1,reg15_0, reg14,...,reg0

dac_reg_rw:read and write access of DAC registers

5’hb 48

dac_reg_read:read only access of DAC registers.

Since the JTAG (TAP-) controller is not SEU safe, data might be transferred wrongly. The read access cannot change the register data. Thus, after writing the DAC registers they should be read back in order to verify the correct register content.

5’hc 48

TABLE 14. JTAG accessibility of I/O ports (Boundary scan).

number direction/logic access length bits

Read or Read/Write

clk40 cmos/in Read 1 4

reset_i cmos/in Read 1 3

auto_temp cmos/in Read/Write 1 2

t_serial cmos/out Read/Write 1 1

seu_error cmos/out Read/Write 1 0

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The Pin numbers and Pin names are given in table 15 and 16.

TABLE 15. Pinout sorted by Pin number

Pin namePin number

GND1 1

SEU 2

VDD1 3

GND2 4

CLK40 5

RESET_I 6

AUTO_TEMP 7

TCK 8

TRST 9

TMS 10

TDI 11

GND3 12

VDD2 13

T_SERIAL 14

TDO 15

GND4 16

VDD3 17

GND5 18

VDD4 19

GND6 20

VDD5 21

GND7 22

VDD6 23

GND8 24

DAC_REF_MID_OUT 25

DAC_REF_MID 26

DAC_REF_VDD 27

DAC_REF_VDD_OUT 28

GND9 29

VDD7 30

T1_ALICE 31

T1_LHCB 32

T2_ALICE 33

T2_LHCB 34

VOUT_BG 35

VDD8 36

GND10 37

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59

VDD9 38

MODE 39

VDD10 40

GND11 41

VDD11 42

TESTLOW_TO_MUX 43

VO_TESTLOW 44

TESTHI_TO_MUX 45

VO_TESTHI 46

VO_GTLD_TO_MUX 47

VO_GTLD 48

VO_GTLA_TO_MUX 49

VO_GTLA 50

VO_DRMID_TO_MUX 51

VO_DRMID 52

VO_DRHI_TO_MUX 53

VO_DRHI 54

DRHI_RESERVE 55

VBIAS_OUT 56

VBIAS 57

DACPCI 58

GND12 59

VDD12 60

DACPCI_REF_13V 61

GND13 62

VDD13 63

GND14 64

RBIAS 65

VREF0_OUT 66

VREF0 67

VREF1_OUT 68

VREF1 69

GND15 70

VDD14 71

GND16 72

VDD15 73

DACPCV 74

VDDAPC 75


Pin namePin number

Appendix

60

VDDDPC 76

AUX4 77

AUX3 78

AUX2 79

AUX1 80

RMEAS1 81

RMEAS2 82

GND17 83

VDD16 84

TABLE 16. Pinout sorted by Pin name

Pin namePin number

AUTO_TEMP 7

AUX1 80

AUX2 79

AUX3 78

AUX4 77

CLK40 5

DAC_REF_MID 26

DAC_REF_MID_OUT 25

DAC_REF_VDD 27

DAC_REF_VDD_OUT 28

DACPCI 58

DACPCI_REF_13V 61

DACPCV 74

DRHI_RESERVE 55

GND1 1

GND10 37

GND11 41

GND12 59

GND13 62

GND14 64

GND15 70

GND16 72

GND17 83


Pin namePin number

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61

GND2 4

GND3 12

GND4 16

GND5 18

GND6 20

GND7 22

GND8 24

GND9 29

MODE 39

RBIAS 65

RESET_I 6

RMEAS1 81

RMEAS2 82

SEU 2

T_SERIAL 14

T1_ALICE 31

T1_LHCB 32

T2_ALICE 33

T2_LHCB 34

TCK 8

TDI 11

TDO 15

TESTHI_TO_MUX 45

TESTLOW_TO_MUX 43

TMS 10

TRST 9

VBIAS 57

VBIAS_OUT 56

VDD1 3

VDD10 40

VDD11 42

VDD12 60

VDD13 63

VDD14 71

VDD15 73

VDD16 84

VDD2 13

VDD3 17


Pin namePin number

References

62

12. References

[1] P. Moreira et al., A 1.25 Gbit/s Serializer LHC Data and Trigger optical links. Proceedings of the fifth Workshop on Electronics for LHC experiments, 1999andP. Moreira et al., G-Link and Gigabit Ethernet Compliant Serializer for LHC data transmission, NSS 2000.

[2] DDL Interface Control Document, ALICE-INT-2004-18.

[3] A. Kluge et al., The ALICE silicon pixel detector front-end and read-out electronics, Proceeding of the VERTEX 2004 conference, to be published in NIM A.

[4] A. Kluge et al., The ALICE Silicon Pixel Detector (SPD), Proceedings of the 8th ICATPP, Como, Sept. 2003.

[5] A. Kluge et al., The Read-Out system of the ALICE pixel detector, Proceedings of the PIXEL 2002 workshop, Carmel, Sept. 2002 published in the SLAC electronics conference archive, CA, 2002, eConf C020909 (2003) .

VDD4 19

VDD5 21

VDD6 23

VDD7 30

VDD8 36

VDD9 38

VDDAPC 75

VDDDPC 76

VO_DRHI 54

VO_DRHI_TO_MUX 53

VO_DRMID 52

VO_DRMID_TO_MUX 51

VO_GTLA 50

VO_GTLA_TO_MUX 49

VO_GTLD 48

VO_GTLD_TO_MUX 47

VO_TESTHI 46

VO_TESTLOW 44

VOUT_BG 35

VREF0 67

VREF0_OUT 66

VREF1 69

VREF1_OUT 68


Pin namePin number

References

63

[6] A. Kluge et al., The ALICE on-detector pixel pilot system - OPS, Proceeding of the 7th workshop on electronics for LHC experiments. CERN-LHCC-2001-034

[7] Boccardi et al., Integration and test of the ALICE SPD readout chain, Proceedings of the 10th workshop on electronics for LHC experiments.

[8] ALICE Pixel Detector Readout when using FastOr and FastMult as ALICE trigger input, PPR Presentation, Alexander Kluge, Feb 7, 2003, http://akluge.home.cern.ch/akluge/work/alice/spd/spd_presentations/200310its_week.pdf

[9] K. Wyllie et al., A pixel readout chip for tracking at ALICE and particle identification at LHCb, Fifth workshop on electronics for LHC Experiments, CERN/LHCC/99-33, 29 October 1999, 93

[10] T. Grassi, Development of the digital read-out system for the CERN Alice pixel detector, UNIVERSITY OF PADOVA - Department of Electronics and Computer Engineering (DEI), Doctoral Thesis, December 31, 1999.

[11] G. Anelli et al. Users document of ANAPIL, to be published

[12] Orlando Villalobos-Baillie et al., Requirement Document for the Central Trigger Processor.

[13] F. Faccio, COTS for the LHC radiation environment: the rules of the game, Proceedings of the 6th workshop for electronics in LHC experiments, LEB2000, Crakow, CERN-LHCC-2000-041

Documents

ALICE Silicon Pixel On Detector Pilot System OPS2003 - The ...akluge.home.cern.ch/akluge/work/alice/spd/spd_documents/ALICE-INT-2004... · System overview of the on detector Pilot