AIDA WP3 Summary

H.-G. MoserMPI Munich

Valerio ReINFN

AIDA WP3 Summary

1

• Status of milestones and deliverables

• Status of sub-projects

• Plans for the last year of AIDA

3rd AIDA annual meeting

Vienna, March 2014


Valerio ReINFN

Objectives

2


Vienna, March 2014


Valerio ReINFN

Sub-Projects

3


Vienna, March 2014

WP3.2 (3D interconnection)

• Bonn/CPPM: Interconnection of the ATLAS FEI4 chips to sensors using bump bonding and TSVs from IZM (large diameter TSV, large interconnection pitch).

• CERN: Interconnection of MEDIPIX3 chips using the CEA-LETI process • INFN/IPHC-IRFU: Interconnection of chips from Tezzaron/Chartered to edgeless sensors and/or CMOS

sensors using an advanced interconnection process (T-MICRO or others)• LAL/LAPP/LPNHE/MPP: Readout ASICs in 65nm technology interconnected to pixel sensors using the

CEA-LETI or EMFT process.• MPP/GLA/LAL/LIV/LPNHE: Interconnection of ATLAS FEI4 chips to sensors using SLID interconnection

and ICV (high density TSVs) from EMFT.• UB: 3D interconnection of 2 layers of Geiger-Mode APD arrays with integrated readout in Tezzaron

Chartered technology. • RAL/UPPSALA: Integration of a 2-Tier readout ASIC for a CZT pixel sensor using EMFT SLID technology

and TSV including redistribution of I/O connections to the backside for a 4-side buttable device.

WP3.3 (IP blocks)

• IP blocks in 65 nm CMOS (coordinated by CERN): The choice of the 65 nm CMOS generation was prompted by the needs of future vertex detectors, which can benefit from modern nanoscale technologies by obtaining smaller and more intelligent pixels in pixel detectors, more compact digital logic and lower power in front-end chips.

• IP blocks in SiGe (coordinated by LAL-CNRS): provide IP blocks for needs in calorimeters and TPCs. These two domains are demanding in high dynamic range and precision, so the choice of technology would be to use Silicon Germanium (SiGe).


Valerio ReINFN

Milestones

4


Vienna, March 2014

post-poned

Milestone achieved if some of the subprojects are successful


Valerio ReINFN

Deliverables

5


Vienna, March 2014

postponed

Deliverable achieved if some of the subprojects are successful


Valerio ReINFN

Agenda

6


Vienna, March 2014


Valerio ReINFN

WP3.2: Bonn/CPPM

7


Vienna, March 2014

3D interconnection of sensor and ATLAS FEI4 chip with TSV in periphery => reduce dead area (final target: 4-side buttable) => post processing, to be applied at existing chip

TSVs, RDL and bump bonding by Fraunhofer IZMTest with FEI2 successful (tapered vias)

Process needs to be changed for FEI4 (no front side processing)Use optimized bonding process for thin chips (<100µm)To be processed this year

ConnectedNot connected


Valerio ReINFN

WP3.2: MPP/GLA/LAL/LIV/LPNH

8


Vienna, March 2014

Interconnection of ATLAS FEI4 to thin, slim edge sensorsÞ 4 side buttalbe (Backside connectivity)Þ high TSV density (small diameter)SLID interconnection and TSV by Fraunhofer EMFT

First SLID tests with FEI2 successfulTSVs etched, but problems with tungsten filling

FEI4 needs different TSV etching technology (fbackside)

StatusTSV design for FEI4 madeDedicated sensors produced (CIS, VTT)

PlansSLID interconnection FEI4/Sensor (w/o TSV)Develop TSV process for FEI4SLID FEI4/sensor with TSV (if time allows)


Valerio ReINFN

WP3.2: LAL/LAPP/LPNHE/MPP

9


Vienna, March 2014

3D device based on OMEGAPIX with high density bonding (35µm x 200µm staggered: 70µm pitch

ASIC: 2-tier OMAGAPIX2, by TEZZARON, ordered Oct 2011, delivered Jan 2014first tests promising

Interconnection: CEA-LETI with slim edge sensors by VTT and CIS (avialble)

Alternative (no new TEZZARON run in sight): 2D version of OMEGAPIX in 65nm technology (by Europractice, CERN?)(wafers needed for interconnect)Submission this year


Valerio ReINFN

WP3.2: INFN/IPHC-IRFU

10


Vienna, March 2014

Establish a procedure to interconnect small pixels (20µm x 20µm) at pixel level

2-tier stack (2 x 50µm)Pixel sensors in both layers Top tier read out via bottom tier

Sensors processed in 180nm CIS technology (TowerJazz)

Thinning & SLID interconnection by Fraunhofer IMS

Status:

6 wafers being processed, expected in May

Plans: SLID interconnection finished in NovemberTest at IPHC: December

top tier

bottom tier

test sensor


Valerio ReINFN

WP3.2: RAL/Uppsala

11


Vienna, March 2014

Demonstrate a pixel readout chip with 2 tiers and TSVs in every pixel

Tier 1 (analogue) based on RAL HEXITEC chip (X-ray imaging)Tier 2 (dgitial): 12 bit DAC and readout

Thinning, TSVs and SLID interconnection by EMFT Fraunhofer (like MPP project)

Some delays due to contract issuesFirst wafers delivered in October 2013 (6 months delay)

TSVs and RDL are generally okSLID interconnection seems to be of poor quality

Plans:Delivered devices will be testedEMFT agreed to produce more devices free of charge12 wafers purchases and sent to EMFTAssembled wafers expected by June 2014


Valerio ReINFN

WP3.2: CERN

12


Vienna, March 2014

4-side buttable readout ASIC (based on Medipix) with TSV

TSVs and RDL by CEA LETI (large diameter TSV, 60µm diam.)

After TSV & thinning: chip performance unchanged

Interconnection (bump bonding) by ADVACAM on edgeless sensors

Sensor/chip assemblies work

Next steps:

Yield studies

Ultrathin assembliesUsing TIMEPIX

(50µm & 50 µm)


Valerio ReINFN

WP3.3: 65nm IP blocks

13


Vienna, March 2014

Contract with TSMC by CERN • Foundry access via IMEC• Long procedures for • Signature of NDA is imminent• Contract covers a period of 5 years (2013-2017)

Rad hard IP blocks designed (CERN)• SRAM compiler• I/O pad library• Monitoring ADC• Bandgap reference• specified to 200Mrad

Rad soft IP blocks designed (CERN)• 2C slave• HDLC communication protocol• 7b8b communication protocol


Valerio ReINFN

WP3.3: SiGe/SOI IP blocks

14


Vienna, March 2014

• Electronics needs in calorimeters and TPCs : – large dynamic range, high speed, low noise, low offset, – need of precise capacitors and resistors, …

• Blocks : – ADC, TDC, DAC, Bandgap, OTA, Rad-tol memory, SEU resistant

flipflop …

• Technology : SiGe or HV SOI- SiGe still moving a lot => shift to AIDA2- Choose XFAB SOI 180 nm (SOI --> fast, low substrate noise, low

cost, HV capability, latchup free)

Chose XFAB 0.18 µm SOI process

Possible run for blocks soumission : 22 September 2014


Valerio ReINFN

WP3.3: Others

15


Vienna, March 2014

AGH-USTWaiting for CERN 65nm contractIn the meantime

Two low power ADCs (6-bit, 10-bit), general purpose PLL and SLVS interfacewere designed in 130 nm, fabricated and tested.• All blocks are fully functional, quantitative tests show excellent results for 6-bit ADC and good results for 10-bit ADC and PLL.• Improved versions were submitted in February 2014

SACLAY: IP blocks desigend, to be submitteds (130 nm)

10-bit SAR ADC for Lumical


Valerio ReINFN

Schedule (WP3.2)

16


Valerio ReINFN

Next year’s objectives

17


Vienna, March 2014

WP3.2Deliverable D3.8: detectors available for 3D assessment

-> already achieved by CERN

Deliverable D3.10:Assemsent of 3D integrated sensors

-> push all subprojects to achieve deliverables Assess performance of 3D sensors taking into account: • cost, processing time• technological challenges • experience with industry and vendors• recommendation for further R&D

WP3.3Deliverables D3.4 (postponed) and D3.9

Prepare for final report

Documents

AIDA WP3 Summary