AFPGA Assignments

IQBAL KHAN 1

1 – Write a module for a 8 to 1 mux.

Mux8.v

module Mux8(i0,i1,i2,i3,i4,i5,i6,i7,con,out);

input [2:0]con; //Control Pins

input i0,i1,i2,i3,i4,i5,i6,i7; //Input Pins

output out; //Output Pin

assign out = (con == 3'b000) ? i0 :

(con == 3'b001) ? i1 :

(con == 3'b010) ? i2 :

(con == 3'b011) ? i3 :

(con == 3'b100) ? i4 :

(con == 3'b101) ? i5 :

(con == 3'b110) ? i6 :

i7;

endmodule

Mux8_TB.v

initial begin

// Initialize Inputs

i0 = 0;

i1 = 0;

i2 = 0;

i3 = 0;

i4 = 0;

i5 = 0;

i6 = 0;

i7 = 0;

con = 0;

#100 i0 = 1;i1 = 0;i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 0;con = 000;

AFPGA Assignments

IQBAL KHAN 2

#100 i0 = 0;i1 = 1;i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 0;con = 001;

#100 i0 = 0;i1 = 0;i2 = 1;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 0;con = 010;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 1;i4 = 0;i5 = 0;i6 = 0;i7 = 0;con = 011;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 0;i4 = 1;i5 = 0;i6 = 0;i7 = 0;con = 100;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 0;i4 = 0;i5 = 1;i6 = 0;i7 = 0;con = 101;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 1;i7 = 0;con = 110;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 1;con = 111;

// Wait 100 ns for global reset to finish

#100;

2 – Use if-else construct to compare two 8-bit inputs a and b. There are three one

bit outputs g(reater), l(ess), e(qual)

Compare_1.v

module Compare_1( input[7:0]A,B, output reg G,

output reg I,

output reg E );

always @ *

begin

if (A == B)

E = 1;

else

E = 0;

AFPGA Assignments

IQBAL KHAN 3

if (A > B)

G = 1;

else

G = 0;

if (A < B)

I = 1;

else

I = 0;

end

endmodule

Compare_1TB.v

initial begin

// Initialize Inputs

A = 00000000;

B = 11111111;

// Wait 100 ns for global reset to finish

#100; A = 11111111; B = 00000000;

#100; A = 00000000; B = 00000000;

#100; A = 11111111; B = 11111111;

// Add stimulus here

AFPGA Assignments

IQBAL KHAN 4

3 – Structure

Struct.v

module Ful_Adr (A,B,CI,S,CO);

input A,B,CI;

output S,CO;

wire N1,N2,N3;

half_adder HA1 (A,B,N1,N2),

HA2 (N1,CI,S,N3);

or P1 (CO,N3,N2);

endmodule

module half_adder(X,Y,S,C);

input X,Y;

output S,C;

xor (S,X,Y);

and (C,X,Y);

endmodule

Struct_TB.v

initial begin

// Initialize Inputs

A = 0;

B = 0;

CI = 0;

// Wait 100 ns for global reset to finish

#100 A = 0; B = 0; CI = 1;

// Add stimulus here

#100 A = 0; B = 1; CI = 0;

#100 A = 0; B = 1; CI = 1;

#100 A = 1; B = 0; CI = 0;

#100 A = 1; B = 0; CI = 1;

AFPGA Assignments

IQBAL KHAN 5

#100 A = 1; B = 1; CI = 0;

#100 A = 1; B = 1; CI = 1;

end

Use case construct to create an 8-bit counter with a two bit control input c, 8-bit

data input din, 8-bit data output dout. All operations are synchronous w.r.t +ve

edge clock clk.

Counter.v

Module Counter(clk, rst, c, din, dout);

input clk, rst, c ;

input [15:0] din;

output [15:0] dout;

reg [15:0] dout;

always @(posedge clk)

casez ({rst, c})

//below given control table is as per reference of 74xx867

2'b00 : dout = 15'b0;

2'b10 : dout = din;

2'b11 : dout = dout + 1;

2'b01 : dout = dout - 1;

default : dout = 15'bx;

endcase

endmodule

AFPGA Assignments

IQBAL KHAN 6

Counter_TB.v

initial begin

// Initialize Inputs

clk = 0;

rst = 0;

c = 0;

din = 0;

// Wait 100 ns for global reset to finish

#100; din[0] = 1; din[2] = 1;

#100; clk = 1; rst=1; c=0; // Load from din to dout

#100; clk = 0;

#100; clk = 1; rst=1; c=1; // Increment 1 Time

#100; clk = 0;

#100; clk = 1; rst=1; c=1; // Increment 1 Time

#100; clk = 0;

#100; clk = 1; rst=0; c=1; // Decrement 1 Time

// Add stimulus here

end

endmodule

AFPGA Assignments

IQBAL KHAN 7