Advanced Packaging Developments: Will It Be FO-WLP, FC-CSP ...€¦ · Mainstream to Mid-end Smartphones Mid-end to High-end Smartphones 1.6 ~ 1.3mm 1.2mm ~ 1.0mm 1.0 mm & below 2009

© 2014 TechSearch International, Inc.

Advanced Packaging Developments: Will It Be FO-WLP, FC-CSP, or 3D IC?

E. Jan Vardaman President

TechSearch International, Inc.

www.techsearchinc.com


PC and Mobile Device Market Growth

•  Growth in CSPs driven by smartphones and modest growth for tablets •  Strong growth in lower-end smartphones puts pressure on advanced

package adoption

Source: TechSearch International, Inc. from IDC and others


Packages for Mobile Devices: Which Ones Do I Use? •  Touch screen controllers: quad flat no-lead (QFN), fine pitch ball

grid arrays (FBGA) •  Antenna: ceramic land grid array (CLGA), QFN •  Power amplifiers: LGA (with laminate substrate), typically wire bond

moving to flip chip •  RFIC: FBGA, flip chip BGA (FC-BGA), wafer level package (WLP),

Fan-out WLP (FO-WLP) •  Modem IC: FC-BGA, stacked die package (FC and WB), package-on-

package (PoP) •  Application processor: FC-BGA, bottom package of PoP •  NAND flash: FBGA •  Power management IC (PMIC): FC-BGA, WLP •  WiFi/Bluetooth: CLGA, LGA (with laminate substrate), WLP •  Near Field Communications (NFC): FBGA •  Sensors: LGA

WLP FO-WLP FC-BGA

LGA module

PoP

QFN


Smartphone ASPs Continue to Decline

•  Smartphone ASPs continue to decline •  Creates price pressure that makes adoption of advanced packaging technology challenging

Source: Adapted from IDC


iPhone Trends: Thin is Still In! 12.3mm

115.

3mm

iPhone 3GS: 4 WLPs

iPhone 4 : 6 WLPs

9.3mm

iPhone 4S : 7 WLPs

9.39㎜

9.46㎜

7.6㎜

iPhone 5 : 11+ WLPs

iPhone (11.6 mm): 2 WLPs iPhone 3 (12.3 mm): 4 WLPs

Source: TechSearch International, Inc., adapted from TPSS.

iPhone 5S : 18+ WLPs

7.6㎜


Huawei Ascend P6 Main Board (Front side)

WLP

Source: TPSS.

eWLB

WLP WLP


Huawei Ascend P6 Main Board (Back side)

WLP

WLP

Source: TPSS.

WLP


What Set the Stage for FO-WLP?

•  Historically, conventional WLPs for low I/O small die

–  2 to 100 I/Os –  Next 100s of I/Os –  Now 400+ I/Os

•  With increased I/O can’t “fan-in” using conventional WLP

Source: Casio Micronics

Source: ASE


Fan-Out Wafer Level Package

•  Reconstituted wafer and perimeter mold compound allows for redistribution of I/O beyond current chip footprint

•  Fan-out WLP from ADL Engineering, Amkor, ASE, Deca Technologies, Freescale Semiconductor, FCI/Fujikura, J-Devices, NANIUM, Nepes, SPIL, STATS ChipPAC, and TSMC

•  Infineon eWLB (wireless operation acquired by Intel) –  Technology licensed by ASE, STATS

ChipPAC, NANIUM

•  Improved reliability with new material sets

•  Fan-out WLP shipments in hundreds of millions per year

Source: Infineon.

Intel Wireless Division LTE analog baseband 5.32 x 5.04 x 0.7mm eWLB 127 balls, 0.4mm pitch

Source: TPSS.


FO-WLP Drivers •  Smaller form factor, lower profile package:

similar to conventional WLP in profile (can be ≤0.4 mm)

•  Thinner than flip chip package (no substrate) •  Support increased I/O density •  Excellent electrical and thermal performance •  Excellent high temperature warpage

performance •  Fine L/S (10/10µm) •  Can enable a low-profile PoP solution as

large as 15 mm x 15 mm •  Multiple die in package possible •  Die fabricated from different technology

nodes can be assembled in a single package •  Future growth requires cost reduction

– Panel process? Activities at Amkor/J-Devices, SPIL, and others

– Lower cost materials?

Source: STATS ChipPAC.


FO-WLP Projections

•  Applications include RF, PMIC, automotive radar, future application processors

•  Assumes that cost targets, business, and reliability requirements are met


What About Flip Chip?

•  Flip chip growth strong –  Many high-end, high

performance packages –  Low-end packages for

diodes, filters •  Trends toward copper pillar •  QFNs with flip chip interconnect •  Micro bumps for 3D IC w/ TSV •  Future flip chip growth in wireless

products –  Driven by form factor and

performance –  Baseband processors in flip

chip –  Application processors in flip

chip –  Bottom package in PoP

(application processor, many with SnAg bump moving to Cu pillar

•  But how can flip chip be a low-cost package??????

Source: TechSearch International,Inc.

Source: ChipWorks

0

2000

4000

6000

8000

10000

12000

2012 2013 2014 2015 2016 2017

300mm Wafers


Huawei Ascend P6 Main Board (Front side)

FC-BGA

Source: TPSS.

FC-BGA


Huawei Ascend P6 Main Board (Back side)

PoP w/FC

Source: TPSS.


Mainstream to Mid-end Smartphones

Mid-end to High-end Smartphones

1.6 ~ 1.3mm 1.2mm ~ 1.0mm 1.0 mm & below

2009 ~ 2014 2010~ 2014

2011~ 2015

Apple’s A7 processor in iPhone 5S

MLP PoP fcPoP (Bare Die) Exposed Die MLP/ eWLB PoP

FAB node reduction, Higher Functionality/ Integration, Higher Data Rate

Source: STATS ChipPAC

Flip Chip Enables Thin PoP


Amkor Early Adoption of Cu Pillar

Cu Pillar for CSP

Flip-chip PoP Fine-pitch flip-chip (50 µm)

Source: Amkor!

Source: TI!

Source: TI!

•  Small form factor (smaller die size) •  Finer bump pitch than solder (down to 50 µm) •  Improved electrical performance •  Pb-free solution


ASE’s aS3 •  Utilizing aS3 as a new simple low cost coreless substrate

–  Embedded Traces & Pads –  Fine Pitch capable –  With or without top soldermask

£  ASE uses mass reflow fine pitch Cu Pillar FC & MUF £  Creates new paradigm in low cost-‐fanout packaging -‐ aS3-‐Plus

–  Chip Last vs Chip First for Higher Assembly yields –  Fine Pitch bumping direct on die pad without RDL –  High Density rouJng –  Thicker Copper allows higher current capacity –  Thin Package –  High thermal conducJvity mold compound gives 3X thermal

performance –  IsolaJon from die allows higher potenJal reliability performance

With Top SM

Without Top SM

Panel1.2013 © 2014 TechSearch International, Inc.

Panel Size: 510 x 410 mm (209,100mm2) Strip Size: 240 x 76.2 mm (X2L) PKG Size: 6.28 x 4.68 mm Strip Array: 34x13 => 442 each Pkg/Per/Panel : 4,420 each

Wafer size : 300mm(70,686mm2) Unit(die) size : 6.28X4.68mm Die/Per/Wafer: 2,130 each

FC Cu Pillar aS3-‐Plus Panel vs Wafer U4liza4on

3:1 Area

No Wafer Fab investment needed, ASE uses standard FlipChip Packaging

> 2:1 Pkgs


How to Cost Reduce Flip Chip Further???

•  Substrate is the biggest cost component of the flip chip package (60 to 75%) •  Why not use a leadframe as the substrate! (Poor man’s FO-WLP solution)

– Etched leadframe concept from QPL – JCET took a license from APS (Singapore) for Molded Interconnect

Substrate (MIS), later purchased APS – JCET licensed etched leadframe technology to leadframe makers MCT

(Singapore), QDOS (Malaysia), Phoenix Pioneer technology (Taiwan) – SPIL version enhanced QFN (eQFN) – Amkor version called “routable MLF: – ASE version a2QFN – Carsem offers routable QFN and purchase leadframes from APS

licensees

Source: ASE

© 2014 TechSearch International, Inc. 20

Multi Layer Solution aS3+ : 40um core 0.09mm

Single layer a2QFN

a2QFN – New Fan-Out WLP Solution!

Source: ASE.


MIS Coreless Substrate with Flip Chip

•  Potential low-cost flip chip solution •  Conventional 1-2-1 substrate (left) •  Two-layer MIS substrate (right)

–  Direct filled microvia down to 50µm diameter for improved routing

Source: APS.


Application Processor Packaging Trends •  Thinner package and smaller footprint

–  Today 1.0mm height requirement –  Future ≤0.8 mm

•  3D IC with TSV provides the ultimate in package height reduction

–  Highest density, highest performance

–  Lowest profile, smallest form factor –  Future package (adoption

continues to shift out) •  PoP in high-end smartphones

–  Embedded capacitors in bottom PoP substrate for improved performance HVM today

–  Option 1: Continue with FC on thin substrate

–  Option 2: Embedded active die (application processor) in bottom laminate substrate

–  Option 3: Fan-out WLP with application processor as bottom package

–  Option 4: 3D IC with TSVs for memory and logic stack (requires new architecture to handle thermal constraints, lower cost, and less risk)

Source: Intel

Source: Renesas.

Source: Amkor Technology.


3D IC with TSV Adoption Timeline

•  Image sensors with backside vias from Toshiba in January 2008, Sony CMOS image sensors + logic

•  Tezzaron DRAM 2013, Micron HMC 2015, SK Hynix HBM 2015 •  Application processor + memory for mobile 2018 at earliest •  Logic on logic 2019 at earliest •  Automotive (image sensor + logic) for safety features

Source: TechSearch International, Inc.


Why the Delay in Memory + Logic? •  Logic and memory stack for

mobile 2018 (at earliest) •  Today more expensive than

PoP solution –  3D IC process yield is low –  Process steps such as debond

during thinning –  Impacts total cost

•  Couples memory and logic supply so can’t easily swap one memory supplier for another

•  Business risk (versus alternatives) –  Mobile products must meet

steep product ramp •  Thermal issues, unless low-

power design is available (requires new architecture)

Source: SK Hynix.


Conclusions •  Mobile world continues to drive…

– Volumes – Package trends – Technology development

•  Lower ASPs for mobile devices make consumer happy , but make adoption of advanced packaging challenges

–  Maybe difficult to meet steep product ramp with new packaging technology (too much risk)

•  Trend in FC and WLP for mobile devices continues – Conventional WLP – FO-WLP – Flip chip (new low-cost options, including leadframes)

•  Adoption of new technology such as 3D IC – Cost/performance trade-off: Cost is critical – Established infrastructure key

Documents

Advanced Packaging Developments: Will It Be FO-WLP, FC-CSP ...€¦ · Mainstream to Mid-end Smartphones Mid-end to High-end Smartphones 1.6 ~ 1.3mm 1.2mm ~ 1.0mm 1.0 mm & below 2009