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Advanced Implantation Detector Array (AIDA): Update & Issues. presented by Tom Davinson on behalf of the AIDA collaboration (Edinburgh – Liverpool – STFC DL & RAL). Tom Davinson School of Physics The University of Edinburgh. DESPEC: Implantation DSSD Concept. - PowerPoint PPT Presentation
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Advanced Implantation Detector Array (AIDA):Update & Issues
Tom DavinsonSchool of PhysicsThe University of Edinburgh
presented byTom Davinson
on behalf of the AIDA collaboration(Edinburgh – Liverpool – STFC DL & RAL)
DESPEC: Implantation DSSD Concept
• SuperFRS, Low Energy Branch (LEB)• Exotic nuclei – energies ~ 50 – 200MeV/u• Implanted into multi-plane, highly segmented DSSD array• Implant – decay correlations• Multi-GeV DSSD implantation events• Observe subsequent p, 2p, , , , p, n … decays• Measure half lives, branching ratios, decay energies …• Tag interesting events for gamma and neutron detector arrays
AIDA: DSSD Array Design
• 8cm x 8cm DSSDscommon wafer design for 8cm x 24cm and 8cm x 8cm configurations
• 8cm x 24cm3 adjacent wafers – horizontal strips series bonded
• 128 p+n junction strips, 128 n+n ohmic strips per wafer• strip pitch 625m• wafer thickness 1mm• E, Veto and up to 6 intermediate planes
4096 channels (8cm x 24cm)• overall package sizes (silicon, PCB, connectors, enclosure … )
~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm
courtesy B.R
ubio
ASIC Design Requirements
Selectable gain 20 1000 20000 MeV FSRLow noise 12 600 50000 keV FWHM
energy measurement of implantation and decay events
Selectable threshold < 0.25 – 10% FSRobserve and measure low energy detection efficiency
Integral non-linearity < 0.1% and differential non-linearity < 2% for > 95% FSRspectrum analysis, calibration, threshold determination
Autonomous overload detection & recovery ~ sobserve and measure fast implantation – decay correlations
Nominal signal processing time < 10sobserve and measure fast decay – decay correlations
Receive (transmit) timestamp datacorrelate events with data from other detector systems
Timing trigger for coincidences with other detector systemsDAQ rate management, neutron ToF
AIDA: Current Status
• Prototype ASIC design
final design review this weeksubmission October 27
• Prototype FEE design
engineering concepts established (specification v.1 available)detailed engineering underwayliquid cooling required (cf. AGATA digitiser module)
• Prototype testing
fully instrumented 8cm x 8cm DSSDin-beam commissioning tests mid-2009
FEE: Block Diagram
Daughtercardconn
ector
16 channelASIC
9252ADFADC
9252ADFADC
16 bitADC
Single
todiff
n.
16
1
2I C controls
x x xxxxxxxxxxxxx xxxxxxx2
Readout controlsClocksReset
10LVDS 20 pins
10LVDS 20 pins
4
Daughtercardconn
ector
16 channelASIC
9252ADFADC
9252ADFADC
16 bit ADC
Single
todiff
n.
16
1
2I C controls
x x xxxxxxxxxxxxx xxxxxxx2
Readout controlsClocksReset
10LVDS 20 pins
10LVDS 20 pins
4
Daughtercardconn
ector
16 channelASIC
9252ADFADC
9252ADFADC
16 bit ADC
Single
todiff
n.
16
1
2I C controls
x x xxxxxxxxxxxxx xxxxxxx2
Readout controlsClocksReset
10LVDS 20 pins
10LVDS 20 pins
4
Daughtercardconn
ector
16 channelASIC
9252ADFADC
9252ADFADC
16 bit ADC
Single
todiff
n.
16
1
2I C controls
x x xxxxxxxxxxxxx xxxxxxx2
Readout controlsClocksReset
10LVDS 20 pins
10LVDS 20 pins
4
Xilinx 5 70XC VFX T-? 1136FF 640 I/O
344 4used for ASICS
ContainsPowerPC processor
Readout State Machine
64 channels ofEnergy/Timing/Waveform
4 channels of ASIC readout
Timestamp logic
TEMACPHY
64MBSDRAM
FLASH for boot load of
LINUX
45RJ
Timestampexternalinterface
Consoleinterface
Oscillators
- -64AIDA FEE ( ) AAAA to DAQ block diagram
High speed Discr OR
JTAG
Gbit Ethernet
BuTiS interface
FEE: VHDL Block Diagram
4One of
64One of
Microblaze runningLINUX
Max rate = ( 60K 8x )
+( 10k 2024 )x
=>20720000, ,bytes/sec
Include edge events=>
61200000, ,bytes/sec
SharedRAM
SharedRAM
SharedRAM
SharedRAM
xx6 0 K events/sec
Statemachine
Q
ADC
ASIC16
channels
Timestamp
16 Discriminators
Sync/Pse/Res
To
Digita
l
Statemachine
Q 1024 x
(48 + 64 + 3)
Energy MWD
Leading Edgediscriminator
Slow in Fast out Waveform RAM "Circulating Buffer"
Timestamp
Sync/Pse/Res
Floating pointtime vernier
calc.
Q 10 36x
Energy
DMAMemorymanager
64DDR
SDRAM 32 bit
FIFO 3072 16x
FEE: Mechanical Structure
45RJGigabit
45RJGigabit
HDMIClock,SYNC,Reset
Power, Disc_out
HDMIClock,SYNC,Reset
Power
JTAG
JTAG
Water cooled metal
Water cooled metal
FPGA & FADCs
FPGA & FADCs
Water cooled metal
Water cooled metal
View A
Kapton Cable toto detector
Oustanding Issues: Time Jitter
• Transient signal analysis currently underway (realistic comparator design)
• Preamplifier risetime ( Cf=0.6pF ) tr=110ns LLD threshold 0.26% 20MeV FSR
20MeV signaljitter ~0.13ns rms ( ID=1nA ), ?ns rms ( ID=100nA )
0.2MeV signaljitter ~2.7ns rms ( ID=1nA ), ~4.0ns rms ( ID=100nA )
events will normally trigger multiple strips ‘simultaneously’S/N improves as n1/2
• Highlights importance ofminimising detector – instrumentation separation
reduces noise and risetimeradiation damage mitigationdetector cooling
• Evaluate prototype & review
Oustanding Issues: Threshold
• Detailed simulation (with realistic component tolerances and behaviour) shows random comparator offset variations in excess of minimum threshold specification (0.25% of 20MeV FSR)
- design optimisation and minimisation- design incorporates per channel offset correction via 6bit DAC- evaluate prototype & review
Outstanding Issues: AIDA Enclosure
• Design study by E.Reillo et al. (CIEMAT)
http://www.ph.ed.ac.uk/~td/AIDA/Meetings/12May2008/AIDA%20chamber.pdf
• Comparison of s/steel, Al and C fibre materials
• ‘Best’ option Al
0.5mm entrance window (path to ToF n-detectors) desirable
• Presumed satisfactory choice for Ge detectors
• TAS? 4 neutron detector?
AIDA Project Information
Project web site
http://www.ph.ed.ac.uk/~td/AIDA/welcome.html
Design Documents
http://www.ph.ed.ac.uk/~td/AIDA/Design/design.html
Project Technical SpecificationASIC Project Specification v1.3FEE Specification v1.0
The University of Edinburgh (lead RO)Phil Woods et al.
The University of LiverpoolRob Page et al.
STFC DL & RALJohn Simpson et al.
Project Manager: Tom Davinson
Acknowledgements
This presentation includes material from other people
Thanks to:
Ian Lazarus & Patrick Coleman-Smith (STFC DL)Steve Thomas & Davide Braga (STFC RAL)Dave Seddon & Rob Page (University of Liverpool)Berta Rubio (IFIC, CSIC University of Valencia)
