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DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

PA Approval: #88ABW-2010-2969 dated: 2 June 2010

Advanced Computing Architectures

Core Technical Competency

Mr. Steven Drager

ACA CTC Lead

Information Directorate

Air Force Research Laboratory

8 June 2010

2010 Info Challenges Conference & Exposition

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Technology Landscape

• Supply chain issues – HW/SW sourced from around the world

• Security -- Fundamental driver for both HW and SW development

• Moore’s Law -- Driving architecture developments

• Disruptive technologies -- Nanotechnology and QIS

• Commodity trends -- drive price/performance

• Complex -- Drive cost/schedule, lacks resiliency

• Green -- Power is critical enabler

Filter

Pyramid of Computation

Situation

Assessment

ID

Tracking

Detect

Trusted Computing

AF Core Functions

• Air Superiority

• Command & Control

• Space Superiority

• Cyberspace Superiority

• Special Ops

• Global Integrated ISR

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Sub-CTCs

•Computing Architectures

•Trusted Computing

•Emerging Models and Technologies for Computation

Advanced Computing Architectures

Core Technology Competency

Vision – Superior, Intelligent, Secure, On-Demand Computing for the Air

Force

Mission – Explore and develop computer architectures with greater capacity, sophistication and assurance for addressing dynamic mission objectives

under constraints imposed by C4, ISR, and strike systems

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Sub-CTC Challenges

• Computing Architectures

• Foundations for exascale (1018 ops/sec) systems

• Scalable SWAP constrained embedded HPCs

• Complex autonomous systems

• Effective multi-core exploitation

• Managing large data applications

• Trusted Computing

• Architectural security and trust• Provably correct complex software systems• Composability and predictability of complex systems

• Emerging Models and Technologies for Computation• Scalable quantum computers and general purpose

quantum computing• Exploiting the 3rd dimension in computer architectures

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Distributed and Layered Computing

Future ISR concepts are inherently distributed and

layered, with exponential growth in demand for

processing capability

Processing in the right place Collaborative use of distributed, heterogeneous resources

in computing networking and sensing over wireless links

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3D

Mesh

OS / Address system supports many flexible nodes

• Mesh Address Architecture

• Microcode support

Signal Processing & Neuromorphic Computing Applications

Create or adapt models of fundamental operations to

effectively use our massively parallel neuromorphic hardware

Neuromorphic HW geometry for large-scale many-node

• Small processor for high density, many-node parallel

clusters

• Associated RAM for node speed, power efficiency

• Asynchronous Field Programmable Gate Array

(AFPGA) for a dynamic system, speed

• Cluster design for lower latency through high

density 3D stacking

• Information Assurance features

SRAM

AFPGA

lower

upper

microseq FPU

FIFO

NIC

cache

Mesh

router

ACS Node within

CyberCog Chip

3D Stacked Cluster

of CyberCog ChipsConcurr

ent

Develo

pm

ent

Concurre

nt D

evelo

pm

ent

Cyber-Cog Architecture

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Exascale Computing

• Objective: Overcome technological impediments to achieving sustained exascale class

computing

• Approach:

– Shrink base computation energy consumption as well as data transport energy

reduction

– Exploit concurrency and communication/synchronization requirements through new

programming models

– Build-in resiliency through adaptable components based on availability and

reliability

Problem: Foundations for Exascale (1018

ops/sec) Systems

SRAM

AFPGA

lower

upper

microseq FPU

FIFO

NIC

cache

Mesh

router

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Sub-CTC Challenges

• Computing Architectures

• Foundations for exascale (1018 ops/sec) systems

• Scalable SWAP constrained embedded HPCs

• Complex autonomous systems

• Effective multi-core exploitation

• Managing large data applications

• Trusted Computing

• Architectural security and trust• Provably correct complex software systems• Composability and predictability of complex systems

• Emerging Models and Technologies for Computation• Scalable quantum computers and general purpose

quantum computing• Exploiting the 3rd dimension in computer architectures

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Trusted Computing

• Resilience and “fight through” properties of a system are a function of all its parts

(processing, communications, etc.) and vulnerabilities exist in all of them

– Develop a high-assurance system for embedded applications via trusted many-core

processors and software

– Secure encapsulation of subsystem components

• Compromises cannot affect other areas

• Reliability improvement

– Attain trust from untrustworthy components

• A systems engineering based approach covering the totality of components responsible

for enforcing policy:

– Multiple Independent Levels of Security including operating systems and middleware

– Hardware including firmware, virtualization, TPM, CPU, motherboard, etc.

– Software including applications, libraries and middleware development through

maintenance

Air Force requires systems that are resilient against attacks and will guarantee mission completion

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Trusted Computing

Problem: Architectural Solutions for Security and Trust

Trusted/Secure/Authenticated Boot

Trusted Execution

Attestation

Trusted MicroKernels

+ + =

Objective: Research and develop a repertoire of trusted computing technologies

such that users can choose levels that are commensurate with threats

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Trusted Computing Technology Targets

• Trusted Software

– Raise the abstraction level to enable provable

properties, automated optimization, increased

comprehension and predictable SW

– Composition methodologies that maintain/

guarantee non-functional properties (IA &

temporal)

– Design Analysis and Optimization of Multi-core

Software

Design

Analyze

Synthesize

Modernize /

Rapid Prototype

• Trusted Hardware

– Provide independent, specialized, smaller, resilient and AF built roots of

trust (ROTs)

– Eliminate shared cache attacks such as side channel and denial of service

attacks

– Plug and play FPGA cards to detect system compromise at firmware level

– Create clean slate tagged architecture to invalidate current malware attacks

– Provide unique and unforgeable identities using physically uncloneable

functions (PUFs)

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Sub-CTC Challenges

• Computing Architectures

• Foundations for exascale (1018 ops/sec) systems

• Scalable SWAP constrained embedded HPCs

• Complex autonomous systems

• Effective multi-core exploitation

• Managing large data applications

• Trusted Computing

• Architectural security and trust• Provably correct complex software systems• Composability and predictability of complex systems

• Emerging Models and Technologies for Computation• Scalable quantum computers and general purpose

quantum computing• Exploiting the 3rd dimension in computer architectures

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Nanotechnology

HP/DARPA/AFRL SNAP NIL

Technology entering commercial

production in CY08.

AFRL/RF Nano/Union Col.

nanotubes for ultra-high density

interconnects.

Capabilities-based program description

• Objective: Research, development and deployment in the

emerging disciplines of nanoscience/nanoengineering

• Technology Areas

• Nanosystems for ultra-high device density, low latency

computer interconnects, lower power and faster

operating speeds

• Novel switching and interconnect nanotechnologies for

processing information

• Nanofabrication technologies for rapid insertion

• Self-organizing nanomaterials

• Technology Benefits

• Reduced consumed power (pJ/gate)

• Reduced thermal dissipation issues (few W/chip)

• Lower latency times.

• Reduced production costs (per chip)

• Three Research Initiatives

• Nanoelectronic Memristive Phenomena

• Crossbar Nanocomputers

• Synthetic Neuromorphic Nanocomputers

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Neuromorphic Computing

Problem: Lack of dynamic real-time information

processing that enables robust and intelligent

decision making capabilities

Key Ideas: Harness parallel computing architecture

of the mammalian brain:

Adaptable intelligent systems

Autonomous operations

Works with incomplete data

Technical Approach:

1.Study architectural issues/scale leading theories:

Brain State in a Box (BSB)

• Text character classifiers

BSB with Simple and Complex Neural Networks

Confabulation (Knowledge/ recall/ correction)

Hierarchical Temporal Model

Spiky Neural Networks

Explore Hybrid Models

• BSB & Confabulation

2. Develop hardware based neuromorphic

computing processors

Developed hybrid confabulation/BSB model, 20% occluded characters

Developing physical architectures, low power & high density

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Quantum Computing and Quantum

Information Science technologyCapabilities-based program description

• Objective: Apply quantum computing and quantum

information science technology to the development

of secure AF processors capable of revolutionary

computational performance

• Technology Areas

– Formulation of new quantum algorithms

– Ultra-secure intra-process/interconnect protocols

– Computational applications for which quantum

computation offers significant advantage

– Modeling and simulation for development of

architecture designs

– Testbed validation of cluster state concepts

– Scalable quantum logic, using teleportation gates

or feed-forwarding and “clustered” optical qubits

• Technology Benefits

– Revolutionary computational capabilities

o Fast database searches

o Sophisticated image / signal processing

o Optimize complex AF system processes

– Ultimate in secure processing

Quantum CAD

Hadamard gate

Simulation ExperimentalSimulation Experimental

In-house data & simulations

In-house generated entangled photons

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Facilities

Quantum Computing Concepts Testbed

RI Emulab

92 Experimental Nodes

Naresky Lab

336 PS3s -> 1748 PS3s

51.5 Teraflops -> 500 Teraflops

Key Collaboration Partner: Albany College of NanoScale Science and Engineering

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Transition Examples

SBIRS Single Board Computer Emulation

• AFRL daughter card with FPGA to emulate SBIRS processor

• Transition to SBIRS-High

HPC-to-the-Field & Real-Time Processing

• TTCP - Swathbuckler• US-Australia DEA-AF-2009-01• AFRL-NRO Task Agreement 6/08

DoD Low-Cost Interactive Supercomputer

• HPCMP Affiliated Research Center

• DUSD (S&T) HPCMP Dedicated High Performance Investment Program

Plug-and-Play Satellite

• Delivered HPC to AFRL/RV PnP Sat

Multiple Independent Levels of Security Certification & Accreditation Tool

• Reduce cost & time to generate C&A packages

• Future transition to B-2

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Procurement Vehicles

• BAA #09-03 Computing Architecture Technologies (POC: Chris Flynn)

• Enhanced processing

• MILS

• SISPI

• Formal architectures

• High assurance/trusted computing architectures

• BAA #09-08 Emerging Computing Technology & Applications (POC:

Stan Lis)

• Emerging Computer Technology

• Wireless computational networking

• Computational science and engineering

• High performance computing

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Business Opportunities

• Multi-Core Computing: Accelerating Software Development and Usage (POC: Guna Seetharaman)

• Security Tagged Architecture Co-Design (POC: Jonathan Heiner)

• Correct Bi-Construction Software for Edmbedded Multi-Core Systems (POC: William McKeever)

• CMOS Memrister Hybrid Nanoelectronics for AES Encription(POC: Joseph Van Nostrand)

• Reconfigurable Electronics for Neuromorphic Computing (POC: Robinson Pino)

• Cluster State Quantum Computing (POC: Paul Alsing)

• Parallel Discrete Event Simulation for Emerging Architectures (POC: Ryan Luley)

• Trusted Barebones Router (POC: Guna Seetharaman)

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Trusted Computing Workshop Plug

• This afternoon 1-4pm, see schedule for location

• This workshop will discuss the ecosystem requirements

for trusted computing platforms. Key for this discussion

are the requirements/measurement/analysis that must

exist to provide adequate confidence for the relying party

to trust, perhaps at graduated levels, in the attestation

provided.

• Modularity

• Interoperability

• Interchangeability

• Affordability

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Contact Information

Steven Drager

Air Force Research Laboratory/RITA

525 Brooks Rd.

Rome, NY 13441

TEL: +1.315.330.2735

Email: Steven.Drager@rl.af.mil

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