ADC-based Embedded RT Simulator for power converters implemented on FPGA

7/25/2019 ADC-based Embedded RT Simulator for power converters implemented on FPGA

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ADC-BASED EMBEDDED RT

SIMULATOR OF A POWERCONVERTER IMPLEMENTEIN AN FPGA

PRESENTED BY

SANJAY KUMAR DHRITLAHARE (15EC65R

VIPES, E&ECE Depart e!t

IIT KHARA"PUR


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OVERVIEW Introduction to Basic Terms.

Previous approaches & limitations. Brief intro to proposed approach. Design constraints for FPGA basedSimulator.

Design Guidelines Design of AD !based "mbedded #TSimulator. onclusion

#eferences


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INTRODUCTIONBASI T"#%I '('GI"S

Associated Discrete ircuit )AD *

"mbedded #eal Time )#T* Simulator

Po+er onverters

FPGA stands for Filed!Programmable Gate

Arra,


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INTRODUCTION (con

o+ada,s #T digital simulation can be seen asadvanced research /eld in Po+er "lectronicsApplications.

%ost #T simulators are applied in conte0t of

hard+are!in!loop )1I(* testing of digitacontrollers. %ain issue of interest is to develop #T

simulators able to accuratel, reproduce thes,stem d,namics and transients.

True for simulatin Po+er onverter.


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EXSISTING METHODS LIMITATIONS

Average %odel Solver )(ac3 of accurac,*. State!Space Solver. 'nl, AD based )high simulation steps*

'nl, FPGA based #T simulators )ver, costl,*


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PROPOSED APPROACHI!"o#t$nt In%o#!$t&on

Simulator is implemented using AD !based "mbedded#T simulators on lo+ cost FPGA.

"mbedded #T simulator 5! Intellectual propert, )IP*module

IP and controllers both implemented and run on sameFPGA device.

Proved b, appl,ing it to a Fault!tolerant grid!connected-!phase $!level 6oltage!Source #ecti/er )6S#*

Thus AD !based embedded #T simulator is associated+ith one of -!phase #( /lter to /nd Grid currents


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DESIGN CONSTRAINTS FORSIMULATOR

T&!&n' Con t#$&nta. hoice of appropriate Simulation Time Step )T s *.b. T s 8 49 to :;9 of the smallest time constant of the controlled

s,stemc. T s long enough to process all model e


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DESIGN CONSTRAINTS FORSIMULATOR (cont.)

F&'-FPGAembedsimula


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DESIGN CONSTRAINTS FORSIMULATOR (cont.)

A+'o#&t ! Con t#$&nta. omple0it,.b. Data onditioning.

FPGA I!"+/!/nt$t&on Con t#$&nta. Parallelism of algorithm.

b. FPGA Integrates %emor, bloc3s 1ard+ired DSP units )e.g. @ilin0 DSP2?":* 1ard+ire processing s,stems )e.g. ,n< FPGA dual!core

orte0!A A#% processor*c. #esource management


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DESIGN GUIDELINES FOR FPGA-BASED EMBEDDED RT SIMULATO

2 %aCor Steps5! Preliminar, S,stem

Speci/cation. Algorithm Development. FPGA Implementation. "0perimentations

:;

DESIGN GUIDELINES FOR FPGA


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DESIGN GUIDELINES FOR FPGA-BASED EMBEDDED RT SIMULATO

(cont.)

F&'-0.guidelinesbased emsimulators


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DESIGN OF ADC-BASEDEMBEDDED RT SIMULATOR

Simulated for Grid connected -!Phase $!level 6S#. Simulator IP is associated +ith one of the -!phase

#(!/lter. Applied in conte0t of a fault tolerant control the

6S#. These IPs estimate the grid currents ) i gi (i=a,b hen fault on the grid current sensors the

measurements are then replaced b, theirestimates.


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:-

DESIGN OF ADC-BASED EMBEDDERT SIMULATOR (cont.)

. P#/+&!&n$#, S, t/! S"/c&1c$t&on2. The po+er stage is composed of Ei* -!phase voltage sources from the grid )$-; 6

and 4; 1=*ii* An autotransformeriii*A three!phase #(!filter )# ;.? ( $;m1*iv* A $;!H6A -!phase $!level 6S# +ith insulated!

gate bipolar transistor )IGBT* diode s+itches.v* A capacitor for the D lin3 )::;; JF ?;; 6*vi*A resistive load ):;; $.4 A*vii* ontactor to connect and disconnect theload F


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The used device is the @ilin0 ,n< FPGA So ) @ > ;edBoard * consists of follo+ings5

:2


:. Integrated dual!core orte0!A A#% processor

$. 4- $;; loo3up tables )(KTs*

-. : ;7 2;; Lip!Lops2. 47;HB #A% bloc3s4. $$; DSP2?":7. Analog peripherals>. Kp to $;; high!speed I '

bloc3s. F&'-4. @ilin0 ,n< FPGA SedBoard*


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:4


F&'-5. Structure of the devel

FPGA %odules5!:. Analog!to!digitalconversion module basedon the integrated @AD .

$. D !lin3 voltage and grid

current regulator.-. AD !based embedded #Tsimulator module of the6S#.

2. "mbedded #T simulator

of the -!phase #(!/lter


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$) XADC con6/# &on *n&t2-Analog!to!digital conversion isachieved using the on!chip dual:$!bit :!%SPS AD .

To ensure conversion of all signals) and * an oM!chip analog mu0has been used."0perimentall, measuredconversion time :.:?Js .

:7


F&'-7.@AD con

DESIGN OF ADC BASED


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:>

DESIGN OF ADC-BASEDEMBEDDED RT SIMULATOR

(cont.)

F&'-8.Digital

Sampling period of @DA isset to $Js. )consideringsettling time of %K@*Ksed h + resources are

- (KTs );.;>9* : > FFs );.:?9*


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:?


9) DC-+&n: Vo+t$'/ $n G#& C*##/ntR/'*+$to#2-

hosen control strateg, is the Direct Sliding!modontrol )DS%P *

%ain obCective is to 3eep the D !lin3 voltage)#eference voltage* +ith controlled P.F.Sampling period of PI regulator is set to 4;Os.Ksed base values are 47-6 for v gs and 2A for currents.For data


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:


1 + resource used b,controller > DSP2?": units )-.:?9* !

for multiplications :--7 (KTs )$.4:9* :;-2 FFs );. >9*

F&'-;. Architecture of the


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$;


T$9+/- . Timing area performances of DS%P ontrollermodules


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$:


"mbedded #T Simulator of the -!Phase #(!/lter5!omputes the grid currents from the measured grid

voltages and the line voltages processed b, 6S#simulator.corresponding discrete!time e


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$$


($)

(9

)F&'-


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$-


Simulator is s,nchroni=ed +ith the 6S# one and has thesame simulation time step i.e. 4;;ns .Base values for normali=ation are same those ofcontroller ) 47- 6 and 2 A *.

The chosen /0ed!point format is -$ $? )-$ total bitnumber and $? bits in the fractional part*2 bits are attributed to the integer part to avoid an,overLo+.FPGA architecture is factori=ed ) methodolog,* tooptimi=e the use of multipliers.


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$2


'nl, one -$!bit multiplier isdeplo,ed that corresponds tofour DSP2?": units )each oneintegrates a $4Q:?bitmultiplier *.Ksed hard+are resources are

i. $ (KTs );.;;-9*.ii. :4 FFs );.;:29*.

Total (atenc, :4 and the"0ecution Time :4;ns )+itha :;;%1= s,stem cloc3 *.

F&'- =. FPGA!based architphase #(!/lter.


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$4


0.A+'o#&t ! D/6/+o"!/nt2

$) Mo /+ S/+/ct&on 2-Adopted modeling approach allo+srepresenting a s+itch as an #( circuit.Allo+s a more accurate modelling ofs+itching d,namics.An AD e


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$7


To solve the problem of overshoots and

oscillations a resistance is placed inseries +ith the acting as a dampingelement.

onsider sho+n circuit During ' state obtained conductance is givenas

During 'FF state conductance is givenas


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$>


The relations bet+een voltages and currents of the

+hole po+er converter is given as a matri0 e


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$?


E>t/n / M$t#&> E?*$t&on

DESIGN OF ADC BASED EMBEDDE


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$


To optimi=e the comple0it, and avoid online matri0inversion relationship bet+een and the conductance matri0 constant independent os+itch state .

This relation is then



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-;


9) Mo *+$# P$#t&t&on&n'2-%odules are de/ned for AD !based model andthat are located in levels $ and - of the IP!(ibrar,."ach module is subdivided into submodulesfrom the lo+er levels.Processing of the states )' 'FF* of s+itches is/rst achieved depending on the s+itchingsignals and the s+itch voltages & currents.



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-:


F&'- . S,noptic of the AD !basedmodel.



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-$


c) D&'&t$+ R/$+&@$t&on2- To satisf, the timing constraint of the embedded #Tsimulator has been set to 4;; ns .the ma0imum s+itching fre


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--


c) A+'o#&t !V$+& $t&on2-

The discrete!time and/0ed point oRinesimulations have been

made +ith the help of%AT(AB Simulin3 tools . The >.4 :7;J1and :.7nF have beenmanuall, tuned and set .

F&'- 0. 'Rine simulation resultss+itches commutation )h5 4;Js d6 div : A div for IGBT ;.4 A



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-2


It is sho+n that +hen inCecting these estimated grid currents

to the controller the load disturbance is correctl, compensatedand V dc remains e


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3 . FPGA I!"+/!/nt$t&on2$) FPGA A#c &t/ct*#$+ D/ &'n2-

Implementing the AD !basedembedded #T simulator IP full, inhard+are and then designing a full,dedicated architecture is onl, option.

This full, hard+are approach enablesalso the portabilit, of the simulator IP.



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-7


F&'- 4. Dearchitecture of theof vector 0U3V.



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->


9) T&!/ A#/$ E6$+*$t&on2-

F&'- 5. Tim



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-?


#egarding the -!phase 6S# embedded #T simulator

the obtained (atenc, $? .Gives a computation time $?;ns )+ith as,stem cloc3 *. #esources Ksedi. :?; DSP2?": units )?:.?:9*ii. - ?$ (KTs )>.49*.iii. 72:; FFs )7.;$9*.

. IP uses 22 -$!bit multipliers to e0emultiplications .

DESIGN OF ADC-BASED EMBEDDE


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-


Finall, the +hole architecture including thethe @AD conversion unit the -!phase #(!/lterembedded #T simulators uses : .7?9 of the ava:- -;; slices

i. ?2.429 of the available $$; DSP2?": units.

ii. ::9 of (KTsiii. 9 of Lip!Lops. IP uses 22 -$!bit multipliers to e0e

multiplications .



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2;


4 . E>"/#&!/nt$t&on 2$) HIL T/ t 2- To ensure a /rst realistic validation of thedeveloped control s,stem an 1I( validationtest has been made.

For this an FPGA!based #T emulator of thepo+er s,stem under control has beenadded to the design.

To debug and to vie+ the internal signalsrunning in FPGA the hipScope anal,ser

has been used



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2:


F&'- 7. losed!loop #during )a* load connecti)b* at stead, state )h5 4;m6 div $.4 A div*.



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2$

DESIGN OF ADC BASED EMBEDDERT SIMULATOR (cont.)

9) E>"/#&!/nt$+ V$+& $t&on2-St/" 2 The resistive load )in the dc side

disconnected . All the s+itching signals applthe po+er converter are set to =ero.magnitude of the dc!lin3 voltage +as set e


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2-

DESIGN OF ADC BASED EMBEDDERT SIMULATOR (cont.)

St/" 32 The resistive load is connected to the dlin3.

St/" 42 The estimated grid currents processed areno+ used b, the controller instead measured ones. S+itching

measured and estimated currents is done b,a simple s+itch that is used to model currentsensor fault occurrence.

St/" 52 The resistive load is alternativel, connected

and disconnected )during fault*

EXPERIMENTAL SETU


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22

EXPERIMENTAL SETU

F&'- 8. )a* & )b* "0perimental setup

($) (9

)

RESULTS


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24

RESULTS

F&'- ;. %easured 6 dc and measured and estimated i ga durinoperation mode )h5 4;ms div v5 4; 6 div $.4 A div*

RESULTS (cont )


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27

RESULTS (cont.)

F&'-


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2>

RESULTS (cont.)

F&'-0=. %easured 6 dc and measured and estimated i+hen

the load is disconnected )h5 4;ms div v5 4; 6 div $.4 A div*.

RESULTS (cont )


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2?

RESULTS (cont.)

F&'-0 .

results dcommutati)h5 4;Js d: A div fofor diode*

CONCLUSION


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CONCLUSION The Proposed simulator +hen implemented +ithcontroller the, can be bene/cial form an, tas3as estimations observations diagnostic healmonitoring and online identi/cations.

The Graphs sho+s that the results are almost sameas estimated. This sho+s accurac, of the approachused.All these IPs +ere implemented in a lo+!cost @ilin0

,n< FPGA So device.Further improvements are intended such asthe dead time and implementing additional tas3s

online identi/cation algorithms to co

REFERENCES


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REFERENCES[1] Mohamed Dagbagi, Asma Hemdani, Lahoucine Idkhajine, Mohamed issem !aoua

#"ama$%e"khodja. &AD'$%ased (mbedded ea"$*ime #imu"a+or o a -owIm/"emen+ed in a Low$'os+ 0- A2 A//"ica+ion +o a 0au"+$*o"eran+ 'on+ro'onnec+ed 3o"+age$#ource ec+i ier4, in I((( *rans. Ind. ("ec+ron., o". 56, no. 77915

[7] '. Du our, *. :u"d %achir, L.$A. r;goire, and

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ADC-based Embedded RT Simulator for power converters implemented on FPGA