A variational model for transistors

Martinez, A., Lozano, M., Barquillas, J. and Carlosena, A. Dpto. Electricidad y Electr6nica, Facultad de Ciencias, University de Zaragoza, Spain

This paper presents a linear variational model for transistors in their typical amplify- ing region, valid for BJTs as well as FETs.

The model allows one to determine the most important parameters of analog elec- tronic systems: small-signal behaviour, thermal drift and effects of device mis- matches.

1. Introduction

The usual way in which analog electronic systems have been studied is based on the linearisa- tion of static characteristics of the active devices. The resulting expressions show the be- haviour of the device only under appropriately limited operating conditions and they can be interpreted in terms of linear equivalent circuits.

In this approach, there are many different linear models for each transistor type. Each one of these models describes different aspects of its behaviour: small-signal operation (incre- mental models1), thermal drift (electrothermal models2'3), and other phenomena associated with the dispersion of transistor parameters (variational models4'5'6). Therefore, the charac- terisation of an analog system requires the use of all these models, and this causes a lot of in- convenience in the development of this procedure.

Trying to solve this problem, a unified incremental model for the bipolar junction (BJT) and field-effect transistor (FET) has been proposed recently 7'8. It allows the small-signal characterisation of a system without specifying the transistor type.

Following this course, a linear variational model is proposed for transistors in their amplifying region. This model comprises all the ones previously mentioned and also permits the characterisation of the effects of device mismatches on the dc performance of systems. This is a basic limitation in integrated circuit design.

2. The unified model of a transistor amplifying region

A generic transistor is a three-terminal electronic device, represented in Fig. 1, whose dc be- haviour, in its amplifying region, presents the following characteristics:

= 1 3 + -

V32 2

Fig 1

MICROELECTRONICS JOURNAL Vol. 18 No. 1 @ 1986 Benn Electronics Publications Ltd, Luton 13

�9 The sum of tile terminal currents must be zero, assuming that these currents are positive when they flow into the transistor.

�9 A s a first-order approximation, the fundamental characteristic of the device is that all the currents depend on a single voltage V12 = Vt - V2.

�9 The dependence of the I2 current on the voltage V12 is proportional to that of 13 on this voltage.

�9 As a second order effect, the three currents depend also on the voltage V32. It affects basically I2 and I3. This effect can be incorporated by a multiplicative linear factor (1 + V32/VA), where VA is a constant (Early voltage).

According to these characteristics, the transistor behaviour in its amplifying region can be de- scribed by:

Ii = d.g ( V t 2 , • )

I3 = O .g (VI2,~) (1 + V32]VA)

I 1 + I 2 + 1 3 = 0

(1.a) (1 .b)

(1 .c)

where the d parameter can take only the values 0 or 1, depending on the transistor type. The g function is specific for each type of device, whereas the device parameters ~ , 0 and VA show a certain dispersion among different units of the same model.

Table I shows the current-voltage characteristics of each type of transistor 9, and the corres- ponding momenclature of the terminals.

The expressions for the parameters of the different devices can be obtained by identifying each one in this set of equations with those in (1). The results obtained are shown in Table II.

3. The variational model

From a design point of view, the parameters of a certain model must be considered as Gaus- sian random variables. So, we must accept the existence of a dispersion of the parameters about their mean values. At the same time, these mean values are a function of temperature. Standard values in integrated technology 9 are shown in Table III.

One of the performance factors in a design is the sensitivity of its overall characteristics to the variation of the component parameters, specially of the active ones. These factors will de- termine the influence on the system behaviour of temperature, device replacement or compo- nent mismatches. This last one is a very important feature in integrated technology.

The classic determination of each quality factor requires a specific method ~'5'6. This means a great effort to characterise the performance system.

We propose a method to obviate these difficulties. The basic idea is to infer a linear model which describes the influence of the characteristic parameter variation on the transistor be- haviour. This equivalent circuit is called the transistor variational model.

In order to deduce this equivalent circuit, we consider the existence of a dispersion of the transistor parameters and a low-frequency variational signal on the terminal voltages. Thus the transistor behaviour can be described by:

I, = d.g (Vt20 + AV,2 , r p "~ /~ ~))

I3 = (0 p.~- /~0 ) .g (V120 + /~VI2, ~ p " F / ~ )

Ii + I2 + IS = 0

(2.a)

(2.b)

(2.c)

14

where subscript Q points out the magnitudes corresponding to the quiescent operating point, while subscript P corresponds to the mean values of the device parameters.

The Taylor expansion applied to these equations up to the second order term gives:

al l ] aIx I a V l 2 d r "~'~'-i a l ~ AIl = Ii - Ilo = aV1------~l Q,P Q,P (3.a)

A 0 A I 3 = 1 3 - 1 3 o = O p -- VAp '4" V32 Q V-'~'- I30 -I- t VAP "Jr V32 O

+

[a I3 "a 13 ) "dr" t ,aV12 ] Q,p av12 -}-" - ~ - I o,v A , (3.b)

The resultant variation in the current I1 can be expressed as:

='Ill[ a II ~V12 I O,V t AVI2 "{"

all I A~ al~ O,P

at, [ BVI2I Q,p

a V l 2 - a v u = ri (4)

where 1 oil I d ag [ - - -- = ~ I (5) ri "~VI2 ] O,p VI2 O.p

~I1[ ~...g.g

~1 O . P ~r Q'P a ~ = aV12 I a r (6) a n d a V u = - ~I...L ] "AgS - ag a~ I I i = c t e .

~VI210,P ~VI2 o,v

According to tile last expression, AVu is the variation of a macroscopic parameter. It can be easily measured and is used in dc characterisation of the device.

The 13 current variation is the result of different contributions. The first term expresses the intrinsic influence that the dispersions of O and VA cause on this current. This term will be called aI0:

AIo= ( AO V~2o AVA / (7) Op VAp+V32Q ~ ] I3Q \

is

The second term depends only on the V23 voltage variation, and corresponds to a second order effect. This contribution can be expressed as follows:

AV32 (8) ro

where 1 _ 130 _ " 13o (9) To V32Q -~- VAp VAp

The last term shows the effect induced on I3 by the dispersion of the ~ parameter and V~2 vol- tage variation. This term can be expressed by:

%_3__] i~Vl2 I O,P

~I;I ) AVIz+ a~ ]q.Va~

aI3 [ ~Vl20,v

Taking Eqn. (6) into account, this last contribution can also be written as:

gm (AV12- AVu)

aI3 ] with gm = aV12

(10)

o,P (11)

Therefore, the resultant variation in the current I3 can be expressed as:

AI3 = AIo + AV32 dr gm (AVI2 -- AVu) ro

(12)

Equations (2.c), (4) and (12) can be easily interpreted in terms of the linear equivalent model as shown in Fig. 2. This circuit is the Variational Model.

AI1 -> 1,

T AVu

3

4,2

Fig 2

16

Table IV shows the approximate expressions of the parameters in this transfer equivalent model.

Finally, it is important to note that this model has been deduced taking into account only the essential physical phenomena that take place in the device. Thus, recombination phenomena in the natural base zone as well as in the emitter-base junction transition zone in the BJT have been neglected. Likewise we have not considered parasitic elements just as re- sistive effects associated with the inactive regions. These approximations are those commonly used in system analysis and design ~'9.

This model is useful to determine the various sensitivity factors that are helpful in the de- sign. It allows one to infer the effects associated with the dispersion of device parameters and so, to obtain the biasing network quality factors. In the same way, we can use this equivalent model to characterise the thermal shift of the operating point. The temperature dependences of device parameters are shown in Table V3'1~

If we substitute AVu and AI0 for the above expressions, we obtain the electrothermal model of each transistor type. Supposing AVu = AI0 = 0, the proposed model describes the small-signal behaviour of these devices.

4. Applications In order to demonstrate the effectiveness of the proposed model for analog system analysis, let us consider the example in Fig. 3. It is a current mirror, where the transistors can be either BJTs or enhancement MOSFETs.

I ref

1 "! 3" 3

' I T I T i 1 ' . i i 11" 2' 2

R

Fig 3 4.1 DC behaviour

If we neglect second order effects, i.e. if we consider VA to be large enough, this analysis can be easily performed.

In this circuit, the 1-2 voltages of the two transistors are forced to be equal. In the case of identical devices, it means:

13 ~-- 13 ; 11 = I~

17

Since I1 is proportional to 13; I~ = d . I3 / e

We can write:

I ,~ I~ + I; = I~ = I3 (1 + 2 d / e )

So, the output current of this structure can be related to if~f as:

13 = e . I~.e(/(e + 2d)

Substituting the values corresponding to BJTs (d = 1, = 13 and FETs (d = 0) in this expres- sion, we obtain:

BJT: I3 = Ird/(1 + 2/B)

MOS: I3 = If~f

The main error source in this BJT current minor is the B dependence. This source of error can be greatly reduced by adding a third transistor in the circuit 9. The resulting structure does not carry any additional advantages with MOS transistors, and therefore is not employed.

4.2 Device parameter d ispers ion

The effects tied to the device parameter dispersion can be analysed replacing each transistor by its variational model as shown in Fig. 4.

The easiest way to solve the above circuit is to use the superposition principle, i.e., to de- termine the resultant variation in the curent I3 associated with the device parameter disper- sion of each transistor.

Therefore, in order to calculate the effect of the variation ofT1 parameters in current I3, the transistor Tz and its associated network can be replaced by its equivalent resistance:

R

I

2'

!

A

I <-- A 13

3

T1 2

B

Fig 4

RE

18

r/

. - A I 3

AVul J' gr AVl A i o,

Fig 5

r[ = ro l/R//ri//(l/gm) ~ l/gin. The resulting circuit is shown in Fig. 5.

=I"o " ( - - g m ' r i A V u i + a l o i ) r0 + rL ri + re

I RL

For the input loop we have:

a v i = - aVul �9 ri/(ri +rl)

The output current is given by:

ro (g~aV1 + Alol) (AI3)I = r o + R L

As ri > > r~and ro > > RL, this expression simplifies to:

(aI3)! Z --gin- aVul + AI01 (13)

In a similar way, the influence of the dispersion of TI parameters can be obtained by the cir- cuit in Fig. 6. The Ti transistor has been replaced by its equivalent resistance ri.

We obtain:

AV2 = - (AIo2re + a V u 2 ) / [1 + (rJri) + gmre]

The variation in current I3 can be expressed by:

(Ai3)2 = ro gmaV~ ~ gm (AV2 + AVu2) " gin" (gmr~AVu2 -- alo2re) ro + R------~ = 1 +gmre + re/ri (14)

Assuming that gm " re > > 1, this expression is reduced to

gmre ) 1 + gmre + re/ri +

(15) (AI3)2 ~ gin" aVu2 -- aIo2

From Eqn. (13) and (14) we have:

a I3 = -- gin" ( AVul -- AVu2

19

+ ( A l o l - g m r c A I o 2 ) (16)

1 +gmre + re/ri

In a practical case, where gm "re > > 1, this expression could be reduced to:

AI3 = - gin" (AVul -- AVu2) + (AIol -- AIo2) (17)

4.3 Thermal drift

Since monolithic components present good temperature tracking properties, we can con- sider:

AVut = AVu2 = AV~

Alol = AIo2 = AIo

In this case, Eqn. (16) can be expressed in the form:

A 13 ~ -- (gin A Vu -- A Io) / (gmre)

This expression shows that this configuration shows good thermal stability.

(18)

4.4 Effects of device mismatches

In spite of the inherent matching of monolithic devices, small mismatches exist between two adjacent, identical transistors or resistors on the same chip.

The effects of these small mismatches in the current mirror can be analysed as in section 4.2. Thus it is enough to set:

AVul = - AVu2 = +AVu/2 and Alol = - AIo2 = -+AIo/2

In accordance with Eqn. (16):

1 1 + 2gmre + re/ri AI3 = -4- - .

2 1 + gmre + re/ri (gmAVu + AIo) ~ 4. (gmAVu +AIo) (19)

where the sign of each component is irrelevant. Comparing Eqn. (18) and (19) we see that this structure is much more sensitive to compo-

nent mismatches than to temperature. It is a typical characteristic in integrated configurations. Applying this expression to each type of transistor, we obtain:

BJT: AI3 = I,~f 1 + 2/13

+ A l s o + AI3 + VCEO AVA /

Iso 13 - VA VA /

+ A K + VDS O AVA I MOST: AI3 = 4- 2- (k.Iref)I/~ �9 AVTt t + Iref" K V A ~AA '/

This analysis can be simplified if we want only to determine the effects of device mismatches. In fact, the error sources in the output current can be determined by considering only the vari-

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ations in the device parameters of one transistor Is. So, /~I 3 could be calculated, for example, using the equivalent model shown in Fig. 6. In this circuit Z~Vul and/kI01 are the mismatches of the parameters of T1 and T{. Equation (17) shows this fact for this specific structure.

,~ gm ,',v2 ,J, AIo 2 Av2 r.-ri//ro//a

-~- AVu2

Fig 6 4.5 Small signal behaviour

As already noted, the proposed variational model describes also the small-signal behaviour of transistors.

The most important characteristic of this structure is its output impendance. This parame- ter can easily be determined by means of the equivalent circuit shown in Fig. 5, with/kVu~ = /kI0~ = 0. In this particular case, it is obvious that the output impendance is r0.

5. Conclusions

The proposed variational model is valid for BJTs as well as for FETs. As a systematic treat- ment, it allows us to determine the most important parameters in an analog system: small-sig- nal behaviour, system sensitivity to device replacements, thermal drift and mismatched com- ponents. This model can be utilised also to characterise low-frequency harmonic distortion in current feedback amplifiers 16.

6. References

[1] Gray, P. and Meyer, R., "Analysis and design of analog integrated circuits", J. Wiley, (1984).

[2] Herpy, M., "Analog integrated circuits", J. Wiley, (1980). [3] Hamilton, D. and Howard, W., "Basic integrated circuit engineering", McGraw-Hill,

(1975). [4] Hunter, L., "Handbook of semiconductor electronics", McGraw-Hill, (1970). [5] Martinez, P. and Barquillas, J., "Polarizaci6n de transistores de efecto de campo",

Rev. Acd. Ciencias Zaragoza, 1-2, (1976). [6] Montijano, J., "Polarizaci6n de transistores de efecto de campo: Factores de es-

tabilidad y recta din~imica de carga", Memoria Licenciatura, Facultad de Ciencias, Zaragoza (1980).

[7] Mart[nez, P. and Polhin, T., "A transconductance model in amplifier stages", I .J .E.E.E., 22, 3 (1985).

[8] Martinez, P. and Polhin, T., "Systematic method of midband ac analysis for transistor amplifiers", I .J .E.E.E., 22, 4, (1985).

[9] Grebene, A., "Bipolar and MOS analog integrated circuit design", J. Wiley, (1984). [10] Lozano, M., "Modelo variacional de transistores", Memoria de Licenciatura, Facultad

de Ciencias, Zaragoza, (1984).

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[11] Hart, B., "DC parameter characterisation of the Early effect in bipolar junction transis- tors", The Radio and Electronic Engineer, 50, 1-2, (1980).

[12] Cobbald, R., "Theory and applications of field-effect transistors", J. Wiley, (1970). [13] Milnes, A., "Semiconductor devices and integrated electronics", Van Nostrand,

(1980). [14] Sevin, L., "Field-Effect transistors", McGraw-Hill, (1965). [15] Martinez, P., "Efectos de asimetrfa en pares equilibrados", Rev. Informfitica y Au-

tom~itica, XV, 54, (1982). [16] Martlnez, P. and Lozano, M., "Nonlinear distortion in current-feedback amplifiers",

Microelectronics Journal, 16, 5, (1985).

TABLE I

TYPE

JBJT

(NPN)

JFET(N)

Depletion MOS (N)

Enhancement

MOS (N)

CHARACTERISTIC EQUATION

Ia = Isoe VBE/VT

VBE/VT Ic = Blsoe (1 + VcE/VA)

I~=0

IDS = IDSS

IDS = Inss

' I _ V ~ s / 2 ( I+VDs ' 1 V p / VAt

I~=0

f VG S -- VT H I 2 ( 1 + VDS / I~ , \ .

k

TERMINALS

1: Base

2: Emitter

3: Collector

1: Gate

2: Source

3: Drain

1: Gate

2: Sot, rce

3: Drain

22

TABLE II

Type g ( V m r )

BJT Iso e VBE/VT

JFET ' ) DepletionMOS t 1 - Vcs 2 Vp

Enhancement (VGs -- V~0 2

MOS

d 0 r VA

1 g Iso VA

0 IDs s Vp V A

0 K VTH VA

TABLE III

Type

BJT

JFET

Standard Value Absolute value tolerance Matching tolerance

B : 50-300

VBE : 0.6- 0.7V

+ 20

+ 20nV

+ 5 %

+ lmV

loss : 400 p.A 200- 800 ~ A + 10%

Vp : 2V _ 500mV _ 15mV

23

TABLE IV

BJT

JFET Depletion

Enhancement MOS

gm ri ro AIo AVu

Ico VT

2 IDSS-IDso Vp2

2 ~KIDso

B VA gm Ice

O O �9 ~ .

ICO ( AB--VcEo.A VA ) --VT AIso B VA VA Iso

VA IDSQ ' AIDSS-- VDSO AVA ~ VGS aVp IDSQ t IDSS VA VA ] Vp

VA IDSQ I AK-- VDS Q AVA i AVTrt IDSO ~ K V A V A t

TABLE V

Type

BJT

JFET Depletion MOS

Enhancement MOS

AVu

-VTaAT, a = 0.1PC

2 Voso cAT, c ~ mvPC Vp

--eVTH AT, e m 0.4 T

AIo

mobAT, b ~ 6 x 103/~

IDSO / - - d + 2 / a T ' d ~ 2 /

f --IDso f AT, - 1.5

T

24