A Single Phase Grid Connected DC/AC Inverter with Reactive Power Control for Residential PV

A Single Phase Grid Connected DC/AC Inverter with

Reactive Power Control for Residential PV Application

by

Xiangdong Zong

A thesis submitted in conformity with the requirementsfor the degree of Master’s of Applied Science

Graduate Department of Electrical and Computer Engineering

University of Toronto

Copyright © 2011 by Xiangdong Zong

Abstract

A Single Phase Grid Connected DC/AC Inverter with Reactive Power Control for

Residential PV Application

Xiangdong Zong

Master’s of Applied Science

Graduate Department of Electrical and Computer Engineering

University of Toronto

2011

This Master of Applied Science thesis presents a single phase grid connected DC/AC

inverter with reactive power (VAR) control for residential photovoltaic (PV) applications.

The inverter, utilizing the voltage sourced inverter (VSI) configuration, allows the local

residential PV generation to actively supply reactive power to the utility grid. A low

complexity grid synchronization method was introduced to generate the parallel and

orthogonal components of the grid voltage in a highly computationally efficient manner

in order to create a synchronized current reference to the current control loop. In addition,

the inverter is able to use a small long life film type capacitor on the DC-link by utilizing a

notch filter on the voltage control loop. Simulations were performed on PSCAD/EMTDC

platform and a prototype was also developed in the lab to prove the effectiveness of the

controllers and the grid synchronization method.

ii

Acknowledgements

First I would like to express my gratitude to my supervisor Professor Peter Lehn for his

wisdom, patience, and for giving me the opportunity to study with him and this exciting

project for my thesis. His guidance and support were the most important assets that led

the completion of this thesis.

I would also like to thank my loving parents Youjin and Guanghui for their uncon-

ditional love and support, and my wife Xiaolin for sticking with me through thick and

thin over the last five years.

Finally I would like to acknowledge and give thanks to all the people working in the

power lab for their support, especially Damien Frost and Gregor Simeonov.

iii

Contents

List of Abbreviations vii

1 Introduction 1

1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Literary Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.1 Grid connected PV systems . . . . . . . . . . . . . . . . . . . . . 4

1.2.2 Controls of the VSI . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2.3 Reducing the Size of the DC-link Capacitor . . . . . . . . . . . . 8

1.2.4 Grid Synchronization Techniques . . . . . . . . . . . . . . . . . . 10

1.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Single Phase Grid Connected Inverter Design 13

2.1 Inverter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 Switching Circuit Configuration . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 DC-link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 Electrolytic Capacitors vs. Film Capacitors . . . . . . . . . . . . 15

2.3.2 Sizing the DC-link Capacitor . . . . . . . . . . . . . . . . . . . . 18

2.4 Output Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.1 Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Controller Design 25

iv

3.1 Current Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.1 Plant Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.2 Proportional Resonant Controller . . . . . . . . . . . . . . . . . . 27

3.1.3 Closed-Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 Grid Synchronization Method . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.1 Grid Voltage Estimator . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.2 Grid Voltage Amplitude Identifier . . . . . . . . . . . . . . . . . . 38

3.2.3 Synchronized Current Reference Creation . . . . . . . . . . . . . . 41

3.2.4 Discussion of the Proposed Grid Synchronization Method . . . . . 41

3.3 Voltage Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.3.1 Voltage Loop Modelling . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.2 DC Voltage Compensator . . . . . . . . . . . . . . . . . . . . . . 46

3.4 Digital Implementation of the Controller . . . . . . . . . . . . . . . . . . 46

3.4.1 Switching Frequency Consideration . . . . . . . . . . . . . . . . . 48

3.4.2 Per-unitize and Fixed Number Format . . . . . . . . . . . . . . . 48

4 PSCAD/EMTDC Simulation Results 49

4.1 Inverter Current Loop Simulation . . . . . . . . . . . . . . . . . . . . . . 49

4.1.1 Steady State Response . . . . . . . . . . . . . . . . . . . . . . . . 51

4.1.2 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.2 Inverter Voltage Loop Simulation . . . . . . . . . . . . . . . . . . . . . . 53

4.2.1 Steady State Response . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2.2 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5 Inverter Experimental Results 58

5.1 Steady State Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.2 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

v

6 Conclusion and Future Work 65

6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

A IEEE-1547 Standard on Harmonic Current Injection 67

B PR Controller Behaviour 68

C Harmonics Table for Switch Mode Inverters 70

Bibliography 71

vi

List of Abbreviations

AC Alternating Current

DC Direct Current

DR Distributed Resources

LF Loop Filter

microFIT micro-feed-in tariff

MPPT Maximum Power Point Tracking

OPA Ontario Power Authority

PCC Point of Common Coupling

PD Phase Detector

PI Proportional Integral

PLL Phase Locked Loop

PR Proportional Resonant

PV photovoltaic

SOGI Second Order Generalised Integrator

SPWM Sinusoidal Pulse Width Modulation

vii

TDD Total Demand Distortion

THD Total Harmonic Distortion

VCO Voltage Controlled Oscillator

VSI Voltage Sourced Inverter

viii

List of Tables

2.1 Inverter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Output filter parameters and their chosen values . . . . . . . . . . . . . . 24

3.1 PR compensator’s parameters and system’s parameters . . . . . . . . . . 30

4.1 Inverter current loop simulation power stage parameters . . . . . . . . . 50

4.2 Active and reactive power measurement of the current loop simulation . . 51

4.3 Active and reactive power measurement of the voltage loop simulation . . 54

5.1 Summary of measured power factor and TDD . . . . . . . . . . . . . . . 59

A.1 Maximum harmonic current distortion in percent of current(I)a . . . . . 67

C.1 Generalized harmonics of VAo for a large mf . . . . . . . . . . . . . . . . 70

ix

List of Figures

1.1 Past technology - centralized inverters . . . . . . . . . . . . . . . . . . . 5

1.2 Two stage inverter configurations . . . . . . . . . . . . . . . . . . . . . . 6

1.3 Instantaneous output power of a single phase inverter at unity displace-

ment factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4 An example of an active power decoupling circuit . . . . . . . . . . . . . 9

2.1 Power stage configuration of the single phase PV inverter . . . . . . . . . 14

2.2 Generic DC-link voltage waveform . . . . . . . . . . . . . . . . . . . . . 15

2.3 Full bridge configuration with PWM unipolar voltage switching scheme . 16

2.4 Output LCL filter of the inverter . . . . . . . . . . . . . . . . . . . . . . 21

2.5 Magnitude plot of the output filter transfer function Hf(s) . . . . . . . . 23

2.6 Magnitude plot of Hf(jω) using selected filter components’ values . . . . 24

3.1 The inverter controller overall block diagram . . . . . . . . . . . . . . . . 26

3.2 Current controller block diagram . . . . . . . . . . . . . . . . . . . . . . 27

3.3 Bode plot of (a) ideal PR compensator, (b) non-ideal PR compensator,

Kcp=1, Kc

i=2000, ζ=0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.4 The bode plot of the uncompensated and compensated current loop gain 31

3.5 Overview of the grid synchronizer and VAR controller . . . . . . . . . . 32

3.6 Feedback loop of the grid voltage estimator . . . . . . . . . . . . . . . . . 33

x

3.7 (a) State trajectory of the estimator, (b)Peak voltage phasor diagram of

the estimator’s input and outputs . . . . . . . . . . . . . . . . . . . . . . 34

3.8 Bode plot ofVg‖(jω)Vg(jω)

andVg⊥(jω)

Vg(jω). . . . . . . . . . . . . . . . . . . . . . . 36

3.9 Turn on trajectory of the estimator’s state variables with different ksync

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.10 Time domain response of the estimator’s state variables . . . . . . . . . . 38

3.11 Zoomed in time domain response of the distorted grid voltage vg(t), the

estimator’s output and its desired values . . . . . . . . . . . . . . . . . . 39

3.12 Power factors vs. grid frequencies for Q=0 while neglecting switching

harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.13 Inverter power stage diagram . . . . . . . . . . . . . . . . . . . . . . . . 43

3.14 Phasor diagram of ig and its two components . . . . . . . . . . . . . . . 44

3.15 Voltage loop of the inverter . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.16 Effect of the double-line frequency ripple on the current reference signal . 45

3.17 Bode plot of the uncompensated and compensated voltage loop gain . . 47

4.1 Inverter current loop simulation setup . . . . . . . . . . . . . . . . . . . . 50

4.2 PSCAD/EMTDC simulation result of the grid voltage estimator’s outputs

and their desired values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.3 Steady state response of the current loop simulation . . . . . . . . . . . . 52

4.4 Step response of the current loop simulation . . . . . . . . . . . . . . . . 53

4.5 Inverter voltage loop simulation setup . . . . . . . . . . . . . . . . . . . . 54

4.6 Steady state response of the current loop simulation . . . . . . . . . . . . 55

4.7 TDD vs. ign when running pure real power and reactive power for voltage

loop simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.8 Voltage loop simulation based on the DC-link voltage step change . . . . 57

4.9 Step response of the voltage loop simulation based on the DC input current

step change and irefg⊥ step change . . . . . . . . . . . . . . . . . . . . . . . 57

xi

5.1 Inverter experimental setup . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.2 Steady state operation of the inverter. From top to bottom: DC-link

voltage V ndc=140V on CH1 at 50V/Div, grid voltage vg=60V(RMS) on

CH4 at 100V/Div and output current ig=10A (RMS) on CH3 at 20A/Div.

Time scale 5ms/Div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3 TDD vs. ign when running pure real power and reactive power . . . . . . 61

5.4 DC-link voltage step response of the inverter. (a) From top to bottom:

DC-link voltage vdc(t) on CH1 at 10V/Div, grid voltage vg(t) on CH4

at 100V/Div and output current ign on CH3 at 2A/Div. Time scale

20ms/Div. (b) From top to bottom: DC-link voltage vdc(t) on CH1 at

50V/Div, grid voltage vg(t) on CH4 at 100V/Div and output current ign(t)

on CH3 at 10A/Div. Time scale 20ms/Div . . . . . . . . . . . . . . . . . 63

5.5 Input power step change and irefg⊥ step change response of the inverter.

(a) from top to bottom: DC-link voltage vdc(t) on CH1 at 50V/Div, grid

voltage vg(t) on CH4 at 100V/Div and output current ign(t) on CH3 at

10A/Div, time scale 10ms/Div. (b) from top to bottom: DC-link voltage

vdc(t) on CH1 at 50V/Div, grid voltage vg(t) on CH4 at 100V/Div and

output current ign(t) on CH3 at 5A/Div, time scale 100ms/Div . . . . . . 64

B.1 Frequency response of the PR controller with each parameter changes . . 69

xii

Chapter 1

Introduction

This chapter introduces the main topic of this thesis, a single phase grid connected

DC/AC inverter with reactive power (VAR) control for residential photovoltaic (PV)

applications. In this work, the foci are on the control of the inverter and the grid

synchronization technique. Another challenge involves the reduction of the size of the

DC-link capacitor in order to use long life film capacitor in a low cost manner.

First, a brief background on the single phase PV grid connected inverter is presented

along with the motivation of this work. Then, a literary review on the PV inverter

system configurations, controls, DC-link capacitor reduction techniques and the grid

synchronization methods are presented. The objectives of this work is stated at the end

of this chapter.

The remainder of the work is organized as follows:

Chapter 2 describes the design of the inverter’s power stage including the selection of

the switching circuits, DC-link capacitor consideration, and the output filter design.

Chapter 3 focuses on the control methods of the inverter which consist of a current

controller along with a low complexity grid synchronization technique and a DC voltage

controller.

Chapter 4 shows the PSCAD/EMTDC simulation results for the grid connected in-

1

Chapter 1. Introduction 2

verter. The validation of the current loop control and the voltage control are shown.

Chapter 5 shows the experimental results for the grid connected inverter. The steady

state operation and the transient response results of the inverter are shown and discussed.

Chapter 6 summarizes the thesis, and the future directions that can be investigated.

1.1 Background and Motivation

Integration of PV power generation systems in the grid plays an important role in securing

the electric power supply in an environmentally-friendly manner. Grid-connected PV

inverters are needed to extract the energy from the PV modules and feed it into the utility

grid while ensuring the power quality follows certain grid interconnection standards such

as IEEE-1547 [1].

In addition to large scale rural solar farms, the market of residential PV power gen-

erations has grown rapidly in recent years by the encouragement of local governments

and utility companies. For example, in 2009, Ontario Power Authority (OPA) launched

the micro-feed-in tariff (microFIT) program to provide opportunities for homeowners,

farmers and small business owners to develop “mircro” renewable electricity generation

projects (10 kilowatts or less in size). Under the microFIT program, they will be paid a

much higher price for the electricity that the projects produce comparing to the standard

price people pay for their electricity. Particularly, for PV rooftop generation, the contract

price paid is 80.2 cents/kWh, whereas the blended rate of electricity in Ontario is 7.74

cents/kWh in the summer period. Therefore, with the help of such stimulation programs,

a growing market exists for residential PV inverters. Many companies such as National

Semiconductor and Enphase are expanding their business in the area of residential PV

inverters.

Unlike rural solar farms, residential PV modules require the grid-connected inverters

to be small, low-power and single-phase units. In North America, a split phase electricity


distribution system, also referred to as 3-wire, single-phase, mid-point neutral system, is

commonly used for single family residential and light commercial applications. There are

two live conductors in the system providing 240V between them; both live conductors

are referred as hot wires. The neutral wire is centre tapped from the output of the

distribution transformer, thus the hot to neutral voltage is 120V. The safety ground

connects cases of equipments to earth ground as a protection against faults. Such a

system makes it possible to supply 120V for ordinary receptacle service at home, while

also having 240V available for major appliances such as electric ranges and water heaters.

The frequency of the system is 60Hz. Therefore, single phase, 60Hz and 120/240V point

of common coupling (PCC) voltage can be used as a basic guideline when designing the

grid connected PV inverters and their controls.

As more distributed resources (DR) become integrated into the grid at the distri-

bution level, the trend that the DR units actively supply reactive power to the grid

has appeared. Having the capability of supplying reactive power with local DR’s would

not only help grid stability [2–4] but will also partially reduce the burden of delivering

reactive power from central generation to the local distribution level for compensating

of inductive load [5]. Although purposeful injection of reactive power or attempting to

regulate voltage by a distributed generator is not currently permitted by IEEE-1547,

there is a trend of changing such standard based on the reasons mentioned above. In

fact, in recent years, researchers have explored methods for single phase inverters to gain

the ability of supplying reactive power to the grid [6] [7]. Therefore, it is beneficial that

the single phase DC/AC grid connected inverter would have the feature of controlling

reactive power.

This thesis will therefore focus on designing a single phase grid connected DC/AC

inverter with VAR control for residential PV application.


1.2 Literary Review

1.2.1 Grid connected PV systems

Grid connected PV systems are categorized based on the number of power stages. The

past technology used single stage centralized inverter configurations. The present and fu-

ture technology focus predominantly on the two stage inverters where a DC/DC converter

is connected in between the PV modules and the DC/AC inverter.

1.2.1.1 Single Stage Centralized Inverters

A general summary of the evolution of the PV system configurations are described in [8].

The first generation of the grid connected PV systems directly connect centralized grid

connected DC/AC inverter to an array of PV modules, shown in Figure 1.1(a). The

PV modules are connected in series, also referred to as PV strings, in order to provide

sufficient output voltage. The PV strings are then connected in parallel through string

diodes in order to achieve high power production. In this configuration, the centralized

DC/AC inverter is subjected to handle, maximum power point tracking (MPPT), grid

current control and voltage amplification if necessary. Although the configuration is

simple, the drawbacks are substantial. One of the biggest is the poor energy harvesting

capabilities of the centralized MPPT due to shading, panel mismatch and degradation

factors [9]. Other drawbacks may include losses in the string diodes and the non-flexibility

of the design.

Reduced power versions of the centralized inverter configuration were developed to

have separated MPPT for each PV string, Figure 1.1(b). The systems are referred to as

string inverters. They offer higher energy harvesting than central converters and eliminate

the loss associated with string diodes. Although this configuration is advantageous in

the two aforementioned ways, people would still try to seek a more flexible design which

allows them to start their PV power plants with fewer modules and to easily enlarge the


DCAC

AC gridPV string

String diodes

(a) Centralized inverter configuration

DCAC

PV string

DCAC

PV string

ACgrid

(b) Reduced centralized inverter con-

figuration

Figure 1.1: Past technology - centralized inverters

system in the future. For this reason, DC/DC converters can be connected in between

the PV modules and the DC/AC inverters to provide MPPT and voltage amplification

so that fewer PV modules can be used in each string. Further system enlargements can

also be easily achieved with the help of the DC/DC converters.

1.2.1.2 Two Stage Inverters

In order to improve the energy harvesting capabilities and design flexibility, dedicated

DC/DC converters, which perform MPPT for each PV string can be connected in the

middle between the PV modules and the DC/AC inverter [8], Figure 1.2. The system

shown in Figure 1.2(a) has its PCC at the AC terminal. This system type benefits

from its modularity and the capability of plug-and-play installation by users that possess

limited knowledge of electrical systems. The output from the DC/DC converter in this

configuration can be either a low ripple DC voltage, or a modulated current that follows a

rectified sine wave. In the latter case, the DC/DC converter handles MPPT and output

current regulation while the DC/AC inverter switches at the grid frequency to unfold

the rectified sine wave. Reference [10] is an example of the unfolding configuration. The


DCAC

DCDC

DCAC

DCDC

ACgrid

PV string

PV string

(a) Two stage inverter PCC at AC terminal

DCAC

DCDC

DCDC

ACgrid

PV string

PV string

(b) Two stage inverter PCC at DC/AC inverter in-

put

Figure 1.2: Two stage inverter configurations

slow switching scheme of the DC/AC inverter allows usage of slow switching devices, e.g

BJT’s. In the case that the output is a low ripple DC voltage, the DC/DC converter

performs MPPT and voltage amplification if necessary. The DC/AC inverter is then a

voltage sourced inverter (VSI) which handles the output current regulation and DC bus

voltage regulation. The VSI usually uses a self commutating half bridge or full bridge

configuration as its switching circuit.

In the system shown in Figure 1.2(b), multiple DC/DC converters feed a single VSI.

The DC/DC converters handle MPPT and voltage amplification if necessary and the

central DC/AC inverter is again a VSI which handles the output current regulation and

intermediate DC bus voltage regulation. In this thesis, we focus on the VSI design of the

DC/AC inverter which is commonly used in the two stage PV inverter systems of types

shown in Figure 1.2(a) and 1.2(b) above.

1.2.2 Controls of the VSI

There are three major output current control techniques for the single phase VSI: hys-

teresis band, predictive, and sinusoidal pulse width modulation (SPWM) control [11] [12].


Traditional hysteresis controllers normally have an error band within a fixed range [13].

In such controllers, if the measured output current is lower than the lower limit of the

hysteresis band of the reference current, the bridge increases its output voltage, increas-

ing the current. On the contrary, when the output current is higher than the upper

limit of the hysteresis band of the reference current, the bridge reduces its output volt-

age, decreasing the current. This type of controller has the advantage of simplicity and

robustness, but the fixed error band would cause constant varying switching frequency,

which may increase the complexity of designing the output filters and the heat sinks of

the switches. An example of an adaptive hysteresis band current controller which can

achieve almost constant switching frequency to overcome the aforementioned problems

is stated in [14].

Predictive controllers calculate the required bridge output voltage to force the mea-

sured output current to follow the reference value. This type of control offers a potential

to achieve precise current control with minimum distortions [15] [16]. However, the

controller needs complicated calculations and requires a very accurate knowledge of the

system parameters. Reference [17] proposed an adaptive predictive current controller

which has more tolerance for system parameter mismatch, i.e. unexpected changes of

actual inductance with magnetic field intensity, temperature, etc. A fuzzy logic controller

was also proposed in [18] which provides robust performance under parameter and load

disturbances.

The SPWM control has a long history and is easy to implement. The traditional

method of SPWM control uses a proportional-integral (PI) compensator in the feedback

loop to regulate the output current. However, while PI compensators have excellent

performances on regulating DC quantities, tracking a sinusoidal current reference would

lead to steady state magnitude and phase errors [19]. Then, over the past two decade,

researchers have explored use of proportional-resonant (PR) controller, while can provide

“infinite” gain at the reference signal’s oscillating frequency [20] [21]. The PR controller,


Pout

t1/(2fg)

VgrmsIg

rms

Figure 1.3: Instantaneous output power of a single phase inverter at unity displacement

factor

based on the “internal model principle” first proposed by Francis and Wonham [22],

has the ability to eliminate the steady state error when tracking a sinusoidal wave and is

commonly used in single phase inverter systems [21,23,24]. This thesis takes advantage of

the PR compensator and implements the current controller using SPWM control theory.

1.2.3 Reducing the Size of the DC-link Capacitor

One of the challenges when designing single phase VSIs for PV application is the selection

of the DC-link capacitor. The instantaneous output power of a single phase inverter is

graphically shown in Figure 1.3, which contains a constant and a double-line frequency

power component. Therefore, the DC-link contains power pulsation with twice the grid

frequency. Often, large electrolytic capacitors are connected to the DC-link to absorb

this power pulsation so that the DC-link voltage ripple can be kept small. However, most

PV module manufactures offer 25 year warranties on 80% of the initial efficiency and five

years warranty on materials and workmanship [8]. Therefore, electrolytic capacitors with

large capacitance can not be used in PV applications because of their short lifetime.

Many techniques were proposed to reduce the size of the DC-link capacitor while

maintaining a good inverter power quality so that a more reliable film type capacitor can


DC

ACvg(t)

iin idc

idecoupleCdc

Cdecouple

S1

S2

Decoupling circuit

Figure 1.4: An example of an active power decoupling circuit

be used.

Methods like [25] and [26] uses an auxiliary circuit to circulate the double-line fre-

quency ripple power. Figure 1.4 is an example shown in [25], where the bidirectional

DC/DC converter is used as the decoupling circuit and the decoupling capacitor is al-

lowed to contain a large ripple component. In addition to the fact that an auxiliary circuit

would increase the energy loss, the inductor and the capacitor size used in the auxiliary

circuit has to be sufficiently large. Meanwhile, the switches used in the auxiliary circuit

must have rating comparable to the main power stage switches. Therefore, although

such methods can solve the problem of double-line frequency ripple, they are not a viable

solution considering the extra cost and energy loss associated with the introduction of

the auxiliary circuit.

Other methods [27] and [28] use control methods such as predictive and hysteresis

band control on the DC-link voltage. Both methods were able to “average out” the

double-line frequency ripple by only sampling the DC-link voltage every AC cycle so

that the output current would stay unaffected by the large ripple component. This thesis

utilizes a notch filter in the control loop to average out the double-line frequency that


appeared on the DC-link voltage. A detail analysis of the DC-link capacitor can be found

in Section 2.3.

1.2.4 Grid Synchronization Techniques

A conventional method of grid synchronization for grid connected DC/AC inverter is to

duplicate the grid voltage so that output current reference has the same phase as the

grid voltage [30]. While this method is simple, it carries the distortions and transients

from the grid to the output current, which is undesirable for grid connected applications.

In addition, this method of grid synchronization cannot provide inverters the ability of

controlling reactive power flow.

Phase locked loops (PLL) are commonly used in the single phase grid connected

inverters. Stationary frame PLLs only take the grid voltage as the input and do not

require additional signal. The typical stationary frame PLL employs a sinusoidal multi-

plier phase detector (PD), a loop filter (LF) and a voltage controlled oscillator (VCO).

Reference [31] modified the stationary frame PLLs with additional state feedback terms.

These feedback terms increase the synchronization speed, improve the immunity to input

noise and disturbances, and eliminate the double-line frequency ripple term generated

from the PD.

Synchronous frame (dq) PLLs are also commonly used in the modern grid connected

inverters. Such types of systems convert the oscillating grid voltage and its emulated

orthogonal component (αβ) to DC quantities (dq) using αβ - dq transform. Then a PI

regulator can be used to regulate either Vd or Vq to be zero so that the phase of the d

or q component can be locked. The methods of generating the orthogonal component

are different. In [32], a all pass filter is used on the input to have the phase of the gird

voltage delayed by 90 ◦. However, the all pass filter would also carry distortions from

the input. Others such as [33] and [34] generate the orthogonal component based on a

second order generalised integrator (SOGI). This structure effectively filters out the high


frequency distortion on the input and the orthogonal component before they are fed into

the αβ - dq transform. The synchronous frame PLLs, although not explicitly specified,

has the potential to provide sufficient phase information to the controller for the reactive

current reference generation. This effectively allows the inverter to have the ability of

controlling reactive power flow. Although this type of PLLs has the aforementioned

merits, its implementation process can be complicated due to the need for an orthogonal

component generator and sin and cos operations in the αβ - dq transform.

This thesis proposes a low complexity grid synchronization method which extracts

both the parallel component and the orthogonal component from the grid voltage while

sufficiently filtering out grid distortions. The grid synchronizer is easy to implement and

provides the inverter the capability of controlling the reactive power generation without

the need for dq frame transformation.

1.3 Objectives

The objectives of this works are as follows:

• Ensure that the voltage on the DC side of the VSI and the output current are well

regulated by choosing appropriate inverter topology, the output filter configuration

and proper control methods.

• The output current should meet the standard associated with larger 3-phase PV

inverters as laid out in IEEE-1547. This will enable grid code compliance if a large

number of inverters are clustered together and grid interfaced at the same PCC.

• Use high reliable energy storage components (i.e. film capacitors) to increase the

life-span of the inverter in a low cost manner.

• Introduce a new method of grid synchronization which gives the inverter the capa-

bility of controlling the reactive power generation at minimal computational burden.


• Exploit new generation MOSFETs and low cost MCUs to maximize switching fre-

quency and drive down output filter size and cost.

Chapter 2

Single Phase Grid Connected

Inverter Design

In this chapter, the design of the single phase PV inverter power stage is described,

Figure 2.1. Firstly, the inverter design specifications are given. Secondly, based on the

specifications, the choice of the switching scheme is briefly described. Thirdly, the selec-

tion of the DC-link capacitor is discussed based on its lifetime and size. Following this,

the design equations on DC-link capacitance are developed based on the power balance

and double-line frequency ripple voltage. Finally, the design guide for the output filter

is discussed based on the IEEE-1547 standard and the filter configuration is described.

2.1 Inverter Specifications

The basic specifications for the inverter design are listed in Table 2.1. Since the design

primarily focuses on the control and the grid synchronization method of the inverter,

the efficiency target of the inverter is not specified because it is outside of the scope.

Although maximizing efficiency is not the focus of this work, loss considerations still

drive selection of a viable converter topology.

In addition, Figure 2.2 illustrates a general waveform of the DC-link voltage to show

13

Chapter 2. Single Phase Grid Connected Inverter Design 14

vg(t)

+

-

ig(t)LgLi

Cf

Rd

+

-

sa sb

salow sb

low

idc(t)

Cdcign(t)vdc(t) vt(t)

Figure 2.1: Power stage configuration of the single phase PV inverter

the definition of the nominal DC-link voltage and the ripple component.

Rated grid voltage, V ratedg 250V (RMS)

Rated grid current, Iratedg 10A (RMS)

Switching frequency range, fsw >20kHz,<45kHz

Nominal DC-link voltage, V ndc 400V

Percentage DC-link voltage ripple (peak to nominal) 10%

Table 2.1: Inverter specifications

2.2 Switching Circuit Configuration

A full bridge configuration with SPWM unipolar voltage switching scheme is used (Fig-

ure 2.3) as the switching circuit of the inverter. By selecting the full bridge configuration,

the minimal allowed DC-link voltage can be set to be the peak value of the AC grid volt-

age (plus margins). Thus, power MOSFETs, instead of higher voltage IGBTs, can be

used as the switching devices which enables use of a high switching frequency (> 20kHz)

without indroduction of excessive switching loss.

Furthermore, showing in Figure 2.3(d), using unipolar voltage switching scheme effec-


vdc(t)

vdc,ripple(t)Vdcn

t

Figure 2.2: Generic DC-link voltage waveform

tively moves the first major harmonic of the bridge output voltage from order mf − 1 to

the order of 2mf −1, where mf is the frequency modulation ratio - the ratio between the

switching frequency and the fundamental frequency. The output filter thus reduces its

size for “free”. Since this full bridge configuration with SPWM unipolar voltage switch-

ing scheme is commonly used in voltage sourced inverters, further investigations will not

be presented in this thesis. A full detail analysis can be found in [35].

2.3 DC-link Capacitor

This section discusses the two types of capacitors that can be used as the DC-link buffer-

ing capacitor. A brief comparison is made based on their life time and power decoupling

ability. Methods of ensuring the inverter’s power quality while using a capacitor that has

a small capacitance are also discussed. Finally, the calculation of the DC-link capacitance

is shown in this section.

2.3.1 Electrolytic Capacitors vs. Film Capacitors

The DC-link capacitor is important for the power decoupling between the input power to

the inverter and their output power to the utility grid. Normally, electrolytic capacitors

are used for their large capacitance and low cost. However, in PV applications where the


+

-vdc(t) +

-vt(t)

sa sb

salow sb

low

A

B

(a) Full bridge configuration

t

vref

(-vref)

vsaw

0

(b) Unipolar SPWM switching scheme

t

vdc

-vdc

0

vt

vt,fund(t)

(c) Waveform of the bridge output voltage

dc

ht

vV )ˆ(

h0

0.2

0.4

0.6

0.8

1.0

1 mf 2mf 3mf 4mf

(2mf-1) (2mf+1)

(d) Harmonics on the nominlized frequency spectrum

Figure 2.3: Full bridge configuration with PWM unipolar voltage switching scheme


inverters are usually exposed to outdoor temperatures, the lifetime of such electrolytic

capacitors is shorten drastically according to the equation below [8] [36]:

Lop = Lop(0) · 2T0−Th

ΔT (2.1)

where Lop is the operational lifetime, Lop(0) is the specified operational lifetime at the

hot-spot temperature T0 (can be found in the product datasheets), Th is the operating

temperature and ΔT is the degree Celsius increase that would results in half the oper-

ational life (also can be found in the product datasheet). Typically, Lop(0) is between

3000 hours to 6000 hours (8 months to 16 months) at 85 ◦C for electrolytic capacitors

with rated voltage above 400V [37].

In PV applications, since most PV module manufactures offer 25 year warranties on

80% of the initial efficiency and five years warranty on materials and workmanship [8],

the lifetime of the electrolytic capacitors have become a major limiting component inside

a PV inverter.

Film capacitors are a clear the alternative given their long life expectancy and wide

operating temperature range. Unfortunately, film capacitors are far more expensive than

the electrolytic ones in term of cost per farad, hence the size of the capacitance has to

be smaller to keep the price of the capacitor acceptable. However, smaller capacitance

would weaken the power decoupling ability of the DC-link capacitor which may cause

DC-link voltage fluctuations that lead to distortion of the inverter output current to the

grid.

There are two factors that can cause undesirable DC-link voltage variations. The

first one, which can be referred to as the transient DC fluctuation is caused by the rapid

increase/decrease of the input power flowing into the DC-link capacitor. The quality

of the output current can be optimized by using a very fast current controller or by an

optimal current adjustment method stated in [29] and [28]. However, in PV application,

the chance of rapid DC input power variation is little due to the nature of the sun as


well as the processing delay of MPPT in the front end DC/DC converter. Therefore, the

transient DC fluctuation is not a major concern when designing a VSI for PV application.

The second factor, which can be referred to as the AC fluctuation of the DC-link

voltage is caused by the double-line frequency ripple power generated from the grid

side (refer to Equation (2.4)). This double-line frequency ripple component can couple

through the DC voltage control loop to cause a significant amount of distortion on the

current reference signal.

Therefore, methods need to be taken so that the inverter output current is immune

to the double-line frequency ripple on the DC-link voltage. A notch filter or an average

filter can be applied to the feedback signal of the DC-link voltage in the voltage control

loop, so that this double-line frequency ripple component is filtered out before entering

the voltage controller. This prevents the output current from having distortions that

are resulted from the DC voltage control loop. Furthermore, we also employ a nonlinear

DC voltage feedforward to the output of the current controller so that the modulation

signal that is sent to the SPWM modulator cancels out the effect of the double-line

frequency ripple that appears on the DC-link (refer to Figure 3.1 in Chapter 3). A

further discussion on the double-line frequency ripple component reduction method can

be found in Section 3.3.

In this thesis, a notch filter is employed in the DC voltage control loop to keep the

output current from the distortion caused by the double-line frequency ripple voltage. As

a result, the inverter has a relatively large tolerance on the voltage ripple that appeared

on the DC-link, thus a film capacitor with relatively small capacitance can be used to

keep the DC-link capacitor at an acceptable price.

2.3.2 Sizing the DC-link Capacitor

To limit the magnitude of the double-line frequency ripple voltage to the specified level,

the DC link capacitor is sized according to the following equations:


Assuming the grid voltage and the grid current are:

vg(t) = Vgcos(ωgt) (2.2)

ig(t) = Igcos(ωgt− φ) (2.3)

Then the instantaneous output power can be easily obtained as:

Pout(t) = Vg Igcos(ωgt)cos(ωgt− φ) = V rmsg Irms

g cosφ+ V rmsg Irms

g cos(2ωgt− φ) (2.4)

This can be rewritten to be:

Pout(t) = Scosφ+ Scos(2ωgt− φ) (2.5)

where S is the apparent power which has a unit of VA. Then assuming (i) the instan-

taneous input power equals to the instantaneous output power of the inverter, (ii) the

DC capacitance filters out the high switching frequency components in the DC current

idc(t), and (iii) the DC-link has a nominal voltage of V ndc,

V ndcidc(t)

∼= Scosφ+ Scos(2ωgt− φ) (2.6)

The idc(t) can be separated as a DC component, Idc and an AC component, idc,ripple(t).

Then the double-line frequency component can be extracted such that:

V ndcidc,ripple(t) = Scos(2ωgt− φ) (2.7)

Rearranging the above equation yields:

idc,ripple(t) =S

V ndc

cos(2ωgt− φ) = Idc,ripplecos(2ωgt− φ) (2.8)


Then the capacitance of the DC-link capacitor can be easily obtained given the mag-

nitude of the maximum allowed ripple voltage, V maxdc,ripple:

Cdc =Idc,ripple

2ωgV maxdc,ripple

=S

2ωgV ndcV

maxdc,ripple

(2.9)

Finally, substituting, these parameters from the inverter specifications.

Cdc =2.5kV A

2 · 377rad/s · 400V · 40V = 207.2μF (2.10)

Based on this, a 230μF Cornell Dubilier film type capacitor which as a life expectancy

of 200,000 hours (44 years) at 60 ◦C was selected to be used in the prototype.

2.4 Output Filter Design

As discussed in Section 2.2, the lowest order harmonics that appeared on the harmonic

spectrum of the output voltage of the full-bridge are at the sidebands of 2mf . Since the

inverter switching frequency is set to be greater than the audible frequency (20kHz), the

lowest order of the harmonics of the inverter is (2mf − 1) = 665. According to the IEEE

DR interconnection standard, IEEE-1547 [1]1, any current harmonic which has an order

that is greater than 35 must have a magnitude that is no greater than 0.3% of the rated

current of the DR output, and the total demand distortion (TDD)2 has to be under 5%

(the original harmonic regulation table in IEEE-1547 can be found in Appendix A). If

the lowest order harmonics of this inverter can be reduced to 0.3%, the TDD can be

readily kept under 5%. Thus, the primary design guide for the inverter output filter is to

make the magnitude of the major harmonic current of the inverter less than 0.3% of the

rated current. In addition, as IEEE-1547 also stated, “the harmonic current injections

shall be exclusive of any harmonic currents due to harmonic voltage distortion present in

the Area Electrical Power System (EPS) without the DR connected”, the output filter


vg(t)vt(t)

Li LgCf

Rd

ig(t)+

-

+

-

LCL Filter

Figure 2.4: Output LCL filter of the inverter

design will not take harmonic grid voltage distortions into consideration.

2.4.1 Filter Configuration

A third order LCL filter, Figure 2.4, was used to meet the aforementioned harmonic

reduction target. A switching frequency of 30kHz was selected based on considerations

for the filter size and the practical implementation of the digital controller.

vt(t) stands for the terminal voltage or the output voltage of the full bridge, which

consists of a fundamental component and higher order harmonics components. Solv-

ing the grid current in Laplace domain using superposition yields the following transfer

functions:

Ig(s)

Vt(s)

∣∣∣∣∣Vg=0

= − sCfRd + 1

s3LiLgCf + s2CfRd(Li + Lg) + s(Li + Lg)(2.11)

Ig(s)

Vg(s)

∣∣∣∣∣Vt=0

=s2LiCf + sCfRd + 1


From the above Equation (2.11) and (2.12), one can observe that the grid current ig(t)

1IEEE-1547 directly references the grid current harmonic distortion limits for general distributionsystems stated in IEEE-519 [38]

2TDD: the total root-sum-square harmonic current distortion, in percent of the maximum demandload current or the rated DR current capacity [1]


depends on both the terminal voltage vt(t) and the grid voltage vg(t). As discussed before,

the output filter design will not take harmonic grid voltage distortion into consideration

because IEEE-1547 allows the presence of harmonic current distortion caused by grid

voltage distortion. Therefore, Equation (2.12) will not be taken into consideration in

output filter design.

The terminal voltage vt(t) contains a fundamental component and higher frequency

components which could result in higher frequency distortions on the grid current ig(t).

Therefore, Equation (2.11) is used as the output filter transfer function as:

Hf(s) =Ig(s)

Vt(s)

∣∣∣∣∣Vg=0

= − sCfRd + 1


The RMS value of the higher order frequency components of vt(t) can be calculated

using the look up table from [35] (refer to Appendix C), given the nominal DC-link

voltage V ndc:

|Vt(jhωg)| = 1√2· 2 · (VAo)h

1/2V ndc

V ndc

2=

1√2· k(h)V n

dc (2.14)

The (VAo)h is the peak value of each harmonic voltage between one leg of the bridge

and the centre point of the DC-link, vAo(t). In full bridge configuration, vt(t) = 2vAo(t).

k(h) = (VAo)h1/2V n

dcis tabulated as a function of ma and the orders of harmonics (refer to

Appendix C for details about the harmonics table). Therefore, combining (2.13) and

(2.14), the RMS value of the harmonic current can be expressed as:

|Ig(jhωg)| = 1√2· |Hf(jhωg)| · k(h) · V n

dc (2.15)

Remember that |Ig(jhωg)| can not exceed 0.3% of the rated current of the inverter.

Therefore, given the RMS value of the rated grid current Iratedg the following relationship

can be derived:


0dB

gi LL1

gif

gi

LLCLL

-70dB

376614

-20dB/dec

-60dB/dec

Peak depends on Rd

|Hf(jw)|

Figure 2.5: Magnitude plot of the output filter transfer function Hf(s)

|Hf(jhωg)| · k(h) · V ndc√

2 · Iratedg

< 0.3% (2.16)

Rewrite for |Hf(jhωg)|, then

|Hf(jhωg)| <0.3% · √2 · Iratedg

V ndc · k(h)

(2.17)

Given from Appendix C, the worst case k(h) at 2mf − 1 is 0.37. Then, substituting

the parameters from the inverter specification and using a switching frequency of 30kHz,

we get the magnitude of the filter transfer function |Hf(jhωg)| at (2mf − 1):

∣∣∣Hf

(j((2mf − 1)377

))∣∣∣ = ∣∣Hf

(j(376614)

)∣∣ = 0.3% · √2 · 10A400V · 0.37 = 2.86× 10−4 ∼= −70dB

(2.18)

With the transfer function of the filter derived in Equation (2.13), the generic magni-

tude plot of Hf(s) can be drawn as shown in Figure 2.5. At ω = 376614, the magnitude

of Hf (j376614) from the magnitude plot of Hf (jω) should at most be -70dB. This is the

guideline of choosing the values for Li, Lg, Cf and Rd. Finally, the LCL filter compo-

nents are chosen following this guideline and the values of each component are shown in

Table 2.2. The MATLAB magnitude plot of the filter is shown in Figure 2.6, and it can


Li Lg Cf Rd

300μH 100μH 30μF 1.5Ω

Table 2.2: Output filter parameters and their chosen values

100 101 102 103 104 105 106−100

−80

−60

−40

−20

0

20

40

60

80M

agni

tude

(dB

)Bode Diagram

Frequency (rad/sec)

Figure 2.6: Magnitude plot of Hf(jω) using selected filter components’ values

be seen that with the components chosen in Table 2.2, the magnitude of Hf(jω) is under

-70dB at ω=376614.

Chapter 3

Controller Design

The discussion of the controller for the inverter can be divided into three parts: 1) current

controller, 2) grid synchronization and 3) DC voltage controller. A block diagram of the

controller is shown in Figure 3.1. Similarly to the control of a three phase VSI, the

current controller is used to regulate the current injected into the grid and the voltage

controller is used to regulate the DC voltage at a desirable level. Unlike the three phase

VSI, the active and the reactive power of the single phase VSI cannot be controlled by

varying id and iq in the d-q frame. Instead, a grid synchronizer block is proposed to

create a grid current reference which has the control of the active and the reactive power

flow.

3.1 Current Controller

A single phase feedback current loop is used to regulate the grid current. A proportional

resonant (PR) compensator is used to track a sinusoidal current reference signal. The

plant modelling, PR compensator design and the closed loop stability is discussed in this

section. The current controller block diagram is shown in Figure 3.2.

25

Chapter 3. Controller Design 26

vg(t)

+

-

ig(t)LgLi

Cf

Rd

+

-

sa sb

salow sb

low

idc(t)

Vdcref Gv(s)

Notch Filter

vdcfil

+

-

ev

refgi || Grid

Synchronization

refgi

refgi

Gi(s)

vdc

vg(t) ig

+- ei

Voltage Controller

Current ControllerGrid

Synchronization

Cdc

SPWM

vrefa

vrefb

sa salow sb sb

low

)(1tvdc

*-1

ign(t)vdc(t) vt(t)

DCvoltage

feedward

Figure 3.1: The inverter controller overall block diagram

3.1.1 Plant Modelling

Before designing the loop compensator, the plant model of the inverter can be derived

from Section 2.4.1 by combining equation (2.11) and (2.12), which yields:

Ig(s) = Gf(s)(s2LiCf + sCfRd + 1

sCfRd + 1Vg − Vt

)(3.1)

where,

Gf(s) =sCfRd + 1


Since the magnitude and phase response ofs2LiCf+sCfRd+1

sCfRd+1are 0dB and 0 ◦ at the

fundamental frequency of Vg(jω). Therefore, equation (3.1) can be simplified to equa-

tion (3.3).

Ig(s).= Gf (s)(Vg − Vt) (3.3)


Gi(s) Gf(s)

Vg(s)

+-

Ig(s)Igref(s) +

-

Vt(s)

PlantCurrent Controller

Figure 3.2: Current controller block diagram

Given the plant model, a PR compensator, Gi(s) is then added to the closed loop

and the equivalent closed loop diagram can be seen in Figure 3.2.

3.1.2 Proportional Resonant Controller

Normally in a three phase VSI SPWM based current controller, the 60Hz three phase grid

signals can be transformed into DC quantities by performing the ABC to d-q transform

(Park’s transform) so that the current reference can be set to be a DC quantity and a

PI compensator is sufficient to track the DC reference signal. However, in a single phase

inverter, the grid signals cannot be transformed into DC quantities so that the reference

signal to the feedback loop has to be sinusoidal.

In high switching frequency converters, such as power factor corrected (PFC) power

supplies, non-DC quantities can still be regulated using a simple PI compensator because

of their fast switching frequency, i.e. 200kHz. However, in this PV inverter, switching at

such high frequency is not an option considering the switching loss associated with the

MOSFETs and their reverse conducting diodes that are connected to a DC-link with a

relatively high voltage level. Therefore, for this PV inverter that is switching at 30kHz, a

PI compensator is no longer sufficient to track the reference. A higher order compensator

is needed to used as a substitute.

According to Figure 3.2, the relationship between the input and the output of the

current loop can be derived as:


Ig(s) = Hi(s)Irefg (s) +Hv(s)Vg(s) (3.4)

where,

Hi(s) =Gi(s)Gf(s)

Gi(s)Gf(s)− 1(3.5)

Hv(s) =Gf (s)

1−Gi(s)Gf(s)(3.6)

To successfully track the irefg (t) signal without steady state errors, the magnitude of

Hi(jω) in Equation (3.5) has to equal to 1 at the fundamental frequency of the irefg (t).

Thus, it is clear that if Gi(jω) has a infinite gain at the fundamental frequency, Hi(jω)

would have a unity gain. On the other hand, if Gi(jω) has a infinite gain at the fundamen-

tal frequency, Hi(jω) in Equation (3.6) would results in 0 at the fundamental frequency

so that the Hv(jω) term can be neglected. Therefore, it is not necessary to have the grid

voltage feed-forward in the current control loop. To conclude, the compensator, Gi(jω)

has to have a infinite gain at the fundamental frequency in order to track the current

reference, irefg (t).

A proportional-resonant (PR) compensator meets the aforementioned controller re-

quirement. An ideal PR compensator which has an infinite gain at ωo has a transfer

function shown in Equation (3.7) and a generic bode plot is shown in Figure 3.3(a).

However, the infinite gain of the controller leads an infinite quality factor of the system,

which cannot be achieved in either analog or digital controller implementation. Further-

more, since the gain of an ideal PR compensator at other frequencies is low, it is no

adequate either to eliminate the higher order harmonics influenced by the grid voltage or

to react to slight grid frequency variation. This is undesirable because the harmonic grid

voltage distortion would results in a significant amount of harmonic grid current distor-

tion. Therefore, a damping term ζ is introduced to form a non-ideal PR compensator

transfer function shown in Equation (3.8). This damping term ζ reduces the infinite gain


0

50

100

150

200

250

300

Mag

nitu

de (d

B)

101 102 103 104−450

−405

−360

−315

−270

Pha

se (d

eg)

Bode Diagram

Frequency (rad/sec)

(a) Ideal PR compensator

0

5

10

15

20

25

30

Mag

nitu

de (d

B)

100 101 102 103 104 105−90

−45

0

45

90

Pha

se (d

eg)

Bode Diagram

Frequency (rad/sec)

(b) Non-deal PR compensator

Figure 3.3: Bode plot of (a) ideal PR compensator, (b) non-ideal PR compensator, Kcp=1,

Kci=2000, ζ=0.1


at the fundamental frequency to a finite large gain but increases the bandwidth of the

compensator. A generic bode plot of the non-ideal PR compensator is shown in Fig-

ure 3.3(b). In order to understand the non-ideal PR controller’s behaviour, three groups

of bode plots are drawn in Appendix B to demonstrate how the PR controller’s response

varies by changing the each parameter in the transfer function.

Gi(s) = Kcp +

Kci s

s2 + ω2o

(3.7)

Gi(s) = Kcp +

Kci s

s2 + 2ζωos+ ω2o

(3.8)

3.1.3 Closed-Loop Stability

The closed loop gain of the current control loop with the PR compensator can be simply

obtained by Equation (3.9). The PR compensator’s parameters and system’s parameters

are chosen in Table 3.1.

Tc(s) = Gi(s)Gf(s) =(Kc

p+Kc

i s

s2 + ζωos+ ω2o

) sCfRd + 1

s3LiLgCf + s2CfRd(Li + Lg) + s(Li + Lg)

(3.9)

Kcp Kc

i ζ Li Lg Cf Rd

3 20000 0.01 300μH 100μH 30μF 1.5Ω

Table 3.1: PR compensator’s parameters and system’s parameters

The bode plot of the uncompensated loop gain and the compensated loop gain is

shown in Figure 3.4. It can be seen from the compensated current loop gain, the large

system bandwidth would give the current controller a fast response. Meanwhile, having

a phase margin of 50.9 ◦ demonstrates closed loop stability.


−100

−80

−60

−40

−20

0

20

Mag

nitu

de (d

B)

103 104 105 106−270

−225

−180

−135

−90

Pha

se (d

eg)

Bode DiagramGm = 9.43 dB (at 2.22e+004 rad/sec) , Pm = 90 deg (at 2.54e+003 rad/sec)

Frequency (rad/sec)

(a) Uncompensated current loop gain

−100

−50

0

50

100

Mag

nitu

de (d

B)

100 101 102 103 104 105 106−225

−180

−135

−90

−45

0

Pha

se (d

eg)

Bode DiagramGm = 14.2 dB (at 3.33e+004 rad/sec) , Pm = 50.9 deg (at 1.12e+004 rad/sec)

Frequency (rad/sec)

(b) Compensated current loop gain

Figure 3.4: The bode plot of the uncompensated and compensated current loop gain


3.2 Grid Synchronization Method

A low complexity method of grid synchronization is introduced in this section. Effort has

been taken to minimize the computational processes of reproducing a parallel component

and an orthogonal component of the grid voltage by means of using only a two by two

state matrix. The reactive power can then be controlled once the orthogonal component

of the grid is obtained.

The grid voltage synchronizer consists of two parts: (i) a grid voltage estimator, (ii)

an amplitude identifier. An overview of the grid synchronizer is shown in Figure 3.5.

3.2.1 Grid Voltage Estimator

The grid voltage estimator takes the grid voltage as its input and outputs one signal

which is aligned with the grid voltage (parallel component) and the other signal which is

90 ◦ leading the grid voltage (orthogonal component). This estimator has a state space

form of:

Grid voltageestimator

vg||gv

gv

refgi ||

Amplitudeidentifier

gV

refgi

ig

ref

Figure 3.5: Overview of the grid synchronizer and VAR controller


vg +

-

e=vg-x1

x1

yeDxCy

eBxAxˆˆ

ˆˆ

x1=[1 0] y

Figure 3.6: Feedback loop of the grid voltage estimator

⎡⎢⎣x1

x2

⎤⎥⎦ =

A︷︸︸︷⎡⎢⎣ 0 ωo

−ωo 0

⎤⎥⎦⎡⎢⎣x1

x2

⎤⎥⎦+

B︷︸︸︷⎡⎢⎣ksync

0

⎤⎥⎦(vg − x1) (3.10)

⎡⎢⎣vg‖

vg⊥

⎤⎥⎦ =

⎡⎢⎣y1y2

⎤⎥⎦ =

C︷︸︸︷⎡⎢⎣1 0

0 1

⎤⎥⎦⎡⎢⎣x1

x2

⎤⎥⎦

The above state space form the estimator takes vg −x1 as its input and outputs x1 as

the parallel component of vg. Thus, this essentially resembles a feedback loop illustrated

in Figure 3.6, where the output x1 tracks vg.

The reference signal of this feedback loop is vg, a sinusoidal signal oscillating at the

grid frequency ωg. The state matrix A provides the grid voltage estimator a internal

oscillator oscillating at the ωo. This provides the estimator an infinite gain at ωo in the

frequency domain.

The ksync term introduces damping to the oscillator which widens the estimator’s

bandwidth and reduces the gain at ωo. As a result, x1 tracks the input vg, at its funda-

mental frequency while also rejecting other harmonics that appeared on the grid voltage.

Following this, the output y1 is denoted as vg‖ to illustrate the its alignment with the

grid voltage and the output y2 is denoted as vg⊥ to illustrate it is orthogonal to the

grid voltage. The state trajectory and the peak voltage phasor diagram are shown in


Im

Re||gV

gV

x1

x2

wo

(a) (b)

Figure 3.7: (a) State trajectory of the estimator, (b)Peak voltage phasor diagram of the

estimator’s input and outputs

Figure 3.7.

The state space form of the compensator (Equation (3.10)) can be further rewritten

to the standard state space form shown in Equation (3.11) so that vg is expressed as the

input to the estimator and the outputs are the parallel component and the orthogonal

component of vg.

⎡⎢⎣x1

x2

⎤⎥⎦ =

A︷︸︸︷⎡⎢⎣−ksync ωo

−ωo 0

⎤⎥⎦⎡⎢⎣x1

x2

⎤⎥⎦+

B︷︸︸︷⎡⎢⎣ksync

0

⎤⎥⎦(vg) (3.11)

⎡⎢⎣vg‖

vg⊥

⎤⎥⎦ =

⎡⎢⎣y1y2

⎤⎥⎦ =

C︷︸︸︷⎡⎢⎣1 0

0 1

⎤⎥⎦⎡⎢⎣x1

x2

⎤⎥⎦

3.2.1.1 Simulations of the Grid Voltage Estimator

The behaviour of this grid synchronizer was further analyzed by means of studying its

responses in both frequency and time domain.

First, the bode plot of each output of the compensator’s responses are shown in Fig-


ure 3.8. In Figure 3.8(a), theVg‖(jω)Vg(jω)

response has a magnitude of 0dB and a phase of

0 ◦ at the grid fundamental frequency and filters out distortions at any other frequen-

cies. In Figure 3.8(b), theVg⊥(jω)

Vg(jω)response also keeps the magnitude at 0dB at the grid

fundamental frequency but only filters out distortions at higher frequencies. Meanwhile,

the phase of theVg⊥(jω)

Vg(jω)response is at 90 ◦ at the grid fundamental frequency so that vg⊥

leads vg by 90 ◦. It can also be observed from Figure 3.8, the more the ksync increases, the

less the synchronizer are sensitive to slight variations of the grid fundamental frequency

but more vulnerable to noise at other frequencies. Furthermore, the larger the ksync gets,

the wider the controller’s bandwidth extends, which means the faster the vg‖ locks on vg.

Then, the “turn-on” trajectories of the state variables x1 and x2 are shown in Fig-

ure 3.9 for different ksync values. Zero initial conditions are assumed in each case. From

the two plots, several observations can be extracted. First, the final state trajectories are

identical circles proving that x1 and x2 are sinusoidal functions with 90 ◦ phase difference.

Second, the radius of the circle equals to the magnitude of the grid voltage indicating

that both sinusoidal functions have an amplitude that equals to the magnitude of the

grid voltage. This effectively proves that the grid estimator resembles the fundamental

component of the grid voltage and emulates an orthogonal component with the same

magnitude. Third, with the initial conditions of states x1 and x2 equal to zero, the plot

with the larger ksync has a faster speed to reach the final trajectory.

Furthermore, we investigate how well the grid estimator responses to inputs that

contain both harmonics and a frequency variation. Figure 3.10 shows the time domain

simulation based on the worst case conditions on the frequency variations of the grid

provided by IEEE-1547 standard [1] and the percentage voltage harmonics on the grid

provided by IEEE-519 standard [38]. According to IEEE-519, the worst case harmonics

that would appear on the grid voltage is 3% of the fundamental voltage at each harmonic,

with a total harmonic distortion (THD) of 5%. The worst grid frequency is 59.3Hz

according to IEEE-1547.


−80

−70

−60

−50

−40

−30

−20

−10

0

Mag

nitu

de (d

B)

100 101 102 103 104 105−90

−45

0

45

90

Pha

se (d

eg)

Bode Diagram

Frequency (rad/sec)

Ksync=100Ksync=300Ksync=500Ksync=1000

(a) bode plot ofVg‖(jω)

Vg(jω)

−100

−80

−60

−40

−20

0

20

Mag

nitu

de (d

B)

100 101 102 103 104 1050

45

90

135

180

Pha

se (d

eg)

Bode Diagram

Frequency (rad/sec)

Ksync=100Ksync=300Ksync=500Ksync=1000

(b) bode plot ofVg⊥(jω)Vg(jω)

Figure 3.8: Bode plot ofVg‖(jω)Vg(jω)

andVg⊥(jω)

Vg(jω)


x2

x1

gV

(a) Turn on trajectory when ksync=200

x2

x1

gV

(b) Turn on trajectory when ksync=600

Figure 3.9: Turn on trajectory of the estimator’s state variables with different ksync values

Normally, the harmonics that appeared on the grid voltage are predominately low

order odd harmonics due to thyristor bridges and diode rectifiers in the system. The

harmonics that are multiple of three are mainly trapped inside the delta connection

of distribution transformers so that they are not presented in the local grid. There-

fore, the predominate harmonics that appeared on the local grid are in the order of

5th, 7th, 11th, 13th.... The simulation takes the worst case percentage of harmonics from

the lowest order and add them up until the worst case THD is reached. Based on this,

the simulation uses a 3% of each harmonic of 5th, 7th and 11th order so that they add up

to have a THD of 5% on the grid voltage. The worst case grid fundamental frequency of

59.3Hz is used in this simulation. ksync = 200 is used for the grid voltage estimator.

While Figure 3.10 illustrates the turn on transition of each state variables of the

estimator in time domain, Figure 3.11 shows the zoomed-in version of the results which

contain the distorted grid voltage, the desired x1 and x2 waveform and the resulting x1

and x2 from the grid estimator.

Finally, given the grid voltage estimator’s internal oscillator’s frequency ωo is 377rads/s


0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−400

−300

−200

−100

0

100

200

300

400x1vg

(a) Time domain response of x1 vs. vg(t)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−400

−300

−200

−100

0

100

200

300

400vgx2

(b) Time domain response of x2 vs. vg(t)

Figure 3.10: Time domain response of the estimator’s state variables

(60Hz), the power factors of the inverter at different grid frequencies are shown in Fig-

ure 3.12 for different ksync values neglecting switching harmonics and assuming the reac-

tive power compensation feature of the inverter is turned off. One can observe that as

ksync gets larger, the more consistent that the power factors become over a certain range

of frequencies.

3.2.2 Grid Voltage Amplitude Identifier

A grid voltage amplitude identifier is needed to determine the amplitude of the grid

voltage. It has a form of the following:


0.114 0.116 0.118 0.12 0.122 0.124 0.126 0.128 0.13−400

−300

−200

−100

0

100

200

300

400Vgx1(desired)

(a) Desired x1 vs. vg(t)

0.114 0.116 0.118 0.12 0.122 0.124 0.126 0.128 0.13−400

−300

−200

−100

0

100

200

300

400x1x1(desired)

(b) Desired x1 vs. x1

0.126 0.128 0.13 0.132 0.134 0.136 0.138 0.14 0.142 0.144−400

−300

−200

−100

0

100

200

300

400Vgx2(desired)

(c) Desired x2 vs. vg(t)

0.128 0.13 0.132 0.134 0.136 0.138 0.14 0.142−400

−300

−200

−100

0

100

200

300

400x2x2(desired)

(d) Desired x2 vs. x2

Figure 3.11: Zoomed in time domain response of the distorted grid voltage vg(t), the

estimator’s output and its desired values


50 52 54 56 58 60 62 64 66 68 70

0.85

0.9

0.95

1

1.05

Freqeuncy (Hz)

Pow

er F

acto

r (P

F)

Ksync=200

Ksync=300

Ksync=500

Ksync=1000

Figure 3.12: Power factors vs. grid frequencies for Q=0 while neglecting switching har-

monics

Vg =√v2g‖ + v2g⊥ (3.12)

Equivalently, we may also write Vg =√x21 + x2

2 which is graphically displayed in the

transient state plane plot of Figure 3.9.

Other options of implementing the amplitude identifier may include peak detection

for the grid voltage or peak detection for either output of the grid voltage estimator. Both

methods avoid using the square root operand, the latter one is more preferred because

the grid voltage estimator filters out the harmonic distortions that appeared on the grid

voltage so that the peak detection for the output of the estimator is more accurate than

for the grid voltage itself.


3.2.3 Synchronized Current Reference Creation

Once the vg‖ and vg⊥ are obtained from the grid voltage estimator, and Vg is obtained

from the amplitude identifier, the control of the phase of the synchronized current refer-

ence becomes possible. Therefore, given the grid reference current’s parallel and orthog-

onal components, irefg‖ and irefg⊥ , a synchronized current reference signal can be obtained

by the following equation:

irefg =irefg‖ vg‖ + irefg⊥ vg⊥

Vg

(3.13)

Since the parallel component of the current reference irefg‖ is aligned with the grid

voltage, this part of the current then controls the active power flow to the grid. On the

other hand, since the orthogonal component of the current reference irefg⊥ is 90 ◦ leading

the grid voltage, this part of the current controls the reactive power flow to the grid.

Therefore, the input irefg‖ and irefg⊥ are the input control commands for the active and

reactive power.

3.2.4 Discussion of the Proposed Grid Synchronization Method

The proposed grid synchronization method is advantageous in two major ways. Firstly,

comparing with the conventional method of single phase grid synchronization method

as discussed in [30] where vg(t) is simply duplicated for parallel synchronization, the

proposed grid synchronizer not only reproduces a filtered signal that is in phase with

grid voltage, but also emulates an orthogonal component of the grid voltage, which can

be used to generate reactive power reference to the inverter. Therefore, the inverter

gains the ability of controlling the reactive power flow comparing to the conventional

PV inverters that only transfer active power due to their inability of reproducing an

orthogonal component of the current reference.

Secondly, other systems [32] [33] [34] which uses a synchronous frame PLL to lock


on the phase of the grid voltage would need zero voltage crossing detection to reset the

integrator and the d-q transformations used which would need sin and cos calculations.

Both actions increase the complexity of the implementing the synchronizer in a digital

processor. On the other hand, the proposed grid synchronizer only uses a two by two

state matrix and a two by two output matrix to generate the parallel component and the

orthogonal component. This method therefore lowers the computational burden of the

digital processor significantly.

The down side of the synchronization method is that since the grid estimator has

a fixed oscillator frequency ωo, exposure to large frequency variation would result in

undesirable power factor downgrade (refer to Figure 3.12). Although increasing ksync

would minimize the effect, the noise suppression ability of the estimator would be hurt.

Another down side of the grid synchronization method is its need of a square root

calculation in the amplitude identifier, which could increase the processing time of the

digital processor. Fortunately, the fast fixed point square root algorithm can be used

in this case which significantly increase the processing speed of square root calculation.

Other viable options such as peak detection on the output of the estimator would avoid

the square root calculation, therefore can be used as a substitute.

Finally, a ksync = 200 is used in the PSCAD/EMTDC simulation and the prototype

designed in the lab. This selection of ksync is more focused on noise suppression than

immunity to frequency variation because the grid frequency can be set exactly in 60Hz

in PSCAD/EMTDC simulation, and the grid frequency in the lab is well regulated at

60Hz with a maximum variation less than 0.5Hz.

3.3 Voltage Controller

The DC-link voltage can be regulated by a closed loop voltage controller. Figure 3.13 is

a simplified power stage diagram which is used to analyze the DC voltage behaviour.


+

-vdc(t)

ig(t)

LgLiCf

Rd

Hvt(t)

vg(t)Cdc

idc(t)

Figure 3.13: Inverter power stage diagram

3.3.1 Voltage Loop Modelling

The differential equation on the DC side is:

Cdcdvdc(t)

dt= idc(t) (3.14)

Again, idc(t) consists of two components, a DC component, Idc and a double-line

frequency AC component, idc,ripple(t). Both of them can be obtained from the power

balance equation:

vdc(t)idc(t) = Vgcos(ωgt)Igcos(ωgt− φ) (3.15)

vdc(t)Idc + vdc(t)idc,ripple(t) =Vg Ig2

cosφ+Vg Ig2

cos(2ωgt− φ) (3.16)

From equation (3.16), the two components of the DC current can be expressed as:

Idc =Vg

2vdc(t)Igcosφ =

V rmsg√2vdc(t)

Igcosφ (3.17)

idc,ripple(t) =Vg Igcos(2ωgt− φ)

2vdc(t)(3.18)

Since we align the parallel component of the current reference signal with the grid

voltage using a grid synchronization function block, the grid current ig(t) has its parallel

component aligned with the grid voltage as shown in the phasor digram in Figure 3.14.


Im

||gI

gI

Re⌀

gI

gV

Figure 3.14: Phasor diagram of ig and its two components

Therefore, Equation (3.17) can be rewritten to be

Idc =V rmsg√2vdc(t)

Ig‖ (3.19)

Then, we linearize these parameters to about the nominal grid voltage V ng and nominal

DC voltage V ndc:

Idc =V ng√2V n

dc

Ig‖ (3.20)

Then, the complete model of the voltage loop can be drawn and is shown in Fig-

ure 3.15.

A notch filter, Hn(s), has a form of Equation (3.21) is applied to the voltage loop

to filter out the double-line frequency current ripple component idc,ripple(t) because the

double-line frequency ripple current produces a double-line frequency ripple voltage on

the DC-link. This is undesirable because this ripple signal would couple through the

voltage controller and cause undesirable high frequency component would appear on the

current reference signal of the current control loop, Figure 3.16. (Note: A, B, C, D, E,

F in the figure are constant numbers)

Hnotch =s2 + 2ζ1ωns+ ω2

n

s2 + 2ζ2ωns+ ω2n

(3.21)


Gv(s)ig||

ref

Gc(s)ig

ref ig

ndc

ng

VV2

Hn(s)dcsC

1 idcvdc

vdcfil

Vdcref +

-

Current Loop

Notch Filter

GridSynchronizationVoltage

Compensator

||||ˆgg Ii

Grid de-synchronization

g

g

Vvˆ

||

||

ˆ

g

g

vV

Figure 3.15: Voltage loop of the inverter

Vdcn+vdc,ripple(t)

Vdcref

+

-DC voltagecompensator

C+Dcos(2wgt)

Gridsychronization

vg(t)

refgi ||

igref

A+Bcos(2wgt) Ecos(wgt)+Fcos(wgt)cos(2wgt)

Grid currentcontrol loop

Undesired!

ig

Figure 3.16: Effect of the double-line frequency ripple on the current reference signal

where ωn is twice the fundamental frequency, ζ1 is chosen to be 0.008 and ζ2 is chosen

to be 1.

The “current synchronization” block in the diagram is the part that the parallel

current reference, which is generated from the voltage controller, is converted to a grid

synchronized sinusoidal signal which is discussed in Section 3.2.

The current loop, Gc(s) has a form of:

Gc(s) =Gi(s)Gf(s)

Gi(s)Gf(s)− 1(3.22)

where Gi(s) is the PR controller from the current loop and Gf(s) is the plant model


derived in Equation (3.2).

The gird de-synchronization block |Vg|Vg‖

is used to extract the current that is equivalent

to the parallel current reference irefg‖ generated from the voltage controller. The output

of this block is denoted as ig‖, and it equals to the peak value of the parallel component

of the grid current Ig‖. This block works like an “inverse d-q transform”, except it is in

a single phase system instead of a three phase system.

3.3.2 DC Voltage Compensator

A simple PI controller is used as the DC voltage loop compensator, which has the form

of:

Gv(s) = Kvp +

Kvi

s(3.23)

The uncompensated loop gain and the compensated loop gain of this voltage feedback

loop is shown in Figure 3.17. A selection of Kvp = 0.1 and Kv

i = 1 yields a phase margin

of 60 ◦ in the compensated loop as shown in Figure3.17(b)

3.4 Digital Implementation of the Controller

A 32-bit fixed point Microchip PIC microcontroller (MCU) was used to implement the

controller. This microcontroller is a relatively low cost choice comparing to other floating

point microcontrollers. Although floating point calculations can be done in this PIC

MCU, it was finally concluded that such computations consume excessive computational

time. Therefore, fixed point calculations must be performed and trigonometry (i.e. sin

and cos) calculations must be avoided. As a result, the digital controller was written in a

per-unitized system using a fixed number format. All the s-domain controller functions

are transfered into the digital domain using the bilinear transform.


−150

−100

−50

0

50

Mag

nitu

de (d

B)

101 102 103 104 105 106−180

−135

−90

−45

0

Pha

se (d

eg)

Bode DiagramGm = Inf , Pm = 18.5 deg (at 558 rad/sec)

Frequency (rad/sec)

(a) Uncompensated voltage loop gain

−200

−150

−100

−50

0

50

100

150

200

Mag

nitu

de (d

B)

10−1 100 101 102 103 104 105 106−180

−135

−90

−45

0

Pha

se (d

eg)

Bode DiagramGm = −Inf dB (at 0 rad/sec) , Pm = 61 deg (at 173 rad/sec)

Frequency (rad/sec)

(b) Compensated voltage loop gain

Figure 3.17: Bode plot of the uncompensated and compensated voltage loop gain


3.4.1 Switching Frequency Consideration

For the design of a MOSFET based inverter, the switching frequency is primarily limited

by the switching loss and the reverse recovery loss of the body diodes. Another limiting

factor to the switching frequency of a DC/AC inverter is the CPU performance of the

digital controller. In our case, the PWM output compare registers have to be updated at

the very beginning of each switching cycle. This means the inverter control computations

have to be finished in one switching cycle. Therefore, the CPU speed and the complexity

of the controller implementation algorithm directly limits the switching frequency of the

inverter. Based on the experimental result, a switching frequency of 30kHz would give

sufficient time for the CPU to finish the controller computation. This chosen switching

frequency would also not introduce excessive losses on the MOSFET switches.

3.4.2 Per-unitize and Fixed Number Format

Inside the digital controller, all the system parameters such as voltages and currents

were per-unitized to their base values, which are normally chosen to be the system rated

values. Then, they were scaled to a fixed number format (e.g. 4.12 format) for fixed point

calculations. For example, a voltage quantity, V being expressed into a 4.12 format and

per-unitized based on Vbase would be:

V p.u4.12 =

V · 212Vbase

(3.24)

Chapter 4

PSCAD/EMTDC Simulation

Results

This chapter shows the PSCAD/EMTDC simulation results of the grid connected in-

verter. The current controller and the voltage controller were simulated separately to

validate each controller. The validation of the grid synchronizer is also shown in the

simulation. Table 4.1 shows the power stage parameters used in the simulation.

In the last chapter, the grid current ig(t) that is used in the control loop has a direction

flowing from the grid to the inverter. In this chapter and Chapter 5, in order to illustrate

the resulting current flowing from the inverter into the grid, ign(t) is used for the grid

current pointing toward the grid from now on.

4.1 Inverter Current Loop Simulation

Figure 4.1 shows the PSCAD/EMTDC simulation setup for the current loop of the

DC/AC inverter. The DC-link capacitor is replaced with a fixed DC voltage source.

irefg‖ and irefg⊥ are the input commands to the controller loop which control the amount of

active and reactive power being generated.

The performance of the grid voltage estimator is shown in Figure 4.2. The estimator’s

49

Chapter 4. PSCAD/EMTDC Simulation Results 50

Grid nominal voltage V ng 250V (RMS)

DC-link nominal voltage V ndc 400V (RMS)

Bridge side inductor Li 300μH

Grid side inductor Lg 100μH

Filter capacitor Cf 30μF

Filter damping resistor Rd 1.5Ω

Switching frequency fsw 30kHz

Table 4.1: Inverter current loop simulation power stage parameters

outputs are shown with their desired values. Since the grid voltage used in the simulation

is a perfect sinusoidal wave with 60Hz, the estimator’s outputs are perfectly aligned with

their desired values in steady state.

Vg(t)LgLi

Cf

Rd

+

-

sa sb

salow sb

low

vdc

refgi || Grid

Synchronization

refgi

refgi

Gi(s)

vg ig

+- ei

Current ControllerGridSynchronization

SPWM

vrefa

vrefb

sa salow sb

)(1tvdc

*-1

DCvoltage

feedward

ig(t)ign(t)

vt(t)

sblow

Figure 4.1: Inverter current loop simulation setup


||gv

gv

vg

gvdesired

(a) Start-up transisient

||gv

gv

vg

gvdesired

(b) Zoomed in result

Figure 4.2: PSCAD/EMTDC simulation result of the grid voltage estimator’s outputs

and their desired values

4.1.1 Steady State Response

The steady state response of the current loop simulation results are shown in Figure 4.3.

Simulation is done for the inverter output grid current ign(t) being regulated at 10A

(RMS). Three different sub-figures are used to show that the inverter’s output grid current

ign(t) and the grid voltage are in phase (Figure 4.3(a)), off phase by 90 ◦ (Figure 4.3(b))

and 45 ◦ off phase (Figure 4.3(c)) . Table 4.2 shows the measured average active power

and reactive power in each case from the P,Q meter of PSCAD/EMTDC to prove that

the inverter is capable of transferring pure active power, pure reactive power and both.

Figure 4.3(a) Figure 4.3(b) Figure 4.3(c)

Measured active power (kW) 2.5 0 1.767

Measured reactive power (kVar) 0 2.5 1.767

Table 4.2: Active and reactive power measurement of the current loop simulation


(a) Grid current and voltage are in phase (b) Grid current lags the voltage by 90 ◦

(c) Grid current lags the voltage by 45 ◦

Figure 4.3: Steady state response of the current loop simulation

4.1.2 Transient Response

The transient response of the current loop simulation results are shown in Figure 4.4

for the output grid current steps up from 0A to 10A (RMS). Simulations are done in

two different circumstances where in Figure 4.4(a), the current is in phase with the grid

voltage and in Figure 4.4(b), the current lags 90 ◦ the grid voltage.

The grid voltage vg(t), inverter output current ign(t) and the current input command

irefg‖ and irefg⊥ are shown from top to bottom of each sub-figure. It can be observed that

the current step response has a settling time less than 2ms and a percentage overshoot

that is less than 30%.



Figure 4.4: Step response of the current loop simulation

4.2 Inverter Voltage Loop Simulation

Figure 4.5 is the PSCAD/EMTDC setup for the voltage loop simulation, the DC current

source is intended to emulate a front-end DC-DC converter which is capable of feeding

constant current or constant power into the DC link. In the control loop, the voltage

controller is added such that the DC-link voltage is regulated by the feedback loop. Unlike

the current loop simulation, irefg‖ is now the output of the voltage controller instead of an

input command. irefg⊥ is still a input command that has the ability to control the reactive

power flow.

4.2.1 Steady State Response

The steady state response of the voltage loop simulation results are shown in Figure 4.6.

Simulation is done for the inverter outputting a grid current of 10A (RMS). The DC-

link voltage vdc(t), grid voltage vg(t) and the output grid current ign(t) are shown from

top to bottom of each sub-figure. Three different sub-figures are used to show that the

inverter’s output grid current ign(t) and the grid voltage are in phase (Figure 4.6(a)),

off phase by 90 ◦ (Figure 4.6(b)) and 45 ◦ off phase (Figure 4.6(c)). Table 4.3 shows the


vg(t)

+

-

ig(t)LgLi

Cf

Rd

+

-

sa sb

salow sb

low

idc(t)

Vdcref Gv(s)

Notch Filter

vdcfil

+

-

ev

refgi || Grid

Synchronization

refgi

refgi

Gi(s)

vdc

vg(t) ig

+- ei

Voltage Controller

Current ControllerGrid

Synchronization

Cdc

SPWM

vrefa

vrefb

sa salow sb sb

low

)(1tvdc

*-1

ign(t)vdc(t) vt(t)

DCvoltage

feedward

Iin

Figure 4.5: Inverter voltage loop simulation setup

Figure 4.6(a) Figure 4.6(b) Figure 4.6(c)

Measured active power (kW) 2.5 0 1.766

Measured reactive power (kVar) 0 2.5 1.767

Table 4.3: Active and reactive power measurement of the voltage loop simulation

measured average active power and reactive power in each case from the P,Q meter of

PSCAD/EMTDC to prove that the inverter is capable of transferring pure active power,

pure reactive power and both.

In addition, the TDDs are measured for the output grid current in the entire current

operating range when the when the inverter is running pure real power, Figure 4.7(a),

and pure reactive power, Figure 4.7(b). One can observe that the grid current TDD is

far below the 5% threshold stated in IEEE-1547/IEEE-5191.

1IEEE-1547 directly references the grid current harmonic distortion limits for general distributionsystems stated in IEEE-519



(c) Grid current lags the voltage by 45 ◦

Figure 4.6: Steady state response of the current loop simulation

4.2.2 Transient Response

Figure 4.8 shows the step response of the system when the DC-link voltage reference

steps up from 400V to 440V. Figure 4.8(a) is based on when the constant DC current

source is disconnect and the reactive power command irefg⊥ is set to be 0A. It can be seen

that when the voltage reference signal requests a step change, the grid output current

has to reverse to supply current to charge the DC-link capacitor to the desired voltage

level.

Figure 4.8(b) is based on when the constant DC-current source is disconnected and


0 1 2 3 4 5 6 7 8 9 100

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

ign(A),90 inphase

TDD

(%)

(a) Grid current and voltage are in phase

0 1 2 3 4 5 6 7 8 9 100

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

ign(A),90 lag

TDD

(%)

(b) Grid current lags the voltage by 90 ◦

Figure 4.7: TDD vs. ign when running pure real power and reactive power for voltage

loop simulation

the reactive power command irefg⊥ is set to be 10A (RMS) so that the inverter is supplying

pure reactive power. It can be seen that the DC-link voltage step causes little impact

on the output current ign(t) when the inverter is supplying pure reactive power. This

is because the voltage loop only depends on the “parallel axis” so that the active power

should have the full impact on the DC-link voltage whereas the reactive power should

have minimum impact. Both DC-link voltage step response has a settling time less than

20ms and a percentage overshoot less than 30%.

The input current step response is simulated based on the DC input current step

change from 0 to 10A (RMS), Figure 4.9(a). The reactive power step response is simulated

based on the irefg⊥ step change from 0 to 10A (RMS), Figure 4.9(b). It can be seen that

the irefg⊥ step change has little impact on the DC-link voltage than the input current step

change. This is because the voltage loop control is decoupled from the “orthogonal axis”.


(a) Grid current is 0A (b) Grid current lags the voltage by 90 ◦

Figure 4.8: Voltage loop simulation based on the DC-link voltage step change

(a) DC input current step change (b) irefg⊥ step change

Figure 4.9: Step response of the voltage loop simulation based on the DC input current

step change and irefg⊥ step change

Chapter 5

Inverter Experimental Results

This chapter shows the inverter’s experimental results. A prototype was built based on

the inverter specification. The inverter’s controller is implemented fully on a 32bits fixed

point PIC32MX340F256H microcontroller. Voltage and current signals are sampled using

the internal 10-bit analog-to-digital converter inside the microcontroller. The output

compare module of the microcontroller allows the modulation signal to be compared

with an internal timer signal to resemble a SPWM function block.

In the experimental setup, a DC voltage source which has a greater magnitude than

the regulated DC-link voltage is connected at the DC-link capacitor through a variable

resistor so that the DC-link gets roughly a constant current from the DC source. This is

used to emulate the front end DC/DC converter in the PV system. A transformer and a

variac are connected at the AC grid end to provide isolation and AC voltage adjustability.

The experimental setup is shown in Figure 5.1.

5.1 Steady State Operation

Figure 5.2 shows the steady state operating DC-link voltage vdc(t), grid voltage vg(t), and

the grid output current ign(t). Due to the limiting voltage level and current limit of the

DC power supply available in the lab, the inverter’s grid voltage is downgraded to 60V

58

Chapter 5. Inverter Experimental Results 59

vg(t)+

-

LgLiCf

Rd

+

-Vt

sa sb

salow sb

low

CdcVin

Rin

1:1

. .vdc(t)

ig(t) ign(t)

Sin

Figure 5.1: Inverter experimental setup

(RMS). Therefore, in this section, the inverter is running 600VA with V ndc=140V, vg=60V

(RMS), ign=10A (RMS) and the grid frequency of 60Hz. The three sub-figures illustrate

when the inverter is outputting pure real power, pure reactive power with 90 ◦ lagging

power factor, and the mix with real and reactive power with 0.8 lagging power factor.

Table 5.1 is a summary of the measured power factor, output current TDD in each case.

It can be seen that the power factor in each case is very close to expected values and

the TDD is under 5% which is under the limit of IEEE-1547/IEEE-519 standard1. This

set of experimental results demonstrate the inverter’s ability of controlling the reactive

power flow. Furthermore, it can also be seen that with a fairly large double line frequency

voltage ripple presented on the DC-link, the output gird current is hardly distorted. This

proves the effectiveness of the notch filter in the voltage control loop.

Theoretical power factor measured power factor TDD (%)

1.0 (Figure 5.2(a)) 0.99 2.73

0 lagging (Figure 5.2(b)) 0.01 lagging 2.26

0.8 lagging (Figure 5.2(c)) 0.79 lagging 2.36

Table 5.1: Summary of measured power factor and TDD

Furthermore, Figure 5.3 shows the amount of output grid current TDD in the entire



vdc(t)

vg(t)

ign(t)

(a) Grid current is in phase with the voltage

vdc(t)

vg(t)

ign(t)


vdc(t)

vg(t)

ign(t)

(c) Grid current lags the voltage by 36.8 ◦ (PF=0.8, lag-

ging)

Figure 5.2: Steady state operation of the inverter. From top to bottom: DC-link voltage

V ndc=140V on CH1 at 50V/Div, grid voltage vg=60V(RMS) on CH4 at 100V/Div and

output current ig=10A (RMS) on CH3 at 20A/Div. Time scale 5ms/Div


0 1 2 3 4 5 6 7 8 9 100

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

ign(A),in phase

TDD

(%)

(a) TDD(%) vs. ign where ign is in phase with Vg

0 1 2 3 4 5 6 7 8 9 100

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

ign(A), 90degree lagging

TDD

(%)

(b) TDD(%) vs. ign where ign is 90 ◦ lags Vg

Figure 5.3: TDD vs. ign when running pure real power and reactive power

current operating range when the inverter is running pure real power, Figure 5.3(a), and

pure reactive power, Figure 5.3(b). In the PSCAD/EMTDC simulation, the TDD in the

entire current operating range is much smaller as compared to the experimental results.

This is because the harmonic distortions that appeared in the experimental results are

mainly caused by the grid voltage low frequency distortions. IEEE-1547 states that the

harmonics current injection shall be exclusive to the grid voltage harmonic distortions, so

the extra percent of harmonic distortions shown in the experimental results is acceptable.

Besides, the amount of TDD in the entire current operating range of this inverter is still

less than 5% threshold stated in IEEE-1547/IEEE-5191.

5.2 Transient Response

The transient response of the inverter is tested through the step change of the DC-link

voltage, input current and the reactive power controlling command irefg⊥ .

Figure 5.4 shows the transient response of the inverter when the DC-link voltage

steps up from 120V to 140V. Figure 5.4(a) is when the grid current is 0A. Figure 5.4(b)

is when the grid current is at 7A, 90 ◦ lagging the grid voltage. The DC voltage transient

response demonstrates good system dynamics where the DC-link voltage settling time is


around 20ms and the percentage overshoot is less than 30% in each case. The result is

similar to the simulation result of the voltage step response, where the DC-link voltage

settling time is around 20ms and the percentage overshoot is less than 30%.

Figure 5.5(a) shows the step response of the input power to the DC-link. This exper-

iment is done by closing the switch (Sin in Figure 5.1) between the DC voltage power

supply and the DC-link after the DC-link has been regulated at 140V. This action enables

an input current step change. The long settling time of the DC-link voltage is expected

because at the transients, the input current cannot be kept at a constant value due to

the interaction between the fixed DC voltage of the DC power supply and the transient

that happens at the DC-link voltage.

Figure 5.5(b) shows the step response of the inverter when the reactive power con-

trolling command irefg⊥ steps up from 0A to 10A (RMS) and the DC-link voltage is kept

at constant 140V. The settling time of the current step is less than 2ms and the percent-

age overshoot is around 30%. As comparing to the input power step response shown in

Figure 5.5(a), this response of the irefg⊥ step change demonstrate good decoupling of the

“parallel” and “orthogonal” axis of the controller as the step change in irefg⊥ causes little

impact on the DC-link voltage.

The transient responses of the inverter have the same behaviour as they are shown in

the simulation section. For the step response in DC-link voltage, both PSCAD/EMTDC

simulation and lab experiment show good system dynamics, where a settling time of 20ms

and a percentage overshoot that is less than 30% are achieved. For the step response in

irefg⊥ , both PSCAD/EMTDC simulation and lab experiment show a good decoupling of

the “parallel axis” and the “orthogonal axis”.


vdc(t)

vg(t)

ign(t)

(a) Grid current ign is 0A

vdc(t)

vg(t)

ign(t)


Figure 5.4: DC-link voltage step response of the inverter. (a) From top to bottom:

DC-link voltage vdc(t) on CH1 at 10V/Div, grid voltage vg(t) on CH4 at 100V/Div and

output current ign on CH3 at 2A/Div. Time scale 20ms/Div. (b) From top to bottom:

DC-link voltage vdc(t) on CH1 at 50V/Div, grid voltage vg(t) on CH4 at 100V/Div and

output current ign(t) on CH3 at 10A/Div. Time scale 20ms/Div


vdc(t)

vg(t)

ign(t)

(a) input power step response of the inverter

vdc(t)

vg(t)

ign(t)

(b) irefg⊥ step response of the inverter

Figure 5.5: Input power step change and irefg⊥ step change response of the inverter. (a)

from top to bottom: DC-link voltage vdc(t) on CH1 at 50V/Div, grid voltage vg(t) on

CH4 at 100V/Div and output current ign(t) on CH3 at 10A/Div, time scale 10ms/Div.

(b) from top to bottom: DC-link voltage vdc(t) on CH1 at 50V/Div, grid voltage vg(t) on

CH4 at 100V/Div and output current ign(t) on CH3 at 5A/Div, time scale 100ms/Div

Chapter 6

Conclusion and Future Work

6.1 Conclusion

This research presented a single phase grid connected DC/AC inverter with reactive

power (VAR) control for residential PV application. It was shown that residential PV

power generation has garnered much attention in today’s demand for renewable energy.

Grid interconnection standards such as IEEE-1547 are used to regulate the power quality

of the local DR power injection. As a consequence, single phase, low power VSI’s are

commonly used for the interconnection between PV modules and the utility grid to ensure

that the power quality meets grid standard. Furthermore, as more distributed resources

such as local PV generation is integrated into the grid at the distribution level, the trend

that the DR units actively supply reactive power to the grid has appeared. Therefore,

this work proposed a solution for the VSI to actively control the reactive power injecting

to the grid. This leads to the main contribution of this work, which is the design of a low

complexity grid synchronization method that does not rely on use of high performance

control platforms for creating parallel and orthogonal component of the grid voltage in

order to control the real and reactive power flow. The synchronization method inherently

attenuates grid distortion and is immune to slight grid frequency variations. Meanwhile,

65

Chapter 6. Conclusion and Future Work 66

due to the manufactures’ guarantee on the life time of PV inverters, the VSI was designed

to use a small, more reliable, film type capacitor on the DC-link in a cost effective way

while maintaining a good output power quality.

Simulations were performed on PSCAD/EMTDC platform and a prototype was also

developed in the lab to prove the effectiveness of the controller and the grid synchroniza-

tion method. A PR compensator and a PI compensator were used in the current control

loop and the voltage control loop respectively. It was shown that the resulting phase

difference between the gird current and the voltage are very close to the expected values,

which proves the inverter’s ability of controlling reactive power flow. Furthermore, with a

small value film type capacitor being place on the DC-link, the notch filter in the voltage

control loop was be able to average out the large double-line frequency voltage ripple

that appeared on the DC-link, so that the output grid current stayed unaffected by the

DC-link double-line frequency voltage ripple. As a result, the total demand distortion of

the grid current stayed under 5 % which is acceptable by the IEEE-1547 grid intercon-

nection standard1. The system outputs, ign(t) and vdc(t) also show acceptable behaviours

during transient responses in terms of percentage overshoot and settling time.

6.2 Future Work

The future work of this research can extend to design the front end DC/DC converter

so that a two stage PV inverter system can be built for the analysis of the inverter’s

response when it is connected to a power source that is generated from the PV modules

instead of a constant DC current source that is used in the lab.

This research furthermore opens up the topic of actively exchanging reactive power

with the utility grid at the distribution level. The control and communication methods

between these type of local DRs and the central dispatch would be a useful area of study.


Appendix A

IEEE-1547 Standard on Harmonic

Current Injection

1

“When the DR is serving balanced linear loads, harmonic current injection into the

Area Electrical Power System (EPS) at the PCC shall not exceed the limits stated below

in Table A.1. The harmonic current injections shall be exclusive of any harmonic currents

due to harmonic voltage distortion present in the Area EPS without the DR connected.”

Table A.1: Maximum harmonic current distortion in percent of current(I)a

Individual Total

harmonic h < 11 11 ≤ h < 17 17 ≤ h < 23 23 ≤ h < 35 35 ≤ h demand

order h distortion

(odd harmonics)b (TDD)

Percent (%) 4.0 2.0 1.5 0.6 0.3 5.0

aI=the DR unit rated current capacity

bEven harmonics are limited to 25% of the odd harmonic limits above


67

Appendix B

PR Controller Behaviour

The PR controller’s behaviour were studied by looking at the bode plots when changing

each parameter. Again, the transfer function of an non-ideal PR controller is:

Gi(s) = Kcp +

Kci s

s2 + 2ζωos+ ω2o

(B.1)

Figure B.1(a) shows the frequency response of the PR controller when Kci changes

from 1 to 1000, with one decade interval. Kcp is set to be 0, ζ is set to be 0.001. As shown

in the plot, with Kci increases, the gain of the controller increases whereas the bandwidth

stays constant.

Figure B.1(b) shows the frequency response of the PR controller when ζ changes from

0.001 to 1, with one decade interval. Kcp is set to be 0, Ki is set to be 1. As shown in the

plot, with ζ increases, the peaking of the magnitude at the resonant frequency decreases.

Figure B.1(c) shows the frequency response of the PR controller when Kcp changes

from 1 to 1000, with one decade interval. Kci is set to be 1000, ζ is set to be 0.001. As

shown in the plot, with Kcp increases, the magnitude at all frequencies increases but the

bandwidth of the controller got reduced and the phase amplitude decreases.

68

Appendix B. PR Controller Behaviour 69

−100

−50

0

50

100

Mag

nitu

de (d

B)

101 102 103 104−90

−45

0

45

90

Pha

se (d

eg)

Bode Diagram

Frequency (rad/sec)

Ki=1Ki=10Ki=100Ki=1000

(a) Frequency response when Kci changes

−100

−80

−60

−40

−20

0

20

Mag

nitu

de (d

B)

101 102 103 104−90

−45

0

45

90

Pha

se (d

eg)

Bode Diagram

Frequency (rad/sec)

ζ=0.001ζ=0.01ζ=0.1ζ=1

(b) Frequency response when ζ changes

0

10

20

30

40

50

60

70

80

Mag

nitu

de (d

B)

100 101 102 103 104 105−90

−45

0

45

90

Pha

se (d

eg)

Bode Diagram

Frequency (rad/sec)

Kp=1Kp=10Kp=100Kp=1000

(c) Frequency response when Kcp changes

Figure B.1: Frequency response of the PR controller with each parameter changes

Appendix C

Harmonics Table for Switch Mode

Inverters

��h

ma0.2 0.4 0.6 0.8 1.0

Fundamental 0.2 0.4 0.6 0.8 1.0

mf 1.242 1.15 1.006 0.818 0.601

mf ± 2 0.016 0.0061 0.131 0.220 0.318

mf ± 4 0.018

2mf ± 1 0.190 0.326 0.370 0.341 0.181

2mf ± 3 0.024 0.071 0.139 0.212

2mf ± 5 0.013 0.033

3mf 0.335 0.123 0.083 0.171 0.113

3mf ± 1 0.044 0.139 0.203 0.176 0.062

3mf ± 3 0.012 0.047 0.104 0.157

3mf ± 5 0.016 0.044

4mf ± 1 0.163 0.157 0.008 0.105 0.068

4mf ± 3 0.012 0.070 0.132 0.115 0.009

4mf ± 5 0.034 0.084 0.119

4mf ± 7 0.017 0.050

Table C.1: Generalized harmonics of VAo for a large mf

70

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Documents

A Single Phase Grid Connected DC/AC Inverter with Reactive Power Control for Residential PV