A Si-Compatible Fabrication Process for Scaled Self-Aligned

InGaAs FinFETs

Alon Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao and Jesús A. del Alamo

Microsystems Technology Laboratories, MITMay 23, 2017

Sponsors: DTRA (HDTRA 1‐14‐1‐0057), NSF E3S STC (grant #0939514) Lam Research

Outline• Motivation• Process technology• Electrical characteristics• Late news• Conclusions

2

3

Historical evolution: InGaAs High-Electron Mobility Transistor

Transconductance (gm=dID/dVGS):

• Superior electron transport properties in InGaAs

High-Electron Mobility Transistor

4

InGaAs MOSFETs vs. HEMTs

Transconductance (gm=dID/dVGS):

• Superior electron transport properties in InGaAs

High-Electron Mobility Transistor

Metal-Oxide-SemiconductorField-Effect Transistor

5

InGaAs MOSFETs vs. HEMTs

Lin, EDL 2016

gm=3.45 mS/μm

Transconductance (gm=dID/dVGS):

• Superior electron transport properties in InGaAs• InGaAs planar MOSFET performance exceeds that of High Electron 

Mobility Transistors (HEMT) 

What happened here?

High-Electron Mobility Transistor

Metal-Oxide-SemiconductorField-Effect Transistor

6

Huang, APL 2005

ALD eliminates residual native oxides that pin Fermi level

“Self cleaning”

Clean, smooth interface without native oxides

Atomic Layer Deposition (ALD)of gate oxide

• First with Al2O3, then with other high-K dielectrics• First in GaAs, then in other III-Vs

InGaAs planar Quantum-Well MOSFETs -short-channel effects

• Short‐channel effects limit scaling to Lg~40 nm• 3D transistors required for further scaling

7

Lin, IEDM 2014

0.01 0.1 1 10

100

150

200

250

300

S min (m

V/de

c)

Lg(m)

tc=12 mn

VDS=0.5 V

7 mn

8

Intel Si Trigate MOSFETs

FinFETs

• FinFETs used in state‐of‐the‐art Si CMOS  • Good balance of SCE and high ON current per footprint

9

InGaAs FinFETs

Radosavljevic ,IEDM 2011Kim, IEDM 2013

• Demonstrations to date: Wf ≥ 15 nm, ARc ≤ 2Kim, TED 2014

Thathachary, VLSI 2015

Waldron, VLSI 2014

Wf~30 nmWf~50 nm

Wf~50 nmZota, IEDM 2016

Djara, VLSI 2015

Wf~15 nm

Wf~25 nm

Goal: Sub-10 nm Wf Self-alignedIII-V FinFETs

• Deeply scaled Wf, Lg and EOT• High channel aspect ratio (ARc)• Self-aligned contacts • CMOS-compatible processes and materials in front-

end10

InAlAs

channel

capW/Mo

LgSiO2

HSQHigh ‐K

Hc

Wf

ARc = Hc/Wf

11

From InGaAs HEMT to finFET

100 nm

del Alamo, CS MANTECH 2011

Lin, CS MANTECH 2015

Vardi, CSMANTECH 2017

• Contact first• Gate recess

InGaAs HEMT

InGaAs Planar MOSFET

InGaAs FinFET

50nm

Fin definition:RIE + Digital etch

12

30 nm100 nm

8 nm170 nm

• BCl3/SiCl4/Ar RIE:smooth, vertical sidewalls and high aspect ratio (>10)

• Digital etch (DE): self‐limiting O2 plasma oxidation + H2SO4 oxide removal

Zhao, EDL 2014Vardi, VLSI 2016

Device fabrication

13

30 nm In0.53Ga0.47As,Si doped 3e19 cm‐3

4 nm InP stopper40 nm In0.53Ga0.47As,

undoped

Si ‐Doping: 4e12 cm‐2

400 nm In0.52Al0.48As buffer

InP semi insulating substrate

• Highly doped cap• 40 nm thick channel layer• Delta doping underneath 

5 nm

Device fabrication

14

Wf directionLg direction

InAlAs

channelcapW/MoSiO2

o Sputtered W/Mo contact o CVD SiO2 hard mask 

Device fabrication

15

35 nm

SiO2

W/Mo

Wf directionLg direction

InAlAs

channelcapW/MoSiO2 Lg

o Sputtered W/Mo contact o CVD SiO2 hard masko Gate lithographyo Gate recess (Dry): 

SiO2/W/Moo Active area definition

Device fabrication

16

35 nm

SiO2

W/Mo

InPW/MoSiO2

20 nmInGaAs

60 nm

Wf directionLg direction

InAlAs

channelcapW/MoSiO2 Lg

Lg

o Sputtered W/Mo contact o CVD SiO2 hard mask o Gate lithographyo Gate recess (Dry): 

SiO2/W/Moo Active area definitiono Gate recess (Wet): Cap 

etch

17

HSQ

HcHf

100 nm

Device fabricationo Sputtered Mo contact o CVD SiO2 hard masko Gate lithographyo Gate recess (Dry): 

SiO2/W/Moo Active area definitiono Gate recess (Wet): Cap 

etcho Fin Lithographyo Fin etch

Buffer

channelcapW/MoSiO2

18

HSQ

HcHf

High‐k/Mo

100 nm

20 nm

Device fabricationo Sputtered W/Mo contact o CVD SiO2 hard masko Gate lithographyo Gate recess (Dry): 

SiO2/W/Moo Active area definitiono Gate recess (Wet): Cap 

etcho Fin lithographyo Fin etcho Digital etchingo ALD gate dielectric 

depositiono Mo gate sputtering

Mo

HSQ

• Double gate FinFET• HfO2 , gate oxide EOT = 0.6 nm

Buffer

channelcapW/MoSiO2

19

Via

SiO2

Gate hat

Device fabricationo Sputtered W/Mo contact o CVD SiO2 hard masko Gate lithographyo Gate recess (Dry): 

SiO2/W/Moo Active area definitiono Gate recess (Wet): Cap 

etcho Fin Lithographyo Fin etcho Digital etchingo ALD gate dielectric 

depositiono Mo gate sputteringo Gate head photo and 

patterno ILD1 depositiono Via openingo Pad formation

• Fin pitch: 200 nm

• 10-50 fins/device

0 0.1 0.2 0.3 0.4 0.5VDS [V]

0

50

100

150

200

250

I d [A/

m]

Long-channel characteristics,Wf=22 nm, Lg=0.5 μm

20

• Slin=68 mV/dec

• Negligible DIBL

• Good electrostatic control over dry etched sidewalls

HfO2, EOT = 0.6 nm

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6VGS [V]

10-12

10-10

10-8

10-6

10-4

I d [A/

m]

68 mV/dec

VGS=0 to 0.75 VΔVGS= 0.25 V

VDS=0.5 V

0.05 V

21

Most aggressively scaled FinFETWf=7 nm, Lg=30 nm, Hc=40 nm (AR=5.7), EOT=0.6 nm:

Vardi, EDL 2016

At VDS=0.5 V:• gm=900 µS/µm• Ron=320 Ω.µm• Ssat=100 mV/dec -0.4 -0.2 0.0 0.2 0.4

0

200

400

600

800

1000

VDS=0.5 V

gm max=900 S/m

g m [

S/m

]

VGS [V]

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.41E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

VDS=50 mVDIBL=90 mV/V

I d [A/m

]

VGS [V]

Ssat=100 mV/dev

VDS=500 mV

0.0 0.1 0.2 0.3 0.4 0.50

100

200

300

400

500

I d [A

/m

]

VDS [V]

VGS=-0.5 to 0.75VGS=0.25 V

Current normalized by 2xHc

22

0 100 200 300 400 500 600 700

-0.6

-0.4

-0.2

0.0

0.2

0.4

EOT

V T [V]

Lg [nm]

0 100 200 300 400 500 600 7000

50

100

150

200

250 A: Al2O3, EOT=2.8 nm B:Al2O3/HfO2, EOT=1 nm C: HfO2, EOT=0.6 nm

S sat [

mV/

dec]

Lg [nm]

EOT60 mV/dec

0 100 200 300 400 500 600 700

0

200

400

600

800

1000

1200

1400

1600

EOT

VDS=0.5 VWf20-22 nm

g m [

S/m

]

Lg [nm]

EOT ↓  gm↑, Smin↓, VT rolloff↓

Classical scaling with Lg and EOT

Lg and EOT scaling (Wf~20 nm)

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0 100 200 300 400 500 600

0

200

400

600

800

1000

1200

1400

1600

Wf= 5 nm

g m m

ax [

S/m

]

Lg [nm]

Wf=22nm

100 10000

50

100

150

Wf=7 nm Wf=12 nm Wf=17 nm Wf=22 nm

S sat,m

in [m

V/de

c]

Lg [nm]

Gate leakage contamination

Wf Scaling

Non-ideal Wf scaling• Wf ↓  gm ↓• Wf ↓  Constant Smin

• Dit (~5x1012 cm-2.eV-1)• mobility degradation• line edge roughness?...

Benchmark

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gm normalized by gate periphery

Hc

WF

• ARc>1 • Sub‐10 nm Wf

Zota, IEDM 2016

Best logic device both III‐V and Si

MIT FinFETs:

Benchmark

25

• Si > III‐V• MIT FinFETs > all other III‐V FInFETs

gm normalized by fin width

Wf

For gm/Wf:0 20 40 60

0

5

10

15

20

0.321

1.8

0.570.8

5.73.3

2.31.8 InGaAs FinFETs

5.3

4.3Si FinFETs (VDD=0.8 V)

g m/W

f [m

S/m

]

Wf [nm]

0.630.6

0.230.66 1 0.18

VDD=0.5 V

0 0.1 0.2 0.3 0.4 0.5VDS [V]

0

50

100

150

I d [A/

m]

-0.2 0 0.2 0.4 0.6 0.8VGS [V]

0

100

200

300

400

500

600

g m [

S/m

]

-0.2 0 0.2 0.4 0.6 0.8VGS [V]

10-12

10-10

10-8

10-6

10-4

I d [A/

m]

65 mV/dec

50 mVVDS= 500 mV

Ig50 mV

VDS= 500 mV

VGS= 0 to 0.5 V in 0.1 V steps

EOT=0.8 nmLg=50 nmWf=5 nmHc=50 nm

Post deadline results

InP

InGaAs5nm

27

Post deadline results - Benchmark

• Record gm at Wf=5 nm• Record AR• Improved SCE 

28

Conclusions

29

• Novel self-aligned gate-last FinFET:– Self-aligned gate to contact metals – CMOS process compatibility – Sub-10 nm fin width– ARc>1 – Double-gate FinFET

• Excellent performance and short-channel effects in devices with Lg=30 nm and Wf=22 nm

• Demonstrated subthreshold swing of 65 mV/dec in short channel devices

• Still short of Si FinFETs performance

Thank you !

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