A scalable DAQ system using A scalable DAQ system using the DRS4 sampling chipthe DRS4 sampling chip

H.Friederich1, G.Davatz1, U.Hartmann2, A.Howard1, H.Meyer1, D.Murer1, S.Ritt2, N.Schlumpf2

1 ETH Zurich, Switzerland

2 Paul Scherrer Institute, Switzerland

Slide 2Hannes Friederich – May 2010

OutlineOutline

1. Introduction WaveDREAM Project DRS4 Chip

2. Realization Analog Frontend Continuous Digitization Digital Backend

3. Results System Bandwidth Noise Power Spectrum System Nonlinearity

Slide 3Hannes Friederich – May 2010

WaveDREAM ProjectWaveDREAM Project Motivation: 1 GSPS, 8-bit, low cost,

multichannel system for pulse shape discrimination and photon counting

Development of a flexible DAQ system Based on the DRS4 chip Active amplification

20 dB gain ≥ 500 MHz bandwidth

Scalable no. of channels Optimized for small amplitude (~10 mV), high frequency

signals (~1 GHz), e.g. PMT Capability for 1 ns global event timestamps Digital Trigger (FPGA)

General purpose board

Slide 4Hannes Friederich – May 2010

DRS4 Chip (Developed at PSI)DRS4 Chip (Developed at PSI) Large Switched Capacitor Array

(SCA) Stores the analog waveform

up to 5 GSPS 11.5 bit SNR

Slower SCA readout Less expensive ADC electronics Region of interest readout

NumberOfBins x 30 ns

8+1 channels Individual Channel depth 1024 bins Channel cascading Parallel or serial channel readout

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

WSROUT

CONFIG REGISTER

RSRLOAD

DENABLE

WSRIN

DWRITE

DSPEED PLLOUT

DOMINO WAVE CIRCUIT

PLL

AGND

DGND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8/MUXOUT

BIASO-OFS

ROFSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS

Slide 5Hannes Friederich – May 2010

DRS4 Transparent ModeDRS4 Transparent Mode

Input directly accessible at output while recording 50 MHz Bandwidth Continuous sampling of the input

Same ADC as DRS readout Digital trigger Arbitrary event record length

Eliminates the need for splitting the signal at the frontend Reduces PCB complexity

SCASCA MU

X

LPTransparent Mode gain: ½ of SCA gain

Slide 6Hannes Friederich – May 2010

Design RealizationDesign RealizationA

nalo

g F

ront

end

Ana

log

Fro

nten

d

DRS4DRS4 ADCADC FPGAFPGAGigabit

EthernetUDP connection to backend

Board-to-boardcommunication

Board-to-boardcommunication

Readout of all 8 pipelines in parallelMinimizes DRS4 dead time

Digital Trigger in the FPGA(e.g. Threshold, CFD)

Slide 7Hannes Friederich – May 2010

Analog FrontendAnalog Frontend

AC coupled input Fixed gain 20 dB Adjustable baseline

Accommodates all signal polarities Input remains in linear range of DRS4

Frontend-only bandwidth > 1 GHz

50

+ 14 dB + 6 dB

DRS4DRS4THS4302

THS4508

50 50

baseline DC offset DACDAC

Input span: 1 V p-pInput levels between 0.1 and 1.5 V

Slide 8Hannes Friederich – May 2010

Continuous DigitizationContinuous Digitization

AD9212: 8 Channel, 10 bit ADC, 65 MSPS Transparent Mode: 50 MHz bandwidth

Sampling theorem: ≥ 100 MSPS or additional low-pass filtering

More bandwidth increases SNR for high-frequency pulses

Solution: 2 AD9212 with 180 degrees clock phase shift, 120 MSPS

DRS4DRS4

AD9212AD9212

AD9212AD9212

FPGAFPGACLK

Trigger

Sample Modes:- Continuous sampling (120 MSPS)- DRS Readout (30 MSPS)

Slide 9Hannes Friederich – May 2010

Global TimestampsGlobal Timestamps

Global Clock & Reference signal distributed to all boards Avoids clock skew Use clock conditioner chips to reduce clock jitter

Sample the reference signal in the DRS4 to extract fine-grain timestamps

Calibrate propagation delays Not tested – No numbers

DRS4DRS4 FPGAFPGA

LP

Slide 10Hannes Friederich – May 2010

Prototype ImplementationPrototype Implementation

Mezzanine Card Analog electronics, DRS4 chip, ADCs

Carrier Card Slots for 2 mezzanine cards 2 FPGAs (Xilinx Spartan 3A) Communication Layer

Gigabit Ethernet UDP / IP / MAC layer in VHDL

Board-to-board communication 960 Mbit/s

USB 2.0 RS-485

VME form factor (6U) Provides mechanical support,

power supply & cooling No support for VME bus

Slide 11Hannes Friederich – May 2010

Results: System BandwidthResults: System Bandwidth

Input capacitance of DRS limits bandwidth 500 MHz Bandwidth

Nonlinear amplification around 300 MHz

Slide 12Hannes Friederich – May 2010

Transparent Mode BandwidthTransparent Mode Bandwidth

Bandwidth [-3dB]: 60 MHz

Slide 13Hannes Friederich – May 2010

Noise Power Spectral Density Noise Power Spectral Density

ENOB 8 – 8.5 bit

DRS Readout (1.024 GSPS)

Slide 14Hannes Friederich – May 2010

Baseline AdjustmentBaseline Adjustment

Baseline can be adjusted Linear adjustment circuit

ADC range [0 1024]

Slide 15Hannes Friederich – May 2010

Amplitude NonlinearityAmplitude Nonlinearity

Amplitude Nonlinearity less than 1 ADC value

Slide 16Hannes Friederich – May 2010

ApplicationsApplications A performant system has been demonstrated Possible applications include

Pulse shape discrimination Photon counting from PMTs Oscilloscope functionality Arbitrarily flexible trigger logic in the digital domain

Window coincidence already implemented

If you’re interested in using the WaveDREAM board, please contact me afterwards

Slide 17Hannes Friederich – May 2010

PMT SignalsPMT Signals

First part of transparent mode signal equals DRS readout signal

Slide 18Hannes Friederich – May 2010

ConclusionConclusion A challenging design realized

Good bandwidth achieved (500 MHz) Region of interest sampling up to 5 GSPS 120 MSPS continuous sampling

Digital Trigger logic ENOB 8 - 8.5 bit Gigabit Ethernet

Cost Effective Flexible design for multiple applications

Thanks to Arktis Radiation Detectors Ltd & CTI for financial support

Slide 19Hannes Friederich – May 2010