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A REMOVABLE EBG-BASED COMMON MODE FILTER FOR PCIE-ORIENTED HIGH-SPEED BUSES

Common Mode (CM) filters for high-speed digital signals have been recently implemented exploiting the so-called electromagnetic bandgap (EBG) structures. A “removable” design for this kind of filter has been proposed, which would enable the filter to be a stand-alone surface-mount component. One of the most crucial and challenging research topics in this field involves the miniaturization of EBG-based CM filters for their application to high-speed and high-density communication buses, such as the well-known PCI Express (PCIe) architecture. This article presents the design workflow of a removable EBG-based CM filter component (R-EBG) which would be suitable for a PCIe bus. In particular, by virtue of the specific modeling features offered by CST Studio Suite® and by using ADS® circuit simulations, the reliability of the design procedure together with the effectiveness of the implemented EBG CM filter are shown through frequen-cy and time-domain results.

Nowadays, almost all the modern electronic high-end technologies are involved in a competitive research for the implementation of faster and faster high-speed and high-density communication buses. A very well-suited example is the development process of the PCI Express bus, which is now approaching the PCIe 4.0 architec-ture.Some of the most common design challenges in this field are typically ascribable to the presence of an undesired common mode (CM) component, inherently occurring in real-world printed circuit board (PCB) designs[1] and induced by either geometrical impair-ments (e.g. different trace length) or electrical impair-ments (i.e. imbalances of rise/fall times in the transmit-ted signals, skew, amplitude mismatch between the single-ended signals). This CM component should be strictly avoided because it is the major source for a wide set of negative effects, such as unwanted radiation[2] and signal integrity (SI) degradation.

A particularly appealing and promising CM filtering tech-nique is the one based on the so-called electromagnetic bandgap (EBG) structures[3], [4], consisting of properly shaped repetitive patterned planes enabling the selective filtering of the CM through a resonant cavity principle.

At the moment CM EBG filters can be implemented fol-lowing two main design solutions:

1. As “planar” EBG filters: in which the resonant struc-tures are embedded inside the same stack-up of the main board[5], [6];

2. As “removable” EBG filters: in which the resonant structures are laid-out on a separate stack-up, so the filter constitutes in practice an independent surface-mount component[7–9].

The first solution offers lower costs but the second one gives much more flexibility and scalability on the final PCB layout. Both solutions share a common challenging research front constituted by their miniaturization toward very high-densi-ty interconnects[10–13].

In the following article, the development procedure of a R-EBG CM filter suitable for PCIe buses is fully described, focusing on two main aspects: the modeling steps followed to overcome the inherently present design issues and the evaluation of its functional and filtering performances, both realized through the use of the 3D EM modeling features offered by CST Studio Suite[14].

I. THE BASIC R-EBG FILTER MODULE

The starting main idea behind the construction of the R-EBG CM bus filtering solution presented in this article is to con-sider an array of basic filter modules, each one devoted to filtering a single differential pair included into the data bus. A reliable starting point for the building of these modules is to consider an elementary R-EBG module based on the so-called “sandwich-type” structure, already analyzed in previous works[7–9], [11] and schematically reported in Figure 2. The rea-sons for the adoption of this kind of structure as the basic filter unit are mainly ascribable to the following features:

• its reduced spatial size

• the good CM filtering properties

• the possibility to have a footprint of the patterned EBG metal layer that can be easily made compliant with the typical PCIe differential pairs layout requirements

II. DESIGN OF A R-EBG CM FILTER FOR A PCIE BUS

In the following, the basic R-EBG working principle and the related structure have been properly customized in order to realize a complete filtering solution for PCIe-like high-speed buses. In particular, some specific design criteria have been developed which are fully detailed hereafter.

A. Overall design principles and starting geometrical details

In order to implement an R-EBG CM filter for a complete communication bus, the proper replication of the basic filter module described previously is required together with some specific design criteria. The features offered by the CST Studio Suite modeling engine are extremely help-ful in this scenario in order to reduce the effort made by the designer.

As a preliminary starting point, by virtue of the very small footprint obtained by using the already introduced “sand-wich” architecture, the comparison between the typical dimensions of a PCIe bus (see Figure 4 and Table 1) and that of an R-EBG CM filter basic module (see Figure 2) allows one to develop a wise EBG array forming the com-plete removable filter component (architecture depicted in Figure 5). In order to better illustrate the design methodol-ogy, the bus is supposed to be limited to only 4 differential pairs, but, without loss of generality, structures having larger number of traces can be taken into account without any change in the design procedure.

B. Development steps and preliminary bus filter design

As a further step, two other considerations should be taken into account at the beginning of the design stage:

a) in order to keep the costs low, the R-EBG component should share the same stack-up as the main board

b) the clearances between the EBG patches and the metal surrounding ground references of all the basic modules should be minimized

At this point, taking into account the schematic architecture reported in Figure 5 and the aforementioned criteria, the development of the full R-EBG bus filtering assembly is pos-sible considering also the following design input data:

1. the filter target frequency

2. the employed dielectric, which is a Megtron 6 laminate having εr = 3.58 and tan δ = 0.004 at 10 GHz

In particular, according to the general design procedure of a single R-EBG module[5], [6] a first trial of the geometry can be obtained by suitably developed analytical formulas.

A paramount characteristic of the sandwich architecture is the folded structure given to the resonant part of the filter itself. As shown in Figure 2 it consists of three EBG sub-structures, each one formed by a pair of metal patches: one patch lies on one layer of the component stack-up, while the other patch lies on a different layer. The two patches are then connected by a proper through-hole via playing the role of the so called “bridge” in the planar EBGs. The signal traces run among the patches as striplines. The EM and filtering properties of this type of structure have been already extensively explored using a related properly devel-oped CST Studio Suite simulation model, which is depicted in Figure 3. As an example behavior of the resonant cavity principle governing the filtering action, the spatial E-Field distribution at a sample resonant frequency of 8 GHz is shown in Figure 3d on which the EM coupling between the resonant patches and the signal traces (striplines) is high-lighted. The general sandwich R-EBG unit can be designed according to the guidelines reported in [7–9], [11], whereas this article focuses on the development of the full bus filter-ing solution instead.

Main Board Dielectric

R-EBG Dielectric Layers

MB Top Gnd Pads

MB Solid GND

Microstrips on MB

GND reference

R-EBG Signal Vias

Top GND reference

EBG Layer 1

Traces Layer (striplines)

EBG Layer 2

GND reference

R-EBG Bottom GND MB Traces

MB GND Reference

d1

d2

d3

d2

d1

d0

SignalVias

GNDVias

A´A´

A-A´ Cross Section

R-EBG patches

R-EBG Bridges

R-EBG Metal top layer

Striplines inside R-EBG

R-EBG internal rings

R-EBG GND Vias

R-EBG Metal bottom layer

B-B' Cross Section

Figure 1: CST Studio Suite model of the Removable EBG-based Common-Mode BUS filter.

Figure 2: Structural details of the “sandwich-type” architecture used as the basic module for the proposed PCIe R-EBG CM filter.

Figure 3: Sandwich R-EBG architecture main details. a) R-EBG mounting site on main board, b) mounted R-EBG filter perspective view, c) internal EBG resonant structures, d) E-Field map at the resonant frequency (e.g. 8GHz).

Figure 4: General layout structure of a PCIe bus.

Figure 5: Schematic cross-section of the R-EBG CM filter for PCIe buses in Figure 4. In the figure is also displayed the modules numbering (#i with i = 1, ..., 4).

Table 1: PCIE bus, stack-up and traces dimensions.

BUS layout constraints Differential pairs & stack-up data

Parameter DescriptionValue [mm]

Parameter DescriptionValue [mm]

Sp Traces spacing 1.655 W Trace width 0.275

Wpad Pads Width 0.508 s Pair spacing 0.185

hpad Pads height 1.090 d1d2d3

Dielectric thickness0.1240.0990.908

g Pad spacing 0.292

p Pads pitch 0.8

Parameter Description Value [mm]

a Patch size 1.5

Ws Stripline trace width 0.2

Ss Stripline traces spacing 0.185

d GND and EBG vias diameter 0.250

D Catch pad diameter 0.5

ds Signal vias diameter 0.350

r Stitching step size 1.160

Tx, Ty Antipad trench sizes 0.9, 1.9

Hx, Hy Bus filter external sizes 9.71, 9.96

Table 2: R-EBG CM filter in Figure 4: Values of the geometrical parameters.

Then, since it appears from Table 1 that the PCIe traces are characterized by a nominal differential impedance of 85 Ω, the next design step is the dimensioning of the strip-line traces running inside the removable part for the same value of differential impedance. After the execution of all the steps, the final output of the design procedure is the layout indicated in Figure 6, whose specific geometrical dimensions are summarized and reported in Table 2.

a)

c)

b)

d)

This layout is the same one to be considered as the prelimi-nary R-EBG bus filtering solution. It should not be consid-ered as the final outcome since other relevant design details also have to be considered. Due to the approximation in the analytical formulas, a subsequent geometry refinement based on 3D EM simulations should be done to precisely match the filtering frequency with the target common mode harmonic to be blocked (8 GHz in the PCI-e case). However, due to the complexity of the resulting 3D struc-ture and since the main scope of this article is only the functional verification of the underlying idea, the target frequency refinement process has been neglected. At this design stage the electromagnetic (EM) responses of the complete R-EBG modules are also studied to verify whether each filter can be considered independent by the adjacent ones. In our case, each filter is isolated by the presence of through-hole vias stitching all the reference (GND) planes and generating an EM fence between the modules, as shown in Figure 6, with a spatial stepping defined by a proper parameter that can be adjusted.

C. R-EBG bus filter design refinement

After the preliminary filter design, resulting in what is reported in Figures 7a and 7b, there are also some other details that should be taken into account, for which a bur-densome refinement stage is justified. For instance, the optimization of the vias transition between the microstrip-lines on the MB and the stripline on the removable compo-nent is strongly desirable. In particular, in this application case, this is performed by a proper sizing of the antipads Tx and Ty in Figure 6, in order to minimize the stray capaci-tances. For the same reason a void in the reference GND planes underneath the differential traces in the antipad area is laid out as will be detailed hereafter.

In particular, the sizing of the antipads and of the GND voids, useful for the tuning of the MB-to-R-EBG differential traces transition, can be done through a proper differential Time Domain Reflectometry (TDR) response analysis.

This kind of study has been realized through a specific CST  Studio  Suite model of the R-EBG bus filter where the differential pairs have been excited using 16 discrete edge ports, as reported in Figure 7c, configured as S-parameter ports and using a maximum frequency of 50 GHz. The opti-mization of the TDR responses has been done exploiting the CST Studio Suite parameter sweep features in a suitable manner, producing the intermediate models reported in Figure 8 and the related results, reported in Figure 9.

At the end of this geometry tuning, the five main refinement steps reported in Figure 8 have been analyzed: the starting one (C1) accounts for the absence of GND voids, the signal vias with external diameter ds = d, and the sizes of the transi-tion antipad Tx = 0.6mm, Ty = 1.5 mm. In Case 2 (C2) the transition antipads have been enlarged to Tx = 0.9 mm, Ty = 1.9 mm, but still capacitive bumps occur on the TDR signal. Because of this, in order to reduce this effect, a void-ing on the GND planes on the MB has been applied as

reported in cases C3 and C4 respectively. In particular in case C3 the voiding dimensions are equal to: Tx = 1.6 mm, Ty = 1.9 mm and in case C4 are: Tx = 1.0 mm, Ty = 1.9 mm. The best results are obtained for the Case 5 (C5) for which there is the same geometry of case C4 but the signal vias have been tuned to a greater diameter, namely ds* = 0.35mm, in order to decrease the part of inductive response in the differential TDR signal of Figure 9. It is shown here that with this design solution the signal mismatch is attenu-ated although the differential characteristic impedance is no more 85 Ω but tends to be around 80 Ω.

Figure 6: Top view and excitation ports of the designed model of the R-EBG filter for a 4 channels PCIe bus, including the parameters defining the geometry inside CST Studio Suite.

Figure 7: Perspective view of the CST models representing: a) the main board with the PCIe bus, b) the preliminary R-EBG bus filtering solution applied on the bus, c) the model used for further design refinements using a TDR analysis.

Figure 8: Design refinement steps followed for the tuning of the filter performances: a) starting filter geometry, Case C1, b) C2, c) C3, d) C4, e) final step, C5.

III. FREQUENCY AND TIME DOMAIN NUMERICAL RESULTS

The performances of the designed R-EBG CM filter for a 4 channel PCIe high-speed bus have been numerically evalu-ated both in frequency and time domain, in particular in the first case by means of CST Studio Suite 3D full wave simula-tions. The mixed mode scattering parameters Scc21 and Sdd21 are taken as figures of merit for the filter performances in frequency domain. The frequency spectrum of the magni-tude of Scc21 represents the filtering action of the designed structure while the frequency spectrum of the magnitude of Sdd21 represents the impact that the removable part has on the transmission of the intentional differential signal. In this spe-cific application case, the obtainment of the scattering parameters is possible by substituting the 16 discrete ports

a)

b)

c)

d)

e)

Figure 9: Differential TDR responses used for signal vias transition improvement through the tuning of the vias diameter, antipad size and main board GND voiding sizes, for the analyzed cases from C1 to C5.

Figure 10: CST Studio Suite model employed for the frequency analysis of the developed R-EBG bus filtering solution. In particular, definition of the multipin waveguide ports used for the computation of the Scc21 and Sdd21 parameters.

excitations of Figure 9 with the respective waveguide port excitations, as depicted in Figure 10.

The waveguide ports, numbered as P1...P8, have been defined as multipin ports in order to obtain the Scc21 and Sdd21

parameter plots directly in CST Studio Suite.

The frequency spectra of the magnitude of these parameters are reported in Figure 11 and Figure 12 respectively for each of the four filter modules. As expected, the notches in Scc21 for all the modules are located around the selected target frequency of 8 GHz, in particular at 8.3 GHz; as already stated, a further design refinement can be used to correct this frequency drift. From the point of view of the EM per-formances, due to the different stray couplings, the inner modules show small differences with respect the outer ones. This is reflected in the different spectra of Scc21 associated to modules #2 and #3 with respect to those associated to #1 and #4. Nevertheless they are characterized by the same Sdd21 performance as shown in Figure 12. The Near End (NEXT) and Far End (FEXT) crosstalk for the CM and differen-tial mode component can also be computed in CST Studio Suite. The CST Studio Suite model with the 16 discrete ports of Figure 7 has been used for this. The results are reported in Figure 13, with analysis between the R-EBG modules #1 and #2 in particular. In Figure 13 the solid upper curves represent the values of Scc21 and Sdd21 for the

a)

c)

b)

channel #1 and are taken as references, with the port num-bering in Figure 10 making indicated in the figures’ legends makes reference to that. The values of the differential mode crosstalk are, at the design target frequency, below -30 dB and the CM crosstalk shows an attenuation of at least -10 dB at the same frequency.

The proposed R-EBG CM filter has also been tested also from a time domain point of view. The circuit schematic in Figure 14 was developed in ADS[15], starting from the 16-ports S-parameter matrix obtained by the 3D full wave simulations. This circuit allows one to investigate the effects of the filter when a rise/fall time mismatch is applied on an input PRBS differential signal, such as rise time = 5 ps and fall time = 15 ps. Figure 15 reports both the input/output CM signals and the output differential eye

pattern. The results in Figure 15 confirm the positive action of the R-EBG CM filter on the PCIe bus: the output CM is significantly reduced (see Figure 15a) and the eye pattern is more open after the filter application on the bus channels (see Figure 15b).

CONCLUSIONS

The process of designing a new R-EBG CM filter suitable for PCIe buses has been illustrated and characterized with accurate numerical simulations, pointing out the reliability of the developed design procedure and the effectiveness of the R-EBG CM bus filtering solution. The necessity of using a 3D EM modeling tool such as CST Studio Suite for the refinement of the overall design has been also highlighted. The performances obtained from frequency domain and time domain results show promis-ing developments for this technology.

Figure 11: Frequency spectrum of the magnitude of Scc21 for the four R-EBG CM filter modules in Figure 4.

Figure 12: Frequency spectrum of the magnitude of Sdd21 for the four R-EBG CM filter modules in Figure 4 versus the baseline (accounting for no R-EBG filter).

Figure 13: Near End Crosstalk (aggressor ports 1 and 3, victim ports 5 and 7) and Far End Crosstalk (aggressor ports 1 and 3, victim ports 6 and 8) analysis between R-EBG module #1 and #2, in particular: (a) CM NEXT and FEXT; (b) Differential Mode NEXT and FEXT.

Figure 15: (a) Input and output CM signal sequence in time domain and (b) output differential eye pattern.

Figure 14: ADS circuit for the time domain analysis of the R-EBG CM filter.

REFERENCES

[1] B.R. Archambeault, PCB Design for Real-World EMI Control, Kluwer Academic Publisher, Norwell, MT, USA, 2002.

[2] B. Archambeault, S. Connor, and J. Diepenbrock, “EMI emissions from mismatch in high-speed differential signal trace and cables,” in Proc. IEEE Int. Symp. Electromagn. Compat., Honolulu, HI, USA, July 2007.

[3] F. de Paulis, B. Archambeault, M. H. Nisanci, S. Connor, A. Orlandi, “Miniaturization of Common mode filter based on EBG Patch Resonance” in Proc. IEC DesignCon 2012, Santa Clara,USA, Jan. 2012.

[4] F. de Paulis, B. Archambeault, S. Connor, A. Orlandi, “Electromagnetic Band Gap Structure for Common Mode Filtering of High Speed Differential Signals”, in Proc. of IEC DesignCon 2011, Santa Clara, CA, USA, January 30 – February 2, 2011.

[5] L. Raimondo, F. de Paulis, A. Orlandi, “A Simple and Efficient Design Procedure for Planar Electromagnetic Bandgap Structures on Printed Circuit Boards,” IEEE Transaction on Electromagnetic Compatibility, vol. 53, no. 2, pp. 482–490, May 2011.

[6] M.H. Nisanci, F. de Paulis, A.Orlandi, B. Archambeault, S.Connor, “Optimum Geometrical parameters for the EBG-Based Common Mode Filter Design”, in Proc. of 2012 IEEE Symposium on EMC, Pittsburgh, PA, USA, Aug. 2012

[7] M.A. Varner, F. de Paulis, A. Orlandi, S. Connor, M. Cracraft, B. Archambeault, et al. “Removable EBG-Based Common-Mode Filter for High-Speed Signaling: Experimental Validation of Prototype Design,” IEEE Trans. Electromagn. Compat., vol.57, no.4, pp.672–679, Aug. 2015

[8] F. de Paulis, et al., “Standalone Removable EBG-Based Common Mode Filter for High Speed Differential Signaling”, in Proc. of 2014 IEEE Intern. Symp. on EMC, Railegh, NC, USA, Aug. 2014.

[9] Q. Liu, et al., “Reduction of EMI Due to Common-Mode Currents Using a Surface-Mount EBG-Based Filter”, IEEE Trans. on Electromagn. Compat., Vol. 58, nr. 5, pp. 1440–1447, Aug. 2016.

[10] F. de Paulis, L. Raimondo, S. Connor, B. Archambeault, A.Orlandi, “Compact configuration for common mode filter design based on electromagnetic band-gap structures,” IEEE Transaction on Electromag. Compat., vol. 54, no. 3, pp. 646–654, June 2012.

[11] C. Olivieri, F. de Paulis, A. Orlandi, S. Connor, and B. Archambeault, “Miniaturization approach for EBG-based common mode filter and interference analysis,” in Proc. of 2015 IEEE International Symposium on EMC, Santa Clara CA, USA, March 2015.

[12] F. de Paulis, M. Cracraft, C. Olivieri, S. Connor, A. Orlandi, B. Archambeault, “EBG-Based Common-Mode Stripline Filters: Experimental Investigation on Interlayer Crosstalk,” in IEEE Trans. on Electromagn. Compat., vol.57, no.6, pp.1416–1424, Dec. 2015.

[13] F. de Paulis, et al. “EBG-Based Common-Mode Microstrip and Stripline Filters: Experimental Investigation of Performances and Crosstalk,” in IEEE Trans. on Electromagn. Compat., vol.57, no.5, pp.996–1004, Oct. 2015.

[14] Computer Simulation Technology, CST Studio Suite 2018, available at www.cst.com.

[15] Keysight, Advanced Design System 2013, available at www.keysight.com

AUTHORS

C. Olivieri, F. de Paulis, A.Orlandi, D.I.I.I.E., University of L’Aquila, L’Aquila, 67100, Italy, antonio.orlandi@univaq.it

S. Connor, IBM Systems, Research Triangle Park, NC 27709, USA, sconnor@us.ibm.com

P. Dixon, LAIRD, 1 Perimeter Rd, #700, Manchester, NH, USA, paul.dixon@lairdtech.com

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