A Nonblocking Multi-stage ATM Switch using Cell-based Routing

with a Hierarchical Cell Sorting Mechanism

David Santosol, Seisho Yasukawa2 , Naoaki Yamanaka二, Tetsuya Mikil

l UniversltyOf Electro-Corrununications

1-5-1 Chofugaoka, Chofu-shi, Tokyo 182-8585, JapanTel: +8 i-424-90-7095

Fax: +8ト424-90-7096

Emailこくdavid-S, m血)@fhh･ee･uec･ac･jp

= NTT Network Semice Svstems Laboratories●ノ

3-9-1 i Midori-cho, Musashino-shi, Tokyo 180-8585, Japan

Tel: +8ト422-59-4769

Fax: +81-422-59-4819

E-mail: (Yasukawa.Seisho, Yamanaka･Naoaki@nslab･ntt･co･jp )

AbstT･aCI

A multi-stag? switching architecture is a key technology for buz-ldlng a high-speedATM SWltCh-

ing system･ An ejfectLVe Way to make a mufti-Stage SWZtCh nonblocking is to use Cell-based roullng.

However: Cell-based routing may Cause Cell-Sequence disorder at the oLLtPut Ofthe SWitchz'ngfabrlC.

ThlSPaPerPrOPOSeS a hierarchical cell-sorting UCS) SWltCh archLteCture, WhlCh is a nonblocklng

Tultl-Stage Anf5Witch lLSlng Cell-based routing technolo甲Each basic HCS SWZtCh peqorms cell sort-ing at every CrOSSPOint･ based on tlme51tamP infor77ation ln the cell-header This arran軍es the cells in

sequence at the output of each baSlC HCS switch, slnCe the crosspolntS are hLerarChically LnterCOnneCted

from the lnPutPOrt tO the outputport ofa basIC HCS jWltCh･ A multl-Stage HCS jWilch lS COnStnJCted byinterconnectlng the mpZft and output llneS Ofthese basLC HCS switches in a hLlerarchlCal manner Thus, the

cell sequence ln eaChflnal output oflhe multl-5･tage jWllch is preserved ln a hz'erarchlCal mmner ln this

way cell-based routlng WLth lOr)% thro乙Eghput lS achieved, wllh no needjbr Lntemal Speed-up techniques,

1. Introduction

A multi-sta芋e s､vitching architecttlre is a feasible and cost-efFective way to construct a high-speed ATM

switching system･ It lS also the best architecture in terms of switch scalability because it can be easily expanded

u?ing additional switching blocks of the sametypellHn a three-Stage Switching architecture, there are twotypes ofvirtual charmel (VC) routing二COnneCtion-based routing and cell-based routing･ The former routes cells of the saヮe

VC throughthe same path, and the latter routes cells of the same VC血oudl aH available paths･ Celトbased routingヽ一/

is known to be an effective way to make a multi-stage switch nonblocking without usmg any Internal speed-up

techniques [2日5十

However, there are two main problems in a multi-stage switching system using Cell-based routing: how to

distribute input traffic to the second-stage switch fairly to keep the switch nonblocking and how to arrange the

distributed cells in sequence at the output of the switching fabric in an effective way･ h this paper we propose a

dynamic cell distributionヮteChanism (COM) in Section 2 to solve the hst problem, and a hierarchical cell sorting

(HCS) mecha空m in Section 3 and a time-stamp distribution mechanism in Section 4 to solve the second problem･

Finally, in SectlOn 5 we describe theperformance of this switch based on computer simulations,

2･ Dynamic Cell Distribution Mechanism

h a cell-based roudng architecture, cell (traFIC) distribution over second-stage switches is a very important

factor in keepulg the switch nonblocking･ For example, let us consider that the incomng cells are randomly dis廿ibuted

265

Figure 1 ･ Dynamic Cell Distribution Mechanismin

three-stage HCS switch

0　　　　　　50000　　　　1 00000　　　1 50000　　　　200000

Time 【cellsl

(a) Connection-based routing and celトbased rou血g

…　　　3 = 0 00　　　81L苅0　　　号njX)0　　　88003　　　舛〕 ㈱

Tlme tceHsl

(b) Random CDM

CeH-based Rou‡-ng

卜､-i･Lh Dl:aamlC CDLu)

柑柳　　　川三耶q　　1 8J,GOO I R6000　　　柑耳Wrj lウ仰

T;me tcdIIl

(C) Dynamic CDM

Figure 21 Load distributions of multi-stage switches usmg

comection and celトbased routlng

to different routes (different second-stage switches) every cell-time･ Even if the route is randomly selected, there

is no guarantee that in a glVenperiod of time each route is selected with the same frequency･ Thus, the number of

cells enter-ng the second-stage switch buffers might become unbalanced and instantaneous load concentration

might occur. Ifthe load concentration continues to occur, lt might cause blocking ln a multi-stage switchinL'

system, which makes celトbased routing useless.

We propose a dynamic cell distribtltion mechanism (dynamic CDM) which considers山e cell addresses

when distributing cells at the first-stage switches･ The main purpose of this mechanism is to balance the distributed

instantaneous load in each second-stage switch buffer (Figllre 1). The cell distribution mechanism is as follows.

Each cell distributor (CD) placed at the input side offirst-stage switches maintains a cell-distribution record of

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which route (which second-stage switch) ceus of the same group have been routed to during agiven psriod of time.

When a cell arrives,the cell dis廿ibutor detemies which groupthe cell belongs to (which third-stage switchthe cell

is going to)･ The switchthen usesthe cell-distribution record to aJTange thatthe cells of the sane group are fairly

distributed to second-stage switches･ This simple ceu distribution mechanism enables cells to be fairly distributed

in a dynamic way over second-stage switches, regardless ofthetype of input trafrlC.

To evaluatethe load balancing Performance of this mechanism, we performedthree computer simulations

of multi-stage switches using 1) Connection-based routing, 2) cell-based routingwithrandom CDM, and 3) cell-

based routlngwithdynamic CDM. h the system using random CDM, cells are randomly distributed to different

routes every cell-time,with no consideration of the cell address. Figure 2 showsthe distributed load of a certain

output buffer of second-stage switches when a particular traffic vo一ume entered the switching system･ With

cormection-based routing, the load was not balanced atal1and blocking (average distributed load > 1.0) occurred at

switches 1 and 3 0fthe second stage, even when the input trafrlC VOlume was below the totalSwitch血g capacity.

In the system using Cell-based routmg with dynamic CDM, blocking could be avoided because the load was fairly

distributed overthe second-stage switches･ Thus, dynamic CDM makes a multi-stage switching system nonblocking

for anytype of input traffic pattem. The system using cell-based routingwithrandom CDM isalso a nonblocking

system, sincethe ayer.age distributed load is below l･0･ However, kom Figures 2(b) and 2(C) we can seethat the

dynamic CDM minlmlZeS the variance of the distributed load of second-stage switches･ This improves the delay

performance of the proposed HCS switch.

3･ Hierarchical Cell Sorting (HCS) Switch Architecture

To arrangethe distributed cellsinsequence atthe output of the switching fabric, We propose a hierarchical

cell sorting meChanism･ The basic idea of 血s mechanism is to sortthe distributed cells by arriValtimeinthe switching

system･ h each basic switching block, we follow the FIFO (First In First Ollt) rule to determine which cell has to be

sent五rst, to aTange the switched cells in sequence･ By peTformlng this cell sortmg ln each basic switch element ofall

stages, we can get the distributed cells in sequence at the output of the switching fabriC･

To control the the-stampand cell routing, we place a time-stamp controller (TR-CTRL) at the input side of

the first-stage switches (Figure 1). Each controller has a counter that is synchro山zed with the cell transmission

the; the counter is incremented by one each cell time･ When a cell enters the switch, the valtle in the counter is

written into the overhead of the cell as a time-stamp･ This time-stamp records the time the cell was received by the

switch and is used in cell sorting throughout the switching fabric.Figure 3 Shows the architecture ofa basic HCS switch element･ It pe血ms cell switching and cell

sorting at the sane time. To avoid havlng tO use internal speed-up techniques, we use crosspolnt buffering ln

switching cells to an output port･ Each cTOSSPOint is constructed &om an address filter (AF), a crosspoint buHer,

a transit buHer, a time-stamp-based arbitration controller (CTRL), and a selector. A transit buffer can store several

cells sent from either the upper crosspolnt buffer or the upper transit buffer.

When the crosspoint buffer or transit buffer has at least one cell, it sends a transmission request (RfQ)

and time-stamp information to its controller･ The controller then compares the time-stamps of the cells in the

crosspolnt and transit buffers for cell-selection and sends the result to the selector for cell-transfer. The transit

buffer sends a NACK s血al to the nexトhigher controller when it becomes丘111. When the upper controller receives1__

this signal, it stops selecting Cells to transmit･ As long as no NACK signal is received from the nextllower transit

bufferフCelトselection and cell-transfer areperformed by the controller and the selector, respectively, once per cell

time. The selected cell is sent to the next-lo､ver transit buffer or to the output line at the lowest crosspolnt･

The cell-selection is performed according to the t品e-stamp-based cell-selection nlles given below. The

controller uses these rules to determine ､vhich cell to send next. RLLle 1: if both the crosspolnt buffer and the transit

buffer have a cell to send, then the celhvith the earliest time-stamp IS Selected･ Ifthe time-stamp of the cell in the

crosspoint buffer equals that of the cell in the transit buffer, the controller determines which cell to transmit by as

follows 〔6]･ Let us consider that crosspoint buffer k and transit buffer k (k is the crosspoint ntunber in a ro､V) each

have a cell with the same time-stamp･ The ceu in crosspolnt buffer k is selected with probability I/k, while the cell

in transit buffer k is selected with probability作,-1):k because the transit buffer k is interconnected with k-I upper

267

input line I

input line二

Input line N

Output line 1 Output line2　　　0utputlineN

Figwe 3. Basic HCS switch architecttu･e

crosspoints, meaning that probability a-1)･ k represents cell transmission丘om k-1 upper crosspoints･ h this way,

a cell is selected fairlv when both cells have the same time-stamp･ RILle 2: if neither the transit buffer nor the

crosspolnt buffer in a crosspolnt has a cell to send, then the controller stops selecting Cells to transmu, to avoid

disrupting the cell sequenceinthe switching system.

By following these cell-selection rules, cells can be distributed in sequence across the switching system.

However, Rule 2 greatlv increases the cell-transfer delay when the offered load is small, because in that case there～...′

is a greater Chance of there being no cell from an input line･ Therefore, we propose a time-stamp distribution

mechanism to improve the cell-transfer delay performance of this switching system.

4･ Time-stamp Distribution Mechanism

To reduce the cell-transfer delay, we introduce a time-stamp distribution mechanism. When no cell enters

the first-Stage SWitch durmg a cell time, the TR-CTRL at the input side of the丘rst-stage switches creates a dummy

cell,andthe value of the counter is writteninto its overhead. The durr-y cell is then passed to the foilowlng basic

switches･ The switches need the information carried by this dummy cell to maintain correct and effective time-

stamp comparisons･ A new cell arTivlngfrom the upper transit buffer or from an upper switch can overwrite a

dumlny Cell waitlngina crosspoint buffer or打ansit buffer, because the new cell brings newer timestampinforma-

tion･ This prevents an excessiveincrease in the cell load.

As shown in Figure 4, when a cell enters a basic switch element, the incoming Cell is copied and distrib-

uted toall output ports before its destination is checked. Then the Af in front of the crosspolnt buffers checks the

type of the incoming celHfthe cell type is R王AL (meaning it is not a dummy cell) and the destination address

corresponds to the AF number (which is equal to the output line number), the cell is written as a ,eat cell in the

followmg crosspolnt buffer･ If the celltyPe is REju and the destination address does not correspond to the Af

number, the cell is w血en as a dummy cell and g"en the same time-stamp as that of the incoming Cell. Ifthe cell

type is DUMMY,the cell is written as a dummy-cell to the following crosspoint buffer.

Asa consequence ofuslng durrmy cells, we needanotherrule for cell-selection to be success魚11. Rule

3: ifboththe crosspolnt buffer and transit buffer have at least a dummy cell to send, dlen the cell with the earliest

time-stamp IS Selected･ Ifthe t也e-stamp of the cell inthe crosspolnt buffer equals that of the cell in山e transit

buffer･ the controller selects the non-dt-y cell. If both are dummy cells, the controller determines which cell to

send by using Rule 2･ The introduction of dummy cells and dlis new cell-selectionru1e enables celトselection to be

268

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hput line 1

Figure 4. Time-stamp distribution mechanism

performed effectively regardless of the ofFered load, which dramatically improves the cell-transfer delay perfor-

mance of也e proposed switch血g system.

5. Performance ofHCS Switch

We evaluatedthe performance of the HCS switchwiththe dynamic CDM andthe time-stamp distribution

mechanism by computer simulation･ In ou干simulation, we modeled a three-Stage HCS switch (Switch size二 N2 x N2)

composed of basic HCS switch (switch size: N x N) elements arrangedwith clos-Connection. The input traffic

fouowed a Bemoulli process andthe ceu destination was given randomly五･om 1 to N2.

Under these simulation conditions, we verifledthat cells wereinsequence at the output of the basic HCS

switches and also at the output of the three-Stage HCS switch･ This shows that the proposed hierarchical cell-

sortlng mechanism works well.

150

0.0　　　　　0,2　　　　　0.4　　　　　0.6　　　　　0.8

0ffered Load

Figure 5. Cell delay perfonnance ofHCS switch

Figure 5 shows the average cell-transfer delay of a basic HCS switch and that ofa three-stage HCS

switch for N-8 and N-12･ The results showthatthese switches can achieve lOO%throughput, the idealthrough-

put performance ofa single output-buffer-type switch l7]･ Theyalso show that a basic HCS switch has a good

269

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delay perform皿Ce due tothe implementation of the timestamp distdbution mechanism･ The difference in delays

between the SWitcheswithN=8 and switches withN-12 depended on the number of cell comparison steps in a

basic壬iCS switch･ Inthis simulation, we modeled a basic HCS switch architecturewith N-1 comparisons. This

explains why our basic HCS switch had at least Nl1 extra delays compared tothe conventionalsingle output-buffer-

type switch･ Sincethe three-stage HCS switch was composed of basic HCS switch elements, it had at least three

times as many extra delays as a basic HCS switch h fact, compamg n ceus at a time can lower the number ofcell

comparison stepsandalsothe delays to N/h.

6. Conclusions

we have proposed dynamic ceu disthbution, hierarchicalcell sorting (HCS), and time-stamp d血ibution

mechanisms to suppoH a nonblocking multi-stage ATM switchthat uses cell-based routmg･ The time-stamp d血i-

bution mechanism enables each basic HCS switch to performeffective cell soHmg at its crosspolntS in a hierarchi-

Calmanner, which resultsinthe distributed cells being arranged in sequence at its output･ Athree-stage HCS switch

i主composed of basic HCS switch elements, So the switched cells at each of its outputs are alsoinsequence. we

veri五ed by computer simulation that the HCS mechamim works well･ The cell-transfer delay performance of this

switch can be improved by reducing the number ofcell comparison steps, if the hardware teclmOlogy permits.

computer simulationsalso showedthatthe dynamic cell distribution mechanism does a good job ofdistrib-

utmg ceus of any input trafFIC pattem over the second-stage switches･Asa result, while the conventional output-

buifer-type switch needsinteTnal speed-up techniques to achieve lOO% throughput, a muユti-stage HCS AIM switch

does not need any to achieve the same throughput performance･ This makes the proposed multi-stage HCS switch

aneffective switching system that is applicable to future broadband AIM networks.

References

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a Melenand JISI Turner, "Nonblocking networks for fast packet switching'" Proc･ hfocom, March 1989.

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