1996 CUG Presentation Nonblocking Assigns

7/27/2019 1996 CUG Presentation Nonblocking Assigns

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Understanding Verilog BlockingUnderstanding Verilog Blockingand Nonand Non--blocking Assignmentsblocking Assignments

International CadenceInternational Cadence

User Group ConferenceUser Group Conference

September 11, 1996September 11, 1996

presented bypresented by

Stuart SutherlandStuart Sutherland

Suther l and HDL Consul t ingSuther l and HDL Consul t ing


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The material in this presentation is copyrighted by Sutherland HThe material in this presentation is copyrighted by Sutherland HDL Consulting,DL Consulting,

Tualatin, Oregon. The presentation is printed with permission aTualatin, Oregon. The presentation is printed with permission as part of thes part of the

proceedings of the 1996 International Cadence User Group Confereproceedings of the 1996 International Cadence User Group Conference. All rightsnce. All rights

are reserved. No material from this presentation may be duplicaare reserved. No material from this presentation may be duplicated or transmitted byted or transmitted by

any means or in any form without the express written permissionany means or in any form without the express written permission of Sutherland HDLof Sutherland HDL

Consulting.Consulting.

copyright noticecopyright notice

Sutherland HDL ConsultingSutherland HDL Consulting

22805 SW 9222805 SW 92ndnd

PlacePlace

Tualatin, OR 97062 USATualatin, OR 97062 USA

phone: (503) 692phone: (503) 692--08980898

fax: (503) 692fax: (503) 692--15121512

ee--mail: info@mail: [email protected]

19961996


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Suther l andSuther l andSuther l and

HHH

DDD LLLObjectivesObjectivesObjectives

The primary objective is to understand:The primary objective is to understand:

What type of hardware is representedWhat type of hardware is represented

by blocking and nonby blocking and non--blockingblockingassignments?assignments?

The material presented is a subset of an advanced VerilogThe material presented is a subset of an advanced Verilog

HDL training courseHDL training course


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Suther l andSuther l andSuther l and

HHH

DDD LLLProcedural AssignmentsProcedural AssignmentsProcedural Assignments

Procedural assignment evaluation can be modeled as:Procedural assignment evaluation can be modeled as:

BlockingBlocking NonNon--blockingblocking

Procedural assignment execution can be modeled as:Procedural assignment execution can be modeled as: SequentialSequential

ConcurrentConcurrent

Procedural assignment timing controls can be modeled as:Procedural assignment timing controls can be modeled as:

Delayed evaluationsDelayed evaluations

Delayed assignmentsDelayed assignments


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Suther l andSuther l andSuther l andHHH

DDD LLL

Blocking

Procedural Assignments

BlockingBlocking

Procedural AssignmentsProcedural Assignments

TheThe == token represents atoken represents a block ing b lock ing procedural assignmentprocedural assignment

Evaluated and assigned in a single stepEvaluated and assigned in a single step Execution flow within the procedure is blocked until theExecution flow within the procedure is blocked until the

assignment is completedassignment is completed

Evaluations of concurrent statements in the same time stepEvaluations of concurrent statements in the same time stepare blocked until the assignment is completedare blocked until the assignment is completed

These examples willThese examples will notnotworkwork Why not?Why not?

//swap bytes in wordalways @(posedge clk)

begin

word[15:8] = word[ 7:0];

word[ 7:0] = word[15:8];

end

//swap bytes in word

always @(posedge clk)

begin

word[15:8] = word[ 7:0];

word[ 7:0] = word[15:8];

end

//swap bytes in wordalways @(posedge clk)

fork

word[15:8] = word[ 7:0];

word[ 7:0] = word[15:8];

join

//swap bytes in word


fork

word[15:8] = word[ 7:0];

word[ 7:0] = word[15:8];

join


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DDD LLL

Non-Blocking


NonNon--BlockingBlocking


TheThe


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DDD LLL

Representing

Simulation Time as Queues

RepresentingRepresenting

Simulation Time as QueuesSimulation Time as Queues

Each Verilog simulation time step is divided into 4 queuesEach Verilog simulation time step is divided into 4 queues

Note: this is an abstract view, not how simulation algorithms arNote: this is an abstract view, not how simulation algorithms are implementede implemented

Time 0:Q1 (in any order) :

Evaluate RHS of all non-blocking assignments Evaluate RHS and change LHS of all blocking assignments Evaluate RHS and change LHS of all continuous assignments

Evaluate inputs and change outputs of all primitives Evaluate and print output from $display and $write

Q2 (in any order) : Change LHS of all non-blocking assignments

Q3 (in any order) :

Evaluate and print output from $monitor and $strobe Call PLI with reason_synchronize

Q4 : Call PLI with reason_rosynchronize

Time 1:

...

Time 0:

Q1 (in any order) : Evaluate RHS of all non-blocking assignments Evaluate RHS and change LHS of all blocking assignments Evaluate RHS and change LHS of all continuous assignments Evaluate inputs and change outputs of all primitives Evaluate and print output from $display and $write

Q2 (in any order) : Change LHS of all non-blocking assignments

Q3 (in any order) : Evaluate and print output from $monitor and $strobe Call PLI with reason_synchronize

Q4 : Call PLI with reason_rosynchronize

Time 1:

...


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DDD LLL

Sequential


SequentialSequential


The order of evaluation isThe order of evaluation is determinatedeterminate AA sequential blocking assignmentsequential blocking assignment evaluates and assignsevaluates and assigns

before continuing on in the procedurebefore continuing on in the procedure

always @(always @(posedge clkposedge clk))

beginbegin

AA

==

1;1;

#5 B#5 B == A + 1;A + 1;

endend

evaluate and assign A immediatelyevaluate and assign A immediatelydelay 5 time units, then evaluate and assigndelay 5 time units, then evaluate and assign

AA sequential nonsequential non--blocking assignmentblocking assignment evaluates, thenevaluates, then

continues on to the next timing control before assigningcontinues on to the next timing control before assigningalways @(always @(posedge clkposedge clk))

beginbegin

AA


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DDD LLL

Concurrent


ConcurrentConcurrent


The order of concurrent evaluation isThe order of concurrent evaluation is indeterminateindeterminate

ConcurrentConcurrent blocking assignmentsblocking assignments havehave unpredictable resultsunpredictable resultsalways @(always @(posedge clkposedge clk))

#5 A#5 A == A + 1;A + 1;

always @(always @(posedge clkposedge clk))#5 B#5 B == A + 1;A + 1;

Unpredictable Result:Unpredictable Result:

(new value of(new value ofBB could be evaluated beforecould be evaluated before

or afteror after

AA

changes)changes)

ConcurrentConcurrent nonnon--blocking assignmentsblocking assignments havehave predictable resultspredictable results


#5 A#5 A


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DDD LLL

Delayed Evaluation


Delayed EvaluationDelayed Evaluation


A timing control before an assignment statement will postponeA timing control before an assignment statement will postponewhen the next assignment is evaluatedwhen the next assignment is evaluated

Evaluation is delayed for the amount of time specifiedEvaluation is delayed for the amount of time specified

beginbegin#5#5 AA == 1;1;

#5#5 AA == A + 1;A + 1;

BB == A + 1;A + 1;

endend

delay for 5, then evaluate and assigndelay for 5, then evaluate and assigndelay 5 more, then evaluate and assigndelay 5 more, then evaluate and assignno delay; evaluate and assignno delay; evaluate and assign

What values do A and B contain after 10 time units?What values do A and B contain after 10 time units?


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DDD LLL

Delayed Assignment


Delayed AssignmentDelayed Assignment


AnAn intraintra--assignment delayassignment delayplaces the timing controlplaces the timing control afterafterthetheassignment tokenassignment token

The rightThe right--hand side is evaluated before the delayhand side is evaluated before the delay

The leftThe left--hand side is assigned after the delayhand side is assigned after the delay

always @(A)always @(A)

BB == #5#5 A;A;

AA is evaluated at the time it changes, butis evaluated at the time it changes, but

is not assigned tois not assigned to BB until after 5 time unitsuntil after 5 time units

always @(always @(negedge clknegedge clk))

QQ


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DDD LLL

Intra-Assignment Delays

With Repeat Loops

IntraIntra--Assignment DelaysAssignment Delays

With Repeat LoopsWith Repeat Loops

An edgeAn edge--sensitive intrasensitive intra--assignment timing control permits aassignment timing control permits aspecial use of the repeat loopspecial use of the repeat loop

The edge sensitive time control may be repeated severalThe edge sensitive time control may be repeated severaltimes before the delay is completedtimes before the delay is completed

Either the blocking or the nonEither the blocking or the non--blocking assignment may beblocking assignment may be

usedused

always @(IN)

OUT


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DDD LLL

Choosing the

Correct Procedural Assignment

Choosing theChoosing the

Correct Procedural AssignmentCorrect Procedural Assignment

Which procedural assignment should be used to model aWhich procedural assignment should be used to model acombinatorial logic buffer?combinatorial logic buffer?

Which procedural assignment should be used to model aWhich procedural assignment should be used to model asequential logic flipsequential logic flip--flop?flop?

The following pages will answer these questionsThe following pages will answer these questions

always @(in)#5 out = in;

always @(in)#5 out


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DDD LLL

Transition

Propagation Methods

TransitionTransition

Propagation MethodsPropagation Methods

Hardware has two primary propagation delay methods:Hardware has two primary propagation delay methods:

Inertial delayInertial delay models devices with finite switching speeds;models devices with finite switching speeds;input glitches do not propagate to the outputinput glitches do not propagate to the output

Transport delayTransport delay models devices with near infinitemodels devices with near infiniteswitching speeds; input glitches propagate to the outputswitching speeds; input glitches propagate to the output

20 6050403010 20 6050403010

Buffer with a 10 nanosecond propagation delay

20 6050403010 20 6050403010

Buffer with a 10 nanosecond propagation delay


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DDD LLL

Combinational Logic


Combinational LogicCombinational Logic


How will these procedural assignments behave?How will these procedural assignments behave?20 6050403010

inin3333 3636 4545

always @(in)always @(in)

o1o1 == in;in;Blocking,Blocking,

No delayNo delay

always @(in)always @(in)o2o2


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DDD LLL

Sequential Logic


Sequential LogicSequential Logic


How will these procedural assignments behave?How will these procedural assignments behave?

Sequential assignmentsSequential assignments No delaysNo delays

20 6050403010

clk


beginbeginy1y1 == in;in;

y2y2 == y1;y1;

endend


beginbegin

y1y1


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DDD LLL

Sequential Logic





Sequential assignmentsSequential assignments Delayed evaluationDelayed evaluation

20 6050403010

clk


beginbegin#5#5 y1y1 == in;in;

#5#5 y2y2 == y1;y1;

endend


beginbegin

#5#5 y1y1


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DDD LLL

Sequential Logic





Sequential assignmentsSequential assignments Delayed assignmentDelayed assignment

20 6050403010

clk


beginbeginy1y1 = #5= #5 in;in;

y2y2 = #5= #5 y1;y1;

endend


beginbegin

y1y1


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DDD LLL

Sequential Logic





Concurrent assignmentsConcurrent assignments No delaysNo delays

y1

y2

20 6050403010

clk


y1y1 == in;in;


y2y2 == y1;y1;

y1

y2


y1y1


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DDD LLL

y2

y1

Sequential Logic





Concurrent assignmentsConcurrent assignments Delayed evaluationDelayed evaluation

20 6050403010

clk


#5#5 y1y1 == in;in;


#5#5 y2y2 == y1;y1;


#5#5 y1y1


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DDD LLL

Sequential Logic





Concurrent assignmentsConcurrent assignments Delayed assignmentDelayed assignment

20 6050403010

clk


y1y1 = #5= #5 in;in;


y2y2 = #5= #5 y1;y1;


y1y1


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DDD LLL

Rules of Thumb for


Rules of Thumb forRules of Thumb for


Combinational Logic:Combinational Logic:

No delays:No delays: Use blocking assignments (Use blocking assignments ( a = b;a = b; )) Inertial delays:Inertial delays: Use delayed evaluation blockingUse delayed evaluation blocking

assignments (assignments ( #5 a = b;#5 a = b; ))

Transport delays:Transport delays: Use delayed assignment nonUse delayed assignment non--blockingblockingassignments (assignments ( a


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DDD LLL

An Exception to Non-blocking

Assignments in Sequential Logic

An Exception to NonAn Exception to Non--blockingblocking

Assignments in Sequential LogicAssignments in Sequential Logic

DoDo notnot use a nonuse a non--blocking assignment if another statement inblocking assignment if another statement inthe procedure requires the new value in the same time stepthe procedure requires the new value in the same time step

begin

#5 A


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DDD LLL

Exercise 3:


Exercise 3:Exercise 3:


Write a procedure for an adder (combinational logic) thatWrite a procedure for an adder (combinational logic) thatassigns C the sum of A plus B with a 7ns propagation delay.assigns C the sum of A plus B with a 7ns propagation delay.

Write the procedure(s) for a 4Write the procedure(s) for a 4--bit wide shift register (positivebit wide shift register (positiveedge triggered) of clock and has a 4ns propagation delay.edge triggered) of clock and has a 4ns propagation delay.

always @(A or B)

#7 C = A + B;

always @(A or B)

#7 C = A + B;


begin

y1


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DDD LLL

Exercise 3 (continued):


Exercise 3 (continued):Exercise 3 (continued):


Write a Verilog procedure for a black box ALU pipeline thatWrite a Verilog procedure for a black box ALU pipeline thattakes 8 clock cycles to execute an instruction. The pipelinetakes 8 clock cycles to execute an instruction. The pipelinetriggers on the positive edge of clock. The black box istriggers on the positive edge of clock. The black box isrepresented as call to a function named ALU with inputs A, Brepresented as call to a function named ALU with inputs A, Band OPCODE.and OPCODE.


alu_out

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1996 CUG Presentation Nonblocking Assigns