Int. J. Electron. Commun. (AEÜ) 96 (2018) 238–245

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International Journal of Electronics andCommunications (AEÜ)

journal homepage: www.elsevier .com/locate /aeue

Regular paper

A New Design Methodology for Time-Based Capacitance-to-DigitalConverters (T-CDCs)

https://doi.org/10.1016/j.aeue.2018.09.0341434-8411/� 2018 Elsevier GmbH. All rights reserved.

⇑ Corresponding author.E-mail addresses: ali.h.hassan@ieee.org (A.H. Hassan), hmostafa@uwaterloo.ca

(H. Mostafa), khaled.salama@kaust.edu.sa (K.N. Salama), asoliman@ieee.org(A.M. Soliman).

Ali H. Hassan a,⇑, Ahmed Fouad b, Hassan Mostafa a,c, Khaled N. Salama d, Ahmed M. Soliman a

a Electronics and Communications Engineering Department, Cairo University, Giza 12613, Egyptb Electronics and Communication Engineering Department, Ain Shams University, Cairo 1153, EgyptcNanotechnology and Nanoelectronics Program, Zewail City of Science and Technology, Sheikh Zayed, 12588, EgyptdKing Abdullah University of Science and Technology (KAUST), Computer, Electrical and Mathematical Science and Engineering Division (CEMSE), Thuwal 23955-6900, Saudi Arabia

a r t i c l e i n f o

Article history:Received 1 April 2018Accepted 23 September 2018

Keywords:Low-powerCMOS scalingEnergy efficientCapacitance-to-digital converter (CDC)Time-basedPulse width modulation (PWM)Capacitive sensorPressure sensorMEMS pressure sensor

a b s t r a c t

This paper introduces a 9-bit time-based capacitance-to-digital converter (T-CDC). This T-CDC adopts anew design methodology for parasitic cancellation with a simple calibration technique. In T-CDCs, theinput sensor capacitance is first converted into a delay pulse using a capacitance-to-time converter(CTC) circuit; then this delay signal is converted into a digital code through a time-to-digital converter(TDC) circuit. A prototype of the proposed T-CDC is implemented in UMC 0.13 lm CMOS technology.This T-CDC consumes 8.42 lW and achieves a maximum SNR of 45.14 dB with a conversion time of1 ls that corresponds to a figure of merit (FoM) of 16.4 fJ/Conv.

� 2018 Elsevier GmbH. All rights reserved.

1. Introduction

Capacitive sensors cover a wide range of applications includingpressure sensing [1], gas sensing [2], displacement sensing [3],and lab-on-chip [4,5]. Over time, multiple design techniques areintroduced for capacitive sensor readout circuits, that is also knownas capacitance-to-digital converters (CDCs). Previously, CDC isformed by capacitance-to-voltage converter (C/V) followed byanalog-to-digital converter (ADC). However, the C/V circuit is apower-hungry circuit so it is not energy efficient for smart sensors.Now, multiple techniques appear to merge the C/V with ADC toform CDC circuit that is energy efficient such as Dual-Slope CDC[1], Multi-Slope CDC [2], SAR-CDC [6],RD CDCs [7], SAR+ RD CDCs[8], SAR+VCO CDC [9], PM CDC [10], and Delay-Chain CDC [11].

With CMOS technology continues scaling, the design of cas-coded analog blocks is facing several challenges such as scalingration between the supply voltage and threshold voltage, currentleakage, and matching [12]. However, the digital domain is taking

all privileges such as speed boosting, subthreshold operation [13].In time-based capacitance-to-digital converters (T-CDCs) [10,14],the input capacitance is first converted to a pulse delay time byusing a capacitance-to-time Converter (CTC) circuit, and then thepulse delay time is digitized using a time-to-digital converter(TDC) circuit as portrayed in Fig. 1. The CTC circuit can be referredto as either a pulse position modulator (PPM) or pulse width mod-ulator (PWM), depending on whether the delay is applied to one orboth edges of the input clock pulses. The TDC circuit consists ofdigital logic and counter circuits [15].

Basically, T-CDC moves the conversion process from the analogdomain into the digital domain. This conversion is done by con-verting the input capacitance coming either from sensor or trans-ducer into the time domain through the CTC circuit.Consequently, all the analog pre-processing blocks are removed.Accordingly, the signal is converted into the time domain and pro-cessed by all digital TDC circuit. Processing the signal in the timedomain results in decreasing the power consumption tremen-dously, while preserving high accuracy and resolution. Moreover,this T-CDC gets the full benefit from the time resolution wherethe time resolution improves as technology node scales. In thispaper, a new design methodology for T-CDCs is proposed. This

Capacitance-to-Time

Converter (CTC)

Time-to-Digital

Converter (TDC)

Sensor

Out

put B

it St

ream

01 .

. . .

. . .

10

Fig. 1. Time-based capacitive-to-digital converter block diagram.

Pa1

Na1

CLK Vout

VDD

CL

Fig. 2. CMOS inverter circuit schematic.

CLK

PWM

NMOS-based Current Starved

Inverter

Vn

CrefCs

CALSEN

PMOS-based Current Starved

Inverter

Vp

M 9-BitTDC

Circuit

B0B1B2

B8

CLK

PWM

PMOS-based Current Starved

Inverter

Vp

CrefCs

CALSEN

NMOS-based Current Starved

Inverter

Vn

M 9-BitTDC

Circuit

B0B1B2

B8

CLK

PPM

NMOS-based Current Starved

Inverter

Vn

CrefCs

CALSEN

NMOS-based Current Starved

Inverter

Vnr

9-BitTDC

Circuit

B0B1B2

B8

CLK

PPM

PMOS-based Current Starved

Inverter

Vp

CrefCs

CALSEN

PMOS-based Current Starved

Inverter

Vpr

9-BitTDC

Circuit

B0B1B2

B8

Fig. 3. Four configurations of the proposed T-CDC: (a) CsNMOS-PMOS; (b) CsPMOS-NMOS; (c) CsNMOS-NMOS;and, (d) CsPMOS-PMOS.

A.H. Hassan et al. / Int. J. Electron. Commun. (AEÜ) 96 (2018) 238–245 239

DC_BiasPb2

Pb1

Nb1

CLK Vout

VDD

DC_Bias

Pa1

Na1

Na2

CLK Vout

VDD

Fig. 4. Current Starved Inverter (CSI) Configuration: (a) PMOS-based CSI;and, (b)NMOS-based CSI.

CLK_

INV

P-CS

IN

-CSI

TG-S

witc

hes

MIM-Ref Capacitor

XNOR

CLK_

INV

N-C

SIP-

CSI

TG-S

witc

hes

MIM-Ref Capacitor

XNOR

CLK_

INV

N-C

SIN

-CSI

TG-S

witc

hes

MIM-Ref Capacitor

XOR

CLK_

INV

P-CS

IP-

CSI

TG-S

witc

hes

MIM-Ref Capacitor

XOR

Fig. 5. Circuit layout of the proposed T-CDC Configurations: (a) CsNMOS-PMOS; (b)CsPMOS-NMOS; (c) CsNMOS-NMOS;and, (d) CsPMOS-PMOS.

240 A.H. Hassan et al. / Int. J. Electron. Commun. (AEÜ) 96 (2018) 238–245

T-CDC improves both linearity and conversion sensitivity.Furthermore, the proposed methodology portrays less area, morespeed, and better energy efficiency.

Applying a clock signal, donated by CLK, on the basic CMOSinverter circuit, shown in Fig. 2, corresponds to a propagation delaytime through either rising or falling edge that is donated by Tp thatis modeled by [16]:

Tp / CL � VDD

Icð1Þ

where CL is the load capacitance, Ic is the charging/discharging cur-rent, and VDD is the supply voltage. From Eq. (1), it is noticed thatthe delay of the CMOS inverter varies by controlling the value ofCL; Ic , or VDD [16].

This paper is organized as follows: In Section 2, the proposeddesign methodology, as well as the circuit implementation, are dis-cussed. Moreover, the circuit layout and post-layout simulationresults are presented in Section 3. Finally, Section 4 concludes thispaper.

2. Proposed T-CDC Architecture

The adopted CTC methodology, shown in Fig. 3, has two modesof operation as follows:

1. Calibration mode where the dc biasing voltage, donated byDC_Bias, is tuned to match the output delay of the proposedT-CDC with the corresponding reference delay in nominal con-ditions. And this reference delay is controlled by connecting anon-chip reference capacitor (Cref ). To save the implementationarea of the calibration circuit: an active capacitor implementa-tion can be adopted similar to [17–20].

2. Sensing mode where the reference capacitor is disconnectedwhile the sensor capacitor is connected to control the outputdelay of the proposed T-CDC.

For the shown Fig. 3(a): it consists of two current starvedinverters (CSI) where the output signals of two CSIs are connectedto an XNOR gate. The PMOS-based CSI, shown in Fig. 4(a), controlsthe rising time, donated by Tr , that corresponds to the parasiticcapacitance (Cp), that is given by Eq. (2). And the NMOS-basedCSI, shown in Fig. 4(b), controls the falling time, donated by Tf thatcorresponds to the sensor capacitance (Cs) in addition to Cp, whichis given by Eq. (3).

Tr ¼ Cp � ðVDD � VMÞIr

ð2Þ

Tf ¼ ðCs þ CpÞ � ðVDD � VMÞIf

ð3Þ

DT ¼ Dþ Tr � Tf ¼ Cs � ðVDD � VMÞIc

ð4Þ

Moreover, the XNOR output, donated by PWM, acts as a sub-tractor for the two cells represents the pulse width (DT) that corre-sponds only to Cs as shown in Eq. (4). The XNOR-gate output signalconsists of two pulses. The first pulse width equals Dþ Tr � Tf

where D is the inverter delay line delay. The second pulse exhibitsa fixed pulse width of D that is independent of Cs [21]. This CTC cir-cuit is followed by a 9-bit ideal TDC circuit that digitizes the firstpulse width, that is controlled by Cs, into a digital word and ignoresthe second pulse (i.e., the pulse of width D). The choice of D isessential to have the first pulse width always larger than zero atall design corners. Correspondingly, the delay D is given by (5):

D ¼ min½ðTf ;max � Tr;minÞ;0� þH ð5Þwhere Tf ;max is the maximum expected falling delay of the NMOS-based CSI, Tr;min is the minimum expected rising delay of the

A.H. Hassan et al. / Int. J. Electron. Commun. (AEÜ) 96 (2018) 238–245 241

PMOS-based CSI, and H is a safety margin which is selected in thisdesign to be the delay of one minimum-size CMOS inverter [21].Finally, the adopted methodology is extended for four different con-figurations as portrayed in Fig. 3.

3. Post-Layout Simulations and Discussions

A prototype of the proposed T-CDC architecture is implementedusing hardware-calibrated UMC 0.13 lm CMOS technology. Usinga 1.0 V supply voltage, 0.5 V dc biasing voltage and Cref ¼ 500 fF:the proposed T-CDC prototype is simulated and verified usingCadence Virtuoso.

3.1. Circuit Layout

The circuit layout of the proposed T-CDC configurations isshown in Fig. 5 where the main design blocks are highlighted.

bin

DN

L [in

LS

B]

-1

0

1

2

avg=0.002, std.dev=0.047, range=0.36

bin

INL

[in L

SB

]

-1

0

1

2

avg=-7.4e-18, std.dev=0.26, range=1.1

bin

DN

L [in

LS

B]

-1

0

1

2

avg=0.002, std.dev=0.088, range=0.23

bin

INL

[in L

SB

]

-1

0

1

2

avg=2e-16, std.dev=0.29, range=1.2

50 100 150 200 250 300 350 400 450 500

50 100 150 200 250 300 350 400 450 500

50 100 150 200 250 300 350 400 450 500

50 100 150 200 250 300 350 400 450 500

Fig. 6. Simulated DNL/INL for the proposed T-CDC Configurations: (a) CsNMO

The active core area of the four configurations is 1577 lm2,1577 lm2, 1463 lm2, and 1463 lm2, respectively, where the refer-ence capacitor occupies approximately 56–61%.

3.2. Linearity

Fig. 6 shows the simulated DNL and INL of the T-CDC configura-tions, where the maximum absolute value is as follows: (1) Config-uration 1 (CsNMOS-PMOS): �0.24 LSB and �0.61 LSB, respectively,(2) Configuration 2 (CsPMOS-NMOS): 0.13 LSB and �0.54 LSB,respectively, Configuration 3 (CsNMOS-NMOS): 0.14 LSB and�0.66 LSB, respectively, and Configuration 4 (CsPMOS-PMOS):0.19 LSB and �0.64 LSB, respectively. Finally, the standard devia-tion (std) of DNL over 5120 point while sweeping the full inputcapacitance range equals 0.047, 0.09, 0.088, and 0.078, respectivelywhile the std of INL equals 0.26, 0.25, 0.29, and 0.28, respectively.

bin

DN

L [in

LS

B]

-1

0

1

2

avg=0.002, std.dev=0.09, range=0.23

bin

INL

[in L

SB

]

-1

0

1

2

avg=-6.3e-17, std.dev=0.25, range=1

bin

DN

L [in

LS

B]

-1

0

1

2

avg=0.002, std.dev=0.078, range=0.24

bin

50 100 150 200 250 300 350 400 450 500

50 100 150 200 250 300 350 400 450 500

50 100 150 200 250 300 350 400 450 500

50 100 150 200 250 300 350 400 450 500

INL

[in L

SB

]

-1

0

1

2

avg=6.5e-17, std.dev=0.28, range=1.2

S-PMOS; (b) CsPMOS-NMOS; (c) CsNMOS-NMOS;and, (d) CsPMOS-PMOS.

Csense(pF)

nois

e(fF)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Csense(pF)

nois

e(fF)

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

Csense(pF)

nois

e(fF)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Csense(pF)

0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5

0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5

nois

e(fF)

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Fig. 7. RMS-noise of the proposed T-CDC Configurations Vs sensor capacitance (Cs): (a) CsNMOS-PMOS; (b) CsPMOS-NMOS; (c) CsNMOS-NMOS;and, (d) CsPMOS-PMOS.

242 A.H. Hassan et al. / Int. J. Electron. Commun. (AEÜ) 96 (2018) 238–245

3.3. Jitter Analysis

A nonlinear periodic noise simulation, similar to [22], is per-formed to determine the noise performance of the proposed T-CDC at various sensor capacitances. Fig. 7 shows the simulated T-CDC output code standard deviation (rms noise) over 1000 sampleper each input versus different sensor capacitances. The simulationresults show that the rms noise is limited by the quantization noiseof the T-CDC.

3.4. Power Consumption

Fig. 8 shows the total power consumption for the four T-CDCconfigurations, where the power consumption increases linearlywith increasing the sensor capacitance Cs. Finally, the power con-sumption distribution is as follows: 96.5% of the power is con-sumed in the current starved inverters while the rest of power isconsumed in digital circuitry.

3.5. Calibration

Fig. 9 shows the output delay of the proposed CTC circuit versustemperature variation, supply variation, and process variation,receptively. Fig. 9(a) shows that there is no need for calibrationwith temperature variation. However, there is an output delay mis-match due to supply variation that is calibrated by DC biasing asshown in Fig. 9(b). Finally, Fig. 9(c) shows the mismatch due toprocess variation that is calibrated by changing dc biasing voltagetoo as highlighted.

3.6. Summary and Discussions

Table 1 presents a performance summary of the four configura-tions of the proposed T-CDC. It is obvious that the sensitivitydepends on where the sensor capacitor is connected to eitherPMOS-based CSI or NMOS-based CSI. For example, the fourth con-figuration has the highest sensitivity as both branches are PMOS-based CSI followed by the second configuration. However, the sen-

Csense(pF)

Pow

er(µ

W)

0

1

2

3

4

5

6

7

8

9

Csense(pF)

Pow

er(µ

W)

0

1

2

3

4

5

6

7

8

9

Csense(pF)

Pow

er(µ

W)

0

1

2

3

4

5

6

7

8

9

10

Csense(pF)

0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5

0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5

Pow

er(µ

W)

0

1

2

3

4

5

6

7

8

9

Fig. 8. Total power consumption for T-CDC Configurations Vs sensor capacitance (Cs): (a) CsNMOS-PMOS; (b) CsPMOS-NMOS; (c) CsNMOS-NMOS; and, (d) CsPMOS-PMOS.

A.H. Hassan et al. / Int. J. Electron. Commun. (AEÜ) 96 (2018) 238–245 243

sitivity is almost constant for the other two configurations that arebased on NMOS-based CSI. PMOS-based CSI has a higher sensitivityas it has a lower current driving capability which increases thedelay that corresponds to the same capacitance range.

Table 2 shows a performance comparison of the proposed T-CDC with the state-of-the-art CDCs with a resolution higher than7-bits. For a fair comparison: the figure-of-merit (FoM) defined inEq. (6) by [11,10] is used:

FoM ¼ P � Tconv

2N ð6Þ

Where P is the power consumption, Tconv is the conversion time, andN is the effective resolution in bits, that is calculated by Eq. (7):

N ¼ SNR� 1:766:02

ð7Þ

Where the signal-to-noise ratio (SNR) is given by:

SNR ¼ 20LogðCapacitanceRange=2ffiffiffi2

p

AbsoluteResolutionÞ ð8Þ

Where the absolute resolution is the rms capacitance resolution.The proposed T-CDC achieves an effective resolution of 9-bit anda FoM of 16.4 fJ/Conv.

In this paper, the implementation area of the proposed T-CDC islower than that in [10,8,9,11,23] by factors of 33X, 304X, 22X, 1.1X,and 36X, respectively. However, the power consumption of theproposed T-CDC is higher than [11]. Since the delay chain-basedarchitecture [11] is implemented in 40 nm technology with supplyscaling down to 0.4 V. Finally, the proposed T-CDC is insensitive tothe temperature variations, while the mismatch results from bothprocess and voltage variation are calibrated by varying DC biasingvoltage.

4. Conclusion

Using a 1.0 V supply and 0.13 lm CMOS process technology, alow-power 9-bit T-CDC is introduced. The proposed T-CDCachieves an energy efficiency of 16.4 fJ/Conv which is two timesbetter than the state-of-the-art. Moreover, this T-CDC is easily cal-

Csense(pF)

Tpp

m(n

s)

0

50

100

150

200

250

Csense(pF)

Tpp

m(n

s)

0

50

100

150

200

2501V0.9V1.1V0.9V with DC=0.48V1.1V with DC=0.52V

Csense(pF)

0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3

0 0.5 1 1.5 2 2.5 3

Tpp

m(n

s)

0

50

100

150

200

250ttssffss @ 0.59Vff @ 0.43V

Fig. 9. Output Delay of T-CDC Configuration (CsNMOS-PMOS) Vs sensor capacitance (Cs): (a) Output Delay Vs sensor capacitance (Cs) with Temperature Variations; (b)Output Delay Vs sensor capacitance (Cs) with Supply Variations;and, (c) Output Delay Vs sensor capacitance (Cs) with Process Variations.

Table 1A performance summary of the proposed T-CDC configurations.

Reference CsNMOS-PMOS CsPMOS-NMOS CsNMOS-NMOS CsPMOS-PMOS

Architecture PWM PWM PPM PPMSupply Voltage (V) 1.0 1.0 1.0 1.0Input Range (pF) 0.2–2.9 0.2–2.5 0.2–3.2 0.2–2.4Abs. Cap. (fFrms) 5.3 4.5 5.86 4.3

SNR (dB) 45.11 45.13 45.15 45.14Conv. Time (ms) 0.001 0.001 0.001 0.001Sensitivity (ns/pF) 74.7 90.7 74.7 98.1

Powerb (lW) 8.63 8.67 9.28 8.42DNL (LSB) �0.24/0.12 �0.09/0.13 �0.09/0.14 �0.05/0.19INL (LSB) �0.61/0.46 �0.54/0.46 �0.66/0.51 �0.64/0.52

Area ðlm2Þ 1577a 1577 1463a 1463a

FoM (fJ/Conv) 16:8a 16:9a 18:1a 16:4a

a Power consumption and area of time-to-digital converter are not included.b Power consumption is calculated at the maximum input capacitance.

244 A.H. Hassan et al. / Int. J. Electron. Commun. (AEÜ) 96 (2018) 238–245

Table 2A comparison between this work and state-of-the-art CDCs.

Reference [10] [8] [9] [11] [23] This Work (CsPMOS-PMOS)

Architecture PWM SAR+P

D SAR + VCO Delay-Chain SAR PPMTechnology (lm) 0.16 0.18 0.04 0.04 0.18 0.13Supply Voltage (V) 1.0 1.4 1 0.45/1.0 0.8/1.2 1.0Input Range (pF) 8 24 5 0.7–11.3 12.66 2.2Abs. Cap. (fFrms) 1.4 0.16 1.1 12:3d 1.2 4.3

SNR (dB) 65.5 94.7 64.2 49.7 71.6 45.14Conv. Time (ms) 0.21 0.23 0.001 0.019 0.016 0.001Powerb (lW) 14 33.7 75 1:84d 6.44 8.42Area ðmm2Þ 0:05a,c 0.456 0.034 0.0017 0.055 0:0015a

Simulated/Measured Measured Measured Measured Measured Measured Post-LayoutFoM (fJ/Conv) 1870a 175 55 141 33 16:4a

a Power consumption and area of time-to-digital converter are not included.b Power consumption is calculated at the maximum input capacitance.c Power Off-chip reference capacitor is employed.d Power Measured when sensing 11.3 pF capacitance w/o parasitic cancellation or calibration.

A.H. Hassan et al. / Int. J. Electron. Commun. (AEÜ) 96 (2018) 238–245 245

ibrated versus process, supply voltage, and temperature variations.The proposed T-CDC tackles the challenges of low-voltage opera-tion in modern CMOS technologies. Furthermore, the proposedstructure is advantageous in deep-submicron technology com-pared to voltage-based CDCs. Finally, this T-CDC is well suited forbiosensors-CMOS platforms that are used for in vitro diagnostic.

Acknowledgment

A preliminary version of this work is published in ICM 2017conference [14]. This research was partially funded by ONE Labat Cairo University, Zewail City of Science and Technology, andKing Abdullah University of Science and Technology (KAUST).

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