A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits

A New Approach forAutomatic Test PatternGeneration in RegisterTransfer Level CircuitsMohammad Mirzaei and Mahmoud Tabandeh

Sharif University of TechnologyBijan Alizadeh and Zainalabedin Navabi

University of Tehran

h IN THIS PAPER, we propose an approach to

generate high-level test patterns from the arithmetic

model of a register-transfer-level (RTL) circuit using

a hybrid canonical data structure based on a deci-

sion diagram. High-level simplified and fast sym-

bolic path activation strategy as well as input

justification is combined with test pattern genera-

tion for circuits under consideration. The current

approach has been implemented for a range of

small to large benchmark circuits. The results clearly

demonstrate that tests generated using the proposed

method have achieved high fault coverage for

known sequential circuit benchmarks in very short

central processing unit (CPU) time and minimum

memory usage.

High fault coverage achievement has tradition-

ally been the main objective of the test development

techniques. As these techniques have matured and

this objective has been attained, other objectives

have become important. Decreasing test generation

and application time as

well as test data volume

are among other such ob-

jectives being pursued. Al-

though the design flow is

moving toward higher

levels of abstraction, auto-

matic test pattern generation (ATPG) and also

design-for-testability (DFT) tools are based on gate-

level techniques. The use of DFT features, such as

scan and built-in-self-test, further exacerbates the

problem.

In order to improve this problem, several ATPG

approaches have been proposed for detecting func-

tional faults. It is shown that test generation is

nonpolynomial (NP complete) [1]. However, obser-

vations show that the test generation complexity of

practically encountered combinational circuits is

polynomial [2]. Also, different techniques for solv-

ing the problem of generating tests for functional

faults have been proposed.

For simplification of a test procedure, some ATPG

approaches have been introduced based on binary

decision diagram (BDD) tools [3]. Since these

methods require the design to be flattened into the

bit level, they cannot be used to deal with large

industrial benchmarks efficiently, either in terms of

memory or runtime. Evolutionary algorithmic

methods used in [4]–[6] are better than the fully

random-based method used in state-of-the-art ATPG

approaches. However, they are not very robust

Editor’s notes:The authors propose a hybrid, canonical representation for high-level testgeneration of arithmetic and RTL circuits.

VMichael Hsiao, Virginia Tech

2168-2356/13 B 2013 IEEEJuly/August 2013 Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC 49

Digital Object Identifier 10.1109/MDT.2012.2217471

Date of publication: 06 September 2013; date of current version:

07 November 2013.

methods for generation of test vectors to achieve

the highest coverage. Although these methods can

get good coverage in small and medium designs,

their random nature made these methods poor in

large circuits where the number of inputs and

registers and flipflops increases drastically.

In [7] and [8], we proposed a method based on a

hybrid Boolean-word level canonical representation

named Horner expansion diagram (HED) [9] to

alleviate the aforementioned problems by generat-

ing high-level test vectors for combinational data

paths and control parts.

In this paper, we show our polynomial-based ap-

proach in order to demonstrate robustness of this

method for applying it to RTL circuits as an auto-

matic modeling and test generation methodology.

As illustrated in Figure 1, we obtain a finite state

machine with datapath (FSMD) model [10] from the

RTL code, which helps us to extract the transition

and output polynomial functions (see section

‘‘Polynomial Model of RTL Circuits’’). A fault model

at the behavioral level of abstraction is defined. Fol-

lowing the proposed polynomial model, a process

that is similar to the time frame expansion is pre-

sented which facilitates handling of fault propaga-

tion as well as justification phases to generate test

patterns at a higher level of abstraction (see section

‘‘Polynomial Model of RTL Circuits’’). Finally, by

considering generated high-level test patterns as

constraints and passing them to an SMT solver, we

are able to automatically and efficiently generate

gate-level test patterns. Then, a commercial gate-

level fault simulator is used to estimate gate-level

fault coverage. Experimental results show robust-

ness and reliability of our

method compared to other ap-

proaches in terms of gate-level

fault coverage percentage and

CPU time.

The rest of this paper is or-

ganized as follows. In the next

section, canonical data struc-

ture named HED is introduced

to represent polynomials in the

test generation process. Follow-

ing the proposed representation

structure, we present a method

of obtaining set of polynomials

to make a formal model of an

RTL circuit to extract the transi-

tion and output polynomial functions in the follow-

ing section. A high-level test pattern generation

approach and conversion of patterns to gate-level

ones are demonstrated in section ‘‘High-Level Test

Generation’’ in order to estimate gate-level fault cov-

erage. Experimental setup and results and a brief

conclusion are given in the last two sections.

Hybrid canonical representationIn this section, we introduce our graph-based re-

presentation structure called HED[9] for functions

with a mixed Boolean and integer domain to integer

range for representing arithmetic operations at a high

level of abstraction. In HED, functions to be repre-

sented aremaintained as a single ordered, normalized

and reduced graph in a strongly canonical form.

HED is a binary graph-based representation

which supports the polynomial function by factoriz-

ing higher orders of Taylor series expansion recur-

sively, as shown in

F ðX ; . . .Þ ¼ F ðX ¼ 0; . . .Þ þ X � F 0ðX ¼ 0; . . .Þ þ . . .½ �¼ constþ X � linear; (1)

where const is independent of variable X, while

linear is the coefficient of variable X .

Definition 1. HED is a directed acyclic graph

G ¼ ðVR; EDÞ with vertex set VR and edge set ED.

The vertex set VR consists of two types of vertices:

constant ðCÞ and variable ðV Þ. The edge set only

indicates integer values as weight attributes. A con-

stant node v has as its attribute a value valðvÞ 2 Z. A

variable node v has as attributes a variable varðvÞ andtwo children constðvÞ and linearðvÞ 2 fV ;Cg.

Figure 1. RTL automatic modeling and test generation methodology.

IEEE Design & Test50

A New Approach for Automatic Test Pattern Generation

According to the above def-

inition, a vertex v in the HED

denotes an integer function f v

that has been defined recur-

sively as follows:

1) if v 2 C (is a constant

node), then f v ¼ valðvÞ;2) if v 2 V (is a variable node),

t h e n f v ¼ constðvÞ þvalðvÞ � linearðvÞ.

To normalize the weights,

any common factor is extracted

by taking the greatest common

divisor (GCD) of the argument

weights. In addition, we adopt

the convention that the sign of the extracted weight

matches that of theconst part. This assumes that GCD

always returns a nonnegative value. As long as all

vertices are created, the graph will remain in the

canonical form.

Example 1. Figure 2 illustrates how f ðX ;Y ; ZÞ ¼24� 8� Z þ 12� Y � Z � 6� X2 � 6� X2 � Z i s

represented by HED.

Let the ordering of variables be X > Y > Z. First,

the decomposition with respect to variable X is taken

into account. As shown in Figure 2a, after rewriting

f ðX ;Y ; ZÞ based on (1), const and linear parts will be

ð24�8� Zþ12� Y�ZÞ and ð�6� X � 6� X � ZÞ.The linear part is decomposedwith respect to variable

X again due to X2 term. After that, the decomposition

is performed with respect to variable Y . By rewriting

24�8�Z þ 12� Y � Z¼ð24� 8� ZÞþY�ð12� ZÞ,it can be determined that the const and linear parts of

the left-hand side Y node in Figure 2b are 24� 8� Z

and 12� Z . Finally, the expressions are decomposed

with respect to variable Z and a reduced diagram is

obtained. To reduce the size of a HED, redundant

nodes are removed and isomorphic subgraphs are

merged. For this purpose, the GCD of the argument

weights are taken to figure out isomorphic subgraphs

as well as redundant nodes. In Figure 2b, 24� 8� Z ,

12� Z , and �6� 6� Z are rewritten by 8� ½3þ Z �ð�1Þ�, 12� ½0þ Z� ð1Þ�, and �6� ½1þ Z � ð1Þ�. Inorder to normalize the weights, GCD ð8; 12Þ ¼ 4 and

GCD ð0;�6Þ ¼ þ6 are taken to extract common

factors. Finally, Figure 2c shows the normalized

graph where GCD ð4;�6Þ ¼ 2 is taken to extract a

common factor between outgoing edges from the X

node. In this representation, dashed and solid lines

indicate const and linear parts, respectively. Note

that, in order to have a simpler graph, paths to 0-

terminal have not been drawn in Figure 2c.

In this representation, basic arithmetic operators

such as adders, subtractors, multipliers, divisors,

shifters, and multiplexers are available that work for

symbolic integer variables. In order to represent

Boolean functions, logical bitwise operations in-

cluding NOT, AND, and OR have been provided [9].

Polynomial model of RTL circuitsIn this section, we introduce a formal model for

describing RTL circuits. The polynomial model of an

RTL circuit is a set of algebraic functions that de-

scribe a given circuit based on its datapath or an

FSMD model. The FSMD is formally defined by a

universal specification model, proposed in [10], that

can represent all hardware designs. The objective of

defining the FSMD model is to save considerable

front–end implementation effort since translating

from RTL to an FSMD is a well-known synthesis-like

process.

Definition 2. An FSMD is defined as an octet

M ¼ f ðPI ; S;V ; PO;U ;AR; trans; funcÞ, where:

1) PI is the set of primary input signals;

2) S is the finite set of control states;

3) V is the set of storage variables;

4) PO is the set of primary output signals;

Figure 2. HED representation of 24�8� Zþ12�Y � Z�6�X2�6 �X2 � Z.

July/August 2013 51

5) U ¼ fx( ejx 2 ðPO [ V Þ and e 2 Eg representsa set of storage or output assignments, and E ¼fgðp; q; r; . . .Þjp; q; r; . . . 2 ðPI [ VÞg represents a

set of arithmetic expressions of input and

storage variables over PI [ V ;

6 ) AR ¼ fRða; bÞja; b 2 E ; and R is any arithme-

tic relationg represents a set of status

signals as arithmetic relations between two

expressions;

7) trans : S � AR ! S is the state transition

function;

8) func : S � AR ! U is the update function of the

output and the storage variables.

The state transition functiontrans is a high-level

expression which describes the next state variables

with respect to the present state and the primary

input signals. This function is modeled by a polyno-

mial function so that it can be easily represented

with a decision diagram. When we need to traverse

the FSMD from primary outputs to primary inputs, a

pre-image computation is necessary in order to

compute which previous state is reachable from a

given present state. To do so, the next state variable

in the polynomial model is replaced by the related

value. Finally, a simple polynomial equation should

be solved to find out the values of the present state

and primary input signals. Also, trans and func

functions should be expressed based on a set of

polynomial functions. For this purpose, each state

Sk 2 S is encoded by a polynomial PnðPS; kÞ definedas follows.

Definition 3. Consider an FSMD which has n states,

S ¼ ðS0; S1; . . . ; Sn�1Þ. If one-hot encoding is used,

each present state PS � Sk 2 S ð0 � k � n� 1Þ canbe described as a polynomial PnðPS; kÞ in (2). In

other words, after replacing PS in (2) by 2k; PnðPS; kÞis computed as 1, and, therefore, we say that

PnðPS; kÞ represents the present state Sk. If PS is

replaced by 2mð0 � m � n� 1;m 6¼ kÞ, then zero

value for ðPS � 2mÞ in

ðPS � SkÞ : PnðPS; kÞ ¼

Qn�1i¼0ðPS � 2iÞ

Qn�1i¼0ð2k � 2iÞ

;

where i 6¼ k (2)

will result PnðPS; kÞ ¼ 0.

According to the concept of Definition 3, the

expression of the transition function transðPS; PIÞ aswell as the output function funcðPS; PIÞ are ex-

pressed in a summation of polynomial functions as

equated in

transðPS; PIÞ ¼Xn�1k¼0

PnðPS; kÞ � ftðPS; PI ; kÞ (3)

funcðPS; PIÞ ¼Xn�1k¼0

PnðPS; kÞ � foðPS; PI ; kÞ (4)

where ftðPS; PI ; kÞ : S � PI � AR ! U and foðPS; PI ;kÞ : S � PI � AR ! U show operations in each state

of the FSMD to generate the next state and output

functions, respectively.

Example 2. Consider the schematic depicted in

Figure 3, the FSMD of which is shown in Figure 4. To

describe the transition functiontrans and the output

function func in terms of the present state PS and

primary input PI , each state is encoded based on an

initial state. The state diagram of this state machine

is shown in Figure 4. Based on Definition 3, each

state has a one-hot code such as reset for the initial

state encoded by 1(0001), and sA, sB, and sC are

encoded by 2(0010), 4(0100), and 8(1000), respec-

tively. Furthermore, by Definition 2, we can extract

PI ; S;V ; PO; E ;U , and AR separately. Primary inputs

and outputs of a circuit can be found from port de-

claration in the circuit’s description. Thus, we can

easily extract these parts, whereby, PI ¼ fX ;Y ; Z ;c1; c2; ig, PO ¼ fSC Og, and S ¼ freset; sA; sB; sCg.Moreover, we can find storage variables which are

temporary variables and signals in the design as the

set V ¼ fT ; T1; T2; T4; T4; T5g. The set of arithmetic

expressions over primary input and storage vari-

ables can be considered as E ¼ fX þ Y ;X � Y ;

T3� Z ; T3þ Zg. Hence, U ¼ fT1 :¼ X þ Y ; T2 :¼X � Y ; T4 :¼ T3� Z ; T5 :¼ T3þ Zg will be the set

of storage and output assignments. Furthermore,

the set of status signals and conditions as

arithmetic relations between two expressions can

be cons idered as AR ¼ fðc1 ¼ 0ÞORðc1 ¼ 1Þ;ðc2 ¼ 0ÞORðc2 ¼ 1Þ; ði ¼ 0ÞORði ¼ 1Þg. N ow we

can compute the func function as illustrated in

T1 ¼ X þ Y (5)

T2 ¼ X � Y (6)



T3 ¼ T1� c1þ T2� ð1� c1Þ¼ ðX þ Y Þ � c1þ ðX � Y Þ � ð1� c1Þ (7)

T4 ¼ T3� Z ¼ ðX þ Y Þ � Z � c1þ ðX � Y Þ� Z � ð1� c1Þ (8)

T5 ¼ T3þ Z ¼ ðX þ Y Þ � c1þ ðX � Y Þ� ð1� c1Þ þ Z (9)

T ¼ T4� ð1� c2Þ þ T5� c2

¼ ðX þ Y Þ � Z � c1� ð1� c2Þ þ ðX � Y Þ � Z

� ð1� c1Þ � ð1� c2Þ þ ðX þ Y Þ � c1� c2

þ ðX � Y Þ � ð1� c1Þ � c2þ Z � c2 (10)

func ¼(SC OðPS; PIÞ

¼ ðPS � 20ÞðPS � 21ÞðPS � 22Þð23 � 20Þð23 � 21Þð23 � 22Þ � T

): (11)

It should be noted that T and

Ti ð1 � i � 5Þ in these equa-

tions are temporary variables,

i.e., based on Definition 2, they

should be described as polyno-

mial functions as well.

Also, thetrans function is

computed as illustrated in

(11). According to each present

state defined by PnðPS; kÞ, it isonly necessary to determine

the appropriate next state val-

ue as ft part of the equation. For example, the third

term in

transðPS; PIÞ

¼X3k¼0

PnðPS;KÞ � f transðPS; PI ;KÞf g

¼X3k¼0

Q3i¼0;i 6¼k

ðPS � 2iÞ

Q3i¼0;i 6¼k

ð2k � 2iÞ� f transðPS; PI ;KÞ

8>>><>>>:

9>>>=>>>;

¼ ðPS � 21ÞðPS � 22ÞðPS � 23Þð20 � 21Þð20 � 22Þð20 � 23Þ � ð2Þ

þ ðPS � 20ÞðPS � 22ÞðPS � 23Þð21 � 20Þð21 � 22Þð21 � 23Þ � ð4Þ

Figure 3. Schematic circuit of the FSMD circuitVExample 2.

Figure 4. State diagram of the FSMD circuitVExample 2.

July/August 2013 53

þ ðPS � 20ÞðPS � 21ÞðPS � 23Þð22 � 20Þð22 � 21Þð22 � 23Þ � ð8ðiÞ þ 4ð1� iÞÞ

þ ðPS � 20ÞðPS � 21ÞðPS � 22Þð23 � 20Þð23 � 21Þð23 � 22Þ � ð2Þ (12)

i.e., PnðPS; 4Þ � ½8� ðiÞ þ 4� ð1� iÞ�, indicates thatif the state machine is in state sB (encoded by 4), the

next state depends on input i. If i ¼ 1, then sB has a

transition to sC (encoded by 8) and the result is 8.

Otherwise, the result will be 4, which indicates that

the next state will be sB (encoded by 4).

In this example, we utilized a one-hot encoding

method to express the state machine with respect to

the state variables. It should be noted that other

encoding techniques such as gray encoding or

integer encoding can easily be used as well. For ex-

ample, to use integer encoding, variables will be rest

¼ ‘‘00’’ ¼ 0, sA ¼ ‘‘01’’ ¼ 1, sB ¼ ‘‘10’’ ¼ sAþ 1, and

sC ¼ ‘‘11’’ ¼ sAþ 2. Although the polynomials for

the next state and output functions obtained from

the integer encoding method are similar to those of

the one-hot encoding method, the processing time

to compute the coefficients in integer encoding is

shorter than that of one-hot encoding.

High-Level test generation

High-level fault injectionAfter representing RTL circuits with algebraic

equations, in order to complete the test generation

procedure, we obtain a set of high-level test se-

quences using various coverage metrics. The key

point that has to be appreciated in this decompo-

sition is that thelinear part indicates under what

conditions the function will be dependent on the

related variable [see (1)]. Now suppose the top va-

riable is a faulty variable named FAULT, as shown in

f ðFAULT; . . .Þ ¼ constþ FAULT� linear (13)

so the linear portion expresses conditions that cause

the FAULT variable to be observed at the output. This

property completely covers path sensitization, while

no computation needs to be performed.

Obviously, the const part is equivalent to the

fault-free behavior, while linear is exploited as a set

of test vectors which are formally represented. In-

deed, the HED representation has an inherent pro-

perty of automatically separating the fault-free

behavior from the faulty part of a faulty design. We

will point out how this property helps us generating

test vectors from the faulty specification.

High-level test pattern extractionIn contrast to other approaches of the test

generation, it is not necessary to perform the

justification/propagation phase, because HED is

able to express primary outputs in terms of primary

inputs. If we can find some conditions that reach the

specified fault to one of the primary outputs,

according to the aforementioned property, we have

already fulfilled path sensitization as well as justifi-

cation phases all together. It should be noted that if

fault propagation needs to go through storage

variables, our method tries to symbolically manip-

ulate the transition function instead of duplicating

the circuit by applying time-frame expansion. In

our proposed high-level test generation, behavioral

specifications (BSs) in hardware description lan-

guages (HDLs) as well as a fault list (FL) are

treated as inputs to the algorithm. Each fault in the

FL is characterized by the name of the affected

signal, the line of the behavioral model, and the

type of stuck at fault. We define a fault model that

comprises two kinds of faults: 1) the bit failure

including stuck at less than (-FAULT) and stuck-at

greater than (+FAULT) the fault-free value; 2) the

condition failure indicates that each condition can

be stuck at true (causing to remove else execution

path) or stuck-at false (causing to remove then

execution path). It is worth noting that such a fault

model provides a good correlation with gate-level

fault models, i.e., stuck at zero and one, while allow-

ing a faster and simpler analysis than gate-level

approaches.

The test generation algorithm starts by selecting

and then injecting a fault into the BS. To do so, a

variable FAULT is added to (subtracted from) the

fault-free symbolic value of the related signal. After

that, the highest order of variables is set to the

FAULT due to the beneficial property of HED

representation discussed earlier. Finally, during the

HED representation of different outputs, they are

checked to see whether the linear child of the

FAULT variable is not zero. As soon as we can find

such an output, the algorithm has succeeded to

detect the fault. Hence, the linear child of the

variable FAULT is returned as a set of test vectors

that are formally represented in HED, otherwise the

fault is undetectable.



Example 3. Consider Example 2 again. The stuck at

greater than faults (FAULT1, FAULT2, FAULT3, and

FAULT4) have been injected in ADDðX þ Y Þ,SUBðX � Y Þ, MULTðC � ZÞ, and SUBðC � ZÞ opera-tors. Figure 5a illustrates the HED representation of

the func variable as a primary output in this exam-

ple. The coefficients of FAULTi ð1 � i � 4Þ variables,i.e., the linear child, express conditions under which

the specified fault can be observed at the output

func. It should be noted that the const child of the

FAULT4 variable represents the fault-free behavior

of the circuit for this fault. Let the variable ordering

be FAULT1 > FAULT2 > FAULT3 > FAULT4 > X >

Y > Z > c1 > c2 > PS. After writing the symbolic

value of func in terms of primary inputs and the

present state [see (15)], replacing T3 from

T3 ¼ ðX þ Y þ FAULT1Þ � c1

þ ðX � Y þ FAULT2Þ � ð1� c1Þ (14)

we obtain

func ¼ ðPS � 20ÞðPS � 21ÞðPS � 22Þð23 � 20Þð23 � 21Þð23 � 22Þ� T3� Z � ð1� c2Þ þ FAULT3ð ÞfþððT3þ ZÞ � c2þ FAULT4g: (15)

In

func ¼ FAULT1� ðTP1Þ þ FAULT2� ðTP2Þ

þ FAULT3� ðTP3Þ þ FAULT4� ðTP4Þ þ FFB (16)

TPi and FFB stand for TestPattern for FAULTi and

FaultFreeBehavior in func, respectively, and they are

TP1 ¼ ðPS � 20ÞðPS � 21ÞðPS � 22Þð23 � 20Þð23 � 21Þð23 � 22Þ� Z � c1� c2þ c1� ð1� c2Þ½ �

TP2 ¼ ðPS � 20ÞðPS � 21ÞðPS � 22Þð23 � 20Þð23 � 21Þð23 � 22Þ� Z � ½ð1� c1Þ � c2þ ð1� c1Þ � ð1� c2Þ½ �

TP3 ¼ ðPS � 20ÞðPS � 21ÞðPS � 22Þð23 � 20Þð23 � 21Þð23 � 22Þ � ½c2�

TP4 ¼ ðPS � 20ÞðPS � 21ÞðPS � 22Þð23 � 20Þð23 � 21Þð23 � 22Þ � ½1� c2�

FFB ¼ ðPS � 20ÞðPS � 21ÞðPS � 22Þð23 � 20Þð23 � 21Þð23 � 22Þ� X � Y � Z � ð1� c1Þ � c2þ ð1� c1Þð½f�ð1� c2ÞÞ þ Z � c1� c2� ð1� c2Þ� þ Y

� Z � c1� c2� ð1� c2Þ½ � � Z � ð1� c2Þg:

The stuck at zero and one faults (FAULT5 and

FAULT6) for input variable i have been injected into

trans. Let the variable ordering be FAULT5 >

FAULT6 > i > PS. We first describe the polynomial

function oftrans in

trans¼ðPS�21ÞðPS�22ÞðPS�23Þ

ð20�21Þð20�22Þð20�23Þ �ð2Þ

þ ðPS�20ÞðPS�22ÞðPS�23Þ

ð21�20Þð21�22Þð21�23Þ �ð4Þ


ð22�20Þð22�21Þð22�23Þ� ð8þFAULT5ÞðiÞþð4þFAULT6Þð1�iÞ½ �


ð23�20Þð23�21Þð23�22Þ �ð2Þ: (17)

Figure 5b illustrates the HED representation oftrans,

according to

trans ¼ FAULT5� ðTP5Þ þ FAULT6

� ðTP6Þ þ FIP ns (18)

where TP5, TP6, and FIPns stand for TestPattern

for FAULT5, FAULT6, and FaultIndependent-Part,

Figure 5. HED fault representationVExample 3.

July/August 2013 55

respectively, and their equations are given in

TP5¼ðPS�20ÞðPS�21ÞðPS�23Þ

ð22�20Þð22�21Þð22�23Þ �ðiÞ

TP6¼ðPS�20ÞðPS�21ÞðPS�23Þ

ð22�20Þð22�21Þð22�23Þ �ð1�iÞ

FIP ns¼ðPS�21ÞðPS�22ÞðPS�23Þ

ð20�21Þð20�22Þð20�23Þ �ð2Þ


ð21�20Þð21�22Þð21�23Þ �ð4Þ


ð22�20Þð22�21Þð22�23Þ� ð8ðiÞþ4ð1�iÞ�


ð23�20Þð23�21Þð23�22Þ �ð2Þ: (19)

The coefficients of FAULT5 and FAULT6 variables

express the conditions under which the state

machine has an incorrect transition.

TP5 indicates that if the input variable i becomes

1, while the present state is PS ¼ 4 (sB in Figure 4),

stuck at zero on i will be detectable due to having

a transition to PS ¼ 4 instead of PS ¼ 8 (sC in

Figure 4). Each TPi in(16) and (18) indicates that the

injected faults will be detected if at least one

condition can be satisfied. Otherwise, TPi becomes

0 and, therefore, that fault will be undetectable.

Gate-level coverage computationAlthough functional tests generated at the behav-

ioral level are effective in traversing through much of

the control space of a digital circuit, exercising all

values of variables is not possible due to the large

number of possible values. Hence, for testing arith-

metic operators, a gate-level approach may be more

effective in finding values that exercise potential

faults. We employ a gate-level ATPG to generate a

test pattern targeting structural faults in the corre-

sponding functional unit. We use functional

methods based on the pre-image computation tech-

niques to compute justification sequences. We

assume that every FSMD has an initial state, and

pre-image computation is continued until the initial

state is reached. Note that we do not assume that the

circuits have synchronizing sequences. According

to conditions generated for this fault, we assign

some values to the related variables in each time

slice to generate a sequence of gate-level test vec-

tors. Although we utilize a PODEM-like algorithm,

any other gate-level test pattern generation algo-

rithms can be applied. Moreover, instead of using

ATPG tools, we are able to take advantage of SMT

Solvers to solve a list of equations extracted from the

high-level test patterns [12].

Example 4. Consider the behavioral test pattern

TP1, generated for FAULT1 in Example 3. This test

shows that in order to detect the fault behavior in the

ADD operation, which provides X þ Y , one of the

following conditions should be satisfied:

1) ðc1Þ 6¼ 0, ðc2Þ 6¼ 0, ðZÞ 6¼ 0, and ððPS � 1ÞðPS�2ÞðPS � 4ÞÞ 6¼ 0;

2 ) ðc1Þ 6¼ 0, ð1� c2Þ 6¼ 0, a n d ððPS � 1ÞðPS�2ÞðPS � 4ÞÞ 6¼ 0.

According to Figure 3 which depicted an RTL

schematic of the FSMD in Example 2, to extract gate-

level tests for condition 1, variables c1 and c2 should

be set to one and variable Z should be set to a non-

zero value at time slice t0, while the state machine

should be reached to a state where ðPS � 1ÞðPS�2ÞðPS � 4Þ 6¼ 0. On the other hand, according to the

state encoding described previously, ðPS � 1ÞðPS�2ÞðPS � 4Þ 6¼ 0 will be satisfied if PS is set to 8, i.e.,

sC state in Figure 4. On the other hand, in order to

reach this state from the initial state sA, we need to

recursively apply the pre-image computation to the

state transition function until the initial state, i.e., sA,

is reached. Therefore, to propagate FAULT1 to the

primary output func, at time slice t0 þ 1, variables c2

and Z should be set to one and a nonzero value,

respectively, at time slice t0. This way, RegC ¼Regb � Z is computed by the MUL unit in Figure 3.

After doing the first pre-image computation, the

present state sB (RegB in Figure 3) is reached where

the primary input i, i.e., the select bit of Mux2,

should be set to one at time slice t0 � 1. Performing

the second pre-image computation gets us to the

initial state sA while variable c1 should be set to one

at time slice t0 � 2. It causes the ADDER unit, the

faulty operation, to compute RegA ¼ X þ Y . In this

example, since there is no constraint on X and Y

variables, all combinations of their values are ap-

plied to the ADDER unit when the conditions for

different time slices are fixed. Note that, in contrast

to the conventional methods of the sequential cir-

cuit test generation, in our method, it is not neces-

sary to have different copies of a circuit for different

time slices as time frames.



Experimental setup and resultsIn this section, we report some experimental re-

sults that show the robustness of the HED-based test

generation compared to other methods. We have

implemented the algorithms in C++ and carried out

on an Intel 933-MHz Processor and 256 MB of mem-

ory running Windows XP. The effectiveness of the

proposed approach has been evaluated on the 1999

International Test Conference VHDL benchmarks

[13]. General information about the benchmark cir-

cuits is given in Table 1. Column VHDL Spec provides

the number of lines in RTL representations. In col-

umns GATE Level Spec, an idea about the size of the

circuits, the number of primary inputs (PI), primary

outputs (PO), combinational gates (CG), flipflops

(FF), total faults (TF), and collapsed faults (CF) are

given. Experimental results have been compared

with ARTIST [4], ARPIA [5], and RAGE99 [6], which

are the behavioral RTL ATPG tools based on evolu-

tionary and genetic algorithm. ARTIST and RAGE99

were run on a Sun Ultra 5 running at 333 MHz with

256 MB of memory and ARPIA was run on a Sun

Enterprise 250 running at 400 MHz and equipped

with 2 GB of memory. In order to represent a design

in HED, first, we utilize GAUT [11] as a high-level

synthesis tool to obtain the FSMD model of the de-

sign. After that, the data path and controller parts of

the design are represented in HED, based on the

polynomial model defined previously.

Table 2 reports the results of running the HED

package for each benchmark. For this purpose, based

on the statement and path coverage metrics, different

high-level faults are taken into account. Time,memory

usage, the number of equations, and the number of

variables needed to generate high-level test patterns

have been reported in columns Time in seconds,

Memory in megabytes, # EQ, and # Var, respectively.

Test patterns generated by HED are simulated at

the gate level when the stuck at faults are consid-

ered. Table 3 summarizes the results of our method

in comparison with ARTIST, ARPIA, and RAGE99. In

this table, columns F.C. and Time indicate the fault

coverage and the CPU time required by the fault

simulator to report the related fault coverage. Al-

though column # Test shows the number of test

vectors reported by methods in Table 3, this infor-

mation was not accessible for the ARPIA approach.

Although the HED package was run on Windows

XP and other methods were run on Sun platforms, in

order to have a fair comparison of their processing

times, we have used the benchmarks in [14], which

evaluate the performance of different platforms. It is

reported in [14] that an Intel 933-MHz processor

running Windows XP is about two times faster than

other platforms mentioned in this paper. For exam-

ple, in circuit b05, ARTIST achieved 33 393 s, ARPIA

achieved 1932.2 s, and RAGE99 achieved 2583.2 s,

while our method achieved 97.3 s, which needs to

be multiplied by 2 since our platform is almost two

times faster than other platforms. Obviously, the

runtimes (columns Time in Table 3) for the test

generation using HED for all circuits reported in our

experiment are almost two orders of magnitude

lower than those of reported using other methods.

Therefore, this gives us ways to use the proposed

approach to get coverage-driven high-level test

generation ability within the practical time.

AN ARITHMETIC APPROACH for modeling RTL cir-

cuits with polynomial expressions using a hybrid

Table 1 Benchmark characteristics for the HED-based approach.

Table 2 HED representation.

July/August 2013 57

canonical data structure based on a decision

diagram was introduced in this paper. Models were

modified to generate test patterns at the behavioral

level. Fault coverage at the logic level was computed

by converting the high-level test vectors to gate-level

test patterns and applying them to the related logic

circuits. We have applied our approach to some

standard benchmarks which include Boolean logic

expressions as well as arithmetic expressions. Expe-

rimental results show the efficiency of our method

even on large industrial circuits. A possible avenue

for future work would be to apply this method for

inserting optimal test points in the circuit in order to

use it for the design for testability. h

h References[1] P. Goel, ‘‘Test generation costs analysis and

projections,’’ in Proc. 17th Design Autom. Conf.,

Jun. 1980, pp. 77–84.

[2] M. K. Prasad, P. Chong, and K. Keutzer, ‘‘Why is

ATPG easy?’’ in Proc. 36th Design Autom. Conf.,

Jun. 1999, pp. 22–28.

[3] M. K. Ganai, A. Aziz, and A. Kuehlmann, ‘‘Enhancing

simulation with BDDs and ATPGs,’’ in Proc. Design

Autom. Conf., 1999, pp. 385–390.

[4] F. Corno, M. S. Reorda, and G. Squillero, ‘‘ITC’99

benchmarks and first ATPG results. IEEE Design

Test Comput., vol. 17, no. 3, pp. 44–53,

Jul.–Sep. 2000.

[5] G. Cumani, ‘‘High-level test of electronic systems,’’

Ph.D. dissertation, Politecnico di Torino, Turin,

Italy, 2003.

[6] F. Corno, M. Sonza Reorda, and G. Squillero,

‘‘High quality test pattern generation for RT-level

VHDL descriptions,’’ in Proc. 2nd Int. Workshop

Microprocessor Test Verif. Common Challenges

Solutions, Atlantic City, NJ, USA, Sep. 1999.

[7] B. Alizadeh and M. Fujita, ‘‘High level test

generation without ILP and SAT solvers,’’ in Proc.

Int. Workshop High Level Design Validat Test., 2007,

pp. 298–304.

[8] B. Alizadeh and M. Fujita, ‘‘Guided gate-level

ATPG for sequential circuits using a high-level test

generation approach,’’ in Proc. Asia South Pacific

Design Autom. Conf., 2010, pp. 425–430.

[9] B. Alizadeh and M. Fujita, ‘‘HED: A canonical and

compact hybrid word-Boolean representation as a

formal model for hardware/software co-designs,’’ in

Proc. 4th Int. Workshop Constraints Formal Verif.,

2007, pp. 15–29.

[10] D. D. Gajski and L. Ramachandran, ‘‘Introduction

to high-level synthesis. IEEE Design Test Comput.,

vol. 11, no. 4, pp. 44–54, Winter 1994.

[11] E. Martin, O. Sentieys, H. Dubois, and J. L. Philippe,

‘‘GAUT: An architectural synthesis tool for dedicated

signal processors,’’ in Proc. Eur. Design Autom. Conf.,

1993, pp. 14–19.

[12] B. Alizadeh and M. Fujita, ‘‘A hybrid approach for

equivalence checking between system level and

RTL descriptions,’’ in Proc. Int. Workshop Logic

Synthesis, 2007, pp. 298–304.

[13] S. Davidson, ‘‘ITC99 benchmarks,’’ 1999. [Online].

Available: http://www.cad.polito.it/tools/itc99.html.

[14] J. L. Henning, ‘‘Standard performance evaluation

corporation (SPEC),’’ 2006. [Online]. Available:

http://www.spec.org/cpu.

Mohammad Mirzaei has a BS in electrical en-gineering from the Khajeh Nasir Toosi of Technology,Tehran, Iran (2005) and an MS in digital electronic

Table 3 Comparing fault coverage of HED method with ARTIST, RAGE99, and ARPIA.



systems from Sharif University of Technology,Tehran, Iran (2007), where he is currently workingtoward a PhD in digital electronic systems. During hisMS study, he worked on the application of word-levelcanonical decision diagrams to formal verification ofarithmetic circuits. His current research interests in-clude the development of high-level design tools withemphasis on testing and design for testability.

Mahmoud Tabandeh is currently an AssociateProfessor with the Department of Electrical Engineer-ing, Sharif University of Technology, Tehran, Iran. Hisresearch interests include digital systems, hardwareand software in general, and image processing inparticular. Tabandeh has an Engineering Diploma inelectronics from INSA, Lyon, France (1967), an MSin control systems from Louisiana State University,Baton Rouge, LA, USA (1969), and a PhD in com-puter systems from the University of California atBerkeley, Berkeley, CA, USA (1974).

Bijan Alizadeh was with Sharif University of Tech-nology, Tehran, Iran, from 2005 to 2008. Since 2009,he has been with the Very-Large-Scale IntegrationDesign and Education Center, University of Tokyo,Tokyo, Japan, where he is currently a PostdoctoralResearch Fellow. His current research interestsinclude the development of better algorithms andheuristics for improving the efficiency of formal veri-fication and high-level synthesis tools. He is alsoresearching the use of word-level decision diagramsand SMT solvers in generating high-level test pat-terns which improve ATPG gate-level fault coverage.Alizadeh has a BS, an MS, and a PhD in computerengineering from the University of Tehran, Tehran,Iran (1995, 1998, and 2004, respectively).

Zainalabedin Navabi is a Professor of Electricaland Computer Engineering at the University ofTehran, Tehran, Iran, and an Adjunct Professor ofElectrical and Computer Engineering at NortheasternUniversity, Boston, MA, USA. He is the author ofseveral textbooks and computer-based trainings onVHDL, Verilog, and related tools and environments.His involvement with hardware descriptionlanguages began in 1976, when he started the de-velopment of a synthesis tool that generated metal–oxide–semiconductor (MOS) layout from an RTLdescription. Since 1981, he has been involved inthe design, definition, and implementation of hard-ware description languages (HDLs). He has writtennumerous papers on the application of HDLs in sim-ulation, synthesis, and test of digital systems. Hestarted one of the first full HDL courses at Northeast-ern University in 1990. Since then he has conductedmany short courses and tutorials on this subject inthe United States and abroad. In addition to being aProfessor, he is also a consultant to CAE companies.Navabi has a BS in electrical engineering from theUniversity of Texas at Austin, Austin, TX, USA (1975)and an MS and a PhD in electrical engineering formthe University of Arizona, Tucson, AZ, USA (1978and 1981, respectively). He is a Senior Member ofthe IEEE and a member of the IEEE Computer So-ciety, the American Society for Engineering Educa-tion (ASEE), and the Association for ComputingMachinery (ACM).

h Direct questions and comments about this paperto Mohammad Mirzaei, Department of Electrical En-gineering, Sharif University of Technology, Tehran,Iran; [email protected].

July/August 2013 59

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