and Synthesis
Second Edition
Samir Palnitkar
Table of Contents
1. Overview of Digital Design with Verilog HDL 3
1.1 Evolution of Computer-Aided Digital Design 3 1.2 Emergence of HDLs 4 1.3 Typical Design Flow 5 1.4 Importance of HDLs 7 1.5 Popularity of Verilog HDL 7 1.6 Trends in HDLs 8
2. Hierarchical Modeling Concepts 11
2.1 Design Methodologies 11 2.2 4-bit Ripple Carry Counter 13 2.3 Modules 14 2.4 Instances 16 2.5 Components of a Simulation 18 2.6 Example 20
2.6.1 Design Block 20 2.6.2 Stimulus Block 21
2.7 Summary 24 2.8 Exercises 24
3. Basic Concepts 27
3.1 Lexical Conventions 27 3.1.1 Whitespace 27 3.1.2 Comments 28 3.1.3 Operators 28
vii
3.1.4 Number Specification 28 Sized numbers 28 Unsized numbers 29 X or Z values 29
Negative numbers 30 Underscore characters and question marks 30
3.1.5 Strings 30 3.1.6 Identifiers and Keywords 30 3.1.7 Escaped Identifiers 31
3.2 Data Types 32 3.2.1 Value Set 32 3.2.2 Nets 33 3.2.3 Registers 33 3.2.4 Vectors 34
Vector Part Select 35 Variable Vector Part Select 35
3.2.5 Integer , Real, and Time Register Data Types 36 Integer 36 Real 36 Time 37
3.2.6 Arrays 37 3.2.7 Memories 38 3.2.8 Parameters 39 3.2.9 Strings 40
3.3 System Tasks and Compiler Directives 40 3.3.1 System Tasks 40
Displaying information 41 Monitoring information 42
Stopping and finishing in a simulation 43 3.3.2 Compiler Directives 44
4define 44 4 include 45
3.4 Summary 45 3.5 Exercises 46
4. Modules and Ports 49
4.1 Modules 49 4.2 Ports 52
4.2.1 List of Ports 53
viii Verilog HDL: A Guide to Digital Design and Synthesis
4.2.2 Port Declaration 54 4.2.3 Port Connection Rules 56
Inputs 56 Outputs 56 Inouts 56 Width matching 56
Unconnected ports 57
4.2.4 Connecting Ports to External Signals 57
Connecting by ordered list 58
Connecting ports by name 58
4.3 Hierarchical Names 59 4.4 Summary 61 4.5 Exercises 61
5. Gate-Level Modeling 63
5.1 Gate Types 64 5.1.1 And/Or Gates 64 5.1.2 Buf/Not Gates 66
Bufif/notif 68
Gate-level multiplexer 71
4-bit Ripple Carry Full Adder 75 5.2 Gate Delays 79
5.2.1 Rise, Fall, and Turn-off Delays 79 Rise delay 79 Fall delay 79 Turn-off delay 79
5.2.2 Min/Typ/Max Values 80 Min value 80 Typ val 80 Max value 80
5.2.3 Delay Example 82 5.3 Summary 84 5.4 Exercises 85
6. Dataflow Modeling 89
6.1 Continuous Assignments 90
Table of Contents ix
6.1.1 Implicit Continuous Assignment 91 6.1.2 Implicit Net Declaration 92
6.2 Delays 92 6.2.1 Regular Assignment Delay 92 6.2.2 Implicit Continuous Assignment Delay 93 6.2.3 Net Declaration Delay 94
6.3 Expressions, Operators, and Operands 94 6.3.1 Expressions 94 6.3.2 Operands 95 6.3.3 Operators 95
6.4 Operator Types 96 6.4.1 Arithmetic Operators 97
Binary operators 97 Unary operators 98
6.4.2 Logical Operators 98 6.4.3 Relational Operators 99 6.4.4 Equality Operators 100 6.4.5 Bitwise Operators 101 6.4.6 Reduction Operators 102 6.4.7 Shift Operators 103 6.4.8 Concatenation Operator 103 6.4.9 Replication Operator 104 6.4.10 Conditional Operator 104 6.4.11 Operator Precedence 105
6.5 Examples 106 6.5.1 4-to-l Multiplexer 106
Method 1: logic equation 106 Method 2: conditional operator 107
6.5.2 4-bit Full Adder 108 Method 1: dataflow operators 108 Method 2: full adder with carry lookahead 108
6.5.3 Ripple Counter 110 6.6 Summary 115 6.7 Exercises 116
7. Behavioral Modeling 119
x Verilog HDL: A Guide to Digital Design and Synthesis
Combined ANSI Style Port Declaration and Initialization 122 7.1.2 always Statement 123
7.2 Procedural Assignments 124 7.2.1 Blocking Assignments 125 7.2.2 Nonblocking Assignments 126
Application of nonblocking assignments 127 7.3 Timing Controls 129
7.3.1 Delay-Based Timing Control 129 Regular delay control 130 Intra-assignment delay control 131 Zero delay control 132
7.3.2 Event-Based Timing Control 133 Regular event control 133 Named event control 133 Event OR Control 134
7.3.3 Level-Sensitive Timing Control 136 7.4 Conditional Statements 137 7.5 Multiway Branching 138
7.5.1 case Statement 138 7.5.2 casex, casez Keywords 141
7.6 Loops 141 7.6.1 While Loop 141 7.6.2 For Loop 143 7.6.3 Repeat Loop 144 7.6.4 Forever loop 146
7.7 Sequential and Parallel Blocks 146 7.7.1 Block Types 147
Sequential blocks 147 Parallel blocks 148
7.7.2 Special Features of Blocks 149 Nested blocks 149 Named blocks 150 Disabling named blocks 151
7.8 Generate Blocks 152 7.8.1 Generate Loop 153 7.8.2 Generate Conditional 156 7.8.3 Generate Case 158
7.9 Examples 159 7.9.1 4-to-l Multiplexer 159
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Specification 161 Verilog description 162 Stimulus 165
7.10 Summary 166 7.11 Exercises 167
8. Tasks and Functions 171
8.1 Differences between Tasks and Functions 171 8.2 Tasks 172
8.2.1 Task Declaration and Invocation 173 8.2.2 Task Examples 174
Use of input and output arguments 174 Asymmetric Sequence Generator 175
8.2.3 Automatic (Re-entrant) Tasks 176 8.3 Functions 177
8.3.1 Function Declaration and Invocation 178 8.3.2 Function Examples 179
Parity calculation 179
Left/right shifter 180 8.3.3 Automatic (Recursive) Functions 181 8.3.4 Constant Functions 182 8.3.5 Signed Functions 183
8.4 Summary 184 8.5 Exercises 185
9. Useful Modeling Techniques 187
9.1 Procedural Continuous Assignments 187 9.1.1 assign and deassign 187 9.1.2 force and release 189
force and release on registers 189
force and release on nets 190
9.2 Overriding Parameters 190 9.2.1 defparam Statement 190 9.2.2 Modulejnstance Parameter Values 192
9.3 Conditional Compilation and Execution 194 9.3.1 Conditional Compilation 194 9.3.2 Conditional Execution 195
9.4 Time Scales 197
xii Verilog HDL: A Guide to Digital Design and Synthesis
9.5 Useful System Tasks 199 9.5.1 File Output 199
Opening a file 199 Writing to files 200 Closing files 201
9.5.2 Displaying Hierarchy 201 9.5.3 Strobing 202 9.5.4 Random Number Generation 203 9.5.5 Initializing Memory from File 204 9.5.6 Value Change Dump File 206
9.6 Summary 208 9.7 Exercises 209
Part 2: Advanced VerilogTopics 213
10. Timing and Delays 215
10.1 Types of Delay Models 216 10.1.1 Distributed Delay 216 10.1.2 Lumped Delay 217 10.1.3 Pin-to-Pin Delays 218
10.2 Path Delay Modeling 219 10.2.1 Specify Blocks 219 10.2.2 Inside Specify Blocks 220
Parallel connection 221 Full connection 222 Edge-Sensitive Paths 223 specparam statements 223 Conditional path delays 224 Rise, fall, and turn-off delays 225 Min, max, and typical delays 226 Handling x transitions 227
10.3 Timing Checks 227 10.3.1 $setup and $hold Checks 228
$setup task 228 $hold task 229
10.3.2 $width Check 230 10.4 Delay Back-Annotation 230 10.5 Summary 232 10.6 Exercises 233
Table of Contents xiii
11. Switch-Level Modeling 235
11.1 Switch-Modeling Elements 235 11.1.1 MOS Switches 236 11.1.2 CMOS Switches 237 11.1.3 Bidirectional Switches 238 11.1.4 Power and Ground 239 11.1.5 Resistive Switches 240 11.1.6 Delay Specification on Switches 241
MOS and CMOS switches 241 Bidirectional pass switches 242 Specify blocks 242
11.2 Examples 242 11.2.1 CMOS Nor Gate 242 11.2.2 2-to-l Multiplexer 245 11.2.3 Simple CMOS Latch 246
11.3 Summary 248 11.4 Exercises 249
12. User-Defined Primitives 251
12.1 UDPbasics 251 12.1.1 Parts of UDP Definition 252 12.1.2 UDP Rules 253
12.2 Combinational UDPs 253 12.2.1 Combinational UDP Definition 253 12.2.2 State Table Entries 255 12.2.3 Shorthand Notation for Don't Cares 256 12.2.4 Instantiating UDP Primitives 257 12.2.5 Example of a Combinational UDP 258
12.3 Sequential UDPs 260 12.3.1 Level-Sensitive Sequential UDPs 261 12.3.2 Edge-Sensitive Sequential UDPs 263 12.3.3 Example of a Sequential UDP 265
12.4 UDP Table Shorthand Symbols 266 12.5 Guidelines for UDP Design 267 12.6 Summary 268 12.7 Exercises 269
13. Programming Language Interface 273
13.1 Uses of PLI 276 13.2 Linking and Invocation of PLI Tasks 277
13.2.1 Linking PLI Tasks 277
xiv Verilog HDL: A Guide to Digital Design and Synthesis
13.2.2 Invoking PLI Tasks 278 13.2.3 General Flow of PLI Task Addition and Invocation 279
13.3 Internal Data Representation 279 13.4 PLI Library Routines 283
13.4.1 Access Routines 283 Mechanics of access routines 284 Types of access routines 285 Examples of access routines 285
13.4.2 Utility Routines 291 Mechanics of utility routines 291 Types of utility routines 292 Example of utility routines 292
13.5 Summary 295 13.6 Exercises 296
14. Logic Synthesis with Verilog HDL 299
14.1 What Is Logic Synthesis? 300 14.2 Impact of Logic Synthesis 303 14.3 Verilog HDL Synthesis 304
14.3.1 Verilog Constructs 305 14.3.2 Verilog Operators 306 14.3.3 Interpretation of a Few Verilog Constructs 307
The assign statement 307 The if-else statement 309 The case statement 309 for loops 310 The function statement 311
14.4 Synthesis Design Flow 311 14.4.1 RTL to Gates 311
RTL description 312 Translation 312 Unoptimized intermediate representation 313 Logic optimization 313 Technology mapping and optimization 313
Technology library 313 Design constraints 314
Optimized gate-level description 315 14.4.2 An Example of RTL-to-Gates 315
Table of Contents xv
Design specification 315 RTL description 316 Technology library 316 Design constraints 317 Logic synthesis 317 Final, Optimized, Gate-Level Description 317 1 Fabrication 320
14.5 Verification of the Gate-Level Netlist 320 14.5.1 Functional Verification 320
Timing verification 323 14.6 Modeling Tips for Logic Synthesis 323
14.6.1 Verilog Coding Style 323 Use meaningful names for signals and variables 324 Avoid mixing positive and negative edge-triggered flipflops 324 Use basic building blocks vs. use continuous assign statements 324 Instantiate multiplexers vs. use if-else or case statements 325 Use parentheses to optimize logic structure 325 Use arithmetic operators *, / , and % vs. design building blocks 325 Be careful with multiple assignments to the same variable 326 Define if-else or case statements explicitly 326
14.6.2 Design Partitioning 327 Horizontal partitioning 327 Vertical Partitioning 328 Parallelizing design structure 328
14.6.3 Design Constraint Specification 329 14.7 Example of Sequential Circuit Synthesis 330
14.7.1 Design Specification 330 14.7.2 Circuit Requirements 330 14.7.3 Finite State Machine (FSM) 330 14.7.4 Verilog Description 331 14.7.5 Technology Library 334 14.7.6 Design Constraints 334 14.7.7 Logic Synthesis 334 14.7.8 Optimized Gate-Level Netlist 335 14.7.9 Verification 337
14.8 Summary 339 14.9 Exercises 340
xvi Verilog HDL: A Guide to Digital Design and Synthesis
15. Advanced Verification Techniques 341
15.1 Traditional Verification Flow 342 15.1.1 Architectural Modeling 343 15.1.2 Functional Verification Environment 344 15.1.3 Simulation 347
Software Simulation 347 Hardware Acceleration 348 Hardware Emulation 349
15.1.4 Analysis 350 15.1.5 Coverage 351
Structural Coverage 351 Functional Coverage 352
15.2 Assertion Checking 352 15.3 Formal Verification 355
15.3.1 Semi-formal Verification 356 15.3.2 Equivalence Checking 358
15.4 Summary 359
A. Strength Modeling and Advanced Net Definitions 363
A.l Strength Levels 363 A.2 Signal Contention 364
A.2.1 Multiple Signals with the Same Value and Different Strength 364 A.2.2 Multiple Signals with Opposite Value and Same Strength 364
A.3 Advanced Net Types 364
A.3.1 tri 364
A.3.2 trireg365 A.3.3 triO and tril 366
A.3.4 supplyO and supplyl 366 A.3.5 wor, wand, trior, and triand 366
B. List of PLI Routines 369
B.l Conventions 369 B.2 Access Routines 369
B.2.1 Handle Routines 369 B.2.2 Next Routines 371 B.2.3 Value Change Link (VCL) Routines 373
Table of Contents xvii
B.2.4 Fetch Routines 373 .2.5 Utility Access Routines 376 B.2.6 Modify Routines 377
B.3 Utility ( t f j Routines 378 B.3.1 Get Calling Task/Function Information 378 B.3.2 Get Argument List Information 378 B.3.3 Get Parameter Values 379 B.3.4 Put Parameter Value 379 B.3.5 Monitor Parameter Value Changes 380 B.3.6 Synchronize Tasks 380 B.3.7 Long Arithmetic 382 B.3.8 Display Messages 382 B.3.9 Miscellaneous Utility Routines 383 B.3.10 Housekeeping Tasks 383
C. List of Keywords, System Tasks, and Compiler Directives 385 C.l Keywords 385 C.2 System Tasks and Functions 387 C.3 Compiler Directives 387
D. Formal Syntax Definition 389 D.l Source Text 390
D. 1.1 Library Source Text 390 D.1.2 Configuration Source Text 390 D.1.3 Module and Primitive Source Text 390 D.I.4 Module Parameters and Ports 391 D.I.5 Module Items 391
D.2 Declarations 393 D.2.1 Declaration Types 393
Module parameter declarations 393 Port declarations 393 Type declarations 394
D.2.2 Declaration Data Types 394 Net and variable types 394 Strengths 395 Delays 395
D.2.3 Declaration Lists 395 D.2.4 Declaration Assignments 396
xviu Verilog HDL: A Guide to Digital Design and Synthesis
D.2.5 Declaration Ranges 396 D.2.6 Function Declarations 396 D.2.7 Task Declarations 397 D.2.8 Block Item Declarations 398
D.3 Primitive Instances 398 D.3.1 Primitive Instantiation and Instances 398 D.3.2 Primitive Strengths 399 D.3.3 Primitive Terminals 399 D.3.4 Primitive Gate and Switch Types 400
D.4 Module and Generated Instantiation 400 D.4.1 Module Instantiation 400 D.4.2 Generated Instantiation 400
D.5 UDP Declaration and Instantiation 401 D.5.1 UDP Declaration 401 D.5.2 UDP Ports 401 D.5.3 UDP Body 402 D.5.4 UDP Instantiation 402
D.6 Behavioral Statements 402
D.6.1 Continuous Assignment Statements 402 D.6.2 Procedural Blocks and Assignments 403
D.6.3 Parallel and Sequential Blocks 403 D.6.4 Statements 403 D.6.5 Timing Control Statements 404
D.6.6 Conditional Statements 405 D.6.7 Case Statements 405
D.6.8 Looping Statements 406 D.6.9 Task Enable Statements 406
D.7 Specify Section 406
D.7.1 Specify Block Declaration 406 D.7.2 Specify Path Declarations 407
D.7.3 Specify Block Terminals 407 D.7.4 Specify Path Delays 408
D.7.5 System Timing Checks 409 System timing check commands 409 System timing check command arguments 410 System timing check event definitions 411
Table of Contents
D.8 Expressions 412 D.8.1 Concatenations 412 D.8.2 Function calls 412 D.8.3 Expressions 413 D.8.4 Primaries 414
D.8.5 Expression Left-Side Values 415
D.8.6 Operators 415 D.8.7 Numbers 416 D.8.8 Strings 417
D.9 General 417
D.9.1 Attributes 417
D.9.2 Comments 417 D.9.3 Identifiers 417 D.9.4 Identifier Branches 419
D.9.5 Whitespace 419
E. Verilog Tidbits 421
Origins of Verilog HDL 421 Interpreted, Compiled, Native Compiled Simulators 421 Event-Driven Simulation, Oblivious Simulation 422
Cycle-Based Simulation 422
Coverage Tools 424
Assertion Checking Tools 424 Equivalence Checking Tools 424 Formal Verification Tools 424
F. Verilog Examples 425
xx Verilog HDL: A Guide to Digital Design and Synthesis
Input ports 434 Inout ports 434
Bibliography 439
Index 441