720B

Author: Wan-Ling Wu, Ching-Yuan Yang, Dung-An Wang

Presenter: Wan-Ling Wu

Date: Sep, 2020

National Chung-Hsing University

Department of Electrical Engineering

Analog Integrated Circuits Design Lab.

A Flipping Active-Diode Rectifier for Piezoelectric-

Vibration Energy-Harvesting

Outline

Introduction

Self-powered Operation

Piezoelectric Conversion

Energy Extraction Improvement

Piezoelectric Energy Harvesting Flipping Rectifier

System Architecture

Proposed Rectifier Scheme

Sub-Circuits Block Implementation

Simulation Results

Chip Photo

Measurement Consideration & Results

Comparison

Reference

2

Outline

3

Introduction

Self-powered Operation

Piezoelectric conversion

Energy Extraction Improvement

Piezoelectric Energy Harvesting Flipping Rectifier and Charging

Management System

System Architecture

Proposed Rectifier Scheme

Sub-Circuits Block Implementation

Simulation Results

Chip Photo

Measurement Consideration & Results

Comparison

Reference

Introduction

Self-powered Operation

4

[1] https://www.fujitsu.com/global/about/resources/news/press-releases/2010/1209-01.html

Full Bridge Rectifier

5

Cp

ip(t)=Ipsin(ωt)

Crect

Vrect

Iload

Vp(t)

io(t)

Vrect

VIN+ VIN-

MP1 MP2

MN1MN2

IP

CP

RP

IP

VIN

Vrect

-Vrect

Qloss

𝑉𝑟𝑒𝑐𝑡 = 𝑉𝑃 − 2𝑉𝐷

𝑉𝑃 = 𝐼𝑃 𝜔𝐶𝑃

𝑄𝑙𝑜𝑠 𝑠 𝑐𝑦 = 4𝐶𝑝𝑉𝑟𝑒𝑐𝑡

Active Diode Rectifier

6

Vrect

VIN+VIN-

MP1MP2

MN1 MN2

IP

CP

RP

CMP1 CMP2

IP

VIN

Vrect

-Vrect

Qloss

Energy Extraction Improvement

7

Synchronized Switch-only Rectifier (SOR)IP

VIN

Vrect

-Vrect

Qloss

VSW

CP RPIP RP

Piezo HarvesterConjugate

Impedance Match

L=1/(ωP2CP)

1

𝜔𝑃𝐶𝑃= −𝜔𝑃𝐿

𝐿 =1

𝜔𝑃2𝐶𝑃

𝑋𝐶 = −𝑋𝐿

(too large)

𝑄𝑙𝑜𝑠 𝑠 𝑐𝑦 = 2𝐶𝑝𝑉𝑟𝑒𝑐𝑡

PEH

AC-DC

Rectifier

VIN+

VIN-

CL RLCPIP

Vrect

Energy Extraction Improvement

8

Flipping Capacitors Rectifier (FCR)

𝑄 𝑙𝑜𝑠𝑠 𝑐𝑦 = 2𝐶𝑝𝑉𝑟𝑒𝑐𝑡(1 −𝑉𝑟𝑉𝑟𝑒𝑐𝑡)

IP

VIN

Vrect

-Vrect

Qloss

ph1p

ph1n

ph00

Vr

𝑉𝑟↑, 𝑄 𝑙𝑜𝑠𝑠 𝑐𝑦 ↓

PEH

AC-DC

Rectifier

VIN+

VIN-

CL RLCPIP

Vrect

ph1p

ph1nph1p

ph1nC1

ph00

Energy Extraction Improvement

9

Flipping Capacitors Rectifier (FCR)

𝑉𝐶𝑝 = 𝑉𝐶1 =𝐶𝑃𝐶𝑃 + 𝐶1

𝑉𝑟𝑒𝑐𝑡

𝑉𝐶𝑝 = 0 𝑉𝐶1 =𝐶𝑃𝐶𝑃 + 𝐶1

𝑉𝑟𝑒𝑐𝑡

𝑉𝐶𝑝 = −𝑉𝐶1 = −𝐶𝑃𝐶1

(𝐶𝑃 + 𝐶12 𝑉𝑟𝑒𝑐𝑡 = −

𝑥

1 + 𝑥 2𝑉𝑟𝑒𝑐𝑡𝐶1 = 𝑥𝐶𝑃

𝑉𝐶𝑝,𝑚𝑖𝑛 = −1

4𝑉𝑟𝑒𝑐𝑡 @ 𝑥 = 1, 𝐶1 = 𝐶𝑃

PEH

AC-DC

Rectifier

VIN+

VIN-

CL RLCPIP

Vrect

ph1p

ph1nph1p

ph1nC1

ph00

Energy Extraction Improvement

10

Flipping Capacitors Rectifier (FCR)

𝑉𝐶𝑝 = 0 𝑉𝐶1 = (1

4+ 1)1

2𝑉𝑟𝑒𝑐𝑡

𝑉𝐶𝑝 = 𝑉𝐶1 = (1

4)2+1

4𝑉𝑟𝑒𝑐𝑡 =

5

16𝑉𝑟𝑒𝑐𝑡

𝑉𝐶𝑝 = −𝑉𝐶1 = −(1

4+ 1)1

2𝑉𝑟𝑒𝑐𝑡

𝑉𝑟 =1

4

n

+⋯+1

4

2

+1

4𝑉𝑟𝑒𝑐𝑡 =

1≤𝑖≤𝑛

1

4

𝑖

𝑉𝑟𝑒𝑐𝑡 ⇒ lim𝑛⟶∞𝑉𝑟 =1

3𝑉𝑟𝑒𝑐𝑡

IP

VIN

Vrect

-Vrect

Qloss

Vr

PEH

AC-DC

Rectifier

VIN+

VIN-

CL RLCPIP

Vrect

ph1p

ph1nph1p

ph1nC1

ph00

Energy Extraction Improvement

11

Flipping Capacitors Rectifier (FCR)

k=1~8, Stop=20Initial

Qp=1, Qn~Qk=0, n=1, L=1

Qp=(Qp+Qn)Cp/(Cp+Cn)

Qn=(Qp+Qn)Cn/(Cp+Cn)

n=k

yes

non=n+1

Qp=0

Qp=(Qp+Qn)Cp/(Cp+Cn)

Qn=(Qp+Qn)Cn/(Cp+Cn)

yes

non=1n=n-1

yes

noL=Stop

Vp=Qp/Cp

Qp=1, L=L+1

Start

End

0.33

0.5

0.6

0.660.710.750.770.8

Energy Extraction Improvement

12

Flipping Capacitors Rectifier (FCR)

VIN

Vrect

-Vrect

Vr

ph1p

ph2p

ph3p

ph4p

ph00

ph4n

ph3n

ph2n

ph1n

IPQloss

(b)

𝑘 = 4, 𝐶1 = 𝐶2 = 𝐶3 = 𝐶𝑘 = 𝐶𝑃

PEH

AC-DC

Rectifier

VIN+

VIN-

CL RL

CPIP

Vrect

ph1p

ph1nph1p

ph1n

C1

ph00

phkp

phkn

Ck

phkkp

phknph2p

ph2nph2p

ph2n

C2

𝑉𝑟 =2

3𝑉𝑟𝑒𝑐𝑡

Energy Extraction Improvement

13

Flipping Capacitors Rectifier (FCR) simulation results with 1C~4C

Outline

14

Introduction

Self-powered Operation

Piezoelectric Conversion

Energy Extraction Improvement

Piezoelectric Energy Harvesting Flipping Rectifier System Architecture

Proposed Rectifier Scheme

Sub-Circuits Block Implementation

Simulation Results

Chip Photo

Measurement Consideration & Results

Comparison

Reference

Common Rectifier

Sub-Circuits Block Implementation

15

Active Diode Rectifier Vrect

VIN+VIN-

MP1MP2

MN1 MN2

IP

CP

RP

CMP1 CMP2

Cout

syn1 syn2

Ip

Vin-

Vin+

Vrect

0.65v

Ip

Vin+

Vin-

Vrect

syn2

syn1

Vrect

VIN+ VIN-

MP1 MP2

MN1MN2

IP

CP

RP

CL RL

3.3v

Sub-Circuits Block Implementation

16

Common-gate Comparator

Schmitt Trigger

Vb

V+ V-

Vout

MN1 MN2

48dBgain

phase

Vdd

Vdd

VoutVin

MN1

MN2

MP3

MN3

MP1

MP2

Vin

Vout

Vout

w/o schmitt trigger

w/ schmitt trigger

2.16v0.8v

Sub-Circuits Block Implementation

17

Pulse Gen.

Pulse Generator

Pulse

Gensyn2

delay

P2,-4

Pulse

Gen

delay

P2,-3

Pulse

Gen

delay

P2,-2

Pulse

Gen

delay

P2,-1

Pulse

Gen

delay

P2,0

Pulse

Gen

delay

P2,1

Pulse

Gen

delay

P2,2

Pulse

Gen

delay

P2,3

Pulse

Gen

P2,4

Pulse

Gensyn1

delay

P1,-4

Pulse

Gen

delay

P1,-3

Pulse

Gen

delay

P1,-2

Pulse

Gen

delay

P1,-1

Pulse

Gen

delay

P1,0

Pulse

Gen

delay

P1,1

Pulse

Gen

delay

P1,2

Pulse

Gen

delay

P1,3

Pulse

Gen

P1,4

outin

ph

a

b

Switch

Sub-Circuits Block Implementation

18

Pulse Generator

VIN-

VIN+

ph1p

ph1nph1p

ph1n

C1

ph00

ph2p

ph2nph2p

ph2n

C2ph3p

ph3nph3p

ph3n

C3ph4p

ph4nph4p

ph4n

C4

ph1p

ph2p

ph3p

ph4p

ph00

ph4n

ph3n

ph2n

ph1n

Simulation Results

19

IP=0.03mA, CP=C1=C2=C3=C4=12nF,

IP

30uA

-30uA

FBR

Active

diode

FCR

sw_only

Va

Vb

Va

Vb

3.29v

0.8v

3.2v5.05v3.75v

Simulation Results

20

Maximum Output Power Improvement

Rectifiers Max. output power Normalize

Full bridge 9.41μW 1

Active 18.4μW 2

Switch only 30.5μW 3.2

Flipping capacitors 43.5μW 4.6

Outline

21

Introduction

Self-powered Operation

Piezoelectric Conversion

Energy Extraction Improvement

Piezoelectric Energy Harvesting Flipping Rectifier and Charging

Management System

System Architecture

Proposed Rectifier Scheme

Sub-Circuits Block Implementation

Simulation Results

Chip Photo

Measurement Consideration & Results

Comparison

Reference

Chip Layout

Chip Photo

22

Switch

Array

Pulse Generator

Active

Diode

Rectifier

Chip Photo

1420μm×1170μm

Top Board

Measurement Consideration

23

Bottom Board

Bias

Cap array

Output

cap

Input

psshi

sw only

ssshi

V+

V-

Vs

Synb

Ph1n

Ph00

Ph1p

PCB Layout

Ideal Input

ChipVIN+

VIN-

Tektronix AFG3252

Arbitrary/Function Generator

Tektronix MDO4104-6

Mixed Domain Oscilloscope

ChipVIN+

VIN-

Shaker VS-5V

Tektronix MDO4104-6

Mixed Domain Oscilloscope

Shaker Control

Piezoelectric Harvester Input

Measurement Results

24

Sinusoidal Voltage Ideal Input 500Hz, Vp=6V

1.4v

Vin

Ph00

Vin+

Vin-

Active Diode Rectifier Switch Only Rectifier

2v

Measurement Results

25

Sinusoidal Voltage Ideal Input 500Hz, Vp=6V

3v

Vin

Ph00

Vin+

Vin-

Flipping Capacitors Rectifier Flipping Capacitors Rectifier

Comparison

26

This work ISSCC2014[8] JSSC2010[7] TPEL[9]

Technology 0.35μm 0.35μm 0.35μm 0.32μm

Extraction Technique

SSHC Energy Pile-Up SSHI SECE

Frequency 100 Hz 100 Hz 225 Hz 60 Hz

Inductor No 10mH 47μH 560μH

PIC/PFBR 4.6 4.2 2.8 3

Outline

Introduction

Self-powered Operation

Piezoelectric Conversion

Energy Extraction Improvement

Piezoelectric Energy Harvesting System

System Architecture

Proposed Rectifier Scheme

Sub-Circuits Block Implementation

Simulation Results

Chip Photo

Measurement Consideration & Results

Comparison

Reference

27

Reference[1] G. Tang, B. Yang, J.-Q. Liu, B. Xu, H.-Y. Zhu, and C.-S. Yang, “Development of high performance piezoelectric d33

mode MEMS vibration energy harvester based on PMN-PT single crystal thick film,” Sens. Actuators A, Phys., vol. 205,

pp. 150–155, Jan. 2014.

[2] N. Elvin and A. Erturk, Advances in Energy Harvesting Methods. New York, NY, USA: Springer, 2013.

[3] Z. Chen, M. Law, P. Mak, W. Ki and R. P. Martins, "Fully integrated inductor-Less flipping-capacitor rectifier for

piezoelectric energy harvesting," IEEE J. Solid-State Circuits, vol. 52, no. 12, pp. 3168-3180, Dec. 2017.

[4] Y. Sun, N.H. Hieu, C.-J. Jeong, and S.-G. Lee, “An Integrated High-Performance Active Rectifier for Piezoelectric

Vibration Energy Harvesting System,” IEEE Transactions onPower Electronics, vol.27, no.2, pp.623-627, Feb. 20

[5] S. M. Abbas, M. A. Taher and A. Al-Shaheen, "Developing efficient RF-DC converter using switch-only rectifier for

biomedical applications," 2013 IEEE Student Conference on Research and Developement, Putrajaya, 2013, pp. 511-

515.

[6] S. Du and A. A. Seshia, "An Inductorless Bias-Flip Rectifier for Piezoelectric Energy Harvesting," in IEEE Journal of

Solid-State Circuits, vol. 52, no. 10, pp. 2746-2757, Oct. 2017.

[7] Y. K. Ramadass and A. P. Chandrakasan, "An efficient piezoelectric energy harvesting interface circuit using a bias-

flip rectifier and shared inductor," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 189-204, Jan. 2010.

[8] Y. Yuk, et al., "23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric

material in a dual-source energy-harvesting interface," 2014 IEEE International Solid-State Circuits Conference Digest of

Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 402-403

[9] M. Dini, A. Romani, M. Filippi and M. Tartagni, "A Nanopower Synchronous Charge Extractor IC for Low-Voltage

Piezoelectric Energy Harvesting With Residual Charge Inversion," in IEEE Transactions on Power Electronics, vol. 31,

no. 2, pp. 1263-1274, Feb. 2016

28

Thank you for your attention.