A Comparative Study of CMOS LNAs

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A Comparative Study of CMOS LNAs

Sherif A. Saleh, Maurits Ortmanns, and Yiannos Manoli

Chair of Microelectronics, Department of Microsystems Engineering - IMTEK,

University of Freiburg, Georges-Koehler-Allee 10279110 Freiburg, Germany

Email: Sherif.mohamed, Ortmanns, [email protected]

Abstract —Three CMOS RF low noise amplifier circuits havebeen designed and simulated. These LNAs are intended for usein 402-405MHz Medical Implant Communication Servicetransceivers. The inductively degenerated common source LNA

(CS-LNA) topology is currently popular because it achieves highgain, low noise figure, and high linearity. In this paper cascodeLNA with inductive source degeneration, LC folded cascodeLNA topology and current reuse technique are used in a CMOSCS-LNA with inductive source degeneration. The performance

target is to achieve a moderate gain and moderate noise figurewithout overly degrading the linearity.

I.

I NTRODUCTION

The use of Radio Frequency in medical applications has brought numerous advantages such as increased patient safety,comfort and mobility, for these reasons highly reliable andultra-low power consumption implanted wireless devices aremostly preferred in medical industry [1]. In direct conversionreceivers, the antenna receives the signal from the implanteddevice, and the LNA amplifies the weak signal. The mixerthen uses the local oscillator signal to demodulate the inputwhich is then down converted to the base band.

The LNAs presented in this paper are intended to be used

as the first stage of a Medical Implant CommunicationsService (MICS) receiver to provide enough gain to overcomethe noise of subsequent stages while adding as little noise as

possible to the incoming signal. Besides, it should amplifylarge signals without distortion, offer enough dynamic rangeand provide input and output impedance matching [2]. LNAdesign involves tradeoffs between linearity, input matching,noise figure, and power dissipation.

The paper is organized as follows: Section II includes thecircuit analysis and design details of the single ended cascodeLNA with inductive source degeneration. Section IIIintroduces the design of the folded cascode (FC) LNA.Section IV shows the design and the advantages of an LNAusing current reuse technique (CRT). The simulation results

and discussion pertaining to S-parameters, linearity and noiseare presented in section V. Conclusions are given in sectionVI.

II. DESIGN OF CASCODE LNA WITH INDUCTIVE SOURCE

DEGENERATION

A cascode LNA with inductive source degenerationstructure is widely used in receiver design. It is easier toachieve input matching for both the power gain and the noisefigure. The channel width of the input transistor determinesthe noise performance of the LNA because the dominant noisesource in CMOS devices is the channel thermal noise [3].Since the biasing current is fixed, an optimum channel width

can be obtained for minimum noise contribution. Fig.1 showsa single ended cascode LNA with source inductivedegeneration. Single ended LNA’s have smaller noise figurescompared to differential LNA’s, they also eliminate the needfor using a balun transformer to interface the antenna to adifferential LNA input, so it consumes less power. The

transistor 1 M and 2 M are same size RF transistors, giving a

better noise isolation. The common-gate transistor

2 M increases the reverse isolation of the LNA, and improves

the stability of the circuit by minimizing the miller effect of

the parasitic gate-drain capacitance of 1 M 1( ) gd C by presenting

a low impedance node at the drain of 1 M [4].

Figure 1. Cascode LNA with inductive source degeneration

1

2

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1.68014121600.5

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d

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The parallel LC-tank circuit ,d d L C is chosen such that the

resonance frequency is at the RF signal of 403MHz and to

provide a DC path for the bias current of both 1 M and 2 M .

When the LC-tank resonates, it functions as an impedance

with a value 2(1 )b ind R Q R= + . The operation of the LC-tank is

limited by the quality factor ( )Q of the tank circuit [5]. A little

current will be lost by the LC-tank for parasitic resistance

( )ind R of the on-chip spiral inductor and a loss factor ( )η is

defined to calculate the loss current.

2

2

1

2 1m

b m

g

R g η =

+ (1)

The larger transconductance of 2 M 2( )m g can be chosen to

minimize the lossy current.

A. Input Matching

The input impedance of the common-source (CS) LNAcan be written as [5]:

1

1 1

1( ) m sin g s

gs gs

g L Z j L L j C C ω ω = + + + (2)

where 1 gsC and 1m g are respectively the parasitic gate-to-source

capacitance and the transconduactance of 1 M . The input

matching at the resonance frequency 0( )ω can be achieved by

setting the real part of (1) to the source impedance ( ) s R and the

imaginary part to zero. The matching conditions are:

1

2

1 0 1

1, s m

s g s

gs gs

L g R L L

C C ω = + = (3)

The input impedance of the CS-LNA takes the form of a series

resonance and the associated effective quality factor of theinput circuit assuming input matching is

0(1 2 ) 1CS gs sQ C Rω = > , the input matching can be adjusted by

tuning g L and s L . Adding a capacitor exC in parallel with the

inductor g L makes the use of a smaller g L feasible, and eases

input matching.

B. Gain

The effective transconductance of the CS-LNA stageneglecting the gate resistance is:

1

, 1

0 1 0( ) (1 )m T

m CS m CS

gs s T s s T s s

g G g Q

C R L R L R

ω

ω ω ω ω = = =

+ + (4)

It can be observed that the effective transconductance is

independent of the 1m g of the device, and is dependent on the

CMOS process parameters through the transition

frequency T ω . Using (4), we can calculate the following

expressions for the voltage gain assuming input matching.

0

( )2

T L

s

R A

Rυ

ω

ω = (5)

where L R is the load resistance of the LNA.

C.

Noise Figure

A major advantage of the CS-LNA with inductive sourcedegeneration is that the resistive impedance is noiseless,unlike other topologies where a noisy resistor is added in the

signal path to create a50Ω termination impedance. The noisein CS-LNA comprises three factors: channel noise, gate noise,and correlated noise. The noise figure of the cascode LNA

with inductive degeneration can be computed as [3]:

01 ( ) g l

s s CS T

R R F

R R Q

ω γ χ

α ω = + + + (6)

where2 2

21 2 (1 )5 5

CS CS c Q Qδα δα

χ γ γ

= + + + ,0

m

d

g

g α , 0d g is

the zero-bias drain source conductance, γ andδ are the bias

dependent coefficients of channel thermal noise and gate noise

respectively, l R represents the series resistance of the

inductor g L , g R is the gate resistance of the NMOS device,

and c is the correlation factor representing the correlation

between the gate noise and the drain noise. Note that the

miller capacitance gd C has been neglected in the interest ofsimplicity. We observe that (6) contains terms which are

proportional to CS Q as well as inversely proportional to CS Q .

Hence, there exists an optimum quality factor that minimizes

the noise figure. Also, the cutoff frequency T ω of the device

should be high, the channel length should be minimized.

D.

Linearity

An important metric of linearity for LNA design is the

input third order modulation point 3( ) IIP of the circuit.

The 3 IIP of the circuit in Fig.1, assuming input matching can

be written as [6]:

3 3, 10 0[ ] [ ] 20log (1 )in gs s IIP dBm IIP dBm C Rω = − (7)

The first term in (7) is the intrinsic 3 IIP of the device, and

arises from the fact that short channel CMOS transistorsexhibit velocity saturation, which gradually linearizes the idealquadratic drain current equation of the long channel transistor.The second term results from the extra voltage boost across

the gsC due to the series tank.

III. THE PROPOSED FOLDED CASCODE LNA

The power consumption is an important issue for radiofrequency integrated circuit design. A FC-LNA structure ismakes a low-voltage operation possible. The common-

gate 2 M of the cascode LNA is folded to another biasing path.

This FC topology gives the chance of increasing the effective

bias voltage. As the effective bias voltage increases, 1m g of

1 M increases, consequently increasing the cutoff frequency,

which results in an overall reduction in the noise figure, (6).

The circuit topology of a FC-LNA design is shown inFig.2. where the CS and CG stages are folded into two paths.At DC the supply voltage needs to bias only one transistor ineach path, which mean that the minimum supply voltage

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(1/ 2) I D (1/ 2) I D

(1/ 2) I D

(1/ 2) I D

+m1 m2g g

(a) (b) (c)

1M

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ddV

0L0C

sL

Gnd Gnd

dLd

C

outRF

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inRF

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exC

3M

outRF

dLdC

2

M1M

sL

ddV

Gnd

inRF

biasV

0C

0L

Gnd

gL

exC

Figure 2. Folded cascode LNA schematic

needs only one threshold voltage ( )thV to drive the transistor.

At AC the RF signal is fed from the CS stage into the CGstage; and actually works as a traditional cascode LNA at the

operation frequency. The( , )d d L C tank is chosen such that the

resonance frequency is at the RF signal frequency 403MHz.At this frequency it provides a high impedance branch to force

the RF signal into the source of 2 M . In order for this

operation to be true it is required that the impedance of the parallel LC-tank at resonance is much higher than the input

resistance seen at the source of 2 M . It can be shown that this

is satisfied by choosing the transconductance of 2 M ,2

2 1m d d g R Q where d R and d Q are the resistance and quality

factor associated with the inductor d L . The tuned

tank 0 0, L C circuit acts as a filter to ensure that the

specifications for center frequency, bandwidth and gain aremet.

IV.

THE PROPOSED LNA USING CRT

Unlike traditional CMOS LNAs that trade off the noisefigure for input matching, the goal here is to achieve a high

transconductance m g and a cutoff frequency T m gs g C ω =

necessary to achieve a high gain with less current. The currentreuse technique (CRT) topology presented in this paper is ableto simultaneously achieve a good input matching and a lownoise figure. Fig.3 (a) shows a single NMOS device that has

the aspect ratioW L with a drain current D I . Fig.3 (b) shows

two NMOS devices in parallel with each device having an

aspect ratio(1 2)W L and drain current (1 2) D I . Thus, the

transconductance of the compound device in Fig.3 (b) is thesame as the transconductance of the device in Fig.3 (a). In

Fig.3(c), a PMOS device is substituted for device 2 M in

Figure 3. Illustration of CRT technique

Fig.3 (b). The total transconductance is 1 2mt m m g g g = + .

With ( ) ( )1 2

(1 2)W L W L W L= = , the input capacitance

is 1 2 gs gsC C + which is nearly equal to gsC in Fig.3 (a).

Fig.4 shows the LNA topology. An inverter stage

( 1 M and 2 M ) with inductive source degeneration is used to

provide more design parameters to achieve a high gain and

low NF at the same time. This configuration provides a hightransconductance necessary to achieve high gain, and lowreverse gain necessary to provide sufficient isolation and to

simplify input and output port matching. The transistor 3 M is

folded to another biasing path. The NF of the LNA neglectingthe gate-drain capacitance can be shown to be [7]:

2 2

11 (8 ) 3 gs s m F C R g ω ≈ + (8)

This LNA in Fig.4 is capable of achieving the desired NF

specification where a large 1m g is typically needed to reduce

the noise figure.

V. SIMULATION RESULTS AND DISCUSSION

The three designed LNAs are simulated using a0.13 m µ CMOS process in the Cadence design environment.

The input signal power ranged from -40 to 0dBm. The S- parameter are used to describe the behavior of a system

working at high frequencies, where 11S represents input

reflection, 22S output reflection, 21S direct gain and 12S is the

reverse gain.

The software ASITIC [8] is then used to generate theequivalent circuit model for spiral inductors to be included inthe simulation. These parasitic effects must be taken intoaccount since they have a significant effect on the overallnoise and the optimum device geometry and power.

Fig.5 shows the power gain 21( )S simulation results of the

three LNAs. The maximum gain is obtained from the LNAusing CRT, where a high transconductance is achieved. Thislarge gain gives the room to reduce the effect of noise fromthe following stages. These three LNA circuits show a good

11S (less than 25dBm− ), 22S (less than 15dBm− ), and input

output isolation. Furthermore, these amplifiers have a goodlinearity.

Figure 4. Degenerated current reuse LNA

1

2

0 0

( ) 350 0.5 1.6( ) 350 0.5 80

14 1214 12160 0.5

s

g

d d

ex Bias

W L L nH W L L nH

L nH C pF L nH C pF C fF V V

1

2

3

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( ) 500 0.13 1( ) 500 0.13 80( ) 600 0.13 160

14 1212 12

s

g

ex

d d

W L L nH W L L nH W L C fF

L nH C pF L nH C pF

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-30 -25 -20 -15 -10 -5 0

-60

-40

-20

0

20

40

O u t p u t P o w e r ( d B m )

Input Power (dBm)

3rd Order

1st Order

IIP3 = - 8.0 dBm

0 200 400 600 800 1000

0

2

4

6

8

10

12

14

16

18

N F ( d B )

Frequency (MHz)

NF (CRT)

NF (FC)

NF (Cascode)

0 200 400 600 800 1000-25

-20

-15

-10

-5

0

5

10

15

20

25

S21(CRT)

S21 (FC)

S21 (Cascode)

S 2 1 ( d B )

Frequency (MHz)

The FC-LNA as indicated in Fig.6 has the best linearity whereonly one single transistor exists in each DC path whichincreases the voltage swing and consequently improves thecircuit linearity. Another important figure of merit is the noisefigure; all three LNAs have a fairly low NF over a frequency

band as shown in Fig. 7. The total power dissipation for theFC-LNA and CRT-LNA is the best due to the hightransconductance with a lower current. Table 1 summarizes

the simulation results obtained from the simulations.

VI. CONCLUSIONS

This paper proposes a low power design techniques for

LNA with a 1-V power supply in a 0.13 m µ CMOS process.

These structures are based on CS-LNA with inductive source

degeneration. The proposed LC-folded cascode topology

maintains the advantages of the cascode LNA structure while

making it feasible for the input amplifier of the cascode

structure to work at a high effective voltage with a less

current. This improves the circuit linearity, increases the inputtransconductance and consequently the power gain. The CRT-

LNA is designed to increase the transconductance of the input

stage at the same bias current to be able to achieve a high gain

with a low noise figure. As a tradeoff an additional LC-tankcircuit is used for both FC-LNA and CRT-LNA which

certainly is a major area contributor. Simulation results show

that the three LNAs designed in this work meet the MICS

requirements.

TABLE I. LNAS SIMULATION RESULTS SUMMARY

Parameter Cascode LNA FC-LNA CRT-LNA

Gain ( )dB 16.1 18.2 23.7

Isolation ( )dB -60.2 -62.03 -40.2

11( )S dB -21.8 -31.78 -41.2

22( )S dB -13.4 -19.5 -18.35

( ) NF dB 0.65 0.60 0.62

3( ) IIP dBm -9.38 -8.0 -10.4

1 ( )dB dBm -19.02 -17.71 -25.5

Power cons.(mW) 1.0 0.8 0.8

Figure 5. The gain (S21) of the three LNAs

Figure 6. Input third-order intercept point of the FC-LNA

Figure 7. The noise figure of the three LNAs

R EFERENCES

[1] Huseyin S., Ahmet Sula, Zheng Wang, Numan S., E. Arvas, “MICStransceivers: regulatory, standards and applications,” IEEE SoutheastCon.2005, pp. 179-182, April 2005.

[2]

R.L. Moreno and E.C. Rodrigues, “CMOS LNA for wireless

biomedical telemetry,” IEE Proc. Circuits Devices and Systems, vol.152, pp.401-406, October 2005.

[3] Derek K. Shaeffer, and Thomas H. Lee, “A 1.5-V, 1.5-GHz CMOSLow Noise Amplifier,”IEEE Journal of Solid-State Circuits, vol.32,

no.32, pp. 745-759, May 1997.

[4] Huseyin S., Ahmet Sula, Zheng Wang, Numan S., E. Arvas, “A 1-VUHF low noise amplifier for ultralow-power applications,” proc. IEEE2006 ISCAS’06, pp. 4495-4498, May 2006.

[5] David J. Allstot, Xiaoyong Li, and Sudip Shekhar, “Design

considerations for CMOS low-noise amplifiers,” symp. IEEE on RFIC, pp.97-100, June 2004

[6] Paul Leroux, Johan Janessens, and Michiel Stayaert, “A 0.8-dB NFESD-protected 9-mW CMOS LNA operating at 1.23 GHz,” IEEEJournal of Solid-State Circuits, vol.37, no.6, pp. 760-765, June 2002.

[7]

Andrew N. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and mixer,”IEEE Journal of Solid-State Circuits, vol.31, no.12, pp. 1939-1944,December 1996.

[8] A. M. Niknejad and R. G. Meyer, “Analsis and optimization ofmonolithic inductors and transformers for RF ICs,” Proc. IEEE 1997CICC, pp.375-378, May 1997.

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A Comparative Study of CMOS LNAs