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Niko Bruels, IFX CPR ST2005-06-08 Page 1
Software-Defined Radio Project
A Baseband Processor Architecture for Multi-Standard Cell Phones
N e v e r s t o p t h i n k i n g .
Hans-Martin Blüthgen, Wolfgang Raab, Cyprian Grassmann, Niko Brüls, Uli RamacherCorporate Research, Infineon Technologies
Niko Bruels, IFX CPR ST2005-06-08 Page 2
2004 2005 2006 2007 2008 2009
Status today:
GSM/UM
TS
Bluetooth
IrDAFM Radio
+ WiFi 802.11b
+ DVB-T/H
+ WiM
ax+ UWB Wireless USB
+ NFC
+ WiFi 802.11g
+ WiFi 802.11n
+ Bluetooth 2.0
+ GPS
+ Galileo
Cognitive Radio
Trend for Cell Phones
Future Cell Phones are Multi-Standard !- Cellular- WLAN- Broadcast- Positioning- PAN
What is the best architecture ?
Niko Bruels, IFX CPR ST2005-06-08 Page 3
Outline
Motivation & Challenges
Levels of Parallelism and Analysis of Baseband Requirements
MuSIC Hardware Architecture
Software Architecture & Tools
Summary and Outlook
Niko Bruels, IFX CPR ST2005-06-08 Page 4
Multi Standard Cell Phone Requirements
More flexibility and scalability necessary for baseband processing– Variety of existing and evolving standards– Diversification of products– Time to market– NRE Costs
one common platform for all regions and product classes
Easy-to-program solution
Efficiency (Power, Area)
Standards to be supported in first prototype (some concurrently)– UMTS FDD at 384 kb/s – CDMA2000 1x DV– GSM/GPRS/EDGE class 12 – IEEE 802.11b / g (802.11g with reduce data rate)– Bluetooth– DAB– GPS
Baseband Processor Architecture with Reconfigurable RF Front-End
Niko Bruels, IFX CPR ST2005-06-08 Page 5
Architecture Challenge for the Baseband Processor
Strategy:Search for most flexible architecture
that meets power constraints !
Baseband performance required: 10’000+ MIPS equivalentsPower budget: 200 mW for UMTSMaximum flexibilitySimplicity of programming model
Performance, Power Flexibility, Simplicity
high parallelism, single processor,dedicated blocks general purpose
Niko Bruels, IFX CPR ST2005-06-08 Page 6
The Different Levels of Parallelism to ExploitData Level Parallelism
– Inherent in most BB alg.’sLocal Data Memory / Register File
ControlUnit
EU1 EU2 EU3 EUN
Instruct.Memory
– SIMD ArchitectureHigh EfficiencyCompiler issuesAmdahl’s Law !
Instruction Level Parallelism
– Complex Instructions
Local Data Memory / Register File
EU1 EU2 EU3 EUN
Instruct.Memory
instruction word Control
Unit
– VLIW ArchitectureCompiler friendlyRegister file issues
Task Level Parallelism– Multiple Interleaved Threads
Relaxed Memory RequirementsIncreased Latency
DataMemory
EUControl
Unit– Multiple Processors Core(ASIPs, Coprocessors, Accelerators)
Best Results By Exploiting All Levels Of Parallelism ! Best Results By Exploiting All Levels Of Parallelism !
Niko Bruels, IFX CPR ST2005-06-08 Page 7
Baseband Processor Stages: Different Requirements
high processing powerfixed by standard
Filter Stage Modem Stage Codec Stage net data bits
ADC
DAC
high proc. powercomplex algorithmshigh flexibilitycontrol & dataflow
moderate processing powercomplex algorithmsdetermined by standard
Encoding/Decoding– (de)interleaving– (de)puncturing– Viterbi, turbo, – rate matching, …
Modulation / Demodulation
– equalizing– synchronization– QAM, PSK, …– CDMA, TDMA, …– MIMO
Filter Operation– signal shaping
– band limitation
– rate conversion
application specificaccelerator (Programmable Filter)
application specificaccelerator (Turbo-Viterbi Processor)
Processor Solution
Niko Bruels, IFX CPR ST2005-06-08 Page 8
Infineon Baseband Processor Architecture MuSIC
SIMD Core 4
40 KMEM
SIMD Core 3
40 KMEM
SIMD Core 2
40 KMEM
Shared Memory
96 K 96 K 96 K
SIMD Core 1
40 KMEM
Accel. Accel.Turbo/Viterbi
SIMD Core ClusterARML1 CtrlMACI & D
Cache
RFInterface
Bus Bridge
96 K
Multi-threaded SIMD Core (MuSIC)
PE0
PE1
PE2
PE3
16 K Loc. MEMI & D Cache16 K + 8 K
PE Array
Multi-Layer System Bus
Peripherals
PE ArrayController
Multiple SIMD CoresAccelerators for FIR and Channel Encoding/Decoding
GP Core for L1 Ctrl & MAC3-Level Memory Hierarchy
- external DRAM/Flash - Shared Memory- Local Memories
FIR Filter
External Memory
IF
Niko Bruels, IFX CPR ST2005-06-08 Page 9
Block Diagram of Multi-Threaded SIMD Core
4-way SIMD Execution Units Long Instruction Word
- Computation Slot(DSP Pipe & IU)
- Memory Slot- Communication Slot
4 Interleaved ThreadsMulti-tasked GP core to control the SIMD core Local Data Memories instead of L1 Cache
Niko Bruels, IFX CPR ST2005-06-08 Page 10
SDR Filter Accelerator
SIMDCore40 K
Loc. MEM
96 K
M-1
SIMD Cluster
Loc. MEM
GPCore MAC
Interface
Shared Memory
InputDataMemory
Multiplier/Adder Array
Filter Accelerator
Con
trol
ler
FilterCoeff.Memory
Register File
filter length data word length coeff. word length sample rate
WCDMA approx. 20 approx. 8 8..10 7.68 MHzWLAN 802.11 15 10..12 10..12 22/40 MHz
Configurable Coprocessor
Multi-threaded (4 contexts)
Complex filter (I/Q)
Niko Bruels, IFX CPR ST2005-06-08 Page 11
SDR Channel Coding Processor
Encoder
hard
dec
isio
n Vi
terb
idec
oder
soft
outp
ut
Vite
rbi(
SO
VA
)
soft-
in s
oft-o
ut
Turb
o de
code
r (S
ISO
)
ACS: add, compare, select
branch metric: add/sub
LLR processor: add, max
SIS
O/S
OV
A
Dec
oder
Enc
oder
Mask, XOR, Shift
traceback processor: shift
from system bus (AHB)
hard or soft output
interleaveraddress
generator
PC
DPILPC
IMEMregextrinsics
memory
interleaveraddress
Lext
systematic and parity
LLR memory
Processor solution
2 Contexts (Viterbi/Turbo)
GP
Niko Bruels, IFX CPR ST2005-06-08 Page 12
Baseband Software Architecture
C and assembly programs for signal processing
ILTISInfineon Lightweight Real-TIme Operating System
multithreading, synch., periph. and accel. drivers, IPC Nucleus (RTOS)
Protocol stacks
L2/L3 control
SIMD Cores and TV / EQ - accelerators ARM 926
Multithreaded C-programs for phy layer ctrl (L1)
WCDMA 2G- GSM /GPRS/EDGE WLANHSDPA
Shared Memory
3G-W
CD
MA
(HS
DP
A)
2G-G
SM
/GP
RS
/ED
GE
WLA
N
WCDMA HSDPA
Common modules
2G- GSM /GPRS/EDGE WLAN
HSDPA
HSDPA
Niko Bruels, IFX CPR ST2005-06-08 Page 13
Programming Model
System function models of radio standardsControl and Signal ProcessingWCDMA, GSM, GPRS, EDGE
HeterogeneousMultiprocessorsystem
SIMD1 SIMD2 SIMD16 T/V FIR ARM9
Shared memory
HomogeneousProgrammingModel withMultiple threads
threadC +Inlineasm
threadC +Inlineasm
threadC +Inlineasm
threadC
threadC
threadC
Mapping
Niko Bruels, IFX CPR ST2005-06-08 Page 14
Software Design Process
Specification of radio standard (e.g. WCDMA)
C functions forsignal processing
Executable model of the radio standardCoCentric/COSSAP, SPW, Simulink, C-prog
1b – Single function verificationon Windows platform
1c – functionalsystem verificationon Windows platf.
Multithreaded C-program of the radio standarduses ILTIS on MuSIC
3b – systemverification& profiling onvirtual prototype
Multithreaded C-program of the radio standarduses ILTIS API on Windows platform
C & Assembly functionsfor signal processing
2c – systemverification& profiling onWindows platf.
2b – Single function verification &profilingon Windows based SIMD simulator
1a – Build functional system basedon inherent functional partitioning
2a – analysis of algorithmswith respect to MuSIC-architecture
Extraction of parallelism
3a – re-compilation re-linking
Niko Bruels, IFX CPR ST2005-06-08 Page 15
Tools
ILTIS alpha(IFX)
Nucleus (Mentor)
RC1632Compiler
(IFX)
ARMCC(ARM)
SIMDCompiler
(IFX)
SystemC Virtual Prototype (CoCentric System Studio)ARMulator
(ARM)
SIMD Cores and TV / EQ - accelerators ARM 926
Shared Memory / System-Bus
SIMD Simulator(IFX)
RC1632 Simulator(IFX with LisaTek/CoWare)
Code Generation
Eclipse (IBM)
Partitioning/Scheduling (IFX) Ctrl Code Generation (IFX)
High-Level System ModellingSimulink
(MathWorks)MLDesigner
(ML Design Technologies)Metropolis/Ptolemy
(UC Berkeley)
CoCentric (COSSAP)(Synopsys)
SPW(CoWare)
ExtensionsConverter (IFX)
Niko Bruels, IFX CPR ST2005-06-08 Page 16
Summary & Outlook
Future multi-standard cell phones require flexible basebandprocessing
Power-efficient and flexible solution based on parallel LIW-SIMD processors combined with accelerators
Software development framework for multi-threaded programs
Infineon’s SDR platform offers versatility and scalability beyond today's cell phone standards
Profiling results show feasibility of approach
Status and outlook
– Virtual prototype of platform available
– Platform demonstrator in Q1 2006
Niko Bruels, IFX CPR ST2005-06-08 Page 17
Thanks for your attention !
Questions ?
Contact:[email protected]
