A Amenable Neuromorphic Integrated Circuit Tolerates

ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)

Volume 6, Issue 8, August 2017

891 All Rights Reserved © 2017 IJARECE

A Amenable Neuromorphic Integrated Circuit

Tolerates Device Mismatch Was Implemented

in Cadence 45 nm Technology

Nadipineni.Rakesh, J.Samuel John Abstract: Neuromorphic systems are adaptive-

electronic Implementation of neural system appeals an

alternative to typical analog IC design technology in

terms of power adequacy and computation using

stochastic components. It solves the problems of

transistor deficiency and device mismatch in an IC. A

developed neuromorphic system called a Trainable

Analog Block (TAB) that tolerates device mismatch

suited for submicron level technology. Thus, degrades

the accuracy of analogue circuits. Methods to conflict

this should increase the complexity of design.

Trainable Analog Block contains three layers namely

input, hidden, and output, constitute the TAB

framework, with the number of hidden layer neurons

far stipulates the input layer neurons. A test cell was

built using TAB framework implemented in Cadence

45nm process technology (and also implemented in

90nm). In this paper, we discuss its learning capability

and also comparison of test cell in 90 & 45 nm. An

offline learning algorithm was used on TAB IC

analytically calculates the pseudo inverse of hidden

layer activation functions with targeted outputs. A

width and length size for each transistor was also

specified. Power dissipation in the TAB test cell with

neuron blocks was also mentioned.

Index Terms – Neuromorphic engineering, stochastic

electronics, Analog integrated circuit design, neural

network hardware, Cadence, nanometer technology.

I. INTRODUCTION

he persistent annual improvement in the

computing power of modern PCs and portable

electronic devices has been enabled, and

stimulated on by the continuing Advancements in

integrated circuit (IC) fabrication technology[5]. Roughly

every 18 months, The minimum feature size in which

transistors can be fabricated shrinks, and the size of a

Single wafer increases, such that the number of transistors

on a single chip doubles – by Moore‘s law. Due to this,

computing devices have become smarter, faster, and more

efficient. The increase in the number of transistors has

been made possible due to a decrease in the minimum

feature size, which has already reduced below 22 nm.

However, preserving Moore‘s law [5] has not been easy.

In sub micrometer technologies, factors such as minor

variations of process, external unidentified fields, minor

layout changes, and leakage currents have large effects on

the performance of analog circuits, making them difficult

to design and thus, creating significant challenges. As the

IC technology advances further into smaller nanometer

feature sizes, problems such as increasing element

failure rate and power limitations present ever more

challenging obstacles [4] to further miniaturization.

An aspect of neuromorphic engineering is to

understand how the individual neurons, circuits and

architectures adores computations, conveys ability to

learn and influences the vigor damage. Biological systems

have been able to overcome many of the problems similar

to those being faced by the IC designers [2], to deliver

reliable, real time computation in neural Circuits.

Although built from low performance components, these

neural circuits have themselves been pushed to the

extreme physical limits of their ‗feature size‘ by

evolution. This serves as a motivation for the

investigation of alternative electronic and Computational

architectures based on neurobiological systems. The goals

of neuromorphic Engineering were to design and

implement microelectronic systems that emulate the

Following characteristics are Low power consumption,

adaptive nature and fault tolerance [5]. They have their

ability to interact with new trending technology for easy

learning and adaptation. Implicating neuromorphic

system offers a method of exploring neural Computation

in a medium whose physical nature acts like analog

module towards biological Nervous systems and that

operate in real time irrespective of size. The implications

of these approaches are both scientific and practical.

Fusion of neuromorphic systems transposes knowledge of

neuroscience into practical devices that can interact

directly with the real world.

In many regions of human brain, information encodes

through patterns of activity over large number of neurons.

A test cell was built using a neuromorphic system called a

trainable analog block (TAB) that works in a manner

applying large number of neurons for encoding input

variables and linearly combines the response to achieve

decoding. The TAB chip architecture tolerates random

device mismatch which were suited for sub micrometer

technology. The TAB attempts to implicate the features

of neurobiological systems, such as low power

consumption, adaptive learning and fault tolerance. In IC

implementation of a neural network, parameters are

learned externally using a software model using batch

learning and then loaded into the IC [3]. It is Very difficult

to build accurate software models for batch learning for an

analogue neural Network [2] IC, because of device

mismatch and circuit nonlinearities [4]. Owing to

adaptivity, these designs are portable across technologies

and an application eliminates the need for custom IC

designs for those functions that can implement in TAB

[15]. The TAB framework used to design systems that will

T




impose hardware variability to achieve sustained goal. The

TAB circuit allows complex process on a simple and

repeated substrate. Many research groups have proposed systems that are

tolerant to device mismatch for computation in silicon.

Several, recent papers have used architectures similar to

TAB design, Inspired either by the neural engineering

frame work (NEF) or the extreme learning machine

(ELM), and implemented using spiking neurons to process

the spike inputs. A machine teaching co-processor (MLCP)

that performs spike-based computation using ELM [15].

The MLCP encodes the ELM algorithm for spike inputs in

many stages, and the decoding on a microcontroller

(MCU) is done individually. The MLCP takes the spike

inputs and then converts them into the analog domain

using a counter and a DAC circuit. The output of the DAC

is then sent as a current input to the Analog neurons, which

convert it back into spikes, and the resultant spikes using a

digital counter with some extra logic blocks are counted to

implement a saturating nonlinearity. The output of the

counter is then sent to an MCU for decoding of the ELM

algorithm. In ELM architecture, the number of hidden

layer neurons is quite large of the input dimensions, to

achieve good accuracy. However, the MLCP supports 128

inputs with only 128 hidden nodes. This system will thus

have a low encoding capacity due to a low number of

hidden nodes for such a high number of input dimensions.

In this paper, TAB system is designed to tolerate device

mismatch to create an analog signal processor, which does

not use spikes. We have simply used a differential pair to

generate the saturating nonlinearity [11]. Our system does

not require any extra circuits such as a digital counter,

spiking neurons, or an input pre-processing unit for

encoding of the input, unlike in the case of the MLCP. The

TAB also performs the decoding of the ELM framework

on to the same chip it does not require a separate MCU or

an FPGA for the decoding logic [15].

This paper is organized as: Section II contains about

framework of TAB. VLSI Implementation of TAB is

described in Section III. The algorithm setup for offline

learning in Section IV and Implications of Transistor

mismatch importance, width sizes of transistors were

mentioned in Section V. In Section VI, We present the

measurements of the building blocks of TAB test cell

implementation in Cadence and Conclusions in Section

VII.

II. FRAMEWORK OF TAB

The TAB framework draws enthusiasm from neural

population coding. Where, neuron in [8] parts of brain

encodes information in collective manner using spike

rates. The accuracy of the information processing in the

brain, which in turn effects neuronal and neural tuning

curves in the shape diversity of responses, where affected

population depends on quality of coding. It is a function

of a neuron to stimulate the input that plots average firing

rate [7]. Examples of the population coding neurons in

monkeys, cricket, cats, bats, and mice encodes arm

movements, such as the direction of a wind, sound

stimulus [15] encode direction, saccade , echo delay, and

the environment in the position of the rat in present

environment. Tab framework was designed to be used

instead of individual spikes curves. Further, uses a diverse

population of neurons undergone in construction of the

tab. The diversity of neurons in network increases the

capacity of encoding information. .

Fig. 1. Architecture of the TAB framework. The

connections from the input layer Nodes (neurons) to the

non-linear hidden nodes (neurons) via random weights

with controllable offsets, O1to OM. The hidden layer

neurons are connected linearly to the output layer neurons

via trainable weights. The output neurons compute a

linearly weighted sum of the hidden layer values.

Accurate encoding of an input occurs when a

population of neurons covers the entire range of the input

variable. This is best succeeded, if the neuronal tuning

curves are similarly spaced, and may be imposed in a

neural system by encoding the defined physical properties

of neurons in each population. Instead, arbitrarily chosen

parameters from the circulation are likely to perform an

equally good approximation. Recently, Caronet al.

showed the existence of such randomness in the olfactory

system, where inputs from the glomeruli to individual

Kenyon cells deficiency with respect to their odor tuning,

anatomical features, or developmental origins. In TAB

framework [15], we have projected the input from the

input layer neurons to the hidden layer neurons in a

random manner. Device mismatch cannot be evaded in

smaller process technology, and instead we are using it in

the TAB framework to encode the input variable

The TAB is a feed-forward network contains three

layers namely input, hidden, and output, well-regulated

on the linear solutions of higher dimensional interlayers

(LSHDI) [8]principle. The input layer nodes are

connected to large number of hidden nodes via fixed

random weights. Frequently, the inputs project randomly

and transforms to a higher dimensional feature space by

nonlinear hidden layer of neurons. Here, input data points,

which are not linear, find a linear hyper plane in higher

dimensional space that represents a classification edge for

the input-output relationship [7]. The output layer node

drives a solution by computing weighted sum of hidden

layer values [15]. These linear weights are analytically

evaluated by computing output values and pseudo inverse

of hidden layer output nodes [11].




III.VLSI IMPLEMENTATION OF TAB

In order to exhibit that the TAB is adequate in smaller

process nodes that are typically forbidden to analog

design [6] (beyond 45nm), we have designed a prototype

in 90 & 45 nm technology tolerates device mismatch

among transistor parameters [15]. Comprising of a

Hidden neuron block and an output weight block of the

proposed architecture allows designing a major block of

circuit with lowest feature size which maximizes

mismatch [5]. More eminently, each hidden node

performs a different nonlinear operation to the input using

a systematic offset for hidden layer neuron [15].

The first version of TAB prototype mentioned here

has a simple configuration, with a single input voltage

and a single output current (SISO) [15]. In this section,

the VLSI implementation of the major building blocks of

the TAB [12], namely the Hidden layer and output

weight block are enlightened.

A .Hidden Neuron

Scientists clearly indicate that individual biological

neuron responds to various stimuli like sound, images

[14]. Each artificial neuron on our chip encodes input

differently based on tuning curve [4]. In the TAB system,

we use a differential pair to implement a simple neuron

model in the TAB. The differential pair performs a

nonlinear operation on its input, similar to tuning curve.

In Fig. 2, Vin (input voltage) and Vref (reference voltage)

are the gate voltages for the differential pair of transistors,

M1 and M2, influence the sharing of currents between

them. If all MOSFETs ('metal-oxide-semiconductor field

effect transistors') operate in weak-inversion region [7],

with slope factor (n) ranging from 0.5 to 1.5 [15]. The currents in transistors M1 and M2 can be followed as:

[ (

)]

[ (

) (

)]

(1)

[ (

)]

[ (

) (

)]

(2)

Where Ib is the maximum bias current, Vin is the ramp

input voltage, Vref is the constant input voltage, and UT is

the thermal voltage.

Fig.2. Hidden Neuron Block. Schematic of the hidden

neuron block that implements the activation function for

the TAB framework.

Fig. 3. Hidden Neuron Block. Schematic of the hidden

neuron block in Cadence gpdk045 that implements the

Activation function for the TAB framework.

The current I1 is copied to Ihid via a current mirror, which

acts as an activation function of hidden neuron. With

these ideal transistors, the currents, I1 and I2 are a function

of Vin and Vref. The voltage at the M3 transistor, V b

sets the bias current (few nano-amperes). In the TAB,

each neuron has a distinct tuning curve depend on several

variations such as offset mismatch between the transistors

in the differential pairs, bias current mismatch due to

variability in M3 and current mirror mismatch. Each

neuron may receive a systematically different V ref in the

TAB [15], which is a failsafe method to achieve a distinct

tuning curve for each neuron. This may be required in the

case of insufficient random variations, similarly in

higher feature size process technology. These variations




can be achieved at each hidden neuron by changes in

Vref.

B. Output weight block:

The output weight block connects the hidden layer and

the output layer via linear weights. These are controlled

by a 13-bit binary number, which is stored in digital

flipflops that regulate the amount of current flowing from

the hidden layer neurons to the output layer neurons [15].

We implemented binary weighted connections using a

splitter

Circuit.

Fig.4. Output Weight Block. Schematic of the output

weight block, comprising a splitter circuit wherein MR

and the two M2R transistors form an R2R network, which

gets repeated 13 times in the block. The splitter is

terminated with a single MR transistor.

Fig. 5. Output Weight Block. Schematic of the output

weight block implemented in cadence gpdk045, contains

13 bit weights and splitter circuit.

The output from the hidden neuron block, Ihid, is the

input current for the output weight block. Ihid is divided

successively to form a geometrically-spaced series of

smaller currents. A digital binary switch controls each

current branch. A fixed fraction of the current is split off

at each branch, and the remaining continues to the later

branches. MR and two M2R transistors forms R2R

network, and splitter is terminated with a single MR

transistor. There are a total of N stages in the splitter

circuit. The master bias voltage Vgbias is the reference

voltage for the P-FET gates in the splitter. As shown in

below figure. 4. Two transistor switches in the lower half

of the circuit route the branch current to either useful

current I good , and current that goes to ground was

Idump . I good is mirrored to generate a current I out ,

which is further routed to currents Ipos (positive current)

or Ineg (negative current), as determined. IoutP and IoutN

currents of each neuron block are connected to each other

and provides the final current that is final output.

This TAB chip was designed for a single input

and a single output configuration with neuron blocks [15],

the number of neuron blocks being constrained by the

chip area. Each neuron block integrates a hidden neuron,

an output weight block and a 13-bit shift register, which

is used for loading the learned Weights. The 13-bit output

weights are connected as shift registers. Internal shift

registers of all the hidden neurons are connected serially

as a long chain at the top level. The shift registers are

loaded with off-chip calculated weights and are used to

regulate the current in the output weight block. At a

particular time, each neuron block receives the same input

voltage Vin , which is weighted by a random weight and a

random offset arising due to process variations.

Additionally, each neuron may exhibit a distinct reference

voltage V ref , in the differential pairs of the hidden

neuron. This leads to different differential voltages for

each neuron block, and as a result different currents, Ihid,

are generated for each block. The poly-silicon wire

behaves as a long distributed resistor element that acts as

a voltage divider and generates different reference

voltages, Vref , for each neuron block. For each new

input, the hidden neuron block calculates Ihid, which

passes to the output weight block. In the output weight

block, I good is mirrored to make I out , which is further

routed to currents IoutP (positive current) or IoutN

(negative current), as determined. IoutP and IoutN

currents of each neuron block are connected globally to

each other, and they are summed up to provide the final

current that is the final output of the TAB.

IV. OFFLINE LEARNING SET-UP

An algorithm used for the offline learning of the TAB IC.

In the TAB framework, learning is achieved by

computing output weights to train the system. The output

weights (between the large hidden layer and the linear

output neurons) are estimated analytically by calculating

the product of the pseudo inverse of the hidden layer

activations with the target outputs. Briefly summarize the

learning setup below. Let us consider a three-layer feed-

forward TAB network with L number of hidden neurons.

Let G(., ., ., ., .)be a real-valued function so that

G(wi(1)

,bi(1)

,oi(1)

,x ,di(1)

) the output of the ith hidden

neuron, corresponding to the input vector X∈Rm. The

random input weight vector wi(1)

= (wi1(1)

,……..wim(1)

),

where wis(1)

is the weight of the connection between the

ith hidden neuron and sth neuron of the input layer, with

random bias bi(1)

∈R, both arising due to random

mismatch of the transistors. The random input weight,




w(1)

, varies according to a log-normal distribution due to

the exponential relationship between the voltage and the

current of a transistor, while the random bias, bi(1)

,

exhibits a Gaussian distribution. Preferred direction (PD),

denoted as di(1)

∈[−1,1] is added to include flexibility of

changing the direction either towards positive or negative

values. PD assignment to the hidden neurons could be

chosen randomly. Systematic offset oi(1)

∈ R is added to

confirm that each neuron exhibits a distinct tuning curve,

which is an essential requirement for learning in the

LSHDI framework . The output vector y ∈ Rk

can be

written as:

𝑦 = ∑

(3)

Where wi(2)

= (w1i(2)

,……,wki(2)

) ∈ Rk is the weight

vector where wji(2)

∈ R is the weight connecting the ith

hidden neuron with the jth neuron of the output layer.

Here, G(.,.,.) takes the following form

G(wi(1)

,bi(1)

,oi(1)

,di(1)

,x) = (g (wi(1)

.x + bi(1)

+oi(1)

)).di(1)

(4)

Where, g: R→R is the activation function.

The output weight vector, wi(2)

, can be written in matrix

form for all the hidden neurons as W(2)

. The least squares

solution of the output weight matrix, W(2)

, as described

as:

W(2)

= H+Y (5)

The above set of equations can be written in the matrix

form as:

HW(2)

= Y (6)

Where,

HMxL =. [ (

)

] (7)

W(2)

LxK = [

] , YCxK = [

𝑦

𝑦

] (8)

Here, the i

th column of H will be the output of the ith

hidden neuron for all the input samples (xl,…, xm).Further,

the matrix H need not be a square matrix. Under the

theory that the activation function g(.) is extremely

differentiable, it has been shown that for fixed input

weight vectors,wi(1)

, and biases, bi(1)

, oi(1)

, the least squares

solution W(2)

for the matrix is:

W(2)

= H+Y (9)

Where, 𝐻+ is the Moore-Penrose generalized

pseudoinverse of the matrix 𝐻. The matrix 𝑌 is the

collection of the output vectors for the training dataset.

A. Characterisation of information encoding in the TAB

IC:

It has been demonstrated that in a neurobiological system,

individual neurons exhibit highly heterogeneous

responses when presented with the same stimuli. This

heterogeneity has been shown to improve the information

encoded in the neuronal population activity by decreasing

the neuronal correlations. We show that the tuning curves

of neurons in our TAB framework should be

heterogeneous so as to have the highest information

encoding capacity.

Let us revisit equation and find W(2)

analytically:

Y = HW(2)

(10)

HTY = H

THW

(2) (11)

(HTH)

-1H

TY=W

(2) (12)

Then estimated output,

Ŷ = HW(2)

= H((HTH)

-1H

TY) (13)

Where, I is the identity matrix.

I = H(HTH)

-1H

T (14)

If matrix H is a full column rank matrix, or equivalently,

columns of the matrix H are linearly independent, then,

I = HH+ (15)

Where, H is the measured matrix containing the hidden

neuron output across the range of input values and H+ =

(HTH)

-1H

T is the pseudoinverse of a matrix.

V .IMPLICATION OF DEVICE MISMATCH

Mismatch is a random process causes variations in

physical quantities of identical designed devices [4].

Minimal power consumption of current processing stages

for a given speed and accuracy indicates further scaling of

technology would not further improve the performance.

Reduction of threshold voltage, mismatch with oxide

thickness towards deeper sub-micron level technologies,

will improve the intrinsic matching of technology [6].

upto now no clear scaling of β mismatch occurred, at this

point further scaling is thought not to improve anymore,

the total performance of analog systems. current

processing block blocks must be biased in strong

inversion to obtain good performance. Mismatch in

threshold voltage and mobility variations influence

current factor variance, dominates the transistor

performance for normal gate source potentials. Thinner

gate oxide decreases the threshold and substrate-factor




mismatch. Current mismatch has many causes affected by

edge effects, implantation, surface state charges, oxide

effects, mobility effects.

Matching properties of transistors, W/L sizes for each

transistor can be assumed as:

( )

(16)

TABLE 1

Transistor sizes for Hidden block in Cadence gpdk045

library (W/L ratios):

Device name W/L(µ)

NM4 0.79/0.045

PM3,PM5 0.64/0.045

NM3,NM5 0.40/0.045

PM4 0.15/0.045

TABLE 2

Transistor sizes for Hidden block in Cadence gpdk090

library (W/L ratios):

Device name W/L(µ)

PM0 1.4/0.1

PM1 1.3/0.1

PM2 0.7/0.1

NM0,NM2 0.3/0.1

NM1 0.2/0.1

TABLE 3

Transistor sizes for output weight block in Cadence

gpdk045 library (W/L ratios):

Device name W/L(µ)

PM0,PM2,PM4,PM18,PM19 1.30/0.045

PM1,PM3,PM6 1.08/0.045

PM185,PM172,PM10,PM35 0.9/0.045

PM20,PM29 0.8/0.045

PM37,PM30,PM32,NM8 0.7/0.045

PM33,PM55,PM50,PM66 0.6/0.045

PM67,PM36,PM54,PM65,PM64 0.4/0.045

PM53,PM47,PM52,PM48,NM1,NM3 0.3/0.045

PM7,PM85,PM83,PM15,PM24,PM37,P

M40,PM79

0.17/0.045

PM58,PM42,PM43 0.16/0.045

PM22,PM84,PM8,PM11,PM27,PM34,P

M78

0.15/0.045

PM190,PM9,PM12,PM13,PM16,PM25,PM39,P

M38,PM45,PM56,PM71,PM73,PM72,PM16

0.14/0.045

PM14,PM77,PM41,PM46 0.13/0.045

TABLE 4

Transistor sizes for Cadence gpdk090 library (W/L

ratios):

Device name W/L(µ)

PM66,PM67,PM62,PM64,PM6

1

1.33/0.1

PM60,PM63,PM65 1.12/0.1

NM0,PM56,PM58 0.61/0.1

NM1,NM2,PM1,PM2,PM3,PM4,PM

5,PM6,PM14,PM15,PM17,PM18,PM

20,PM21,PM23,PM24,PM26,PM29,

PM30,PM32,PM33,PM35,PM36,PM

38,PM39,PM41,PM42,PM45,PM46,

PM47,PM48,PM50,PM51,PM53,PM

54

0.58/0.1


,PM52,PM55,PM57,PM59

0.34/0.1


7,PM40,PM43,PM44,PM49,P

M0

0.26/0.1

VI .RESULTS

A. Characterization of TAB IC in Cadence :

A TAB prototype was built using TAB framework was

implemented in 90 & 45 nm process technologies with

hidden neuron block and output weight block. Table

summarizes the system level features of TAB chip. In the

TAB, we have used a current gain circuit consisting of

two sets of current mirrors amplifies to get final output

current for measurement purposes, which may not be

required in actual applications. The actual power

dissipation of TAB is much smaller than that of the output

stage. Thus in table 6 we report the power consumption.

We also characterized the speed of the TAB by the step

response .The measured time constant of the TAB for the

step response is 2.5ns. The actual time constant of the

TAB without the output current mirror would be much

smaller than this, but we cannot measure it in current

system. Each neuron block contains a hidden neuron and

output weight block (SECTION III) with shift registers.

The shift registers of all the hidden neurons are connected

as chain. Large number of hidden neurons are not feasible

to have dedicated output current. The output weight block

behaves as a current splitter, i.e., if all the weight values

are one, the output current of the output weight block

would be same as input current, and if weights are zeros,

the output weight block will produce nearly zero output.

In order to calculate the random voltage offset , Vref is

used for all hidden neurons. Similarly, when the input of a

neuron is equal to Vref , the neuron reaches half of its

output current.




B.Simulation results in Cadence tool:

Fig. 6. Schematic of Hidden block implemented in

Cadence gpdk090 library, provides activation framework

for TAB framework.

C.Dc analysis:

Generally dc analysis is done for providing dc operating

points for all parameters of mos circuit with dc sources.

This analysis provides to find power dissipation, current,

current consumption, and to find state of region for

transistor.

(a)

(b)

(c)

(d)

(e)

Fig. 7.simulation results, dc analysis for hidden and

output weight block in gpdk45, gpdk090. (a) Ihid

(output) of Hidden layer in gpdk045, (b) Ihid of Hidden

layer in gpdk090, (c) Iout of output weight block in

gpdk45, (d) Iout of output weight block in gpdk090, (e)

dc analysis for 13 weight values of output weight block

in gpdk045 provides current for each node.




D. Transient analysis:

In time domain, transient analysis measures rise and fall

time, quality factor.

(a)

(b)

(c)

(d)

(e)

(f)

Fig. 8.Simulation results of Hidden block and output

weight block time domain transient analysis. (a)

Represents Ihid time for each cycle of hidden block in

gpdk45. (b) Presents Ihid time for each cycle of hidden

block in gpdk90. (c) Presents time of output weight block

in gpdk45. (d) Represents time for clock of output weight

block in gpdk90. (e) Time of each clock cycle done for 13

weight value blocks of own in gpdk45. (f) Time for each

clock cycle in own for calculating 13 weight values of

own in gpdk90.




TABLE 5

Features of the TAB prototype (SISO chip Configuration)

Technology (Cadence) 45nm 90nm

Supply voltage 1.2v 1.2v

Input voltage of neuron block 1.2 1

Time constant of TAB

Hidden

2.5ns 2.5ns

Time constant of Output weight

block

10ns 10ns

Time constant of 13 bit weight

registers

10ns 10ns

Current obtain from Hidden

block

20.56pA 71.49pA

Current obtain from Output

weight block

78.39pA 208.69pA

VII .CONCLUSION

In this paper, we have conferred a framework containing

TAB prototype that tolerates random device mismatch in

circuits and performs reliable computation. We have

presented measurement results of first prototype IC

designed in 45nm (and also in 90nm) for a single input

and a single output configuration of the TAB system.

TAB incorporates system offset as a failsafe method, may

be required when there is insufficient random variation

among transistors which are likely in higher feature size

process technology. Additionally, we have shown the

learning capability of the TAB system through offline

learning algorithm.

The implementation of TAB framework in the analog

domain tenders more advantage over digital

implementations. For example, addition in analog circuit

computes by connecting outputs to sum the currents and

multiplication in TAB is implemented using output

weights with a few transistors, which saves extra circuits

for conversion, while digital implant requires thousands

of transistors for each computation. Our system tenders

low power consumption in the range of a few µw with

high capacity of encoding, adapts to local change and the

ability to learn. Analog implant of TAB is easy to merge

with sensors, by their nature, compared to digital ones,

which always require an analog –to-digital converter

(ADC).

The TAB is influenced by neural population coding

which is very tough in damage of few neurons, and does

not effect on information encoding across many neurons.

The TAB system is projected using neuromorphic

principles based on stochastic computation. We confront

the TAB to conquer limits of analog IC design at low

process nodes and hitch the integration process with

digital blocks in circuit and node.

The main significances of our TAB, that works better

with huge amount of device mismatch, and maps input

values to output values without needing to architect the

effect of device mismatch of the circuit, as is done

correctly. It may find applications in analog/digital

converter (ADC) and digital-to-analog converter (DAC)

for sub micrometer chips as those used in mobile

processor chips and data acquisition chips. Future work

will aim to test the learning capability of multi-input TAB

(MISO) chip configuration. Furthermore, as the TAB

framework desires large random device mismatch among

devices and as mismatch is contrarily relative to device

area, could lead to reduction in chip area. Also failure of

neurons would not affect the performance of the TAB as

information encodes in large number of neurons.

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Authors N. Rakesh, Studying M.Tech, Final year in VLSI & ES

Specialization, ECE Department, Velagapudi

Ramakrishna Siddhartha Engineering College, Kanuru,

Vijayawada-7, Affiliated to Jawaharlal Nehru

Technological University –Kakinada, Andhra Pradesh.

Email:[email protected]

J.Samuel John , Assistant Professor, ECE Department,

Velagapudi Ramakrishna Siddhartha Engineering

College, Kanuru, Vijayawada-7, Affiliated to Jawaharlal

Nehru Technological University –Kakinada, Andhra

Pradesh. Email: [email protected]

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A Amenable Neuromorphic Integrated Circuit Tolerates